sys/dev/netif/sk/if_sk.c

   1 /*
   2  * Copyright (c) 1997, 1998, 1999, 2000
   3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * $OpenBSD: if_sk.c,v 1.129 2006/10/16 12:30:08 tom Exp $
  33  * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $
  34  */
  35
  36 /*
  37  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  38  *
  39  * Permission to use, copy, modify, and distribute this software for any
  40  * purpose with or without fee is hereby granted, provided that the above
  41  * copyright notice and this permission notice appear in all copies.
  42  *
  43  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  44  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  45  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  46  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  47  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  48  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  49  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  50  */
  51
  52 /*
  53  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  54  * the SK-984x series adapters, both single port and dual port.
  55  * References:
  56  *      The XaQti XMAC II datasheet,
  57  * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  58  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  59  *
  60  * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
  61  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  62  * convenience to others until Vitesse corrects this problem:
  63  *
  64  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  65  *
  66  * Written by Bill Paul <wpaul@ee.columbia.edu>
  67  * Department of Electrical Engineering
  68  * Columbia University, New York City
  69  */
  70
  71 /*
  72  * The SysKonnect gigabit ethernet adapters consist of two main
  73  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  74  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  75  * components and a PHY while the GEnesis controller provides a PCI
  76  * interface with DMA support. Each card may have between 512K and
  77  * 2MB of SRAM on board depending on the configuration.
  78  *
  79  * The SysKonnect GEnesis controller can have either one or two XMAC
  80  * chips connected to it, allowing single or dual port NIC configurations.
  81  * SysKonnect has the distinction of being the only vendor on the market
  82  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  83  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  84  * XMAC registers. This driver takes advantage of these features to allow
  85  * both XMACs to operate as independent interfaces.
  86  */
  87
  88 #include <sys/param.h>
  89 #include <sys/bus.h>
  90 #include <sys/endian.h>
  91 #include <sys/in_cksum.h>
  92 #include <sys/kernel.h>
  93 #include <sys/interrupt.h>
  94 #include <sys/mbuf.h>
  95 #include <sys/malloc.h>
  96 #include <sys/queue.h>
  97 #include <sys/rman.h>
  98 #include <sys/serialize.h>
  99 #include <sys/socket.h>
 100 #include <sys/sockio.h>
 101 #include <sys/sysctl.h>
 102
 103 #include <net/bpf.h>
 104 #include <net/ethernet.h>
 105 #include <net/if.h>
 106 #include <net/if_arp.h>
 107 #include <net/if_dl.h>
 108 #include <net/if_media.h>
 109 #include <net/ifq_var.h>
 110 #include <net/vlan/if_vlan_var.h>
 111
 112 #include <netinet/ip.h>
 113 #include <netinet/udp.h>
 114
 115 #include <dev/netif/mii_layer/mii.h>
 116 #include <dev/netif/mii_layer/miivar.h>
 117 #include <dev/netif/mii_layer/brgphyreg.h>
 118
 119 #include <bus/pci/pcireg.h>
 120 #include <bus/pci/pcivar.h>
 121 #include <bus/pci/pcidevs.h>
 122
 123 #include <dev/netif/sk/if_skreg.h>
 124 #include <dev/netif/sk/yukonreg.h>
 125 #include <dev/netif/sk/xmaciireg.h>
 126 #include <dev/netif/sk/if_skvar.h>
 127
 128 #include "miibus_if.h"
 129
 130 #if 0
 131 #define SK_DEBUG
 132 #endif
 133
 134 #if 0
 135 #define SK_RXCSUM
 136 #endif
 137
 138 /* supported device vendors */
 139 static const struct skc_type {
 140         uint16_t        skc_vid;
 141         uint16_t        skc_did;
 142         const char      *skc_name;
 143 } skc_devs[] = {
 144         { PCI_VENDOR_3COM,              PCI_PRODUCT_3COM_3C940,
 145           "3Com 3C940" },
 146         { PCI_VENDOR_3COM,              PCI_PRODUCT_3COM_3C940B,
 147           "3Com 3C940B" },
 148
 149         { PCI_VENDOR_CNET,              PCI_PRODUCT_CNET_GIGACARD,
 150           "CNet GigaCard" },
 151
 152         { PCI_VENDOR_DLINK,             PCI_PRODUCT_DLINK_DGE530T_A1,
 153           "D-Link DGE-530T A1" },
 154         { PCI_VENDOR_DLINK,             PCI_PRODUCT_DLINK_DGE530T_B1,
 155           "D-Link DGE-530T B1" },
 156
 157         { PCI_VENDOR_LINKSYS,           PCI_PRODUCT_LINKSYS_EG1032,
 158           "Linksys EG1032 v2" },
 159         { PCI_VENDOR_LINKSYS,           PCI_PRODUCT_LINKSYS_EG1064,
 160           "Linksys EG1064" },
 161
 162         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON,
 163           "Marvell Yukon 88E8001/8003/8010" },
 164         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_BELKIN,
 165           "Belkin F5D5005" },
 166
 167         { PCI_VENDOR_SCHNEIDERKOCH,     PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE,
 168           "SysKonnect SK-NET" },
 169         { PCI_VENDOR_SCHNEIDERKOCH,     PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2,
 170           "SysKonnect SK9821 v2" },
 171
 172         { 0, 0, NULL }
 173 };
 174
 175 static int      skc_probe(device_t);
 176 static int      skc_attach(device_t);
 177 static int      skc_detach(device_t);
 178 static void     skc_shutdown(device_t);
 179 static int      skc_sysctl_imtime(SYSCTL_HANDLER_ARGS);
 180
 181 static int      sk_probe(device_t);
 182 static int      sk_attach(device_t);
 183 static int      sk_detach(device_t);
 184 static void     sk_tick(void *);
 185 static void     sk_yukon_tick(void *);
 186 static void     sk_intr(void *);
 187 static void     sk_intr_bcom(struct sk_if_softc *);
 188 static void     sk_intr_xmac(struct sk_if_softc *);
 189 static void     sk_intr_yukon(struct sk_if_softc *);
 190 static void     sk_rxeof(struct sk_if_softc *);
 191 static void     sk_txeof(struct sk_if_softc *);
 192 static int      sk_encap(struct sk_if_softc *, struct mbuf **, uint32_t *);
 193 static void     sk_start(struct ifnet *);
 194 static int      sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 195 static void     sk_init(void *);
 196 static void     sk_init_xmac(struct sk_if_softc *);
 197 static void     sk_init_yukon(struct sk_if_softc *);
 198 static void     sk_stop(struct sk_if_softc *);
 199 static void     sk_watchdog(struct ifnet *);
 200 static int      sk_ifmedia_upd(struct ifnet *);
 201 static void     sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 202 static void     sk_reset(struct sk_softc *);
 203 static int      sk_newbuf_jumbo(struct sk_if_softc *, int, int);
 204 static int      sk_newbuf_std(struct sk_if_softc *, int, int);
 205 static int      sk_jpool_alloc(device_t);
 206 static void     sk_jpool_free(struct sk_if_softc *);
 207 static struct sk_jpool_entry
 208                 *sk_jalloc(struct sk_if_softc *);
 209 static void     sk_jfree(void *);
 210 static void     sk_jref(void *);
 211 static int      sk_init_rx_ring(struct sk_if_softc *);
 212 static int      sk_init_tx_ring(struct sk_if_softc *);
 213
 214 static int      sk_miibus_readreg(device_t, int, int);
 215 static int      sk_miibus_writereg(device_t, int, int, int);
 216 static void     sk_miibus_statchg(device_t);
 217
 218 static int      sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
 219 static int      sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int);
 220 static void     sk_xmac_miibus_statchg(struct sk_if_softc *);
 221
 222 static int      sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
 223 static int      sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int);
 224 static void     sk_marv_miibus_statchg(struct sk_if_softc *);
 225
 226 static void     sk_setfilt(struct sk_if_softc *, caddr_t, int);
 227 static void     sk_setmulti(struct sk_if_softc *);
 228 static void     sk_setpromisc(struct sk_if_softc *);
 229
 230 #ifdef SK_RXCSUM
 231 static void     sk_rxcsum(struct ifnet *, struct mbuf *, const uint16_t,
 232                           const uint16_t);
 233 #endif
 234 static int      sk_dma_alloc(device_t);
 235 static void     sk_dma_free(device_t);
 236
 237 #ifdef SK_DEBUG
 238 #define DPRINTF(x)      if (skdebug) kprintf x
 239 #define DPRINTFN(n,x)   if (skdebug >= (n)) kprintf x
 240 static int      skdebug = 2;
 241
 242 static void     sk_dump_txdesc(struct sk_tx_desc *, int);
 243 static void     sk_dump_mbuf(struct mbuf *);
 244 static void     sk_dump_bytes(const char *, int);
 245 #else
 246 #define DPRINTF(x)
 247 #define DPRINTFN(n,x)
 248 #endif
 249
 250 /* Interrupt moderation time. */
 251 static int      skc_imtime = SK_IMTIME_DEFAULT;
 252 TUNABLE_INT("hw.skc.imtime", &skc_imtime);
 253
 254 /*
 255  * Note that we have newbus methods for both the GEnesis controller
 256  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 257  * the miibus code is a child of the XMACs. We need to do it this way
 258  * so that the miibus drivers can access the PHY registers on the
 259  * right PHY. It's not quite what I had in mind, but it's the only
 260  * design that achieves the desired effect.
 261  */
 262 static device_method_t skc_methods[] = {
 263         /* Device interface */
 264         DEVMETHOD(device_probe,         skc_probe),
 265         DEVMETHOD(device_attach,        skc_attach),
 266         DEVMETHOD(device_detach,        skc_detach),
 267         DEVMETHOD(device_shutdown,      skc_shutdown),
 268
 269         /* bus interface */
 270         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 271         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 272
 273         { 0, 0 }
 274 };
 275
 276 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc));
 277 static devclass_t skc_devclass;
 278
 279 static device_method_t sk_methods[] = {
 280         /* Device interface */
 281         DEVMETHOD(device_probe,         sk_probe),
 282         DEVMETHOD(device_attach,        sk_attach),
 283         DEVMETHOD(device_detach,        sk_detach),
 284         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 285
 286         /* bus interface */
 287         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 288         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 289
 290         /* MII interface */
 291         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 292         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 293         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 294
 295         { 0, 0 }
 296 };
 297
 298 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc));
 299 static devclass_t sk_devclass;
 300
 301 DECLARE_DUMMY_MODULE(if_sk);
 302 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, NULL, NULL);
 303 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, NULL, NULL);
 304 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, NULL, NULL);
 305
 306 static __inline uint32_t
 307 sk_win_read_4(struct sk_softc *sc, uint32_t reg)
 308 {
 309         return CSR_READ_4(sc, reg);
 310 }
 311
 312 static __inline uint16_t
 313 sk_win_read_2(struct sk_softc *sc, uint32_t reg)
 314 {
 315         return CSR_READ_2(sc, reg);
 316 }
 317
 318 static __inline uint8_t
 319 sk_win_read_1(struct sk_softc *sc, uint32_t reg)
 320 {
 321         return CSR_READ_1(sc, reg);
 322 }
 323
 324 static __inline void
 325 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x)
 326 {
 327         CSR_WRITE_4(sc, reg, x);
 328 }
 329
 330 static __inline void
 331 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x)
 332 {
 333         CSR_WRITE_2(sc, reg, x);
 334 }
 335
 336 static __inline void
 337 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x)
 338 {
 339         CSR_WRITE_1(sc, reg, x);
 340 }
 341
 342 static __inline int
 343 sk_newbuf(struct sk_if_softc *sc_if, int idx, int wait)
 344 {
 345         int ret;
 346
 347         if (sc_if->sk_use_jumbo)
 348                 ret = sk_newbuf_jumbo(sc_if, idx, wait);
 349         else
 350                 ret = sk_newbuf_std(sc_if, idx, wait);
 351         return ret;
 352 }
 353
 354 static int
 355 sk_miibus_readreg(device_t dev, int phy, int reg)
 356 {
 357         struct sk_if_softc *sc_if = device_get_softc(dev);
 358
 359         if (SK_IS_GENESIS(sc_if->sk_softc))
 360                 return sk_xmac_miibus_readreg(sc_if, phy, reg);
 361         else
 362                 return sk_marv_miibus_readreg(sc_if, phy, reg);
 363 }
 364
 365 static int
 366 sk_miibus_writereg(device_t dev, int phy, int reg, int val)
 367 {
 368         struct sk_if_softc *sc_if = device_get_softc(dev);
 369
 370         if (SK_IS_GENESIS(sc_if->sk_softc))
 371                 return sk_xmac_miibus_writereg(sc_if, phy, reg, val);
 372         else
 373                 return sk_marv_miibus_writereg(sc_if, phy, reg, val);
 374 }
 375
 376 static void
 377 sk_miibus_statchg(device_t dev)
 378 {
 379         struct sk_if_softc *sc_if = device_get_softc(dev);
 380
 381         if (SK_IS_GENESIS(sc_if->sk_softc))
 382                 sk_xmac_miibus_statchg(sc_if);
 383         else
 384                 sk_marv_miibus_statchg(sc_if);
 385 }
 386
 387 static int
 388 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
 389 {
 390         int i;
 391
 392         DPRINTFN(9, ("sk_xmac_miibus_readreg\n"));
 393
 394         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
 395                 return(0);
 396
 397         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 398         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 399         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 400                 for (i = 0; i < SK_TIMEOUT; i++) {
 401                         DELAY(1);
 402                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 403                             XM_MMUCMD_PHYDATARDY)
 404                                 break;
 405                 }
 406
 407                 if (i == SK_TIMEOUT) {
 408                         if_printf(&sc_if->arpcom.ac_if,
 409                                   "phy failed to come ready\n");
 410                         return(0);
 411                 }
 412         }
 413         DELAY(1);
 414         return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
 415 }
 416
 417 static int
 418 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
 419 {
 420         int i;
 421
 422         DPRINTFN(9, ("sk_xmac_miibus_writereg\n"));
 423
 424         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 425         for (i = 0; i < SK_TIMEOUT; i++) {
 426                 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
 427                         break;
 428         }
 429
 430         if (i == SK_TIMEOUT) {
 431                 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
 432                 return(ETIMEDOUT);
 433         }
 434
 435         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 436         for (i = 0; i < SK_TIMEOUT; i++) {
 437                 DELAY(1);
 438                 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
 439                         break;
 440         }
 441
 442         if (i == SK_TIMEOUT)
 443                 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
 444         return(0);
 445 }
 446
 447 static void
 448 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if)
 449 {
 450         struct mii_data *mii;
 451
 452         mii = device_get_softc(sc_if->sk_miibus);
 453         DPRINTFN(9, ("sk_xmac_miibus_statchg\n"));
 454
 455         /*
 456          * If this is a GMII PHY, manually set the XMAC's
 457          * duplex mode accordingly.
 458          */
 459         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 460                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
 461                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 462                 else
 463                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 464         }
 465 }
 466
 467 static int
 468 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
 469 {
 470         uint16_t val;
 471         int i;
 472
 473         if (phy != 0 ||
 474             (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 475              sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
 476                 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n",
 477                              phy, reg));
 478                 return(0);
 479         }
 480
 481         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 482                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 483
 484         for (i = 0; i < SK_TIMEOUT; i++) {
 485                 DELAY(1);
 486                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 487                 if (val & YU_SMICR_READ_VALID)
 488                         break;
 489         }
 490
 491         if (i == SK_TIMEOUT) {
 492                 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
 493                 return(0);
 494         }
 495
 496         DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i,
 497                      SK_TIMEOUT));
 498
 499         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 500
 501         DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n",
 502                      phy, reg, val));
 503
 504         return(val);
 505 }
 506
 507 static int
 508 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
 509 {
 510         int i;
 511
 512         DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n",
 513                      phy, reg, val));
 514
 515         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 516         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 517                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 518
 519         for (i = 0; i < SK_TIMEOUT; i++) {
 520                 DELAY(1);
 521                 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
 522                         break;
 523         }
 524
 525         if (i == SK_TIMEOUT)
 526                 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
 527
 528         return(0);
 529 }
 530
 531 static void
 532 sk_marv_miibus_statchg(struct sk_if_softc *sc_if)
 533 {
 534         DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n",
 535                      SK_YU_READ_2(sc_if, YUKON_GPCR)));
 536 }
 537
 538 #define HASH_BITS       6
 539
 540 static uint32_t
 541 sk_xmac_hash(caddr_t addr)
 542 {
 543         uint32_t crc;
 544
 545         crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
 546         return (~crc & ((1 << HASH_BITS) - 1));
 547 }
 548
 549 static uint32_t
 550 sk_yukon_hash(caddr_t addr)
 551 {
 552         uint32_t crc;
 553
 554         crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
 555         return (crc & ((1 << HASH_BITS) - 1));
 556 }
 557
 558 static void
 559 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot)
 560 {
 561         int base;
 562
 563         base = XM_RXFILT_ENTRY(slot);
 564
 565         SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0]));
 566         SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2]));
 567         SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4]));
 568 }
 569
 570 static void
 571 sk_setmulti(struct sk_if_softc *sc_if)
 572 {
 573         struct sk_softc *sc = sc_if->sk_softc;
 574         struct ifnet *ifp = &sc_if->arpcom.ac_if;
 575         uint32_t hashes[2] = { 0, 0 };
 576         int h = 0, i;
 577         struct ifmultiaddr *ifma;
 578         uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
 579
 580         /* First, zot all the existing filters. */
 581         switch(sc->sk_type) {
 582         case SK_GENESIS:
 583                 for (i = 1; i < XM_RXFILT_MAX; i++)
 584                         sk_setfilt(sc_if, (caddr_t)&dummy, i);
 585
 586                 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
 587                 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
 588                 break;
 589         case SK_YUKON:
 590         case SK_YUKON_LITE:
 591         case SK_YUKON_LP:
 592                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
 593                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
 594                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
 595                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
 596                 break;
 597         }
 598
 599         /* Now program new ones. */
 600         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 601                 hashes[0] = 0xFFFFFFFF;
 602                 hashes[1] = 0xFFFFFFFF;
 603         } else {
 604                 i = 1;
 605                 /* First find the tail of the list. */
 606                 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
 607                     ifma_link) {
 608                         caddr_t maddr;
 609
 610                         if (ifma->ifma_addr->sa_family != AF_LINK)
 611                                 continue;
 612
 613                         maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
 614
 615                         /*
 616                          * Program the first XM_RXFILT_MAX multicast groups
 617                          * into the perfect filter. For all others,
 618                          * use the hash table.
 619                          */
 620                         if (SK_IS_GENESIS(sc) && i < XM_RXFILT_MAX) {
 621                                 sk_setfilt(sc_if, maddr, i);
 622                                 i++;
 623                                 continue;
 624                         }
 625
 626                         switch(sc->sk_type) {
 627                         case SK_GENESIS:
 628                                 h = sk_xmac_hash(maddr);
 629                                 break;
 630
 631                         case SK_YUKON:
 632                         case SK_YUKON_LITE:
 633                         case SK_YUKON_LP:
 634                                 h = sk_yukon_hash(maddr);
 635                                 break;
 636                         }
 637                         if (h < 32)
 638                                 hashes[0] |= (1 << h);
 639                         else
 640                                 hashes[1] |= (1 << (h - 32));
 641                 }
 642         }
 643
 644         switch(sc->sk_type) {
 645         case SK_GENESIS:
 646                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
 647                                XM_MODE_RX_USE_PERFECT);
 648                 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
 649                 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
 650                 break;
 651         case SK_YUKON:
 652         case SK_YUKON_LITE:
 653         case SK_YUKON_LP:
 654                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 655                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 656                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 657                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 658                 break;
 659         }
 660 }
 661
 662 static void
 663 sk_setpromisc(struct sk_if_softc *sc_if)
 664 {
 665         struct sk_softc *sc = sc_if->sk_softc;
 666         struct ifnet *ifp = &sc_if->arpcom.ac_if;
 667
 668         switch(sc->sk_type) {
 669         case SK_GENESIS:
 670                 if (ifp->if_flags & IFF_PROMISC)
 671                         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 672                 else
 673                         SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 674                 break;
 675         case SK_YUKON:
 676         case SK_YUKON_LITE:
 677         case SK_YUKON_LP:
 678                 if (ifp->if_flags & IFF_PROMISC) {
 679                         SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
 680                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 681                 } else {
 682                         SK_YU_SETBIT_2(sc_if, YUKON_RCR,
 683                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 684                 }
 685                 break;
 686         }
 687 }
 688
 689 static int
 690 sk_init_rx_ring(struct sk_if_softc *sc_if)
 691 {
 692         struct sk_chain_data *cd = &sc_if->sk_cdata;
 693         struct sk_ring_data *rd = &sc_if->sk_rdata;
 694         int i, nexti, error;
 695
 696         bzero(rd->sk_rx_ring, SK_RX_RING_SIZE);
 697
 698         for (i = 0; i < SK_RX_RING_CNT; i++) {
 699                 bus_addr_t paddr;
 700
 701                 if (i == (SK_RX_RING_CNT - 1))
 702                         nexti = 0;
 703                 else
 704                         nexti = i + 1;
 705                 paddr = rd->sk_rx_ring_paddr +
 706                         (nexti * sizeof(struct sk_rx_desc));
 707
 708                 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(paddr));
 709                 rd->sk_rx_ring[i].sk_csum1_start = htole16(ETHER_HDR_LEN);
 710                 rd->sk_rx_ring[i].sk_csum2_start =
 711                         htole16(ETHER_HDR_LEN + sizeof(struct ip));
 712
 713                 error = sk_newbuf(sc_if, i, 1);
 714                 if (error) {
 715                         if_printf(&sc_if->arpcom.ac_if,
 716                                   "failed alloc of %dth mbuf\n", i);
 717                         return error;
 718                 }
 719         }
 720
 721         cd->sk_rx_prod = 0;
 722         cd->sk_rx_cons = 0;
 723
 724         return (0);
 725 }
 726
 727 static int
 728 sk_init_tx_ring(struct sk_if_softc *sc_if)
 729 {
 730         struct sk_ring_data *rd = &sc_if->sk_rdata;
 731         int i, nexti;
 732
 733         bzero(rd->sk_tx_ring, SK_TX_RING_SIZE);
 734
 735         for (i = 0; i < SK_TX_RING_CNT; i++) {
 736                 bus_addr_t paddr;
 737
 738                 if (i == (SK_TX_RING_CNT - 1))
 739                         nexti = 0;
 740                 else
 741                         nexti = i + 1;
 742                 paddr = rd->sk_tx_ring_paddr +
 743                         (nexti * sizeof(struct sk_tx_desc));
 744
 745                 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(paddr));
 746         }
 747
 748         sc_if->sk_cdata.sk_tx_prod = 0;
 749         sc_if->sk_cdata.sk_tx_cons = 0;
 750         sc_if->sk_cdata.sk_tx_cnt = 0;
 751
 752         return (0);
 753 }
 754
 755 static int
 756 sk_newbuf_jumbo(struct sk_if_softc *sc_if, int idx, int wait)
 757 {
 758         struct sk_jpool_entry *entry;
 759         struct mbuf *m_new = NULL;
 760         struct sk_rx_desc *r;
 761         bus_addr_t paddr;
 762
 763         KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
 764
 765         MGETHDR(m_new, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 766         if (m_new == NULL)
 767                 return ENOBUFS;
 768
 769         /* Allocate the jumbo buffer */
 770         entry = sk_jalloc(sc_if);
 771         if (entry == NULL) {
 772                 m_freem(m_new);
 773                 DPRINTFN(1, ("%s jumbo allocation failed -- packet "
 774                     "dropped!\n", sc_if->arpcom.ac_if.if_xname));
 775                 return ENOBUFS;
 776         }
 777
 778         m_new->m_ext.ext_arg = entry;
 779         m_new->m_ext.ext_buf = entry->buf;
 780         m_new->m_ext.ext_free = sk_jfree;
 781         m_new->m_ext.ext_ref = sk_jref;
 782         m_new->m_ext.ext_size = SK_JLEN;
 783
 784         m_new->m_flags |= M_EXT;
 785
 786         m_new->m_data = m_new->m_ext.ext_buf;
 787         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 788
 789         paddr = entry->paddr;
 790
 791         /*
 792          * Adjust alignment so packet payload begins on a
 793          * longword boundary. Mandatory for Alpha, useful on
 794          * x86 too.
 795          */
 796         m_adj(m_new, ETHER_ALIGN);
 797         paddr += ETHER_ALIGN;
 798
 799         sc_if->sk_cdata.sk_rx_mbuf[idx] = m_new;
 800
 801         r = &sc_if->sk_rdata.sk_rx_ring[idx];
 802         r->sk_data_lo = htole32(SK_ADDR_LO(paddr));
 803         r->sk_data_hi = htole32(SK_ADDR_HI(paddr));
 804         r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
 805
 806         return 0;
 807 }
 808
 809 static int
 810 sk_newbuf_std(struct sk_if_softc *sc_if, int idx, int wait)
 811 {
 812         struct mbuf *m_new = NULL;
 813         struct sk_chain_data *cd = &sc_if->sk_cdata;
 814         struct sk_rx_desc *r;
 815         bus_dma_segment_t seg;
 816         bus_dmamap_t map;
 817         int error, nseg;
 818
 819         KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
 820
 821         m_new = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 822         if (m_new == NULL)
 823                 return ENOBUFS;
 824
 825         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 826
 827         /*
 828          * Adjust alignment so packet payload begins on a
 829          * longword boundary. Mandatory for Alpha, useful on
 830          * x86 too.
 831          */
 832         m_adj(m_new, ETHER_ALIGN);
 833
 834         error = bus_dmamap_load_mbuf_segment(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp,
 835                         m_new, &seg, 1, &nseg, BUS_DMA_NOWAIT);
 836         if (error) {
 837                 m_freem(m_new);
 838                 if (wait) {
 839                         if_printf(&sc_if->arpcom.ac_if,
 840                                   "could not map RX mbuf\n");
 841                 }
 842                 return error;
 843         }
 844
 845         /* Unload originally mapped mbuf */
 846         if (cd->sk_rx_mbuf[idx] != NULL) {
 847                 bus_dmamap_sync(cd->sk_rx_dtag, cd->sk_rx_dmap[idx],
 848                                 BUS_DMASYNC_POSTREAD);
 849                 bus_dmamap_unload(cd->sk_rx_dtag, cd->sk_rx_dmap[idx]);
 850         }
 851
 852         /* Switch DMA map with tmp DMA map */
 853         map = cd->sk_rx_dmap_tmp;
 854         cd->sk_rx_dmap_tmp = cd->sk_rx_dmap[idx];
 855         cd->sk_rx_dmap[idx] = map;
 856
 857         cd->sk_rx_mbuf[idx] = m_new;
 858
 859         r = &sc_if->sk_rdata.sk_rx_ring[idx];
 860         r->sk_data_lo = htole32(SK_ADDR_LO(seg.ds_addr));
 861         r->sk_data_hi = htole32(SK_ADDR_HI(seg.ds_addr));
 862         r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
 863
 864         return 0;
 865 }
 866
 867 /*
 868  * Allocate a jumbo buffer.
 869  */
 870 struct sk_jpool_entry *
 871 sk_jalloc(struct sk_if_softc *sc_if)
 872 {
 873         struct sk_chain_data *cd = &sc_if->sk_cdata;
 874         struct sk_jpool_entry *entry;
 875
 876         lwkt_serialize_enter(&cd->sk_jpool_serializer);
 877
 878         entry = SLIST_FIRST(&cd->sk_jpool_free_ent);
 879         if (entry != NULL) {
 880                 SLIST_REMOVE_HEAD(&cd->sk_jpool_free_ent, entry_next);
 881                 entry->inuse = 1;
 882         } else {
 883                 DPRINTF(("no free jumbo buffer\n"));
 884         }
 885
 886         lwkt_serialize_exit(&cd->sk_jpool_serializer);
 887         return entry;
 888 }
 889
 890 /*
 891  * Release a jumbo buffer.
 892  */
 893 void
 894 sk_jfree(void *arg)
 895 {
 896         struct sk_jpool_entry *entry = arg;
 897         struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
 898
 899         if (&cd->sk_jpool_ent[entry->slot] != entry)
 900                 panic("%s: free wrong jumbo buffer", __func__);
 901         else if (entry->inuse == 0)
 902                 panic("%s: jumbo buffer already freed", __func__);
 903
 904         lwkt_serialize_enter(&cd->sk_jpool_serializer);
 905
 906         atomic_subtract_int(&entry->inuse, 1);
 907         if (entry->inuse == 0)
 908                 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
 909
 910         lwkt_serialize_exit(&cd->sk_jpool_serializer);
 911 }
 912
 913 static void
 914 sk_jref(void *arg)
 915 {
 916         struct sk_jpool_entry *entry = arg;
 917         struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
 918
 919         if (&cd->sk_jpool_ent[entry->slot] != entry)
 920                 panic("%s: free wrong jumbo buffer", __func__);
 921         else if (entry->inuse == 0)
 922                 panic("%s: jumbo buffer already freed", __func__);
 923
 924         atomic_add_int(&entry->inuse, 1);
 925 }
 926
 927 /*
 928  * Set media options.
 929  */
 930 static int
 931 sk_ifmedia_upd(struct ifnet *ifp)
 932 {
 933         struct sk_if_softc *sc_if = ifp->if_softc;
 934         struct mii_data *mii;
 935
 936         mii = device_get_softc(sc_if->sk_miibus);
 937         sk_init(sc_if);
 938         mii_mediachg(mii);
 939
 940         return(0);
 941 }
 942
 943 /*
 944  * Report current media status.
 945  */
 946 static void
 947 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 948 {
 949         struct sk_if_softc *sc_if;
 950         struct mii_data *mii;
 951
 952         sc_if = ifp->if_softc;
 953         mii = device_get_softc(sc_if->sk_miibus);
 954
 955         mii_pollstat(mii);
 956         ifmr->ifm_active = mii->mii_media_active;
 957         ifmr->ifm_status = mii->mii_media_status;
 958 }
 959
 960 static int
 961 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 962 {
 963         struct sk_if_softc *sc_if = ifp->if_softc;
 964         struct ifreq *ifr = (struct ifreq *)data;
 965         struct mii_data *mii;
 966         int error = 0;
 967
 968         ASSERT_SERIALIZED(ifp->if_serializer);
 969
 970         switch(command) {
 971         case SIOCSIFMTU:
 972                 if (ifr->ifr_mtu > SK_JUMBO_MTU)
 973                         error = EINVAL;
 974                 else {
 975                         ifp->if_mtu = ifr->ifr_mtu;
 976                         ifp->if_flags &= ~IFF_RUNNING;
 977                         sk_init(sc_if);
 978                 }
 979                 break;
 980         case SIOCSIFFLAGS:
 981                 if (ifp->if_flags & IFF_UP) {
 982                         if (ifp->if_flags & IFF_RUNNING) {
 983                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
 984                                     & IFF_PROMISC) {
 985                                         sk_setpromisc(sc_if);
 986                                         sk_setmulti(sc_if);
 987                                 }
 988                         } else
 989                                 sk_init(sc_if);
 990                 } else {
 991                         if (ifp->if_flags & IFF_RUNNING)
 992                                 sk_stop(sc_if);
 993                 }
 994                 sc_if->sk_if_flags = ifp->if_flags;
 995                 break;
 996         case SIOCADDMULTI:
 997         case SIOCDELMULTI:
 998                 sk_setmulti(sc_if);
 999                 break;
1000         case SIOCGIFMEDIA:
1001         case SIOCSIFMEDIA:
1002                 mii = device_get_softc(sc_if->sk_miibus);
1003                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1004                 break;
1005         default:
1006                 error = ether_ioctl(ifp, command, data);
1007                 break;
1008         }
1009
1010         return(error);
1011 }
1012
1013 /*
1014  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1015  * IDs against our list and return a device name if we find a match.
1016  */
1017 static int
1018 skc_probe(device_t dev)
1019 {
1020         const struct skc_type *t;
1021         uint16_t vid, did;
1022
1023         vid = pci_get_vendor(dev);
1024         did = pci_get_device(dev);
1025
1026         /*
1027          * Only attach to rev.2 of the Linksys EG1032 adapter.
1028          * Rev.3 is supported by re(4).
1029          */
1030         if (vid == PCI_VENDOR_LINKSYS &&
1031             did == PCI_PRODUCT_LINKSYS_EG1032 &&
1032             pci_get_subdevice(dev) != SUBDEVICEID_LINKSYS_EG1032_REV2)
1033                 return ENXIO;
1034
1035         for (t = skc_devs; t->skc_name != NULL; t++) {
1036                 if (vid == t->skc_vid && did == t->skc_did) {
1037                         device_set_desc(dev, t->skc_name);
1038                         return 0;
1039                 }
1040         }
1041         return ENXIO;
1042 }
1043
1044 /*
1045  * Force the GEnesis into reset, then bring it out of reset.
1046  */
1047 static void
1048 sk_reset(struct sk_softc *sc)
1049 {
1050         DPRINTFN(2, ("sk_reset\n"));
1051
1052         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1053         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1054         if (SK_IS_YUKON(sc))
1055                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1056
1057         DELAY(1000);
1058         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1059         DELAY(2);
1060         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1061         if (SK_IS_YUKON(sc))
1062                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1063
1064         DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR)));
1065         DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n",
1066                      CSR_READ_2(sc, SK_LINK_CTRL)));
1067
1068         if (SK_IS_GENESIS(sc)) {
1069                 /* Configure packet arbiter */
1070                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1071                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1072                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1073                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1074                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1075         }
1076
1077         /* Enable RAM interface */
1078         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1079
1080         /*
1081          * Configure interrupt moderation. The moderation timer
1082          * defers interrupts specified in the interrupt moderation
1083          * timer mask based on the timeout specified in the interrupt
1084          * moderation timer init register. Each bit in the timer
1085          * register represents one tick, so to specify a timeout in
1086          * microseconds, we have to multiply by the correct number of
1087          * ticks-per-microsecond.
1088          */
1089         KKASSERT(sc->sk_imtimer_ticks != 0 && sc->sk_imtime != 0);
1090         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc, sc->sk_imtime));
1091         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1092             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1093         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1094 }
1095
1096 static int
1097 sk_probe(device_t dev)
1098 {
1099         struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1100         const char *revstr = "", *name = NULL;
1101         char devname[80];
1102
1103         switch (sc->sk_type) {
1104         case SK_GENESIS:
1105                 name = "SysKonnect GEnesis";
1106                 break;
1107         case SK_YUKON:
1108                 name = "Marvell Yukon";
1109                 break;
1110         case SK_YUKON_LITE:
1111                 name = "Marvell Yukon Lite";
1112                 switch (sc->sk_rev) {
1113                 case SK_YUKON_LITE_REV_A0:
1114                         revstr = " rev.A0";
1115                         break;
1116                 case SK_YUKON_LITE_REV_A1:
1117                         revstr = " rev.A1";
1118                         break;
1119                 case SK_YUKON_LITE_REV_A3:
1120                         revstr = " rev.A3";
1121                         break;
1122                 }
1123                 break;
1124         case SK_YUKON_LP:
1125                 name = "Marvell Yukon LP";
1126                 break;
1127         default:
1128                 return ENXIO;
1129         }
1130
1131         ksnprintf(devname, sizeof(devname), "%s%s (0x%x)",
1132                  name, revstr, sc->sk_rev);
1133         device_set_desc_copy(dev, devname);
1134         return 0;
1135 }
1136
1137 /*
1138  * Each XMAC chip is attached as a separate logical IP interface.
1139  * Single port cards will have only one logical interface of course.
1140  */
1141 static int
1142 sk_attach(device_t dev)
1143 {
1144         struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1145         struct sk_if_softc *sc_if = device_get_softc(dev);
1146         struct ifnet *ifp = &sc_if->arpcom.ac_if;
1147         int i, error, if_attached = 0;
1148
1149         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1150
1151         sc_if->sk_port = *(int *)device_get_ivars(dev);
1152         KKASSERT(sc_if->sk_port == SK_PORT_A || sc_if->sk_port == SK_PORT_B);
1153
1154         sc_if->sk_softc = sc;
1155         sc->sk_if[sc_if->sk_port] = sc_if;
1156
1157         kfree(device_get_ivars(dev), M_DEVBUF);
1158         device_set_ivars(dev, NULL);
1159
1160         if (sc_if->sk_port == SK_PORT_A)
1161                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1162         if (sc_if->sk_port == SK_PORT_B)
1163                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1164
1165         DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port));
1166
1167         /*
1168          * Get station address for this interface. Note that
1169          * dual port cards actually come with three station
1170          * addresses: one for each port, plus an extra. The
1171          * extra one is used by the SysKonnect driver software
1172          * as a 'virtual' station address for when both ports
1173          * are operating in failover mode. Currently we don't
1174          * use this extra address.
1175          */
1176         for (i = 0; i < ETHER_ADDR_LEN; i++) {
1177                 /* XXX */
1178                 sc_if->arpcom.ac_enaddr[i] =
1179                     sk_win_read_1(sc, SK_MAC0_0 + (sc_if->sk_port * 8) + i);
1180         }
1181
1182         /*
1183          * Set up RAM buffer addresses. The NIC will have a certain
1184          * amount of SRAM on it, somewhere between 512K and 2MB. We
1185          * need to divide this up a) between the transmitter and
1186          * receiver and b) between the two XMACs, if this is a
1187          * dual port NIC. Our algorithm is to divide up the memory
1188          * evenly so that everyone gets a fair share.
1189          */
1190         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1191                 uint32_t chunk, val;
1192
1193                 chunk = sc->sk_ramsize / 2;
1194                 val = sc->sk_rboff / sizeof(uint64_t);
1195                 sc_if->sk_rx_ramstart = val;
1196                 val += (chunk / sizeof(uint64_t));
1197                 sc_if->sk_rx_ramend = val - 1;
1198                 sc_if->sk_tx_ramstart = val;
1199                 val += (chunk / sizeof(uint64_t));
1200                 sc_if->sk_tx_ramend = val - 1;
1201         } else {
1202                 uint32_t chunk, val;
1203
1204                 chunk = sc->sk_ramsize / 4;
1205                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1206                     sizeof(uint64_t);
1207                 sc_if->sk_rx_ramstart = val;
1208                 val += (chunk / sizeof(uint64_t));
1209                 sc_if->sk_rx_ramend = val - 1;
1210                 sc_if->sk_tx_ramstart = val;
1211                 val += (chunk / sizeof(uint64_t));
1212                 sc_if->sk_tx_ramend = val - 1;
1213         }
1214
1215         DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n"
1216                      "           tx_ramstart=%#x tx_ramend=%#x\n",
1217                      sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
1218                      sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
1219
1220         /* Read and save PHY type */
1221         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1222
1223         /* Set PHY address */
1224         if (SK_IS_GENESIS(sc)) {
1225                 switch (sc_if->sk_phytype) {
1226                 case SK_PHYTYPE_XMAC:
1227                         sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1228                         break;
1229                 case SK_PHYTYPE_BCOM:
1230                         sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1231                         break;
1232                 default:
1233                         device_printf(dev, "unsupported PHY type: %d\n",
1234                             sc_if->sk_phytype);
1235                         error = ENXIO;
1236                         goto fail;
1237                 }
1238         }
1239
1240         if (SK_IS_YUKON(sc)) {
1241                 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1242                     sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) {
1243                         /* not initialized, punt */
1244                         sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1245                         sc->sk_coppertype = 1;
1246                 }
1247
1248                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1249
1250                 if (!(sc->sk_coppertype))
1251                         sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1252         }
1253
1254         error = sk_dma_alloc(dev);
1255         if (error)
1256                 goto fail;
1257
1258         ifp->if_softc = sc_if;
1259         ifp->if_mtu = ETHERMTU;
1260         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1261         ifp->if_ioctl = sk_ioctl;
1262         ifp->if_start = sk_start;
1263         ifp->if_watchdog = sk_watchdog;
1264         ifp->if_init = sk_init;
1265         ifp->if_baudrate = 1000000000;
1266         ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1);
1267         ifq_set_ready(&ifp->if_snd);
1268
1269         ifp->if_capabilities = IFCAP_VLAN_MTU;
1270
1271         /* Don't use jumbo buffers by default */
1272         sc_if->sk_use_jumbo = 0;
1273
1274         /*
1275          * Call MI attach routines.
1276          *
1277          * NOTE:
1278          * This must be done before following sk_init_xxx(), in which
1279          * if_multiaddrs will be used.
1280          */
1281         ether_ifattach(ifp, sc_if->arpcom.ac_enaddr, &sc->sk_serializer);
1282         if_attached = 1;
1283
1284         /*
1285          * Do miibus setup.
1286          */
1287         switch (sc->sk_type) {
1288         case SK_GENESIS:
1289                 sk_init_xmac(sc_if);
1290                 break;
1291         case SK_YUKON:
1292         case SK_YUKON_LITE:
1293         case SK_YUKON_LP:
1294                 sk_init_yukon(sc_if);
1295                 break;
1296         default:
1297                 device_printf(dev, "unknown device type %d\n", sc->sk_type);
1298                 error = ENXIO;
1299                 goto fail;
1300         }
1301
1302         DPRINTFN(2, ("sk_attach: 1\n"));
1303
1304         error = mii_phy_probe(dev, &sc_if->sk_miibus,
1305                               sk_ifmedia_upd, sk_ifmedia_sts);
1306         if (error) {
1307                 device_printf(dev, "no PHY found!\n");
1308                 goto fail;
1309         }
1310
1311         callout_init(&sc_if->sk_tick_timer);
1312
1313         DPRINTFN(2, ("sk_attach: end\n"));
1314         return 0;
1315 fail:
1316         if (if_attached)
1317                 ether_ifdetach(ifp);
1318         sk_detach(dev);
1319         sc->sk_if[sc_if->sk_port] = NULL;
1320         return error;
1321 }
1322
1323 /*
1324  * Attach the interface. Allocate softc structures, do ifmedia
1325  * setup and ethernet/BPF attach.
1326  */
1327 static int
1328 skc_attach(device_t dev)
1329 {
1330         struct sk_softc *sc = device_get_softc(dev);
1331         uint8_t skrs;
1332         int *port;
1333         int error, cpuid;
1334
1335         DPRINTFN(2, ("begin skc_attach\n"));
1336
1337         sc->sk_dev = dev;
1338         lwkt_serialize_init(&sc->sk_serializer);
1339
1340 #ifndef BURN_BRIDGES
1341         /*
1342          * Handle power management nonsense.
1343          */
1344         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1345                 uint32_t iobase, membase, irq;
1346
1347                 /* Save important PCI config data. */
1348                 iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1349                 membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1350                 irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1351
1352                 /* Reset the power state. */
1353                 device_printf(dev, "chip is in D%d power mode "
1354                               "-- setting to D0\n", pci_get_powerstate(dev));
1355
1356                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1357
1358                 /* Restore PCI config data. */
1359                 pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1360                 pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1361                 pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1362         }
1363 #endif  /* BURN_BRIDGES */
1364
1365         /*
1366          * Map control/status registers.
1367          */
1368         pci_enable_busmaster(dev);
1369
1370         sc->sk_res_rid = SK_PCI_LOMEM;
1371         sc->sk_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1372                                             &sc->sk_res_rid, RF_ACTIVE);
1373         if (sc->sk_res == NULL) {
1374                 device_printf(dev, "couldn't map memory\n");
1375                 error = ENXIO;
1376                 goto fail;
1377         }
1378         sc->sk_btag = rman_get_bustag(sc->sk_res);
1379         sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1380
1381         sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1382         sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
1383
1384         /* Bail out here if chip is not recognized */
1385         if (!SK_IS_GENESIS(sc) && !SK_IS_YUKON(sc)) {
1386                 device_printf(dev, "unknown chip type: %d\n", sc->sk_type);
1387                 error = ENXIO;
1388                 goto fail;
1389         }
1390
1391         DPRINTFN(2, ("skc_attach: allocate interrupt\n"));
1392
1393         /* Allocate interrupt */
1394         sc->sk_irq_rid = 0;
1395         sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sk_irq_rid,
1396                                             RF_SHAREABLE | RF_ACTIVE);
1397         if (sc->sk_irq == NULL) {
1398                 device_printf(dev, "couldn't map interrupt\n");
1399                 error = ENXIO;
1400                 goto fail;
1401         }
1402
1403         switch (sc->sk_type) {
1404         case SK_GENESIS:
1405                 sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS;
1406                 break;
1407         default:
1408                 sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
1409                 break;
1410         }
1411         sc->sk_imtime = skc_imtime;
1412
1413         /* Reset the adapter. */
1414         sk_reset(sc);
1415
1416         skrs = sk_win_read_1(sc, SK_EPROM0);
1417         if (SK_IS_GENESIS(sc)) {
1418                 /* Read and save RAM size and RAMbuffer offset */
1419                 switch(skrs) {
1420                 case SK_RAMSIZE_512K_64:
1421                         sc->sk_ramsize = 0x80000;
1422                         sc->sk_rboff = SK_RBOFF_0;
1423                         break;
1424                 case SK_RAMSIZE_1024K_64:
1425                         sc->sk_ramsize = 0x100000;
1426                         sc->sk_rboff = SK_RBOFF_80000;
1427                         break;
1428                 case SK_RAMSIZE_1024K_128:
1429                         sc->sk_ramsize = 0x100000;
1430                         sc->sk_rboff = SK_RBOFF_0;
1431                         break;
1432                 case SK_RAMSIZE_2048K_128:
1433                         sc->sk_ramsize = 0x200000;
1434                         sc->sk_rboff = SK_RBOFF_0;
1435                         break;
1436                 default:
1437                         device_printf(dev, "unknown ram size: %d\n", skrs);
1438                         error = ENXIO;
1439                         goto fail;
1440                 }
1441         } else {
1442                 if (skrs == 0x00)
1443                         sc->sk_ramsize = 0x20000;
1444                 else
1445                         sc->sk_ramsize = skrs * (1<<12);
1446                 sc->sk_rboff = SK_RBOFF_0;
1447         }
1448
1449         DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n",
1450                      sc->sk_ramsize, sc->sk_ramsize / 1024,
1451                      sc->sk_rboff));
1452
1453         /* Read and save physical media type */
1454         sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1455
1456         if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1457                 sc->sk_coppertype = 1;
1458         else
1459                 sc->sk_coppertype = 0;
1460
1461         /* Yukon Lite Rev A0 needs special test, from sk98lin driver */
1462         if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1463                 uint32_t flashaddr;
1464                 uint8_t testbyte;
1465
1466                 flashaddr = sk_win_read_4(sc, SK_EP_ADDR);
1467
1468                 /* Test Flash-Address Register */
1469                 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff);
1470                 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3);
1471
1472                 if (testbyte != 0) {
1473                         /* This is a Yukon Lite Rev A0 */
1474                         sc->sk_type = SK_YUKON_LITE;
1475                         sc->sk_rev = SK_YUKON_LITE_REV_A0;
1476                         /* Restore Flash-Address Register */
1477                         sk_win_write_4(sc, SK_EP_ADDR, flashaddr);
1478                 }
1479         }
1480
1481         /*
1482          * Create sysctl nodes.
1483          */
1484         sysctl_ctx_init(&sc->sk_sysctl_ctx);
1485         sc->sk_sysctl_tree = SYSCTL_ADD_NODE(&sc->sk_sysctl_ctx,
1486                                              SYSCTL_STATIC_CHILDREN(_hw),
1487                                              OID_AUTO,
1488                                              device_get_nameunit(dev),
1489                                              CTLFLAG_RD, 0, "");
1490         if (sc->sk_sysctl_tree == NULL) {
1491                 device_printf(dev, "can't add sysctl node\n");
1492                 error = ENXIO;
1493                 goto fail;
1494         }
1495         SYSCTL_ADD_PROC(&sc->sk_sysctl_ctx,
1496                         SYSCTL_CHILDREN(sc->sk_sysctl_tree),
1497                         OID_AUTO, "imtime", CTLTYPE_INT | CTLFLAG_RW,
1498                         sc, 0, skc_sysctl_imtime, "I",
1499                         "Interrupt moderation time (usec).");
1500
1501         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1502         port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1503         *port = SK_PORT_A;
1504         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1505
1506         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1507                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1508                 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1509                 *port = SK_PORT_B;
1510                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1511         }
1512
1513         /* Turn on the 'driver is loaded' LED. */
1514         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1515
1516         bus_generic_attach(dev);
1517
1518         error = bus_setup_intr(dev, sc->sk_irq, INTR_MPSAFE, sk_intr, sc,
1519                                &sc->sk_intrhand, &sc->sk_serializer);
1520         if (error) {
1521                 device_printf(dev, "couldn't set up irq\n");
1522                 goto fail;
1523         }
1524
1525         cpuid = rman_get_cpuid(sc->sk_irq);
1526         if (sc->sk_if[0] != NULL)
1527                 ifq_set_cpuid(&sc->sk_if[0]->arpcom.ac_if.if_snd, cpuid);
1528         if (sc->sk_if[1] != NULL)
1529                 ifq_set_cpuid(&sc->sk_if[1]->arpcom.ac_if.if_snd, cpuid);
1530
1531         return 0;
1532 fail:
1533         skc_detach(dev);
1534         return error;
1535 }
1536
1537 static int
1538 sk_detach(device_t dev)
1539 {
1540         struct sk_if_softc *sc_if = device_get_softc(dev);
1541
1542         if (device_is_attached(dev)) {
1543                 struct sk_softc *sc = sc_if->sk_softc;
1544                 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1545
1546                 lwkt_serialize_enter(ifp->if_serializer);
1547
1548                 if (sc->sk_intrhand != NULL) {
1549                         if (sc->sk_if[SK_PORT_A] != NULL)
1550                                 sk_stop(sc->sk_if[SK_PORT_A]);
1551                         if (sc->sk_if[SK_PORT_B] != NULL)
1552                                 sk_stop(sc->sk_if[SK_PORT_B]);
1553
1554                         bus_teardown_intr(sc->sk_dev, sc->sk_irq,
1555                                           sc->sk_intrhand);
1556                         sc->sk_intrhand = NULL;
1557                 }
1558
1559                 lwkt_serialize_exit(ifp->if_serializer);
1560
1561                 ether_ifdetach(ifp);
1562         }
1563
1564         if (sc_if->sk_miibus != NULL)
1565                 device_delete_child(dev, sc_if->sk_miibus);
1566
1567         sk_dma_free(dev);
1568         return 0;
1569 }
1570
1571 static int
1572 skc_detach(device_t dev)
1573 {
1574         struct sk_softc *sc = device_get_softc(dev);
1575         int *port;
1576
1577 #ifdef INVARIANTS
1578         if (device_is_attached(dev)) {
1579                 KASSERT(sc->sk_intrhand == NULL,
1580                         ("intr has not been torn down yet"));
1581         }
1582 #endif
1583
1584         if (sc->sk_devs[SK_PORT_A] != NULL) {
1585                 port = device_get_ivars(sc->sk_devs[SK_PORT_A]);
1586                 if (port != NULL) {
1587                         kfree(port, M_DEVBUF);
1588                         device_set_ivars(sc->sk_devs[SK_PORT_A], NULL);
1589                 }
1590                 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1591         }
1592         if (sc->sk_devs[SK_PORT_B] != NULL) {
1593                 port = device_get_ivars(sc->sk_devs[SK_PORT_B]);
1594                 if (port != NULL) {
1595                         kfree(port, M_DEVBUF);
1596                         device_set_ivars(sc->sk_devs[SK_PORT_B], NULL);
1597                 }
1598                 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1599         }
1600
1601         if (sc->sk_irq != NULL) {
1602                 bus_release_resource(dev, SYS_RES_IRQ, sc->sk_irq_rid,
1603                                      sc->sk_irq);
1604         }
1605         if (sc->sk_res != NULL) {
1606                 bus_release_resource(dev, SYS_RES_MEMORY, sc->sk_res_rid,
1607                                      sc->sk_res);
1608         }
1609
1610         if (sc->sk_sysctl_tree != NULL)
1611                 sysctl_ctx_free(&sc->sk_sysctl_ctx);
1612
1613         return 0;
1614 }
1615
1616 static int
1617 sk_encap(struct sk_if_softc *sc_if, struct mbuf **m_head0, uint32_t *txidx)
1618 {
1619         struct sk_chain_data *cd = &sc_if->sk_cdata;
1620         struct sk_ring_data *rd = &sc_if->sk_rdata;
1621         struct sk_tx_desc *f = NULL;
1622         uint32_t frag, cur, sk_ctl;
1623         bus_dma_segment_t segs[SK_NTXSEG];
1624         bus_dmamap_t map;
1625         int i, error, maxsegs, nsegs;
1626
1627         DPRINTFN(2, ("sk_encap\n"));
1628
1629         maxsegs = SK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - SK_NDESC_RESERVE;
1630         KASSERT(maxsegs >= SK_NDESC_SPARE, ("not enough spare TX desc"));
1631         if (maxsegs > SK_NTXSEG)
1632                 maxsegs = SK_NTXSEG;
1633
1634         cur = frag = *txidx;
1635
1636 #ifdef SK_DEBUG
1637         if (skdebug >= 2)
1638                 sk_dump_mbuf(*m_head0);
1639 #endif
1640
1641         map = cd->sk_tx_dmap[*txidx];
1642
1643         error = bus_dmamap_load_mbuf_defrag(cd->sk_tx_dtag, map, m_head0,
1644                         segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1645         if (error) {
1646                 m_freem(*m_head0);
1647                 *m_head0 = NULL;
1648                 return error;
1649         }
1650
1651         DPRINTFN(2, ("sk_encap: nsegs=%d\n", nsegs));
1652
1653         /* Sync the DMA map. */
1654         bus_dmamap_sync(cd->sk_tx_dtag, map, BUS_DMASYNC_PREWRITE);
1655
1656         for (i = 0; i < nsegs; i++) {
1657                 f = &rd->sk_tx_ring[frag];
1658                 f->sk_data_lo = htole32(SK_ADDR_LO(segs[i].ds_addr));
1659                 f->sk_data_hi = htole32(SK_ADDR_HI(segs[i].ds_addr));
1660                 sk_ctl = segs[i].ds_len | SK_OPCODE_DEFAULT;
1661                 if (i == 0)
1662                         sk_ctl |= SK_TXCTL_FIRSTFRAG;
1663                 else
1664                         sk_ctl |= SK_TXCTL_OWN;
1665                 f->sk_ctl = htole32(sk_ctl);
1666                 cur = frag;
1667                 SK_INC(frag, SK_TX_RING_CNT);
1668         }
1669
1670         cd->sk_tx_mbuf[cur] = *m_head0;
1671         /* Switch DMA map */
1672         cd->sk_tx_dmap[*txidx] = cd->sk_tx_dmap[cur];
1673         cd->sk_tx_dmap[cur] = map;
1674
1675         rd->sk_tx_ring[cur].sk_ctl |=
1676                 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR);
1677         rd->sk_tx_ring[*txidx].sk_ctl |= htole32(SK_TXCTL_OWN);
1678
1679         sc_if->sk_cdata.sk_tx_cnt += nsegs;
1680
1681 #ifdef SK_DEBUG
1682         if (skdebug >= 2) {
1683                 struct sk_tx_desc *desc;
1684                 uint32_t idx;
1685
1686                 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) {
1687                         desc = &sc_if->sk_rdata->sk_tx_ring[idx];
1688                         sk_dump_txdesc(desc, idx);
1689                 }
1690         }
1691 #endif
1692
1693         *txidx = frag;
1694
1695         DPRINTFN(2, ("sk_encap: completed successfully\n"));
1696
1697         return (0);
1698 }
1699
1700 static void
1701 sk_start(struct ifnet *ifp)
1702 {
1703         struct sk_if_softc *sc_if = ifp->if_softc;
1704         struct sk_softc *sc = sc_if->sk_softc;
1705         uint32_t idx = sc_if->sk_cdata.sk_tx_prod;
1706         int trans = 0;
1707
1708         DPRINTFN(2, ("sk_start\n"));
1709
1710         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1711                 return;
1712
1713         while (sc_if->sk_cdata.sk_tx_mbuf[idx] == NULL) {
1714                 struct mbuf *m_head;
1715
1716                 if (SK_IS_OACTIVE(sc_if)) {
1717                         ifq_set_oactive(&ifp->if_snd);
1718                         break;
1719                 }
1720
1721                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1722                 if (m_head == NULL)
1723                         break;
1724
1725                 /*
1726                  * Pack the data into the transmit ring. If we
1727                  * don't have room, set the OACTIVE flag and wait
1728                  * for the NIC to drain the ring.
1729                  */
1730                 if (sk_encap(sc_if, &m_head, &idx)) {
1731                         if (sc_if->sk_cdata.sk_tx_cnt == 0) {
1732                                 continue;
1733                         } else {
1734                                 ifq_set_oactive(&ifp->if_snd);
1735                                 break;
1736                         }
1737                 }
1738
1739                 trans = 1;
1740                 BPF_MTAP(ifp, m_head);
1741         }
1742         if (!trans)
1743                 return;
1744
1745         /* Transmit */
1746         if (idx != sc_if->sk_cdata.sk_tx_prod) {
1747                 sc_if->sk_cdata.sk_tx_prod = idx;
1748                 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1749
1750                 /* Set a timeout in case the chip goes out to lunch. */
1751                 ifp->if_timer = 5;
1752         }
1753 }
1754
1755 static void
1756 sk_watchdog(struct ifnet *ifp)
1757 {
1758         struct sk_if_softc *sc_if = ifp->if_softc;
1759
1760         ASSERT_SERIALIZED(ifp->if_serializer);
1761         /*
1762          * Reclaim first as there is a possibility of losing Tx completion
1763          * interrupts.
1764          */
1765         sk_txeof(sc_if);
1766         if (sc_if->sk_cdata.sk_tx_cnt != 0) {
1767                 if_printf(&sc_if->arpcom.ac_if, "watchdog timeout\n");
1768                 ifp->if_oerrors++;
1769                 ifp->if_flags &= ~IFF_RUNNING;
1770                 sk_init(sc_if);
1771         }
1772 }
1773
1774 static void
1775 skc_shutdown(device_t dev)
1776 {
1777         struct sk_softc *sc = device_get_softc(dev);
1778
1779         DPRINTFN(2, ("sk_shutdown\n"));
1780
1781         lwkt_serialize_enter(&sc->sk_serializer);
1782
1783         /* Turn off the 'driver is loaded' LED. */
1784         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1785
1786         /*
1787          * Reset the GEnesis controller. Doing this should also
1788          * assert the resets on the attached XMAC(s).
1789          */
1790         sk_reset(sc);
1791
1792         lwkt_serialize_exit(&sc->sk_serializer);
1793 }
1794
1795 static __inline int
1796 sk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len)
1797 {
1798         if (sc->sk_type == SK_GENESIS) {
1799                 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
1800                     XM_RXSTAT_BYTES(stat) != len)
1801                         return (0);
1802         } else {
1803                 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
1804                     YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
1805                     YU_RXSTAT_JABBER)) != 0 ||
1806                     (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
1807                     YU_RXSTAT_BYTES(stat) != len)
1808                         return (0);
1809         }
1810
1811         return (1);
1812 }
1813
1814 static void
1815 sk_rxeof(struct sk_if_softc *sc_if)
1816 {
1817         struct sk_softc *sc = sc_if->sk_softc;
1818         struct ifnet *ifp = &sc_if->arpcom.ac_if;
1819         struct sk_chain_data *cd = &sc_if->sk_cdata;
1820         struct sk_ring_data *rd = &sc_if->sk_rdata;
1821         int i, max_frmlen;
1822
1823         DPRINTFN(2, ("sk_rxeof\n"));
1824
1825         i = cd->sk_rx_prod;
1826
1827         if (sc_if->sk_use_jumbo)
1828                 max_frmlen = SK_JUMBO_FRAMELEN;
1829         else
1830                 max_frmlen = ETHER_MAX_LEN;
1831
1832         for (;;) {
1833                 struct sk_rx_desc *cur_desc;
1834                 uint32_t rxstat, sk_ctl;
1835 #ifdef SK_RXCSUM
1836                 uint16_t csum1, csum2;
1837 #endif
1838                 int cur, total_len;
1839                 struct mbuf *m;
1840
1841                 cur = i;
1842                 cur_desc = &rd->sk_rx_ring[cur];
1843
1844                 sk_ctl = le32toh(cur_desc->sk_ctl);
1845                 if (sk_ctl & SK_RXCTL_OWN) {
1846                         /* Invalidate the descriptor -- it's not ready yet */
1847                         cd->sk_rx_prod = cur;
1848                         break;
1849                 }
1850
1851                 rxstat = le32toh(cur_desc->sk_xmac_rxstat);
1852                 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl));
1853
1854 #ifdef SK_RXCSUM
1855                 csum1 = le16toh(cur_desc->sk_csum1);
1856                 csum2 = le16toh(cur_desc->sk_csum2);
1857 #endif
1858
1859                 m = cd->sk_rx_mbuf[cur];
1860
1861                 /*
1862                  * Bump 'i' here, so we can keep going, even if the current
1863                  * RX descriptor reaping fails later.  'i' shoult NOT be used
1864                  * in the following processing any more.
1865                  */
1866                 SK_INC(i, SK_RX_RING_CNT);
1867
1868                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
1869                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
1870                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
1871                     total_len < SK_MIN_FRAMELEN || total_len > max_frmlen ||
1872                     sk_rxvalid(sc, rxstat, total_len) == 0) {
1873                         ifp->if_ierrors++;
1874                         cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
1875                         continue;
1876                 }
1877
1878                 /*
1879                  * Try to allocate a new RX buffer. If that fails,
1880                  * copy the packet to mbufs and put the RX buffer
1881                  * back in the ring so it can be re-used. If
1882                  * allocating mbufs fails, then we have to drop
1883                  * the packet.
1884                  */
1885                 if (sk_newbuf(sc_if, cur, 0)) {
1886                         ifp->if_ierrors++;
1887                         cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
1888                         continue;
1889                 } else {
1890                         m->m_pkthdr.rcvif = ifp;
1891                         m->m_pkthdr.len = m->m_len = total_len;
1892                 }
1893
1894 #ifdef SK_RXCSUM
1895                 sk_rxcsum(ifp, m, csum1, csum2);
1896 #endif
1897
1898                 ifp->if_ipackets++;
1899                 ifp->if_input(ifp, m);
1900         }
1901 }
1902
1903 #ifdef SK_RXCSUM
1904 static void
1905 sk_rxcsum(struct ifnet *ifp, struct mbuf *m,
1906           const uint16_t csum1, const uint16_t csum2)
1907 {
1908         struct ether_header *eh;
1909         struct ip *ip;
1910         uint8_t *pp;
1911         int hlen, len, plen;
1912         uint16_t iph_csum, ipo_csum, ipd_csum, csum;
1913
1914         pp = mtod(m, uint8_t *);
1915         plen = m->m_pkthdr.len;
1916         if (plen < sizeof(*eh))
1917                 return;
1918         eh = (struct ether_header *)pp;
1919         iph_csum = in_addword(csum1, (~csum2 & 0xffff));
1920
1921         if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1922                 uint16_t *xp = (uint16_t *)pp;
1923
1924                 xp = (uint16_t *)pp;
1925                 if (xp[1] != htons(ETHERTYPE_IP))
1926                         return;
1927                 iph_csum = in_addword(iph_csum, (~xp[0] & 0xffff));
1928                 iph_csum = in_addword(iph_csum, (~xp[1] & 0xffff));
1929                 xp = (uint16_t *)(pp + sizeof(struct ip));
1930                 iph_csum = in_addword(iph_csum, xp[0]);
1931                 iph_csum = in_addword(iph_csum, xp[1]);
1932                 pp += EVL_ENCAPLEN;
1933         } else if (eh->ether_type != htons(ETHERTYPE_IP)) {
1934                 return;
1935         }
1936
1937         pp += sizeof(*eh);
1938         plen -= sizeof(*eh);
1939
1940         ip = (struct ip *)pp;
1941
1942         if (ip->ip_v != IPVERSION)
1943                 return;
1944
1945         hlen = ip->ip_hl << 2;
1946         if (hlen < sizeof(struct ip))
1947                 return;
1948         if (hlen > ntohs(ip->ip_len))
1949                 return;
1950
1951         /* Don't deal with truncated or padded packets. */
1952         if (plen != ntohs(ip->ip_len))
1953                 return;
1954
1955         len = hlen - sizeof(struct ip);
1956         if (len > 0) {
1957                 uint16_t *p;
1958
1959                 p = (uint16_t *)(ip + 1);
1960                 ipo_csum = 0;
1961                 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++)
1962                         ipo_csum = in_addword(ipo_csum, *p);
1963                 iph_csum = in_addword(iph_csum, ipo_csum);
1964                 ipd_csum = in_addword(csum2, (~ipo_csum & 0xffff));
1965         } else {
1966                 ipd_csum = csum2;
1967         }
1968
1969         if (iph_csum != 0xffff)
1970                 return;
1971         m->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID;
1972
1973         if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1974                 return;                 /* ip frag, we're done for now */
1975
1976         pp += hlen;
1977
1978         /* Only know checksum protocol for udp/tcp */
1979         if (ip->ip_p == IPPROTO_UDP) {
1980                 struct udphdr *uh = (struct udphdr *)pp;
1981
1982                 if (uh->uh_sum == 0)    /* udp with no checksum */
1983                         return;
1984         } else if (ip->ip_p != IPPROTO_TCP) {
1985                 return;
1986         }
1987
1988         csum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1989             htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum);
1990         if (csum == 0xffff) {
1991                 m->m_pkthdr.csum_data = csum;
1992                 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1993         }
1994 }
1995 #endif
1996
1997 static void
1998 sk_txeof(struct sk_if_softc *sc_if)
1999 {
2000         struct sk_chain_data *cd = &sc_if->sk_cdata;
2001         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2002         uint32_t idx;
2003
2004         DPRINTFN(2, ("sk_txeof\n"));
2005
2006         /*
2007          * Go through our tx ring and free mbufs for those
2008          * frames that have been sent.
2009          */
2010         idx = cd->sk_tx_cons;
2011         while (idx != cd->sk_tx_prod) {
2012                 struct sk_tx_desc *cur_tx;
2013                 uint32_t sk_ctl;
2014
2015                 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2016                 sk_ctl = le32toh(cur_tx->sk_ctl);
2017 #ifdef SK_DEBUG
2018                 if (skdebug >= 2)
2019                         sk_dump_txdesc(cur_tx, idx);
2020 #endif
2021                 if (sk_ctl & SK_TXCTL_OWN)
2022                         break;
2023                 if (sk_ctl & SK_TXCTL_LASTFRAG)
2024                         ifp->if_opackets++;
2025                 if (cd->sk_tx_mbuf[idx] != NULL) {
2026                         bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[idx]);
2027                         m_freem(cd->sk_tx_mbuf[idx]);
2028                         cd->sk_tx_mbuf[idx] = NULL;
2029                 }
2030                 sc_if->sk_cdata.sk_tx_cnt--;
2031                 SK_INC(idx, SK_TX_RING_CNT);
2032         }
2033
2034         if (!SK_IS_OACTIVE(sc_if))
2035                 ifq_clr_oactive(&ifp->if_snd);
2036
2037         if (sc_if->sk_cdata.sk_tx_cnt == 0)
2038                 ifp->if_timer = 0;
2039
2040         sc_if->sk_cdata.sk_tx_cons = idx;
2041 }
2042
2043 static void
2044 sk_tick(void *xsc_if)
2045 {
2046         struct sk_if_softc *sc_if = xsc_if;
2047         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2048         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2049         int i;
2050
2051         DPRINTFN(2, ("sk_tick\n"));
2052
2053         lwkt_serialize_enter(ifp->if_serializer);
2054
2055         if ((ifp->if_flags & IFF_UP) == 0) {
2056                 lwkt_serialize_exit(ifp->if_serializer);
2057                 return;
2058         }
2059
2060         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2061                 sk_intr_bcom(sc_if);
2062                 lwkt_serialize_exit(ifp->if_serializer);
2063                 return;
2064         }
2065
2066         /*
2067          * According to SysKonnect, the correct way to verify that
2068          * the link has come back up is to poll bit 0 of the GPIO
2069          * register three times. This pin has the signal from the
2070          * link sync pin connected to it; if we read the same link
2071          * state 3 times in a row, we know the link is up.
2072          */
2073         for (i = 0; i < 3; i++) {
2074                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2075                         break;
2076         }
2077
2078         if (i != 3) {
2079                 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if);
2080                 lwkt_serialize_exit(ifp->if_serializer);
2081                 return;
2082         }
2083
2084         /* Turn the GP0 interrupt back on. */
2085         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2086         SK_XM_READ_2(sc_if, XM_ISR);
2087         mii_tick(mii);
2088         callout_stop(&sc_if->sk_tick_timer);
2089         lwkt_serialize_exit(ifp->if_serializer);
2090 }
2091
2092 static void
2093 sk_yukon_tick(void *xsc_if)
2094 {
2095         struct sk_if_softc *sc_if = xsc_if;
2096         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2097         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2098
2099         lwkt_serialize_enter(ifp->if_serializer);
2100         mii_tick(mii);
2101         callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
2102         lwkt_serialize_exit(ifp->if_serializer);
2103 }
2104
2105 static void
2106 sk_intr_bcom(struct sk_if_softc *sc_if)
2107 {
2108         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2109         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2110         int status;
2111
2112         DPRINTFN(2, ("sk_intr_bcom\n"));
2113
2114         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2115
2116         /*
2117          * Read the PHY interrupt register to make sure
2118          * we clear any pending interrupts.
2119          */
2120         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2121
2122         if ((ifp->if_flags & IFF_RUNNING) == 0) {
2123                 sk_init_xmac(sc_if);
2124                 return;
2125         }
2126
2127         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2128                 int lstat;
2129
2130                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2131                     BRGPHY_MII_AUXSTS);
2132
2133                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2134                         mii_mediachg(mii);
2135                         /* Turn off the link LED. */
2136                         SK_IF_WRITE_1(sc_if, 0,
2137                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
2138                         sc_if->sk_link = 0;
2139                 } else if (status & BRGPHY_ISR_LNK_CHG) {
2140                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2141                             BRGPHY_MII_IMR, 0xFF00);
2142                         mii_tick(mii);
2143                         sc_if->sk_link = 1;
2144                         /* Turn on the link LED. */
2145                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2146                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2147                             SK_LINKLED_BLINK_OFF);
2148                 } else {
2149                         mii_tick(mii);
2150                         callout_reset(&sc_if->sk_tick_timer, hz,
2151                                       sk_tick, sc_if);
2152                 }
2153         }
2154
2155         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2156 }
2157
2158 static void
2159 sk_intr_xmac(struct sk_if_softc *sc_if)
2160 {
2161         uint16_t status;
2162
2163         status = SK_XM_READ_2(sc_if, XM_ISR);
2164         DPRINTFN(2, ("sk_intr_xmac\n"));
2165
2166         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC &&
2167             (status & (XM_ISR_GP0_SET | XM_ISR_AUTONEG_DONE))) {
2168                 if (status & XM_ISR_GP0_SET)
2169                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2170
2171                 callout_reset(&sc_if->sk_tick_timer, hz,
2172                               sk_tick, sc_if);
2173         }
2174
2175         if (status & XM_IMR_TX_UNDERRUN)
2176                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2177
2178         if (status & XM_IMR_RX_OVERRUN)
2179                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2180 }
2181
2182 static void
2183 sk_intr_yukon(struct sk_if_softc *sc_if)
2184 {
2185         uint8_t status;
2186
2187         status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
2188         /* RX overrun */
2189         if ((status & SK_GMAC_INT_RX_OVER) != 0) {
2190                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2191                     SK_RFCTL_RX_FIFO_OVER);
2192         }
2193         /* TX underrun */
2194         if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
2195                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2196                     SK_TFCTL_TX_FIFO_UNDER);
2197         }
2198
2199         DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status));
2200 }
2201
2202 static void
2203 sk_intr(void *xsc)
2204 {
2205         struct sk_softc *sc = xsc;
2206         struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
2207         struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B];
2208         struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2209         uint32_t status;
2210
2211         ASSERT_SERIALIZED(&sc->sk_serializer);
2212
2213         status = CSR_READ_4(sc, SK_ISSR);
2214         if (status == 0 || status == 0xffffffff)
2215                 return;
2216
2217         if (sc_if0 != NULL)
2218                 ifp0 = &sc_if0->arpcom.ac_if;
2219         if (sc_if1 != NULL)
2220                 ifp1 = &sc_if1->arpcom.ac_if;
2221
2222         for (; (status &= sc->sk_intrmask) != 0;) {
2223                 /* Handle receive interrupts first. */
2224                 if (sc_if0 && (status & SK_ISR_RX1_EOF)) {
2225                         sk_rxeof(sc_if0);
2226                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2227                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2228                 }
2229                 if (sc_if1 && (status & SK_ISR_RX2_EOF)) {
2230                         sk_rxeof(sc_if1);
2231                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2232                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2233                 }
2234
2235                 /* Then transmit interrupts. */
2236                 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) {
2237                         sk_txeof(sc_if0);
2238                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2239                             SK_TXBMU_CLR_IRQ_EOF);
2240                 }
2241                 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) {
2242                         sk_txeof(sc_if1);
2243                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2244                             SK_TXBMU_CLR_IRQ_EOF);
2245                 }
2246
2247                 /* Then MAC interrupts. */
2248                 if (sc_if0 && (status & SK_ISR_MAC1) &&
2249                     (ifp0->if_flags & IFF_RUNNING)) {
2250                         if (SK_IS_GENESIS(sc))
2251                                 sk_intr_xmac(sc_if0);
2252                         else
2253                                 sk_intr_yukon(sc_if0);
2254                 }
2255
2256                 if (sc_if1 && (status & SK_ISR_MAC2) &&
2257                     (ifp1->if_flags & IFF_RUNNING)) {
2258                         if (SK_IS_GENESIS(sc))
2259                                 sk_intr_xmac(sc_if1);
2260                         else
2261                                 sk_intr_yukon(sc_if1);
2262                 }
2263
2264                 if (status & SK_ISR_EXTERNAL_REG) {
2265                         if (sc_if0 != NULL &&
2266                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
2267                                 sk_intr_bcom(sc_if0);
2268
2269                         if (sc_if1 != NULL &&
2270                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
2271                                 sk_intr_bcom(sc_if1);
2272                 }
2273                 status = CSR_READ_4(sc, SK_ISSR);
2274         }
2275
2276         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2277
2278         if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd))
2279                 if_devstart(ifp0);
2280         if (ifp1 != NULL && !ifq_is_empty(&ifp1->if_snd))
2281                 if_devstart(ifp1);
2282 }
2283
2284 static void
2285 sk_init_xmac(struct sk_if_softc *sc_if)
2286 {
2287         struct sk_softc *sc = sc_if->sk_softc;
2288         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2289         static const struct sk_bcom_hack bhack[] = {
2290         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2291         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2292         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2293         { 0, 0 } };
2294
2295         DPRINTFN(2, ("sk_init_xmac\n"));
2296
2297         /* Unreset the XMAC. */
2298         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2299         DELAY(1000);
2300
2301         /* Reset the XMAC's internal state. */
2302         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2303
2304         /* Save the XMAC II revision */
2305         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2306
2307         /*
2308          * Perform additional initialization for external PHYs,
2309          * namely for the 1000baseT cards that use the XMAC's
2310          * GMII mode.
2311          */
2312         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2313                 int i = 0;
2314                 uint32_t val;
2315
2316                 /* Take PHY out of reset. */
2317                 val = sk_win_read_4(sc, SK_GPIO);
2318                 if (sc_if->sk_port == SK_PORT_A)
2319                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2320                 else
2321                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2322                 sk_win_write_4(sc, SK_GPIO, val);
2323
2324                 /* Enable GMII mode on the XMAC. */
2325                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2326
2327                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2328                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2329                 DELAY(10000);
2330                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2331                     BRGPHY_MII_IMR, 0xFFF0);
2332
2333                 /*
2334                  * Early versions of the BCM5400 apparently have
2335                  * a bug that requires them to have their reserved
2336                  * registers initialized to some magic values. I don't
2337                  * know what the numbers do, I'm just the messenger.
2338                  */
2339                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2340                     == 0x6041) {
2341                         while(bhack[i].reg) {
2342                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2343                                     bhack[i].reg, bhack[i].val);
2344                                 i++;
2345                         }
2346                 }
2347         }
2348
2349         /* Set station address */
2350         SK_XM_WRITE_2(sc_if, XM_PAR0,
2351             *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2352         SK_XM_WRITE_2(sc_if, XM_PAR1,
2353             *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2354         SK_XM_WRITE_2(sc_if, XM_PAR2,
2355             *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2356         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2357
2358         if (ifp->if_flags & IFF_BROADCAST)
2359                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2360         else
2361                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2362
2363         /* We don't need the FCS appended to the packet. */
2364         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2365
2366         /* We want short frames padded to 60 bytes. */
2367         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2368
2369         /*
2370          * Enable the reception of all error frames. This is
2371          * a necessary evil due to the design of the XMAC. The
2372          * XMAC's receive FIFO is only 8K in size, however jumbo
2373          * frames can be up to 9000 bytes in length. When bad
2374          * frame filtering is enabled, the XMAC's RX FIFO operates
2375          * in 'store and forward' mode. For this to work, the
2376          * entire frame has to fit into the FIFO, but that means
2377          * that jumbo frames larger than 8192 bytes will be
2378          * truncated. Disabling all bad frame filtering causes
2379          * the RX FIFO to operate in streaming mode, in which
2380          * case the XMAC will start transfering frames out of the
2381          * RX FIFO as soon as the FIFO threshold is reached.
2382          */
2383         if (sc_if->sk_use_jumbo) {
2384                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2385                     XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2386                     XM_MODE_RX_INRANGELEN);
2387         }
2388
2389         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2390
2391         /*
2392          * Bump up the transmit threshold. This helps hold off transmit
2393          * underruns when we're blasting traffic from both ports at once.
2394          */
2395         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2396
2397         /* Set promiscuous mode */
2398         sk_setpromisc(sc_if);
2399
2400         /* Set multicast filter */
2401         sk_setmulti(sc_if);
2402
2403         /* Clear and enable interrupts */
2404         SK_XM_READ_2(sc_if, XM_ISR);
2405         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2406                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2407         else
2408                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2409
2410         /* Configure MAC arbiter */
2411         switch(sc_if->sk_xmac_rev) {
2412         case XM_XMAC_REV_B2:
2413                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2414                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2415                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2416                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2417                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2418                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2419                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2420                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2421                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2422                 break;
2423         case XM_XMAC_REV_C1:
2424                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2425                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2426                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2427                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2428                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2429                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2430                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2431                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2432                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2433                 break;
2434         default:
2435                 break;
2436         }
2437         sk_win_write_2(sc, SK_MACARB_CTL,
2438             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2439
2440         sc_if->sk_link = 1;
2441 }
2442
2443 static void
2444 sk_init_yukon(struct sk_if_softc *sc_if)
2445 {
2446         uint32_t phy, v;
2447         uint16_t reg;
2448         struct sk_softc *sc;
2449         int i;
2450
2451         sc = sc_if->sk_softc;
2452
2453         DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n",
2454                      CSR_READ_4(sc_if->sk_softc, SK_CSR)));
2455
2456         if (sc->sk_type == SK_YUKON_LITE &&
2457             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2458                 /*
2459                  * Workaround code for COMA mode, set PHY reset.
2460                  * Otherwise it will not correctly take chip out of
2461                  * powerdown (coma)
2462                  */
2463                 v = sk_win_read_4(sc, SK_GPIO);
2464                 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
2465                 sk_win_write_4(sc, SK_GPIO, v);
2466         }
2467
2468         DPRINTFN(6, ("sk_init_yukon: 1\n"));
2469
2470         /* GMAC and GPHY Reset */
2471         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2472         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2473         DELAY(1000);
2474
2475         DPRINTFN(6, ("sk_init_yukon: 2\n"));
2476
2477         if (sc->sk_type == SK_YUKON_LITE &&
2478             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2479                 /*
2480                  * Workaround code for COMA mode, clear PHY reset
2481                  */
2482                 v = sk_win_read_4(sc, SK_GPIO);
2483                 v |= SK_GPIO_DIR9;
2484                 v &= ~SK_GPIO_DAT9;
2485                 sk_win_write_4(sc, SK_GPIO, v);
2486         }
2487
2488         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2489                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2490
2491         if (sc->sk_coppertype)
2492                 phy |= SK_GPHY_COPPER;
2493         else
2494                 phy |= SK_GPHY_FIBER;
2495
2496         DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy));
2497
2498         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2499         DELAY(1000);
2500         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2501         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2502                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2503
2504         DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n",
2505                      SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
2506
2507         DPRINTFN(6, ("sk_init_yukon: 3\n"));
2508
2509         /* unused read of the interrupt source register */
2510         DPRINTFN(6, ("sk_init_yukon: 4\n"));
2511         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2512
2513         DPRINTFN(6, ("sk_init_yukon: 4a\n"));
2514         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2515         DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2516
2517         /* MIB Counter Clear Mode set */
2518         reg |= YU_PAR_MIB_CLR;
2519         DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2520         DPRINTFN(6, ("sk_init_yukon: 4b\n"));
2521         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2522
2523         /* MIB Counter Clear Mode clear */
2524         DPRINTFN(6, ("sk_init_yukon: 5\n"));
2525         reg &= ~YU_PAR_MIB_CLR;
2526         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2527
2528         /* receive control reg */
2529         DPRINTFN(6, ("sk_init_yukon: 7\n"));
2530         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2531
2532         /* transmit parameter register */
2533         DPRINTFN(6, ("sk_init_yukon: 8\n"));
2534         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2535                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2536
2537         /* serial mode register */
2538         DPRINTFN(6, ("sk_init_yukon: 9\n"));
2539         reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
2540         if (sc_if->sk_use_jumbo)
2541                 reg |= YU_SMR_MFL_JUMBO;
2542         SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
2543
2544         DPRINTFN(6, ("sk_init_yukon: 10\n"));
2545         /* Setup Yukon's address */
2546         for (i = 0; i < 3; i++) {
2547                 /* Write Source Address 1 (unicast filter) */
2548                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2549                               sc_if->arpcom.ac_enaddr[i * 2] |
2550                               sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2551         }
2552
2553         for (i = 0; i < 3; i++) {
2554                 reg = sk_win_read_2(sc_if->sk_softc,
2555                                     SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2556                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2557         }
2558
2559         /* Set promiscuous mode */
2560         sk_setpromisc(sc_if);
2561
2562         /* Set multicast filter */
2563         DPRINTFN(6, ("sk_init_yukon: 11\n"));
2564         sk_setmulti(sc_if);
2565
2566         /* enable interrupt mask for counter overflows */
2567         DPRINTFN(6, ("sk_init_yukon: 12\n"));
2568         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2569         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2570         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2571
2572         /* Configure RX MAC FIFO Flush Mask */
2573         v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
2574             YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
2575             YU_RXSTAT_JABBER;
2576         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
2577
2578         /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
2579         if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
2580                 v = SK_TFCTL_OPERATION_ON;
2581         else
2582                 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
2583         /* Configure RX MAC FIFO */
2584         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2585         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
2586
2587         /* Increase flush threshould to 64 bytes */
2588         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
2589             SK_RFCTL_FIFO_THRESHOLD + 1);
2590
2591         /* Configure TX MAC FIFO */
2592         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2593         SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2594
2595         DPRINTFN(6, ("sk_init_yukon: end\n"));
2596 }
2597
2598 /*
2599  * Note that to properly initialize any part of the GEnesis chip,
2600  * you first have to take it out of reset mode.
2601  */
2602 static void
2603 sk_init(void *xsc_if)
2604 {
2605         struct sk_if_softc *sc_if = xsc_if;
2606         struct sk_softc *sc = sc_if->sk_softc;
2607         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2608         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2609
2610         DPRINTFN(2, ("sk_init\n"));
2611
2612         ASSERT_SERIALIZED(ifp->if_serializer);
2613
2614         if (ifp->if_flags & IFF_RUNNING)
2615                 return;
2616
2617         /* Cancel pending I/O and free all RX/TX buffers. */
2618         sk_stop(sc_if);
2619
2620         /*
2621          * NOTE: Change sk_use_jumbo after sk_stop(),
2622          *       but before real initialization.
2623          */
2624         if (ifp->if_mtu > ETHER_MAX_LEN)
2625                 sc_if->sk_use_jumbo = 1;
2626         else
2627                 sc_if->sk_use_jumbo = 0;
2628         DPRINTF(("use jumbo buffer: %s\n", sc_if->sk_use_jumbo ? "YES" : "NO"));
2629
2630         if (SK_IS_GENESIS(sc)) {
2631                 /* Configure LINK_SYNC LED */
2632                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2633                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2634                         SK_LINKLED_LINKSYNC_ON);
2635
2636                 /* Configure RX LED */
2637                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2638                         SK_RXLEDCTL_COUNTER_START);
2639
2640                 /* Configure TX LED */
2641                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2642                         SK_TXLEDCTL_COUNTER_START);
2643         }
2644
2645         /*
2646          * Configure descriptor poll timer
2647          *
2648          * SK-NET GENESIS data sheet says that possibility of losing Start
2649          * transmit command due to CPU/cache related interim storage problems
2650          * under certain conditions. The document recommends a polling
2651          * mechanism to send a Start transmit command to initiate transfer
2652          * of ready descriptors regulary. To cope with this issue sk(4) now
2653          * enables descriptor poll timer to initiate descriptor processing
2654          * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
2655          * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
2656          * command instead of waiting for next descriptor polling time.
2657          * The same rule may apply to Rx side too but it seems that is not
2658          * needed at the moment.
2659          * Since sk(4) uses descriptor polling as a last resort there is no
2660          * need to set smaller polling time than maximum allowable one.
2661          */
2662         SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
2663
2664         /* Configure I2C registers */
2665
2666         /* Configure XMAC(s) */
2667         switch (sc->sk_type) {
2668         case SK_GENESIS:
2669                 sk_init_xmac(sc_if);
2670                 break;
2671         case SK_YUKON:
2672         case SK_YUKON_LITE:
2673         case SK_YUKON_LP:
2674                 sk_init_yukon(sc_if);
2675                 break;
2676         }
2677         mii_mediachg(mii);
2678
2679         if (SK_IS_GENESIS(sc)) {
2680                 /* Configure MAC FIFOs */
2681                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2682                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2683                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2684
2685                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2686                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2687                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2688         }
2689
2690         /* Configure transmit arbiter(s) */
2691         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2692             SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON);
2693
2694         /* Configure RAMbuffers */
2695         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2696         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2697         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2698         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2699         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2700         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2701
2702         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2703         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2704         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2705         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2706         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2707         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2708         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2709
2710         /* Configure BMUs */
2711         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2712         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2713                       SK_ADDR_LO(sc_if->sk_rdata.sk_rx_ring_paddr));
2714         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
2715                       SK_ADDR_HI(sc_if->sk_rdata.sk_rx_ring_paddr));
2716
2717         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2718         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2719                       SK_ADDR_LO(sc_if->sk_rdata.sk_tx_ring_paddr));
2720         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
2721                       SK_ADDR_HI(sc_if->sk_rdata.sk_tx_ring_paddr));
2722
2723         /* Init descriptors */
2724         if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2725                 if_printf(ifp, "initialization failed: "
2726                           "no memory for rx buffers\n");
2727                 sk_stop(sc_if);
2728                 return;
2729         }
2730
2731         if (sk_init_tx_ring(sc_if) == ENOBUFS) {
2732                 if_printf(ifp, "initialization failed: "
2733                           "no memory for tx buffers\n");
2734                 sk_stop(sc_if);
2735                 return;
2736         }
2737
2738         /* Configure interrupt handling */
2739         CSR_READ_4(sc, SK_ISSR);
2740         if (sc_if->sk_port == SK_PORT_A)
2741                 sc->sk_intrmask |= SK_INTRS1;
2742         else
2743                 sc->sk_intrmask |= SK_INTRS2;
2744
2745         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2746
2747         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2748
2749         /* Start BMUs. */
2750         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2751
2752         if (SK_IS_GENESIS(sc)) {
2753                 /* Enable XMACs TX and RX state machines */
2754                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2755                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD,
2756                                XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2757         }
2758
2759         if (SK_IS_YUKON(sc)) {
2760                 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2761                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2762 #if 0
2763                 /* XXX disable 100Mbps and full duplex mode? */
2764                 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
2765 #endif
2766                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2767         }
2768
2769         /* Activate descriptor polling timer */
2770         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
2771         /* Start transfer of Tx descriptors */
2772         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2773
2774         ifp->if_flags |= IFF_RUNNING;
2775         ifq_clr_oactive(&ifp->if_snd);
2776
2777         if (SK_IS_YUKON(sc))
2778                 callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
2779 }
2780
2781 static void
2782 sk_stop(struct sk_if_softc *sc_if)
2783 {
2784         struct sk_softc *sc = sc_if->sk_softc;
2785         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2786         struct sk_chain_data *cd = &sc_if->sk_cdata;
2787         uint32_t val;
2788         int i;
2789
2790         ASSERT_SERIALIZED(ifp->if_serializer);
2791
2792         DPRINTFN(2, ("sk_stop\n"));
2793
2794         callout_stop(&sc_if->sk_tick_timer);
2795
2796         ifp->if_flags &= ~IFF_RUNNING;
2797         ifq_clr_oactive(&ifp->if_snd);
2798
2799         /* Stop Tx descriptor polling timer */
2800         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
2801
2802         /* Stop transfer of Tx descriptors */
2803         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
2804         for (i = 0; i < SK_TIMEOUT; i++) {
2805                 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
2806                 if (!(val & SK_TXBMU_TX_STOP))
2807                         break;
2808                 DELAY(1);
2809         }
2810         if (i == SK_TIMEOUT)
2811                 if_printf(ifp, "cannot stop transfer of Tx descriptors\n");
2812
2813         /* Stop transfer of Rx descriptors */
2814         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
2815         for (i = 0; i < SK_TIMEOUT; i++) {
2816                 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
2817                 if (!(val & SK_RXBMU_RX_STOP))
2818                         break;
2819                 DELAY(1);
2820         }
2821         if (i == SK_TIMEOUT)
2822                 if_printf(ifp, "cannot stop transfer of Rx descriptors\n");
2823
2824         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2825                 /* Put PHY back into reset. */
2826                 val = sk_win_read_4(sc, SK_GPIO);
2827                 if (sc_if->sk_port == SK_PORT_A) {
2828                         val |= SK_GPIO_DIR0;
2829                         val &= ~SK_GPIO_DAT0;
2830                 } else {
2831                         val |= SK_GPIO_DIR2;
2832                         val &= ~SK_GPIO_DAT2;
2833                 }
2834                 sk_win_write_4(sc, SK_GPIO, val);
2835         }
2836
2837         /* Turn off various components of this interface. */
2838         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2839         switch (sc->sk_type) {
2840         case SK_GENESIS:
2841                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2842                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2843                 break;
2844         case SK_YUKON:
2845         case SK_YUKON_LITE:
2846         case SK_YUKON_LP:
2847                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2848                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2849                 break;
2850         }
2851         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2852         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF);
2853         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2854         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST,
2855             SK_RBCTL_RESET | SK_RBCTL_OFF);
2856         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2857         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2858         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2859         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2860         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2861
2862         /* Disable interrupts */
2863         if (sc_if->sk_port == SK_PORT_A)
2864                 sc->sk_intrmask &= ~SK_INTRS1;
2865         else
2866                 sc->sk_intrmask &= ~SK_INTRS2;
2867         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2868
2869         SK_XM_READ_2(sc_if, XM_ISR);
2870         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2871
2872         /* Free RX and TX mbufs still in the queues. */
2873         for (i = 0; i < SK_RX_RING_CNT; i++) {
2874                 if (cd->sk_rx_mbuf[i] != NULL) {
2875                         if (!sc_if->sk_use_jumbo) {
2876                                 bus_dmamap_unload(cd->sk_rx_dtag,
2877                                                   cd->sk_rx_dmap[i]);
2878                         }
2879                         m_freem(cd->sk_rx_mbuf[i]);
2880                         cd->sk_rx_mbuf[i] = NULL;
2881                 }
2882         }
2883         for (i = 0; i < SK_TX_RING_CNT; i++) {
2884                 if (cd->sk_tx_mbuf[i] != NULL) {
2885                         bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
2886                         m_freem(cd->sk_tx_mbuf[i]);
2887                         cd->sk_tx_mbuf[i] = NULL;
2888                 }
2889         }
2890 }
2891
2892 #ifdef SK_DEBUG
2893 static void
2894 sk_dump_txdesc(struct sk_tx_desc *desc, int idx)
2895 {
2896 #define DESC_PRINT(X)                                   \
2897         if (X)                                  \
2898                 kprintf("txdesc[%d]." #X "=%#x\n",      \
2899                        idx, X);
2900
2901         DESC_PRINT(le32toh(desc->sk_ctl));
2902         DESC_PRINT(le32toh(desc->sk_next));
2903         DESC_PRINT(le32toh(desc->sk_data_lo));
2904         DESC_PRINT(le32toh(desc->sk_data_hi));
2905         DESC_PRINT(le32toh(desc->sk_xmac_txstat));
2906         DESC_PRINT(le16toh(desc->sk_rsvd0));
2907         DESC_PRINT(le16toh(desc->sk_csum_startval));
2908         DESC_PRINT(le16toh(desc->sk_csum_startpos));
2909         DESC_PRINT(le16toh(desc->sk_csum_writepos));
2910         DESC_PRINT(le16toh(desc->sk_rsvd1));
2911 #undef PRINT
2912 }
2913
2914 static void
2915 sk_dump_bytes(const char *data, int len)
2916 {
2917         int c, i, j;
2918
2919         for (i = 0; i < len; i += 16) {
2920                 kprintf("%08x  ", i);
2921                 c = len - i;
2922                 if (c > 16) c = 16;
2923
2924                 for (j = 0; j < c; j++) {
2925                         kprintf("%02x ", data[i + j] & 0xff);
2926                         if ((j & 0xf) == 7 && j > 0)
2927                                 kprintf(" ");
2928                 }
2929
2930                 for (; j < 16; j++)
2931                         kprintf("   ");
2932                 kprintf("  ");
2933
2934                 for (j = 0; j < c; j++) {
2935                         int ch = data[i + j] & 0xff;
2936                         kprintf("%c", ' ' <= ch && ch <= '~' ? ch : ' ');
2937                 }
2938
2939                 kprintf("\n");
2940
2941                 if (c < 16)
2942                         break;
2943         }
2944 }
2945
2946 static void
2947 sk_dump_mbuf(struct mbuf *m)
2948 {
2949         int count = m->m_pkthdr.len;
2950
2951         kprintf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len);
2952
2953         while (count > 0 && m) {
2954                 kprintf("m=%p, m->m_data=%p, m->m_len=%d\n",
2955                        m, m->m_data, m->m_len);
2956                 sk_dump_bytes(mtod(m, char *), m->m_len);
2957
2958                 count -= m->m_len;
2959                 m = m->m_next;
2960         }
2961 }
2962 #endif
2963
2964 /*
2965  * Allocate jumbo buffer storage. The SysKonnect adapters support
2966  * "jumbograms" (9K frames), although SysKonnect doesn't currently
2967  * use them in their drivers. In order for us to use them, we need
2968  * large 9K receive buffers, however standard mbuf clusters are only
2969  * 2048 bytes in size. Consequently, we need to allocate and manage
2970  * our own jumbo buffer pool. Fortunately, this does not require an
2971  * excessive amount of additional code.
2972  */
2973 static int
2974 sk_jpool_alloc(device_t dev)
2975 {
2976         struct sk_if_softc *sc_if = device_get_softc(dev);
2977         struct sk_chain_data *cd = &sc_if->sk_cdata;
2978         bus_dmamem_t dmem;
2979         bus_addr_t paddr;
2980         caddr_t buf;
2981         int error, i;
2982
2983         lwkt_serialize_init(&cd->sk_jpool_serializer);
2984
2985         error = bus_dmamem_coherent(cd->sk_buf_dtag, PAGE_SIZE /* XXX */, 0,
2986                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2987                                     SK_JMEM, BUS_DMA_WAITOK, &dmem);
2988         if (error) {
2989                 device_printf(dev, "can't allocate jumbo frame pool\n");
2990                 return error;
2991         }
2992         cd->sk_jpool_dtag = dmem.dmem_tag;
2993         cd->sk_jpool_dmap = dmem.dmem_map;
2994         cd->sk_jpool = dmem.dmem_addr;
2995         paddr = dmem.dmem_busaddr;
2996
2997         SLIST_INIT(&cd->sk_jpool_free_ent);
2998         buf = cd->sk_jpool;
2999
3000         /*
3001          * Now divide it up into SK_JLEN pieces.
3002          */
3003         for (i = 0; i < SK_JSLOTS; i++) {
3004                 struct sk_jpool_entry *entry = &cd->sk_jpool_ent[i];
3005
3006                 entry->sc_if = sc_if;
3007                 entry->inuse = 0;
3008                 entry->slot = i;
3009                 entry->buf = buf;
3010                 entry->paddr = paddr;
3011
3012                 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
3013
3014                 buf += SK_JLEN;
3015                 paddr += SK_JLEN;
3016         }
3017         return 0;
3018 }
3019
3020 static void
3021 sk_jpool_free(struct sk_if_softc *sc_if)
3022 {
3023         struct sk_chain_data *cd = &sc_if->sk_cdata;
3024
3025         if (cd->sk_jpool_dtag != NULL) {
3026                 bus_dmamap_unload(cd->sk_jpool_dtag, cd->sk_jpool_dmap);
3027                 bus_dmamem_free(cd->sk_jpool_dtag, cd->sk_jpool,
3028                                 cd->sk_jpool_dmap);
3029                 bus_dma_tag_destroy(cd->sk_jpool_dtag);
3030                 cd->sk_jpool_dtag = NULL;
3031         }
3032 }
3033
3034 static int
3035 sk_dma_alloc(device_t dev)
3036 {
3037         struct sk_if_softc *sc_if = device_get_softc(dev);
3038         struct sk_chain_data *cd = &sc_if->sk_cdata;
3039         struct sk_ring_data *rd = &sc_if->sk_rdata;
3040         bus_dmamem_t dmem;
3041         int i, j, error;
3042
3043         /* Create parent DMA tag */
3044         error = bus_dma_tag_create(NULL, 1, 0,
3045                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3046                                    NULL, NULL,
3047                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3048                                    BUS_SPACE_MAXSIZE_32BIT,
3049                                    0, &sc_if->sk_parent_dtag);
3050         if (error) {
3051                 device_printf(dev, "can't create parent DMA tag\n");
3052                 return error;
3053         }
3054
3055         /* Create top level ring DMA tag */
3056         error = bus_dma_tag_create(sc_if->sk_parent_dtag,
3057                                    1, SK_RING_BOUNDARY,
3058                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3059                                    NULL, NULL,
3060                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3061                                    BUS_SPACE_MAXSIZE_32BIT,
3062                                    0, &rd->sk_ring_dtag);
3063         if (error) {
3064                 device_printf(dev, "can't create ring DMA tag\n");
3065                 return error;
3066         }
3067
3068         /* Create top level buffer DMA tag */
3069         error = bus_dma_tag_create(sc_if->sk_parent_dtag, 1, 0,
3070                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3071                                    NULL, NULL,
3072                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3073                                    BUS_SPACE_MAXSIZE_32BIT,
3074                                    0, &cd->sk_buf_dtag);
3075         if (error) {
3076                 device_printf(dev, "can't create buf DMA tag\n");
3077                 return error;
3078         }
3079
3080         /* Allocate the TX descriptor queue. */
3081         error = bus_dmamem_coherent(rd->sk_ring_dtag, SK_RING_ALIGN, 0,
3082                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3083                                     SK_TX_RING_SIZE,
3084                                     BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3085         if (error) {
3086                 device_printf(dev, "can't allocate TX ring\n");
3087                 return error;
3088         }
3089         rd->sk_tx_ring_dtag = dmem.dmem_tag;
3090         rd->sk_tx_ring_dmap = dmem.dmem_map;
3091         rd->sk_tx_ring = dmem.dmem_addr;
3092         rd->sk_tx_ring_paddr = dmem.dmem_busaddr;
3093
3094         /* Allocate the RX descriptor queue. */
3095         error = bus_dmamem_coherent(rd->sk_ring_dtag, SK_RING_ALIGN, 0,
3096                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3097                                     SK_RX_RING_SIZE,
3098                                     BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3099         if (error) {
3100                 device_printf(dev, "can't allocate TX ring\n");
3101                 return error;
3102         }
3103         rd->sk_rx_ring_dtag = dmem.dmem_tag;
3104         rd->sk_rx_ring_dmap = dmem.dmem_map;
3105         rd->sk_rx_ring = dmem.dmem_addr;
3106         rd->sk_rx_ring_paddr = dmem.dmem_busaddr;
3107
3108         /* Try to allocate memory for jumbo buffers. */
3109         error = sk_jpool_alloc(dev);
3110         if (error) {
3111                 device_printf(dev, "jumbo buffer allocation failed\n");
3112                 return error;
3113         }
3114
3115         /* Create DMA tag for TX. */
3116         error = bus_dma_tag_create(cd->sk_buf_dtag, 1, 0,
3117                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3118                                    NULL, NULL,
3119                                    SK_JLEN, SK_NTXSEG, SK_JLEN,
3120                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3121                                    BUS_DMA_ONEBPAGE,
3122                                    &cd->sk_tx_dtag);
3123         if (error) {
3124                 device_printf(dev, "can't create TX DMA tag\n");
3125                 return error;
3126         }
3127
3128         /* Create DMA maps for TX. */
3129         for (i = 0; i < SK_TX_RING_CNT; i++) {
3130                 error = bus_dmamap_create(cd->sk_tx_dtag,
3131                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3132                                           &cd->sk_tx_dmap[i]);
3133                 if (error) {
3134                         device_printf(dev, "can't create %dth TX DMA map\n", i);
3135
3136                         for (j = 0; j < i; ++j) {
3137                                 bus_dmamap_destroy(cd->sk_tx_dtag,
3138                                                    cd->sk_tx_dmap[i]);
3139                         }
3140                         bus_dma_tag_destroy(cd->sk_tx_dtag);
3141                         cd->sk_tx_dtag = NULL;
3142                         return error;
3143                 }
3144         }
3145
3146         /* Create DMA tag for RX. */
3147         error = bus_dma_tag_create(cd->sk_buf_dtag, 1, 0,
3148                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3149                                    NULL, NULL,
3150                                    MCLBYTES, 1, MCLBYTES,
3151                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3152                                    &cd->sk_rx_dtag);
3153         if (error) {
3154                 device_printf(dev, "can't create RX DMA tag\n");
3155                 return error;
3156         }
3157
3158         /* Create a spare RX DMA map. */
3159         error = bus_dmamap_create(cd->sk_rx_dtag, BUS_DMA_WAITOK,
3160                                   &cd->sk_rx_dmap_tmp);
3161         if (error) {
3162                 device_printf(dev, "can't create spare RX DMA map\n");
3163                 bus_dma_tag_destroy(cd->sk_rx_dtag);
3164                 cd->sk_rx_dtag = NULL;
3165                 return error;
3166         }
3167
3168         /* Create DMA maps for RX. */
3169         for (i = 0; i < SK_RX_RING_CNT; ++i) {
3170                 error = bus_dmamap_create(cd->sk_rx_dtag, BUS_DMA_WAITOK,
3171                                           &cd->sk_rx_dmap[i]);
3172                 if (error) {
3173                         device_printf(dev, "can't create %dth RX DMA map\n", i);
3174
3175                         for (j = 0; j < i; ++j) {
3176                                 bus_dmamap_destroy(cd->sk_rx_dtag,
3177                                                    cd->sk_rx_dmap[i]);
3178                         }
3179                         bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3180                         bus_dma_tag_destroy(cd->sk_rx_dtag);
3181                         cd->sk_rx_dtag = NULL;
3182                         return error;
3183                 }
3184         }
3185         return 0;
3186 }
3187
3188 static void
3189 sk_dma_free(device_t dev)
3190 {
3191         struct sk_if_softc *sc_if = device_get_softc(dev);
3192         struct sk_chain_data *cd = &sc_if->sk_cdata;
3193         struct sk_ring_data *rd = &sc_if->sk_rdata;
3194         int i;
3195
3196         if (cd->sk_tx_dtag != NULL) {
3197                 for (i = 0; i < SK_TX_RING_CNT; ++i) {
3198                         KASSERT(cd->sk_tx_mbuf[i] == NULL,
3199                                 ("sk_stop() is not called before %s()",
3200                                  __func__));
3201                         bus_dmamap_destroy(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
3202                 }
3203                 bus_dma_tag_destroy(cd->sk_tx_dtag);
3204         }
3205
3206         if (cd->sk_rx_dtag != NULL) {
3207                 for (i = 0; i < SK_RX_RING_CNT; ++i) {
3208                         KASSERT(cd->sk_rx_mbuf[i] == NULL,
3209                                 ("sk_stop() is not called before %s()",
3210                                  __func__));
3211                         bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap[i]);
3212                 }
3213                 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3214                 bus_dma_tag_destroy(cd->sk_rx_dtag);
3215         }
3216
3217         sk_jpool_free(sc_if);
3218
3219         if (rd->sk_rx_ring_dtag != NULL) {
3220                 bus_dmamap_unload(rd->sk_rx_ring_dtag, rd->sk_rx_ring_dmap);
3221                 bus_dmamem_free(rd->sk_rx_ring_dtag, rd->sk_rx_ring,
3222                                 rd->sk_rx_ring_dmap);
3223                 bus_dma_tag_destroy(rd->sk_rx_ring_dtag);
3224         }
3225
3226         if (rd->sk_tx_ring_dtag != NULL) {
3227                 bus_dmamap_unload(rd->sk_tx_ring_dtag, rd->sk_tx_ring_dmap);
3228                 bus_dmamem_free(rd->sk_tx_ring_dtag, rd->sk_tx_ring,
3229                                 rd->sk_tx_ring_dmap);
3230                 bus_dma_tag_destroy(rd->sk_tx_ring_dtag);
3231         }
3232
3233         if (rd->sk_ring_dtag != NULL)
3234                 bus_dma_tag_destroy(rd->sk_ring_dtag);
3235         if (cd->sk_buf_dtag != NULL)
3236                 bus_dma_tag_destroy(cd->sk_buf_dtag);
3237         if (sc_if->sk_parent_dtag != NULL)
3238                 bus_dma_tag_destroy(sc_if->sk_parent_dtag);
3239 }
3240
3241 static int
3242 skc_sysctl_imtime(SYSCTL_HANDLER_ARGS)
3243 {
3244         struct sk_softc *sc = arg1;
3245         struct lwkt_serialize *slize = &sc->sk_serializer;
3246         int error = 0, v;
3247
3248         lwkt_serialize_enter(slize);
3249
3250         v = sc->sk_imtime;
3251         error = sysctl_handle_int(oidp, &v, 0, req);
3252         if (error || req->newptr == NULL)
3253                 goto back;
3254         if (v <= 0) {
3255                 error = EINVAL;
3256                 goto back;
3257         }
3258
3259         if (sc->sk_imtime != v) {
3260                 sc->sk_imtime = v;
3261                 sk_win_write_4(sc, SK_IMTIMERINIT,
3262                                SK_IM_USECS(sc, sc->sk_imtime));
3263
3264                 /*
3265                  * Force interrupt moderation timer to
3266                  * reload new value.
3267                  */
3268                 sk_win_write_4(sc, SK_IMTIMER, 0);
3269         }
3270 back:
3271         lwkt_serialize_exit(slize);
3272         return error;
3273 }