sys/dev/agp/agp_i810.c

   1 /*
   2  * Copyright (c) 2000 Doug Rabson
   3  * Copyright (c) 2000 Ruslan Ermilov
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  *      $FreeBSD: src/sys/dev/agp/agp_i810.c,v 1.43 2007/11/12 21:51:36 jhb Exp $
  28  */
  29
  30 /*
  31  * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
  32  * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
  33  */
  34
  35 #include "opt_bus.h"
  36
  37 #include <sys/param.h>
  38 #include <sys/systm.h>
  39 #include <sys/malloc.h>
  40 #include <sys/kernel.h>
  41 #include <sys/bus.h>
  42 #include <sys/lock.h>
  43 #include <sys/rman.h>
  44
  45 #include <bus/pci/pcivar.h>
  46 #include <bus/pci/pcireg.h>
  47 #include "agppriv.h"
  48 #include "agpreg.h"
  49
  50 #include <vm/vm.h>
  51 #include <vm/vm_object.h>
  52 #include <vm/vm_page.h>
  53 #include <vm/vm_pageout.h>
  54 #include <vm/pmap.h>
  55
  56 #include <machine/md_var.h>
  57
  58 #define bus_read_1(r, o) \
  59                    bus_space_read_1((r)->r_bustag, (r)->r_bushandle, (o))
  60 #define bus_read_4(r, o) \
  61                    bus_space_read_4((r)->r_bustag, (r)->r_bushandle, (o))
  62 #define bus_write_4(r, o, v) \
  63                     bus_space_write_4((r)->r_bustag, (r)->r_bushandle, (o), (v))
  64
  65 MALLOC_DECLARE(M_AGP);
  66
  67 enum {
  68         CHIP_I810,      /* i810/i815 */
  69         CHIP_I830,      /* 830M/845G */
  70         CHIP_I855,      /* 852GM/855GM/865G */
  71         CHIP_I915,      /* 915G/915GM */
  72         CHIP_I965,      /* G965 */
  73         CHIP_G33,       /* G33/Q33/Q35 */
  74         CHIP_IGD,       /* G33 like IGD */
  75         CHIP_G4X,       /* G45/Q45 */
  76 };
  77
  78 /* The i810 through i855 have the registers at BAR 1, and the GATT gets
  79  * allocated by us.  The i915 has registers in BAR 0 and the GATT is at the
  80  * start of the stolen memory, and should only be accessed by the OS through
  81  * BAR 3.  The G965 has registers and GATT in the same BAR (0) -- first 512KB
  82  * is registers, second 512KB is GATT.
  83  */
  84 static struct resource_spec agp_i810_res_spec[] = {
  85         { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
  86         { -1, 0 }
  87 };
  88
  89 static struct resource_spec agp_i915_res_spec[] = {
  90         { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
  91         { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
  92         { -1, 0 }
  93 };
  94
  95 static struct resource_spec agp_i965_res_spec[] = {
  96         { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
  97         { -1, 0 }
  98 };
  99
 100 struct agp_i810_softc {
 101         struct agp_softc agp;
 102         u_int32_t initial_aperture;     /* aperture size at startup */
 103         struct agp_gatt *gatt;
 104         int chiptype;                   /* i810-like or i830 */
 105         u_int32_t dcache_size;          /* i810 only */
 106         u_int32_t stolen;               /* number of i830/845 gtt entries for stolen memory */
 107         device_t bdev;                  /* bridge device */
 108
 109         void *argb_cursor;              /* contigmalloc area for ARGB cursor */
 110
 111         struct resource_spec * sc_res_spec;
 112         struct resource *sc_res[2];
 113 };
 114
 115 /* For adding new devices, devid is the id of the graphics controller
 116  * (pci:0:2:0, for example).  The placeholder (usually at pci:0:2:1) for the
 117  * second head should never be added.  The bridge_offset is the offset to
 118  * subtract from devid to get the id of the hostb that the device is on.
 119  */
 120 static const struct agp_i810_match {
 121         int devid;
 122         int chiptype;
 123         int bridge_offset;
 124         char *name;
 125 } agp_i810_matches[] = {
 126         {0x71218086, CHIP_I810, 0x00010000,
 127             "Intel 82810 (i810 GMCH) SVGA controller"},
 128         {0x71238086, CHIP_I810, 0x00010000,
 129             "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
 130         {0x71258086, CHIP_I810, 0x00010000,
 131             "Intel 82810E (i810E GMCH) SVGA controller"},
 132         {0x11328086, CHIP_I810, 0x00020000,
 133             "Intel 82815 (i815 GMCH) SVGA controller"},
 134         {0x35778086, CHIP_I830, 0x00020000,
 135             "Intel 82830M (830M GMCH) SVGA controller"},
 136         {0x25628086, CHIP_I830, 0x00020000,
 137             "Intel 82845M (845M GMCH) SVGA controller"},
 138         {0x35828086, CHIP_I855, 0x00020000,
 139             "Intel 82852/855GM SVGA controller"},
 140         {0x25728086, CHIP_I855, 0x00020000,
 141             "Intel 82865G (865G GMCH) SVGA controller"},
 142         {0x25828086, CHIP_I915, 0x00020000,
 143             "Intel 82915G (915G GMCH) SVGA controller"},
 144         {0x258A8086, CHIP_I915, 0x00020000,
 145             "Intel E7221 SVGA controller"},
 146         {0x25928086, CHIP_I915, 0x00020000,
 147             "Intel 82915GM (915GM GMCH) SVGA controller"},
 148         {0x27728086, CHIP_I915, 0x00020000,
 149             "Intel 82945G (945G GMCH) SVGA controller"},
 150         {0x27A28086, CHIP_I915, 0x00020000,
 151             "Intel 82945GM (945GM GMCH) SVGA controller"},
 152         {0x27AE8086, CHIP_I915, 0x00020000,
 153             "Intel 945GME SVGA controller"},
 154         {0x29728086, CHIP_I965, 0x00020000,
 155             "Intel 946GZ SVGA controller"},
 156         {0x29828086, CHIP_I965, 0x00020000,
 157             "Intel G965 SVGA controller"},
 158         {0x29928086, CHIP_I965, 0x00020000,
 159             "Intel Q965 SVGA controller"},
 160         {0x29A28086, CHIP_I965, 0x00020000,
 161             "Intel G965 SVGA controller"},
 162         {0x29B28086, CHIP_G33, 0x00020000,
 163             "Intel Q35 SVGA controller"},
 164         {0x29C28086, CHIP_G33, 0x00020000,
 165             "Intel G33 SVGA controller"},
 166         {0x29D28086, CHIP_G33, 0x00020000,
 167             "Intel Q33 SVGA controller"},
 168         {0x2A028086, CHIP_I965, 0x00020000,
 169             "Intel GM965 SVGA controller"},
 170         {0x2A128086, CHIP_I965, 0x00020000,
 171             "Intel GME965 SVGA controller"},
 172         {0x2A428086, CHIP_G4X, 0x00020000,
 173             "Intel GM45 SVGA controller"},
 174         {0x2E028086, CHIP_G4X, 0x00020000,
 175             "Intel 4 Series SVGA controller"},
 176         {0x2E128086, CHIP_G4X, 0x00020000,
 177             "Intel Q45 SVGA controller"},
 178         {0x2E228086, CHIP_G4X, 0x00020000,
 179             "Intel G45 SVGA controller"},
 180         {0x2E328086, CHIP_G4X, 0x00020000,
 181             "Intel G41 SVGA controller"},
 182         {0xA0018086, CHIP_IGD, 0x00010000,
 183             "Intel IGD SVGA controller"},
 184         {0xA0118086, CHIP_IGD, 0x00010000,
 185             "Intel IGD SVGA controller"},
 186         {0, 0, 0, NULL}
 187 };
 188
 189 static const struct agp_i810_match*
 190 agp_i810_match(device_t dev)
 191 {
 192         int i, devid;
 193
 194         if (pci_get_class(dev) != PCIC_DISPLAY
 195             || pci_get_subclass(dev) != PCIS_DISPLAY_VGA)
 196                 return NULL;
 197
 198         devid = pci_get_devid(dev);
 199         for (i = 0; agp_i810_matches[i].devid != 0; i++) {
 200                 if (agp_i810_matches[i].devid == devid)
 201                     break;
 202         }
 203         if (agp_i810_matches[i].devid == 0)
 204                 return NULL;
 205         else
 206                 return &agp_i810_matches[i];
 207 }
 208
 209 /*
 210  * Find bridge device.
 211  */
 212 static device_t
 213 agp_i810_find_bridge(device_t dev)
 214 {
 215         device_t *children, child;
 216         int nchildren, i;
 217         u_int32_t devid;
 218         const struct agp_i810_match *match;
 219
 220         match = agp_i810_match(dev);
 221         devid = match->devid - match->bridge_offset;
 222
 223         if (device_get_children(device_get_parent(device_get_parent(dev)),
 224                     &children, &nchildren))
 225                 return 0;
 226
 227         for (i = 0; i < nchildren; i++) {
 228                 child = children[i];
 229
 230                 if (pci_get_devid(child) == devid) {
 231                         kfree(children, M_TEMP);
 232                         return child;
 233                 }
 234         }
 235         kfree(children, M_TEMP);
 236         return 0;
 237 }
 238
 239 static void
 240 agp_i810_identify(driver_t *driver, device_t parent)
 241 {
 242
 243         if (device_find_child(parent, "agp", -1) == NULL &&
 244             agp_i810_match(parent))
 245                 device_add_child(parent, "agp", -1);
 246 }
 247
 248 static int
 249 agp_i810_probe(device_t dev)
 250 {
 251         device_t bdev;
 252         const struct agp_i810_match *match;
 253         u_int8_t smram;
 254         int gcc1, deven;
 255
 256         if (resource_disabled("agp", device_get_unit(dev)))
 257                 return (ENXIO);
 258         match = agp_i810_match(dev);
 259         if (match == NULL)
 260                 return ENXIO;
 261
 262         bdev = agp_i810_find_bridge(dev);
 263         if (!bdev) {
 264                 if (bootverbose)
 265                         kprintf("I810: can't find bridge device\n");
 266                 return ENXIO;
 267         }
 268
 269         /*
 270          * checking whether internal graphics device has been activated.
 271          */
 272         switch (match->chiptype) {
 273         case CHIP_I810:
 274                 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
 275                 if ((smram & AGP_I810_SMRAM_GMS) ==
 276                     AGP_I810_SMRAM_GMS_DISABLED) {
 277                         if (bootverbose)
 278                                 kprintf("I810: disabled, not probing\n");
 279                         return ENXIO;
 280                 }
 281                 break;
 282         case CHIP_I830:
 283         case CHIP_I855:
 284                 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
 285                 if ((gcc1 & AGP_I830_GCC1_DEV2) ==
 286                     AGP_I830_GCC1_DEV2_DISABLED) {
 287                         if (bootverbose)
 288                                 kprintf("I830: disabled, not probing\n");
 289                         return ENXIO;
 290                 }
 291                 break;
 292         case CHIP_I915:
 293         case CHIP_I965:
 294         case CHIP_G33:
 295         case CHIP_IGD:
 296         case CHIP_G4X:
 297                 deven = pci_read_config(bdev, AGP_I915_DEVEN, 4);
 298                 if ((deven & AGP_I915_DEVEN_D2F0) ==
 299                     AGP_I915_DEVEN_D2F0_DISABLED) {
 300                         if (bootverbose)
 301                                 kprintf("I915: disabled, not probing\n");
 302                         return ENXIO;
 303                 }
 304                 break;
 305         }
 306
 307         device_verbose(dev);
 308         if (match->devid == 0x35828086) {
 309                 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
 310                 case AGP_I855_GME:
 311                         device_set_desc(dev,
 312                             "Intel 82855GME (855GME GMCH) SVGA controller");
 313                         break;
 314                 case AGP_I855_GM:
 315                         device_set_desc(dev,
 316                             "Intel 82855GM (855GM GMCH) SVGA controller");
 317                         break;
 318                 case AGP_I852_GME:
 319                         device_set_desc(dev,
 320                             "Intel 82852GME (852GME GMCH) SVGA controller");
 321                         break;
 322                 case AGP_I852_GM:
 323                         device_set_desc(dev,
 324                             "Intel 82852GM (852GM GMCH) SVGA controller");
 325                         break;
 326                 default:
 327                         device_set_desc(dev,
 328                             "Intel 8285xM (85xGM GMCH) SVGA controller");
 329                         break;
 330                 }
 331         } else {
 332                 device_set_desc(dev, match->name);
 333         }
 334
 335         return BUS_PROBE_DEFAULT;
 336 }
 337
 338 static void
 339 agp_i810_dump_regs(device_t dev)
 340 {
 341         struct agp_i810_softc *sc = device_get_softc(dev);
 342
 343         device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
 344             bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
 345
 346         switch (sc->chiptype) {
 347         case CHIP_I810:
 348                 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
 349                     pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
 350                 break;
 351         case CHIP_I830:
 352                 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
 353                     pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
 354                 break;
 355         case CHIP_I855:
 356                 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
 357                     pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
 358                 break;
 359         case CHIP_I915:
 360         case CHIP_I965:
 361         case CHIP_G33:
 362         case CHIP_IGD:
 363         case CHIP_G4X:
 364                 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
 365                     pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
 366                 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
 367                     pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
 368                 break;
 369         }
 370         device_printf(dev, "Aperture resource size: %d bytes\n",
 371             AGP_GET_APERTURE(dev));
 372 }
 373
 374 static int
 375 agp_i810_attach(device_t dev)
 376 {
 377         struct agp_i810_softc *sc = device_get_softc(dev);
 378         struct agp_gatt *gatt;
 379         const struct agp_i810_match *match;
 380         int error;
 381
 382         sc->bdev = agp_i810_find_bridge(dev);
 383         if (!sc->bdev)
 384                 return ENOENT;
 385
 386         match = agp_i810_match(dev);
 387         sc->chiptype = match->chiptype;
 388
 389         switch (sc->chiptype) {
 390         case CHIP_I810:
 391         case CHIP_I830:
 392         case CHIP_I855:
 393                 sc->sc_res_spec = agp_i810_res_spec;
 394                 agp_set_aperture_resource(dev, AGP_APBASE);
 395                 break;
 396         case CHIP_I915:
 397         case CHIP_G33:
 398         case CHIP_IGD:
 399                 sc->sc_res_spec = agp_i915_res_spec;
 400                 agp_set_aperture_resource(dev, AGP_I915_GMADR);
 401                 break;
 402         case CHIP_I965:
 403         case CHIP_G4X:
 404                 sc->sc_res_spec = agp_i965_res_spec;
 405                 agp_set_aperture_resource(dev, AGP_I915_GMADR);
 406                 break;
 407         }
 408
 409         error = agp_generic_attach(dev);
 410         if (error)
 411                 return error;
 412
 413         if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 &&
 414             sc->chiptype != CHIP_IGD && sc->chiptype != CHIP_G4X &&
 415             ptoa((vm_paddr_t)Maxmem) > 0xfffffffful)
 416         {
 417                 device_printf(dev, "agp_i810.c does not support physical "
 418                     "memory above 4GB.\n");
 419                 return ENOENT;
 420         }
 421
 422         if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) {
 423                 agp_generic_detach(dev);
 424                 return ENODEV;
 425         }
 426
 427         sc->initial_aperture = AGP_GET_APERTURE(dev);
 428         if (sc->initial_aperture == 0) {
 429                 device_printf(dev, "bad initial aperture size, disabling\n");
 430                 return ENXIO;
 431         }
 432
 433         gatt = kmalloc( sizeof(struct agp_gatt), M_AGP, M_INTWAIT);
 434         sc->gatt = gatt;
 435
 436         gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
 437
 438         if ( sc->chiptype == CHIP_I810 ) {
 439                 /* Some i810s have on-chip memory called dcache */
 440                 if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) &
 441                     AGP_I810_DRT_POPULATED)
 442                         sc->dcache_size = 4 * 1024 * 1024;
 443                 else
 444                         sc->dcache_size = 0;
 445
 446                 /* According to the specs the gatt on the i810 must be 64k */
 447                 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0,
 448                                         0, ~0, PAGE_SIZE, 0);
 449                 if (!gatt->ag_virtual) {
 450                         if (bootverbose)
 451                                 device_printf(dev, "contiguous allocation failed\n");
 452                         bus_release_resources(dev, sc->sc_res_spec,
 453                             sc->sc_res);
 454                         kfree(gatt, M_AGP);
 455                         agp_generic_detach(dev);
 456                         return ENOMEM;
 457                 }
 458                 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t));
 459
 460                 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
 461                 agp_flush_cache();
 462                 /* Install the GATT. */
 463                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
 464                     gatt->ag_physical | 1);
 465         } else if ( sc->chiptype == CHIP_I830 ) {
 466                 /* The i830 automatically initializes the 128k gatt on boot. */
 467                 unsigned int gcc1, pgtblctl;
 468
 469                 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
 470                 switch (gcc1 & AGP_I830_GCC1_GMS) {
 471                         case AGP_I830_GCC1_GMS_STOLEN_512:
 472                                 sc->stolen = (512 - 132) * 1024 / 4096;
 473                                 break;
 474                         case AGP_I830_GCC1_GMS_STOLEN_1024:
 475                                 sc->stolen = (1024 - 132) * 1024 / 4096;
 476                                 break;
 477                         case AGP_I830_GCC1_GMS_STOLEN_8192:
 478                                 sc->stolen = (8192 - 132) * 1024 / 4096;
 479                                 break;
 480                         default:
 481                                 sc->stolen = 0;
 482                                 device_printf(dev, "unknown memory configuration, disabling\n");
 483                                 bus_release_resources(dev, sc->sc_res_spec,
 484                                     sc->sc_res);
 485                                 kfree(gatt, M_AGP);
 486                                 agp_generic_detach(dev);
 487                                 return EINVAL;
 488                 }
 489                 if (sc->stolen > 0) {
 490                         device_printf(dev, "detected %dk stolen memory\n",
 491                             sc->stolen * 4);
 492                 }
 493                 device_printf(dev, "aperture size is %dM\n",
 494                     sc->initial_aperture / 1024 / 1024);
 495
 496                 /* GATT address is already in there, make sure it's enabled */
 497                 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
 498                 pgtblctl |= 1;
 499                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
 500
 501                 gatt->ag_physical = pgtblctl & ~1;
 502         } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 ||
 503             sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
 504             sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
 505                 unsigned int gcc1, pgtblctl, stolen, gtt_size;
 506
 507                 /* Stolen memory is set up at the beginning of the aperture by
 508                  * the BIOS, consisting of the GATT followed by 4kb for the
 509                  * BIOS display.
 510                  */
 511                 switch (sc->chiptype) {
 512                 case CHIP_I855:
 513                         gtt_size = 128;
 514                         break;
 515                 case CHIP_I915:
 516                         gtt_size = 256;
 517                         break;
 518                 case CHIP_I965:
 519                         switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
 520                             AGP_I810_PGTBL_SIZE_MASK) {
 521                         case AGP_I810_PGTBL_SIZE_128KB:
 522                                 gtt_size = 128;
 523                                 break;
 524                         case AGP_I810_PGTBL_SIZE_256KB:
 525                                 gtt_size = 256;
 526                                 break;
 527                         case AGP_I810_PGTBL_SIZE_512KB:
 528                                 gtt_size = 512;
 529                                 break;
 530                         case AGP_I965_PGTBL_SIZE_1MB:
 531                                 gtt_size = 1024;
 532                                 break;
 533                         case AGP_I965_PGTBL_SIZE_2MB:
 534                                 gtt_size = 2048;
 535                                 break;
 536                         case AGP_I965_PGTBL_SIZE_1_5MB:
 537                                 gtt_size = 1024 + 512;
 538                                 break;
 539                         default:
 540                                 device_printf(dev, "Bad PGTBL size\n");
 541                                 bus_release_resources(dev, sc->sc_res_spec,
 542                                     sc->sc_res);
 543                                 kfree(gatt, M_AGP);
 544                                 agp_generic_detach(dev);
 545                                 return EINVAL;
 546                         }
 547                         break;
 548                 case CHIP_G33:
 549                         gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
 550                         switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
 551                         case AGP_G33_MGGC_GGMS_SIZE_1M:
 552                                 gtt_size = 1024;
 553                                 break;
 554                         case AGP_G33_MGGC_GGMS_SIZE_2M:
 555                                 gtt_size = 2048;
 556                                 break;
 557                         default:
 558                                 device_printf(dev, "Bad PGTBL size\n");
 559                                 bus_release_resources(dev, sc->sc_res_spec,
 560                                     sc->sc_res);
 561                                 kfree(gatt, M_AGP);
 562                                 agp_generic_detach(dev);
 563                                 return EINVAL;
 564                         }
 565                         break;
 566                 case CHIP_IGD:
 567                 case CHIP_G4X:
 568                         gtt_size = 0;
 569                         break;
 570                 default:
 571                         device_printf(dev, "Bad chiptype\n");
 572                         bus_release_resources(dev, sc->sc_res_spec,
 573                             sc->sc_res);
 574                         kfree(gatt, M_AGP);
 575                         agp_generic_detach(dev);
 576                         return EINVAL;
 577                 }
 578
 579                 /* GCC1 is called MGGC on i915+ */
 580                 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
 581                 switch (gcc1 & AGP_I855_GCC1_GMS) {
 582                 case AGP_I855_GCC1_GMS_STOLEN_1M:
 583                         stolen = 1024;
 584                         break;
 585                 case AGP_I855_GCC1_GMS_STOLEN_4M:
 586                         stolen = 4 * 1024;
 587                         break;
 588                 case AGP_I855_GCC1_GMS_STOLEN_8M:
 589                         stolen = 8 * 1024;
 590                         break;
 591                 case AGP_I855_GCC1_GMS_STOLEN_16M:
 592                         stolen = 16 * 1024;
 593                         break;
 594                 case AGP_I855_GCC1_GMS_STOLEN_32M:
 595                         stolen = 32 * 1024;
 596                         break;
 597                 case AGP_I915_GCC1_GMS_STOLEN_48M:
 598                         if (sc->chiptype == CHIP_I915 ||
 599                             sc->chiptype == CHIP_I965 ||
 600                             sc->chiptype == CHIP_G33 ||
 601                             sc->chiptype == CHIP_IGD ||
 602                             sc->chiptype == CHIP_G4X) {
 603                                 stolen = 48 * 1024;
 604                         } else {
 605                                 stolen = 0;
 606                         }
 607                         break;
 608                 case AGP_I915_GCC1_GMS_STOLEN_64M:
 609                         if (sc->chiptype == CHIP_I915 ||
 610                             sc->chiptype == CHIP_I965 ||
 611                             sc->chiptype == CHIP_G33 ||
 612                             sc->chiptype == CHIP_IGD ||
 613                             sc->chiptype == CHIP_G4X) {
 614                                 stolen = 64 * 1024;
 615                         } else {
 616                                 stolen = 0;
 617                         }
 618                         break;
 619                 case AGP_G33_GCC1_GMS_STOLEN_128M:
 620                         if (sc->chiptype == CHIP_I965 ||
 621                             sc->chiptype == CHIP_G33 ||
 622                             sc->chiptype == CHIP_IGD ||
 623                             sc->chiptype == CHIP_G4X) {
 624                                 stolen = 128 * 1024;
 625                         } else {
 626                                 stolen = 0;
 627                         }
 628                         break;
 629                 case AGP_G33_GCC1_GMS_STOLEN_256M:
 630                         if (sc->chiptype == CHIP_I965 ||
 631                             sc->chiptype == CHIP_G33 ||
 632                             sc->chiptype == CHIP_IGD ||
 633                             sc->chiptype == CHIP_G4X) {
 634                                 stolen = 256 * 1024;
 635                         } else {
 636                                 stolen = 0;
 637                         }
 638                         break;
 639                 case AGP_G4X_GCC1_GMS_STOLEN_96M:
 640                         if (sc->chiptype == CHIP_I965 ||
 641                             sc->chiptype == CHIP_G4X) {
 642                                 stolen = 96 * 1024;
 643                         } else {
 644                                 stolen = 0;
 645                         }
 646                         break;
 647                 case AGP_G4X_GCC1_GMS_STOLEN_160M:
 648                         if (sc->chiptype == CHIP_I965 ||
 649                             sc->chiptype == CHIP_G4X) {
 650                                 stolen = 160 * 1024;
 651                         } else {
 652                                 stolen = 0;
 653                         }
 654                         break;
 655                 case AGP_G4X_GCC1_GMS_STOLEN_224M:
 656                         if (sc->chiptype == CHIP_I965 ||
 657                             sc->chiptype == CHIP_G4X) {
 658                                 stolen = 224 * 1024;
 659                         } else {
 660                                 stolen = 0;
 661                         }
 662                         break;
 663                 case AGP_G4X_GCC1_GMS_STOLEN_352M:
 664                         if (sc->chiptype == CHIP_I965 ||
 665                             sc->chiptype == CHIP_G4X) {
 666                                 stolen = 352 * 1024;
 667                         } else {
 668                                 stolen = 0;
 669                         }
 670                         break;
 671                 default:
 672                         device_printf(dev, "unknown memory configuration, "
 673                             "disabling\n");
 674                         bus_release_resources(dev, sc->sc_res_spec,
 675                             sc->sc_res);
 676                         kfree(gatt, M_AGP);
 677                         agp_generic_detach(dev);
 678                         return EINVAL;
 679                 }
 680
 681                 gtt_size += 4;
 682
 683                 sc->stolen = (stolen - gtt_size) * 1024 / 4096;
 684                 if (sc->stolen > 0)
 685                         device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
 686                 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
 687
 688                 /* GATT address is already in there, make sure it's enabled */
 689                 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
 690                 pgtblctl |= 1;
 691                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
 692
 693                 gatt->ag_physical = pgtblctl & ~1;
 694         }
 695
 696         if (0)
 697                 agp_i810_dump_regs(dev);
 698
 699         return 0;
 700 }
 701
 702 static int
 703 agp_i810_detach(device_t dev)
 704 {
 705         struct agp_i810_softc *sc = device_get_softc(dev);
 706
 707         agp_free_cdev(dev);
 708
 709         /* Clear the GATT base. */
 710         if ( sc->chiptype == CHIP_I810 ) {
 711                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
 712         } else {
 713                 unsigned int pgtblctl;
 714                 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
 715                 pgtblctl &= ~1;
 716                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
 717         }
 718
 719         /* Put the aperture back the way it started. */
 720         AGP_SET_APERTURE(dev, sc->initial_aperture);
 721
 722         if ( sc->chiptype == CHIP_I810 ) {
 723                 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
 724         }
 725         kfree(sc->gatt, M_AGP);
 726
 727         bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
 728         agp_free_res(dev);
 729
 730         return 0;
 731 }
 732
 733 static int
 734 agp_i810_resume(device_t dev)
 735 {
 736         struct agp_i810_softc *sc;
 737         sc = device_get_softc(dev);
 738
 739         AGP_SET_APERTURE(dev, sc->initial_aperture);
 740
 741         /* Install the GATT. */
 742         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
 743         sc->gatt->ag_physical | 1);
 744
 745         return (bus_generic_resume(dev));
 746 }
 747
 748 /**
 749  * Sets the PCI resource size of the aperture on i830-class and below chipsets,
 750  * while returning failure on later chipsets when an actual change is
 751  * requested.
 752  *
 753  * This whole function is likely bogus, as the kernel would probably need to
 754  * reconfigure the placement of the AGP aperture if a larger size is requested,
 755  * which doesn't happen currently.
 756  */
 757 static int
 758 agp_i810_set_aperture(device_t dev, u_int32_t aperture)
 759 {
 760         struct agp_i810_softc *sc = device_get_softc(dev);
 761         u_int16_t miscc, gcc1;
 762
 763         switch (sc->chiptype) {
 764         case CHIP_I810:
 765                 /*
 766                  * Double check for sanity.
 767                  */
 768                 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
 769                         device_printf(dev, "bad aperture size %d\n", aperture);
 770                         return EINVAL;
 771                 }
 772
 773                 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
 774                 miscc &= ~AGP_I810_MISCC_WINSIZE;
 775                 if (aperture == 32 * 1024 * 1024)
 776                         miscc |= AGP_I810_MISCC_WINSIZE_32;
 777                 else
 778                         miscc |= AGP_I810_MISCC_WINSIZE_64;
 779
 780                 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
 781                 break;
 782         case CHIP_I830:
 783                 if (aperture != 64 * 1024 * 1024 &&
 784                     aperture != 128 * 1024 * 1024) {
 785                         device_printf(dev, "bad aperture size %d\n", aperture);
 786                         return EINVAL;
 787                 }
 788                 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
 789                 gcc1 &= ~AGP_I830_GCC1_GMASIZE;
 790                 if (aperture == 64 * 1024 * 1024)
 791                         gcc1 |= AGP_I830_GCC1_GMASIZE_64;
 792                 else
 793                         gcc1 |= AGP_I830_GCC1_GMASIZE_128;
 794
 795                 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
 796                 break;
 797         case CHIP_I855:
 798         case CHIP_I915:
 799         case CHIP_I965:
 800         case CHIP_G33:
 801         case CHIP_IGD:
 802         case CHIP_G4X:
 803                 return agp_generic_set_aperture(dev, aperture);
 804         }
 805
 806         return 0;
 807 }
 808
 809 /**
 810  * Writes a GTT entry mapping the page at the given offset from the beginning
 811  * of the aperture to the given physical address.
 812  */
 813 static void
 814 agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical,
 815     int enabled)
 816 {
 817         struct agp_i810_softc *sc = device_get_softc(dev);
 818         u_int32_t pte;
 819
 820         pte = (u_int32_t)physical | 1;
 821         if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
 822             sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
 823                 pte |= (physical & 0x0000000f00000000ull) >> 28;
 824         } else {
 825                 /* If we do actually have memory above 4GB on an older system,
 826                  * crash cleanly rather than scribble on system memory,
 827                  * so we know we need to fix it.
 828                  */
 829                 KASSERT((pte & 0x0000000f00000000ull) == 0,
 830                     (">4GB physical address in agp"));
 831         }
 832
 833         switch (sc->chiptype) {
 834         case CHIP_I810:
 835         case CHIP_I830:
 836         case CHIP_I855:
 837                 bus_write_4(sc->sc_res[0],
 838                     AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte);
 839                 break;
 840         case CHIP_I915:
 841         case CHIP_G33:
 842         case CHIP_IGD:
 843                 bus_write_4(sc->sc_res[1],
 844                     (offset >> AGP_PAGE_SHIFT) * 4, pte);
 845                 break;
 846         case CHIP_I965:
 847                 bus_write_4(sc->sc_res[0],
 848                     (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte);
 849                 break;
 850         case CHIP_G4X:
 851                 bus_write_4(sc->sc_res[0],
 852                     (offset >> AGP_PAGE_SHIFT) * 4 + (2 * 1024 * 1024), pte);
 853                 break;
 854         }
 855 }
 856
 857 static int
 858 agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical)
 859 {
 860         struct agp_i810_softc *sc = device_get_softc(dev);
 861
 862         if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
 863                 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries);
 864                 return EINVAL;
 865         }
 866
 867         if ( sc->chiptype != CHIP_I810 ) {
 868                 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
 869                         device_printf(dev, "trying to bind into stolen memory");
 870                         return EINVAL;
 871                 }
 872         }
 873
 874         agp_i810_write_gtt_entry(dev, offset, physical, 1);
 875
 876         return 0;
 877 }
 878
 879 static int
 880 agp_i810_unbind_page(device_t dev, int offset)
 881 {
 882         struct agp_i810_softc *sc = device_get_softc(dev);
 883
 884         if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
 885                 return EINVAL;
 886
 887         if ( sc->chiptype != CHIP_I810 ) {
 888                 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
 889                         device_printf(dev, "trying to unbind from stolen memory");
 890                         return EINVAL;
 891                 }
 892         }
 893
 894         agp_i810_write_gtt_entry(dev, offset, 0, 0);
 895
 896         return 0;
 897 }
 898
 899 /*
 900  * Writing via memory mapped registers already flushes all TLBs.
 901  */
 902 static void
 903 agp_i810_flush_tlb(device_t dev)
 904 {
 905 }
 906
 907 static int
 908 agp_i810_enable(device_t dev, u_int32_t mode)
 909 {
 910
 911         return 0;
 912 }
 913
 914 static struct agp_memory *
 915 agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
 916 {
 917         struct agp_i810_softc *sc = device_get_softc(dev);
 918         struct agp_memory *mem;
 919
 920         if ((size & (AGP_PAGE_SIZE - 1)) != 0)
 921                 return 0;
 922
 923         if (sc->agp.as_allocated + size > sc->agp.as_maxmem)
 924                 return 0;
 925
 926         if (type == 1) {
 927                 /*
 928                  * Mapping local DRAM into GATT.
 929                  */
 930                 if ( sc->chiptype != CHIP_I810 )
 931                         return 0;
 932                 if (size != sc->dcache_size)
 933                         return 0;
 934         } else if (type == 2) {
 935                 /*
 936                  * Type 2 is the contiguous physical memory type, that hands
 937                  * back a physical address.  This is used for cursors on i810.
 938                  * Hand back as many single pages with physical as the user
 939                  * wants, but only allow one larger allocation (ARGB cursor)
 940                  * for simplicity.
 941                  */
 942                 if (size != AGP_PAGE_SIZE) {
 943                         if (sc->argb_cursor != NULL)
 944                                 return 0;
 945
 946                         /* Allocate memory for ARGB cursor, if we can. */
 947                         sc->argb_cursor = contigmalloc(size, M_AGP,
 948                            0, 0, ~0, PAGE_SIZE, 0);
 949                         if (sc->argb_cursor == NULL)
 950                                 return 0;
 951                 }
 952         }
 953
 954         mem = kmalloc(sizeof *mem, M_AGP, M_INTWAIT);
 955         mem->am_id = sc->agp.as_nextid++;
 956         mem->am_size = size;
 957         mem->am_type = type;
 958         if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
 959                 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
 960                                                  atop(round_page(size)));
 961         else
 962                 mem->am_obj = 0;
 963
 964         if (type == 2) {
 965                 if (size == AGP_PAGE_SIZE) {
 966                         /*
 967                          * Allocate and wire down the page now so that we can
 968                          * get its physical address.
 969                          */
 970                         vm_page_t m;
 971
 972                         m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NORMAL |
 973                                                          VM_ALLOC_ZERO |
 974                                                          VM_ALLOC_RETRY);
 975                         vm_page_wire(m);
 976                         mem->am_physical = VM_PAGE_TO_PHYS(m);
 977                         vm_page_wakeup(m);
 978                 } else {
 979                         /* Our allocation is already nicely wired down for us.
 980                          * Just grab the physical address.
 981                          */
 982                         mem->am_physical = vtophys(sc->argb_cursor);
 983                 }
 984         } else {
 985                 mem->am_physical = 0;
 986         }
 987
 988         mem->am_offset = 0;
 989         mem->am_is_bound = 0;
 990         TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
 991         sc->agp.as_allocated += size;
 992
 993         return mem;
 994 }
 995
 996 static int
 997 agp_i810_free_memory(device_t dev, struct agp_memory *mem)
 998 {
 999         struct agp_i810_softc *sc = device_get_softc(dev);
1000
1001         if (mem->am_is_bound)
1002                 return EBUSY;
1003
1004         if (mem->am_type == 2) {
1005                 if (mem->am_size == AGP_PAGE_SIZE) {
1006                         /*
1007                          * Unwire the page which we wired in alloc_memory.
1008                          */
1009                         vm_page_t m;
1010
1011                         vm_object_hold(mem->am_obj);
1012                         m = vm_page_lookup_busy_wait(mem->am_obj, 0,
1013                                                      FALSE, "agppg");
1014                         vm_object_drop(mem->am_obj);
1015                         vm_page_unwire(m, 0);
1016                         vm_page_wakeup(m);
1017                 } else {
1018                         contigfree(sc->argb_cursor, mem->am_size, M_AGP);
1019                         sc->argb_cursor = NULL;
1020                 }
1021         }
1022
1023         sc->agp.as_allocated -= mem->am_size;
1024         TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
1025         if (mem->am_obj)
1026                 vm_object_deallocate(mem->am_obj);
1027         kfree(mem, M_AGP);
1028         return 0;
1029 }
1030
1031 static int
1032 agp_i810_bind_memory(device_t dev, struct agp_memory *mem,
1033                      vm_offset_t offset)
1034 {
1035         struct agp_i810_softc *sc = device_get_softc(dev);
1036         vm_offset_t i;
1037
1038         /* Do some sanity checks first. */
1039         if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 ||
1040             offset + mem->am_size > AGP_GET_APERTURE(dev)) {
1041                 device_printf(dev, "binding memory at bad offset %#x\n",
1042                     (int)offset);
1043                 return EINVAL;
1044         }
1045
1046         if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1047                 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1048                 if (mem->am_is_bound) {
1049                         lockmgr(&sc->agp.as_lock, LK_RELEASE);
1050                         return EINVAL;
1051                 }
1052                 /* The memory's already wired down, just stick it in the GTT. */
1053                 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1054                         agp_i810_write_gtt_entry(dev, offset + i,
1055                             mem->am_physical + i, 1);
1056                 }
1057                 agp_flush_cache();
1058                 mem->am_offset = offset;
1059                 mem->am_is_bound = 1;
1060                 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1061                 return 0;
1062         }
1063
1064         if (mem->am_type != 1)
1065                 return agp_generic_bind_memory(dev, mem, offset);
1066
1067         if ( sc->chiptype != CHIP_I810 )
1068                 return EINVAL;
1069
1070         for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1071                 bus_write_4(sc->sc_res[0],
1072                     AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
1073         }
1074
1075         return 0;
1076 }
1077
1078 static int
1079 agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
1080 {
1081         struct agp_i810_softc *sc = device_get_softc(dev);
1082         vm_offset_t i;
1083
1084         if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1085                 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1086                 if (!mem->am_is_bound) {
1087                         lockmgr(&sc->agp.as_lock, LK_RELEASE);
1088                         return EINVAL;
1089                 }
1090
1091                 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1092                         agp_i810_write_gtt_entry(dev, mem->am_offset + i,
1093                             0, 0);
1094                 }
1095                 agp_flush_cache();
1096                 mem->am_is_bound = 0;
1097                 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1098                 return 0;
1099         }
1100
1101         if (mem->am_type != 1)
1102                 return agp_generic_unbind_memory(dev, mem);
1103
1104         if ( sc->chiptype != CHIP_I810 )
1105                 return EINVAL;
1106
1107         for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1108                 bus_write_4(sc->sc_res[0],
1109                     AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0);
1110         }
1111
1112         return 0;
1113 }
1114
1115 static device_method_t agp_i810_methods[] = {
1116         /* Device interface */
1117         DEVMETHOD(device_identify,      agp_i810_identify),
1118         DEVMETHOD(device_probe,         agp_i810_probe),
1119         DEVMETHOD(device_attach,        agp_i810_attach),
1120         DEVMETHOD(device_detach,        agp_i810_detach),
1121         DEVMETHOD(device_suspend,       bus_generic_suspend),
1122         DEVMETHOD(device_resume,        agp_i810_resume),
1123
1124         /* AGP interface */
1125         DEVMETHOD(agp_get_aperture,     agp_generic_get_aperture),
1126         DEVMETHOD(agp_set_aperture,     agp_i810_set_aperture),
1127         DEVMETHOD(agp_bind_page,        agp_i810_bind_page),
1128         DEVMETHOD(agp_unbind_page,      agp_i810_unbind_page),
1129         DEVMETHOD(agp_flush_tlb,        agp_i810_flush_tlb),
1130         DEVMETHOD(agp_enable,           agp_i810_enable),
1131         DEVMETHOD(agp_alloc_memory,     agp_i810_alloc_memory),
1132         DEVMETHOD(agp_free_memory,      agp_i810_free_memory),
1133         DEVMETHOD(agp_bind_memory,      agp_i810_bind_memory),
1134         DEVMETHOD(agp_unbind_memory,    agp_i810_unbind_memory),
1135
1136         { 0, 0 }
1137 };
1138
1139 static driver_t agp_i810_driver = {
1140         "agp",
1141         agp_i810_methods,
1142         sizeof(struct agp_i810_softc),
1143 };
1144
1145 static devclass_t agp_devclass;
1146
1147 DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, NULL, NULL);
1148 MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
1149 MODULE_DEPEND(agp_i810, pci, 1, 1, 1);