0eea31ca3a8f3986c1317867746d10834cc032c0
[dragonfly.git] / sys / dev / agp / agp_i810.c
1 /*
2  * Copyright (c) 2000 Doug Rabson
3  * Copyright (c) 2000 Ruslan Ermilov
4  * Copyright (c) 2011 The FreeBSD Foundation
5  * All rights reserved.
6  *
7  * Portions of this software were developed by Konstantin Belousov
8  * under sponsorship from the FreeBSD Foundation.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  * SUCH DAMAGE.
30  *
31  * $FreeBSD: src/sys/dev/agp/agp_i810.c,v 1.56 2010/03/12 21:34:23 rnoland Exp $
32  */
33
34 /*
35  * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
36  * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
37  *
38  * This is generic Intel GTT handling code, morphed from the AGP
39  * bridge code.
40  */
41
42 #include "opt_bus.h"
43
44 #if 0
45 #define KTR_AGP_I810    KTR_DEV
46 #else
47 #define KTR_AGP_I810    0
48 #endif
49
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/malloc.h>
53 #include <sys/kernel.h>
54 #include <sys/bus.h>
55 #include <sys/lock.h>
56 #include <sys/rman.h>
57
58 #include <bus/pci/pcivar.h>
59 #include <bus/pci/pcireg.h>
60 #include "agppriv.h"
61 #include "agpreg.h"
62 #include <dev/agp/agp_i810.h>
63
64 #include <vm/vm.h>
65 #include <vm/vm_object.h>
66 #include <vm/vm_page.h>
67 #include <vm/vm_pageout.h>
68 #include <vm/pmap.h>
69
70 #include <machine/md_var.h>
71
72 #define bus_read_1(r, o) \
73                    bus_space_read_1((r)->r_bustag, (r)->r_bushandle, (o))
74 #define bus_read_4(r, o) \
75                    bus_space_read_4((r)->r_bustag, (r)->r_bushandle, (o))
76 #define bus_write_4(r, o, v) \
77                     bus_space_write_4((r)->r_bustag, (r)->r_bushandle, (o), (v))
78
79 MALLOC_DECLARE(M_AGP);
80
81 struct agp_i810_match;
82
83 static int agp_i810_check_active(device_t bridge_dev);
84 static int agp_i830_check_active(device_t bridge_dev);
85 static int agp_i915_check_active(device_t bridge_dev);
86 static int agp_sb_check_active(device_t bridge_dev);
87
88 static void agp_82852_set_desc(device_t dev,
89     const struct agp_i810_match *match);
90 static void agp_i810_set_desc(device_t dev, const struct agp_i810_match *match);
91
92 static void agp_i810_dump_regs(device_t dev);
93 static void agp_i830_dump_regs(device_t dev);
94 static void agp_i855_dump_regs(device_t dev);
95 static void agp_i915_dump_regs(device_t dev);
96 static void agp_i965_dump_regs(device_t dev);
97 static void agp_sb_dump_regs(device_t dev);
98
99 static int agp_i810_get_stolen_size(device_t dev);
100 static int agp_i830_get_stolen_size(device_t dev);
101 static int agp_i915_get_stolen_size(device_t dev);
102 static int agp_sb_get_stolen_size(device_t dev);
103
104 static int agp_i810_get_gtt_mappable_entries(device_t dev);
105 static int agp_i830_get_gtt_mappable_entries(device_t dev);
106 static int agp_i915_get_gtt_mappable_entries(device_t dev);
107
108 static int agp_i810_get_gtt_total_entries(device_t dev);
109 static int agp_i965_get_gtt_total_entries(device_t dev);
110 static int agp_gen5_get_gtt_total_entries(device_t dev);
111 static int agp_sb_get_gtt_total_entries(device_t dev);
112
113 static int agp_i810_install_gatt(device_t dev);
114 static int agp_i830_install_gatt(device_t dev);
115
116 static void agp_i810_deinstall_gatt(device_t dev);
117 static void agp_i830_deinstall_gatt(device_t dev);
118
119 static void agp_i810_install_gtt_pte(device_t dev, u_int index,
120     vm_offset_t physical, int flags);
121 static void agp_i830_install_gtt_pte(device_t dev, u_int index,
122     vm_offset_t physical, int flags);
123 static void agp_i915_install_gtt_pte(device_t dev, u_int index,
124     vm_offset_t physical, int flags);
125 static void agp_i965_install_gtt_pte(device_t dev, u_int index,
126     vm_offset_t physical, int flags);
127 static void agp_g4x_install_gtt_pte(device_t dev, u_int index,
128     vm_offset_t physical, int flags);
129 static void agp_sb_install_gtt_pte(device_t dev, u_int index,
130     vm_offset_t physical, int flags);
131
132 static void agp_i810_write_gtt(device_t dev, u_int index, uint32_t pte);
133 static void agp_i915_write_gtt(device_t dev, u_int index, uint32_t pte);
134 static void agp_i965_write_gtt(device_t dev, u_int index, uint32_t pte);
135 static void agp_g4x_write_gtt(device_t dev, u_int index, uint32_t pte);
136 static void agp_sb_write_gtt(device_t dev, u_int index, uint32_t pte);
137
138 static u_int32_t agp_i810_read_gtt_pte(device_t dev, u_int index);
139 static u_int32_t agp_i915_read_gtt_pte(device_t dev, u_int index);
140 static u_int32_t agp_i965_read_gtt_pte(device_t dev, u_int index);
141 static u_int32_t agp_g4x_read_gtt_pte(device_t dev, u_int index);
142
143 static vm_paddr_t agp_i810_read_gtt_pte_paddr(device_t dev, u_int index);
144 static vm_paddr_t agp_i915_read_gtt_pte_paddr(device_t dev, u_int index);
145 static vm_paddr_t agp_sb_read_gtt_pte_paddr(device_t dev, u_int index);
146
147 static int agp_i810_set_aperture(device_t dev, u_int32_t aperture);
148 static int agp_i830_set_aperture(device_t dev, u_int32_t aperture);
149 static int agp_i915_set_aperture(device_t dev, u_int32_t aperture);
150
151 static int agp_i810_chipset_flush_setup(device_t dev);
152 static int agp_i915_chipset_flush_setup(device_t dev);
153 static int agp_i965_chipset_flush_setup(device_t dev);
154
155 static void agp_i810_chipset_flush_teardown(device_t dev);
156 static void agp_i915_chipset_flush_teardown(device_t dev);
157 static void agp_i965_chipset_flush_teardown(device_t dev);
158
159 static void agp_i810_chipset_flush(device_t dev);
160 static void agp_i830_chipset_flush(device_t dev);
161 static void agp_i915_chipset_flush(device_t dev);
162
163 enum {
164         CHIP_I810,      /* i810/i815 */
165         CHIP_I830,      /* 830M/845G */
166         CHIP_I855,      /* 852GM/855GM/865G */
167         CHIP_I915,      /* 915G/915GM */
168         CHIP_I965,      /* G965 */
169         CHIP_G33,       /* G33/Q33/Q35 */
170         CHIP_IGD,       /* Pineview */
171         CHIP_G4X,       /* G45/Q45 */
172         CHIP_SB,        /* SandyBridge */
173 };
174
175 /* The i810 through i855 have the registers at BAR 1, and the GATT gets
176  * allocated by us.  The i915 has registers in BAR 0 and the GATT is at the
177  * start of the stolen memory, and should only be accessed by the OS through
178  * BAR 3.  The G965 has registers and GATT in the same BAR (0) -- first 512KB
179  * is registers, second 512KB is GATT.
180  */
181 static struct resource_spec agp_i810_res_spec[] = {
182         { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
183         { -1, 0 }
184 };
185
186 static struct resource_spec agp_i915_res_spec[] = {
187         { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
188         { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
189         { -1, 0 }
190 };
191
192 static struct resource_spec agp_i965_res_spec[] = {
193         { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
194         { -1, 0 }
195 };
196
197 static struct resource_spec agp_g4x_res_spec[] = {
198         { SYS_RES_MEMORY, AGP_G4X_MMADR, RF_ACTIVE | RF_SHAREABLE },
199         { SYS_RES_MEMORY, AGP_G4X_GTTADR, RF_ACTIVE | RF_SHAREABLE },
200         { -1, 0 }
201 };
202
203 struct agp_i810_softc {
204         struct agp_softc agp;
205         u_int32_t initial_aperture;     /* aperture size at startup */
206         struct agp_gatt *gatt;
207         u_int32_t dcache_size;          /* i810 only */
208         u_int32_t stolen;               /* number of i830/845 gtt
209                                            entries for stolen memory */
210         u_int stolen_size;              /* BIOS-reserved graphics memory */
211         u_int gtt_total_entries;        /* Total number of gtt ptes */
212         u_int gtt_mappable_entries;     /* Number of gtt ptes mappable by CPU */
213         device_t bdev;                  /* bridge device */
214         void *argb_cursor;              /* contigmalloc area for ARGB cursor */
215         struct resource *sc_res[2];
216         const struct agp_i810_match *match;
217         int sc_flush_page_rid;
218         struct resource *sc_flush_page_res;
219         void *sc_flush_page_vaddr;
220         int sc_bios_allocated_flush_page;
221 };
222
223 static device_t intel_agp;
224
225 struct agp_i810_driver {
226         int chiptype;
227         int gen;
228         int busdma_addr_mask_sz;
229         struct resource_spec *res_spec;
230         int (*check_active)(device_t);
231         void (*set_desc)(device_t, const struct agp_i810_match *);
232         void (*dump_regs)(device_t);
233         int (*get_stolen_size)(device_t);
234         int (*get_gtt_total_entries)(device_t);
235         int (*get_gtt_mappable_entries)(device_t);
236         int (*install_gatt)(device_t);
237         void (*deinstall_gatt)(device_t);
238         void (*write_gtt)(device_t, u_int, uint32_t);
239         void (*install_gtt_pte)(device_t, u_int, vm_offset_t, int);
240         u_int32_t (*read_gtt_pte)(device_t, u_int);
241         vm_paddr_t (*read_gtt_pte_paddr)(device_t , u_int);
242         int (*set_aperture)(device_t, u_int32_t);
243         int (*chipset_flush_setup)(device_t);
244         void (*chipset_flush_teardown)(device_t);
245         void (*chipset_flush)(device_t);
246 };
247
248 static const struct agp_i810_driver agp_i810_i810_driver = {
249         .chiptype = CHIP_I810,
250         .gen = 1,
251         .busdma_addr_mask_sz = 32,
252         .res_spec = agp_i810_res_spec,
253         .check_active = agp_i810_check_active,
254         .set_desc = agp_i810_set_desc,
255         .dump_regs = agp_i810_dump_regs,
256         .get_stolen_size = agp_i810_get_stolen_size,
257         .get_gtt_mappable_entries = agp_i810_get_gtt_mappable_entries,
258         .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
259         .install_gatt = agp_i810_install_gatt,
260         .deinstall_gatt = agp_i810_deinstall_gatt,
261         .write_gtt = agp_i810_write_gtt,
262         .install_gtt_pte = agp_i810_install_gtt_pte,
263         .read_gtt_pte = agp_i810_read_gtt_pte,
264         .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
265         .set_aperture = agp_i810_set_aperture,
266         .chipset_flush_setup = agp_i810_chipset_flush_setup,
267         .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
268         .chipset_flush = agp_i810_chipset_flush,
269 };
270
271 static const struct agp_i810_driver agp_i810_i815_driver = {
272         .chiptype = CHIP_I810,
273         .gen = 2,
274         .busdma_addr_mask_sz = 32,
275         .res_spec = agp_i810_res_spec,
276         .check_active = agp_i810_check_active,
277         .set_desc = agp_i810_set_desc,
278         .dump_regs = agp_i810_dump_regs,
279         .get_stolen_size = agp_i810_get_stolen_size,
280         .get_gtt_mappable_entries = agp_i830_get_gtt_mappable_entries,
281         .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
282         .install_gatt = agp_i810_install_gatt,
283         .deinstall_gatt = agp_i810_deinstall_gatt,
284         .write_gtt = agp_i810_write_gtt,
285         .install_gtt_pte = agp_i810_install_gtt_pte,
286         .read_gtt_pte = agp_i810_read_gtt_pte,
287         .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
288         .set_aperture = agp_i810_set_aperture,
289         .chipset_flush_setup = agp_i810_chipset_flush_setup,
290         .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
291         .chipset_flush = agp_i830_chipset_flush,
292 };
293
294 static const struct agp_i810_driver agp_i810_i830_driver = {
295         .chiptype = CHIP_I830,
296         .gen = 2,
297         .busdma_addr_mask_sz = 32,
298         .res_spec = agp_i810_res_spec,
299         .check_active = agp_i830_check_active,
300         .set_desc = agp_i810_set_desc,
301         .dump_regs = agp_i830_dump_regs,
302         .get_stolen_size = agp_i830_get_stolen_size,
303         .get_gtt_mappable_entries = agp_i830_get_gtt_mappable_entries,
304         .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
305         .install_gatt = agp_i830_install_gatt,
306         .deinstall_gatt = agp_i830_deinstall_gatt,
307         .write_gtt = agp_i810_write_gtt,
308         .install_gtt_pte = agp_i830_install_gtt_pte,
309         .read_gtt_pte = agp_i810_read_gtt_pte,
310         .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
311         .set_aperture = agp_i830_set_aperture,
312         .chipset_flush_setup = agp_i810_chipset_flush_setup,
313         .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
314         .chipset_flush = agp_i830_chipset_flush,
315 };
316
317 static const struct agp_i810_driver agp_i810_i855_driver = {
318         .chiptype = CHIP_I855,
319         .gen = 2,
320         .busdma_addr_mask_sz = 32,
321         .res_spec = agp_i810_res_spec,
322         .check_active = agp_i830_check_active,
323         .set_desc = agp_82852_set_desc,
324         .dump_regs = agp_i855_dump_regs,
325         .get_stolen_size = agp_i915_get_stolen_size,
326         .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
327         .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
328         .install_gatt = agp_i830_install_gatt,
329         .deinstall_gatt = agp_i830_deinstall_gatt,
330         .write_gtt = agp_i810_write_gtt,
331         .install_gtt_pte = agp_i830_install_gtt_pte,
332         .read_gtt_pte = agp_i810_read_gtt_pte,
333         .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
334         .set_aperture = agp_i830_set_aperture,
335         .chipset_flush_setup = agp_i810_chipset_flush_setup,
336         .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
337         .chipset_flush = agp_i830_chipset_flush,
338 };
339
340 static const struct agp_i810_driver agp_i810_i865_driver = {
341         .chiptype = CHIP_I855,
342         .gen = 2,
343         .busdma_addr_mask_sz = 32,
344         .res_spec = agp_i810_res_spec,
345         .check_active = agp_i830_check_active,
346         .set_desc = agp_i810_set_desc,
347         .dump_regs = agp_i855_dump_regs,
348         .get_stolen_size = agp_i915_get_stolen_size,
349         .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
350         .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
351         .install_gatt = agp_i830_install_gatt,
352         .deinstall_gatt = agp_i830_deinstall_gatt,
353         .write_gtt = agp_i810_write_gtt,
354         .install_gtt_pte = agp_i830_install_gtt_pte,
355         .read_gtt_pte = agp_i810_read_gtt_pte,
356         .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
357         .set_aperture = agp_i915_set_aperture,
358         .chipset_flush_setup = agp_i810_chipset_flush_setup,
359         .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
360         .chipset_flush = agp_i830_chipset_flush,
361 };
362
363 static const struct agp_i810_driver agp_i810_i915_driver = {
364         .chiptype = CHIP_I915,
365         .gen = 3,
366         .busdma_addr_mask_sz = 32,
367         .res_spec = agp_i915_res_spec,
368         .check_active = agp_i915_check_active,
369         .set_desc = agp_i810_set_desc,
370         .dump_regs = agp_i915_dump_regs,
371         .get_stolen_size = agp_i915_get_stolen_size,
372         .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
373         .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
374         .install_gatt = agp_i830_install_gatt,
375         .deinstall_gatt = agp_i830_deinstall_gatt,
376         .write_gtt = agp_i915_write_gtt,
377         .install_gtt_pte = agp_i915_install_gtt_pte,
378         .read_gtt_pte = agp_i915_read_gtt_pte,
379         .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
380         .set_aperture = agp_i915_set_aperture,
381         .chipset_flush_setup = agp_i915_chipset_flush_setup,
382         .chipset_flush_teardown = agp_i915_chipset_flush_teardown,
383         .chipset_flush = agp_i915_chipset_flush,
384 };
385
386 static const struct agp_i810_driver agp_i810_g965_driver = {
387         .chiptype = CHIP_I965,
388         .gen = 4,
389         .busdma_addr_mask_sz = 36,
390         .res_spec = agp_i965_res_spec,
391         .check_active = agp_i915_check_active,
392         .set_desc = agp_i810_set_desc,
393         .dump_regs = agp_i965_dump_regs,
394         .get_stolen_size = agp_i915_get_stolen_size,
395         .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
396         .get_gtt_total_entries = agp_i965_get_gtt_total_entries,
397         .install_gatt = agp_i830_install_gatt,
398         .deinstall_gatt = agp_i830_deinstall_gatt,
399         .write_gtt = agp_i965_write_gtt,
400         .install_gtt_pte = agp_i965_install_gtt_pte,
401         .read_gtt_pte = agp_i965_read_gtt_pte,
402         .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
403         .set_aperture = agp_i915_set_aperture,
404         .chipset_flush_setup = agp_i965_chipset_flush_setup,
405         .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
406         .chipset_flush = agp_i915_chipset_flush,
407 };
408
409 static const struct agp_i810_driver agp_i810_g33_driver = {
410         .chiptype = CHIP_G33,
411         .gen = 3,
412         .busdma_addr_mask_sz = 36,
413         .res_spec = agp_i915_res_spec,
414         .check_active = agp_i915_check_active,
415         .set_desc = agp_i810_set_desc,
416         .dump_regs = agp_i965_dump_regs,
417         .get_stolen_size = agp_i915_get_stolen_size,
418         .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
419         .get_gtt_total_entries = agp_i965_get_gtt_total_entries,
420         .install_gatt = agp_i830_install_gatt,
421         .deinstall_gatt = agp_i830_deinstall_gatt,
422         .write_gtt = agp_i915_write_gtt,
423         .install_gtt_pte = agp_i915_install_gtt_pte,
424         .read_gtt_pte = agp_i915_read_gtt_pte,
425         .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
426         .set_aperture = agp_i915_set_aperture,
427         .chipset_flush_setup = agp_i965_chipset_flush_setup,
428         .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
429         .chipset_flush = agp_i915_chipset_flush,
430 };
431
432 static const struct agp_i810_driver agp_i810_igd_driver = {
433         .chiptype = CHIP_IGD,
434         .gen = 3,
435         .busdma_addr_mask_sz = 36,
436         .res_spec = agp_i915_res_spec,
437         .check_active = agp_i915_check_active,
438         .set_desc = agp_i810_set_desc,
439         .dump_regs = agp_i915_dump_regs,
440         .get_stolen_size = agp_i915_get_stolen_size,
441         .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
442         .get_gtt_total_entries = agp_i965_get_gtt_total_entries,
443         .install_gatt = agp_i830_install_gatt,
444         .deinstall_gatt = agp_i830_deinstall_gatt,
445         .write_gtt = agp_i915_write_gtt,
446         .install_gtt_pte = agp_i915_install_gtt_pte,
447         .read_gtt_pte = agp_i915_read_gtt_pte,
448         .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
449         .set_aperture = agp_i915_set_aperture,
450         .chipset_flush_setup = agp_i965_chipset_flush_setup,
451         .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
452         .chipset_flush = agp_i915_chipset_flush,
453 };
454
455 static const struct agp_i810_driver agp_i810_g4x_driver = {
456         .chiptype = CHIP_G4X,
457         .gen = 5,
458         .busdma_addr_mask_sz = 36,
459         .res_spec = agp_i965_res_spec,
460         .check_active = agp_i915_check_active,
461         .set_desc = agp_i810_set_desc,
462         .dump_regs = agp_i965_dump_regs,
463         .get_stolen_size = agp_i915_get_stolen_size,
464         .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
465         .get_gtt_total_entries = agp_gen5_get_gtt_total_entries,
466         .install_gatt = agp_i830_install_gatt,
467         .deinstall_gatt = agp_i830_deinstall_gatt,
468         .write_gtt = agp_g4x_write_gtt,
469         .install_gtt_pte = agp_g4x_install_gtt_pte,
470         .read_gtt_pte = agp_g4x_read_gtt_pte,
471         .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
472         .set_aperture = agp_i915_set_aperture,
473         .chipset_flush_setup = agp_i965_chipset_flush_setup,
474         .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
475         .chipset_flush = agp_i915_chipset_flush,
476 };
477
478 static const struct agp_i810_driver agp_i810_sb_driver = {
479         .chiptype = CHIP_SB,
480         .gen = 6,
481         .busdma_addr_mask_sz = 40,
482         .res_spec = agp_g4x_res_spec,
483         .check_active = agp_sb_check_active,
484         .set_desc = agp_i810_set_desc,
485         .dump_regs = agp_sb_dump_regs,
486         .get_stolen_size = agp_sb_get_stolen_size,
487         .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
488         .get_gtt_total_entries = agp_sb_get_gtt_total_entries,
489         .install_gatt = agp_i830_install_gatt,
490         .deinstall_gatt = agp_i830_deinstall_gatt,
491         .write_gtt = agp_sb_write_gtt,
492         .install_gtt_pte = agp_sb_install_gtt_pte,
493         .read_gtt_pte = agp_g4x_read_gtt_pte,
494         .read_gtt_pte_paddr = agp_sb_read_gtt_pte_paddr,
495         .set_aperture = agp_i915_set_aperture,
496         .chipset_flush_setup = agp_i810_chipset_flush_setup,
497         .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
498         .chipset_flush = agp_i810_chipset_flush,
499 };
500
501 /* For adding new devices, devid is the id of the graphics controller
502  * (pci:0:2:0, for example).  The placeholder (usually at pci:0:2:1) for the
503  * second head should never be added.  The bridge_offset is the offset to
504  * subtract from devid to get the id of the hostb that the device is on.
505  */
506 static const struct agp_i810_match {
507         int devid;
508         char *name;
509         const struct agp_i810_driver *driver;
510 } agp_i810_matches[] = {
511         {
512                 .devid = 0x71218086,
513                 .name = "Intel 82810 (i810 GMCH) SVGA controller",
514                 .driver = &agp_i810_i810_driver
515         },
516         {
517                 .devid = 0x71238086,
518                 .name = "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller",
519                 .driver = &agp_i810_i810_driver
520         },
521         {
522                 .devid = 0x71258086,
523                 .name = "Intel 82810E (i810E GMCH) SVGA controller",
524                 .driver = &agp_i810_i810_driver
525         },
526         {
527                 .devid = 0x11328086,
528                 .name = "Intel 82815 (i815 GMCH) SVGA controller",
529                 .driver = &agp_i810_i815_driver
530         },
531         {
532                 .devid = 0x35778086,
533                 .name = "Intel 82830M (830M GMCH) SVGA controller",
534                 .driver = &agp_i810_i830_driver
535         },
536         {
537                 .devid = 0x25628086,
538                 .name = "Intel 82845M (845M GMCH) SVGA controller",
539                 .driver = &agp_i810_i830_driver
540         },
541         {
542                 .devid = 0x35828086,
543                 .name = "Intel 82852/855GM SVGA controller",
544                 .driver = &agp_i810_i855_driver
545         },
546         {
547                 .devid = 0x25728086,
548                 .name = "Intel 82865G (865G GMCH) SVGA controller",
549                 .driver = &agp_i810_i865_driver
550         },
551         {
552                 .devid = 0x25828086,
553                 .name = "Intel 82915G (915G GMCH) SVGA controller",
554                 .driver = &agp_i810_i915_driver
555         },
556         {
557                 .devid = 0x258A8086,
558                 .name = "Intel E7221 SVGA controller",
559                 .driver = &agp_i810_i915_driver
560         },
561         {
562                 .devid = 0x25928086,
563                 .name = "Intel 82915GM (915GM GMCH) SVGA controller",
564                 .driver = &agp_i810_i915_driver
565         },
566         {
567                 .devid = 0x27728086,
568                 .name = "Intel 82945G (945G GMCH) SVGA controller",
569                 .driver = &agp_i810_i915_driver
570         },
571         {
572                 .devid = 0x27A28086,
573                 .name = "Intel 82945GM (945GM GMCH) SVGA controller",
574                 .driver = &agp_i810_i915_driver
575         },
576         {
577                 .devid = 0x27AE8086,
578                 .name = "Intel 945GME SVGA controller",
579                 .driver = &agp_i810_i915_driver
580         },
581         {
582                 .devid = 0x29728086,
583                 .name = "Intel 946GZ SVGA controller",
584                 .driver = &agp_i810_g965_driver
585         },
586         {
587                 .devid = 0x29828086,
588                 .name = "Intel G965 SVGA controller",
589                 .driver = &agp_i810_g965_driver
590         },
591         {
592                 .devid = 0x29928086,
593                 .name = "Intel Q965 SVGA controller",
594                 .driver = &agp_i810_g965_driver
595         },
596         {
597                 .devid = 0x29A28086,
598                 .name = "Intel G965 SVGA controller",
599                 .driver = &agp_i810_g965_driver
600         },
601         {
602                 .devid = 0x29B28086,
603                 .name = "Intel Q35 SVGA controller",
604                 .driver = &agp_i810_g33_driver
605         },
606         {
607                 .devid = 0x29C28086,
608                 .name = "Intel G33 SVGA controller",
609                 .driver = &agp_i810_g33_driver
610         },
611         {
612                 .devid = 0x29D28086,
613                 .name = "Intel Q33 SVGA controller",
614                 .driver = &agp_i810_g33_driver
615         },
616         {
617                 .devid = 0xA0018086,
618                 .name = "Intel Pineview SVGA controller",
619                 .driver = &agp_i810_igd_driver
620         },
621         {
622                 .devid = 0xA0118086,
623                 .name = "Intel Pineview (M) SVGA controller",
624                 .driver = &agp_i810_igd_driver
625         },
626         {
627                 .devid = 0x2A028086,
628                 .name = "Intel GM965 SVGA controller",
629                 .driver = &agp_i810_g965_driver
630         },
631         {
632                 .devid = 0x2A128086,
633                 .name = "Intel GME965 SVGA controller",
634                 .driver = &agp_i810_g965_driver
635         },
636         {
637                 .devid = 0x2A428086,
638                 .name = "Intel GM45 SVGA controller",
639                 .driver = &agp_i810_g4x_driver
640         },
641         {
642                 .devid = 0x2E028086,
643                 .name = "Intel Eaglelake SVGA controller",
644                 .driver = &agp_i810_g4x_driver
645         },
646         {
647                 .devid = 0x2E128086,
648                 .name = "Intel Q45 SVGA controller",
649                 .driver = &agp_i810_g4x_driver
650         },
651         {
652                 .devid = 0x2E228086,
653                 .name = "Intel G45 SVGA controller",
654                 .driver = &agp_i810_g4x_driver
655         },
656         {
657                 .devid = 0x2E328086,
658                 .name = "Intel G41 SVGA controller",
659                 .driver = &agp_i810_g4x_driver
660         },
661         {
662                 .devid = 0x00428086,
663                 .name = "Intel Ironlake (D) SVGA controller",
664                 .driver = &agp_i810_g4x_driver
665         },
666         {
667                 .devid = 0x00468086,
668                 .name = "Intel Ironlake (M) SVGA controller",
669                 .driver = &agp_i810_g4x_driver
670         },
671         {
672                 .devid = 0x01028086,
673                 .name = "SandyBridge desktop GT1 IG",
674                 .driver = &agp_i810_sb_driver
675         },
676         {
677                 .devid = 0x01128086,
678                 .name = "SandyBridge desktop GT2 IG",
679                 .driver = &agp_i810_sb_driver
680         },
681         {
682                 .devid = 0x01228086,
683                 .name = "SandyBridge desktop GT2+ IG",
684                 .driver = &agp_i810_sb_driver
685         },
686         {
687                 .devid = 0x01068086,
688                 .name = "SandyBridge mobile GT1 IG",
689                 .driver = &agp_i810_sb_driver
690         },
691         {
692                 .devid = 0x01168086,
693                 .name = "SandyBridge mobile GT2 IG",
694                 .driver = &agp_i810_sb_driver
695         },
696         {
697                 .devid = 0x01268086,
698                 .name = "SandyBridge mobile GT2+ IG",
699                 .driver = &agp_i810_sb_driver
700         },
701         {
702                 .devid = 0x010a8086,
703                 .name = "SandyBridge server IG",
704                 .driver = &agp_i810_sb_driver
705         },
706         {
707                 .devid = 0x01528086,
708                 .name = "IvyBridge desktop GT1 IG",
709                 .driver = &agp_i810_sb_driver
710         },
711         {
712                 .devid = 0x01628086,
713                 .name = "IvyBridge desktop GT2 IG",
714                 .driver = &agp_i810_sb_driver
715         },
716         {
717                 .devid = 0x01568086,
718                 .name = "IvyBridge mobile GT1 IG",
719                 .driver = &agp_i810_sb_driver
720         },
721         {
722                 .devid = 0x01668086,
723                 .name = "IvyBridge mobile GT2 IG",
724                 .driver = &agp_i810_sb_driver
725         },
726         {
727                 .devid = 0x015a8086,
728                 .name = "IvyBridge server GT1 IG",
729                 .driver = &agp_i810_sb_driver
730         },
731         {
732                 .devid = 0x016a8086,
733                 .name = "IvyBridge server GT2 IG",
734                 .driver = &agp_i810_sb_driver
735         },
736         {
737                 .devid = 0,
738         }
739 };
740
741 static const struct agp_i810_match*
742 agp_i810_match(device_t dev)
743 {
744         int i, devid;
745
746         if (pci_get_class(dev) != PCIC_DISPLAY)
747                 return (NULL);
748
749         devid = pci_get_devid(dev);
750         for (i = 0; agp_i810_matches[i].devid != 0; i++) {
751                 if (agp_i810_matches[i].devid == devid)
752                         break;
753         }
754         if (agp_i810_matches[i].devid == 0)
755                 return (NULL);
756         else
757                 return (&agp_i810_matches[i]);
758 }
759
760 /*
761  * Find bridge device.
762  */
763 static device_t
764 agp_i810_find_bridge(device_t dev)
765 {
766
767         return (pci_find_dbsf(0, 0, 0, 0));
768 }
769
770 static void
771 agp_i810_identify(driver_t *driver, device_t parent)
772 {
773
774         if (device_find_child(parent, "agp", -1) == NULL &&
775             agp_i810_match(parent))
776                 device_add_child(parent, "agp", -1);
777 }
778
779 static int
780 agp_i810_check_active(device_t bridge_dev)
781 {
782         u_int8_t smram;
783
784         smram = pci_read_config(bridge_dev, AGP_I810_SMRAM, 1);
785         if ((smram & AGP_I810_SMRAM_GMS) == AGP_I810_SMRAM_GMS_DISABLED)
786                 return (ENXIO);
787         return (0);
788 }
789
790 static int
791 agp_i830_check_active(device_t bridge_dev)
792 {
793         int gcc1;
794
795         gcc1 = pci_read_config(bridge_dev, AGP_I830_GCC1, 1);
796         if ((gcc1 & AGP_I830_GCC1_DEV2) == AGP_I830_GCC1_DEV2_DISABLED)
797                 return (ENXIO);
798         return (0);
799 }
800
801 static int
802 agp_i915_check_active(device_t bridge_dev)
803 {
804         int deven;
805
806         deven = pci_read_config(bridge_dev, AGP_I915_DEVEN, 4);
807         if ((deven & AGP_I915_DEVEN_D2F0) == AGP_I915_DEVEN_D2F0_DISABLED)
808                 return (ENXIO);
809         return (0);
810 }
811
812 static int
813 agp_sb_check_active(device_t bridge_dev)
814 {
815         int deven;
816
817         deven = pci_read_config(bridge_dev, AGP_I915_DEVEN, 4);
818         if ((deven & AGP_SB_DEVEN_D2EN) == AGP_SB_DEVEN_D2EN_DISABLED)
819                 return (ENXIO);
820         return (0);
821 }
822
823 static void
824 agp_82852_set_desc(device_t dev, const struct agp_i810_match *match)
825 {
826
827         switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
828         case AGP_I855_GME:
829                 device_set_desc(dev,
830                     "Intel 82855GME (855GME GMCH) SVGA controller");
831                 break;
832         case AGP_I855_GM:
833                 device_set_desc(dev,
834                     "Intel 82855GM (855GM GMCH) SVGA controller");
835                 break;
836         case AGP_I852_GME:
837                 device_set_desc(dev,
838                     "Intel 82852GME (852GME GMCH) SVGA controller");
839                 break;
840         case AGP_I852_GM:
841                 device_set_desc(dev,
842                     "Intel 82852GM (852GM GMCH) SVGA controller");
843                 break;
844         default:
845                 device_set_desc(dev,
846                     "Intel 8285xM (85xGM GMCH) SVGA controller");
847                 break;
848         }
849 }
850
851 static void
852 agp_i810_set_desc(device_t dev, const struct agp_i810_match *match)
853 {
854
855         device_set_desc(dev, match->name);
856 }
857
858 static int
859 agp_i810_probe(device_t dev)
860 {
861         device_t bdev;
862         const struct agp_i810_match *match;
863         int err;
864
865         if (resource_disabled("agp", device_get_unit(dev)))
866                 return (ENXIO);
867         match = agp_i810_match(dev);
868         if (match == NULL)
869                 return (ENXIO);
870
871         bdev = agp_i810_find_bridge(dev);
872         if (bdev == NULL) {
873                 if (bootverbose)
874                         kprintf("I810: can't find bridge device\n");
875                 return (ENXIO);
876         }
877
878         /*
879          * checking whether internal graphics device has been activated.
880          */
881         err = match->driver->check_active(bdev);
882         if (err != 0) {
883                 if (bootverbose)
884                         kprintf("i810: disabled, not probing\n");
885                 return (err);
886         }
887
888         match->driver->set_desc(dev, match);
889         return (BUS_PROBE_DEFAULT);
890 }
891
892 static void
893 agp_i810_dump_regs(device_t dev)
894 {
895         struct agp_i810_softc *sc = device_get_softc(dev);
896
897         device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
898             bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
899         device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
900             pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
901 }
902
903 static void
904 agp_i830_dump_regs(device_t dev)
905 {
906         struct agp_i810_softc *sc = device_get_softc(dev);
907
908         device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
909             bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
910         device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
911             pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
912 }
913
914 static void
915 agp_i855_dump_regs(device_t dev)
916 {
917         struct agp_i810_softc *sc = device_get_softc(dev);
918
919         device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
920             bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
921         device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
922             pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
923 }
924
925 static void
926 agp_i915_dump_regs(device_t dev)
927 {
928         struct agp_i810_softc *sc = device_get_softc(dev);
929
930         device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
931             bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
932         device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
933             pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
934         device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
935             pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
936 }
937
938 static void
939 agp_i965_dump_regs(device_t dev)
940 {
941         struct agp_i810_softc *sc = device_get_softc(dev);
942
943         device_printf(dev, "AGP_I965_PGTBL_CTL2: %08x\n",
944             bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2));
945         device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
946             pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
947         device_printf(dev, "AGP_I965_MSAC: 0x%02x\n",
948             pci_read_config(sc->bdev, AGP_I965_MSAC, 1));
949 }
950
951 static void
952 agp_sb_dump_regs(device_t dev)
953 {
954         struct agp_i810_softc *sc = device_get_softc(dev);
955
956         device_printf(dev, "AGP_SNB_GFX_MODE: %08x\n",
957             bus_read_4(sc->sc_res[0], AGP_SNB_GFX_MODE));
958         device_printf(dev, "AGP_SNB_GCC1: 0x%04x\n",
959             pci_read_config(sc->bdev, AGP_SNB_GCC1, 2));
960 }
961
962 static int
963 agp_i810_get_stolen_size(device_t dev)
964 {
965         struct agp_i810_softc *sc;
966
967         sc = device_get_softc(dev);
968         sc->stolen = 0;
969         sc->stolen_size = 0;
970         return (0);
971 }
972
973 static int
974 agp_i830_get_stolen_size(device_t dev)
975 {
976         struct agp_i810_softc *sc;
977         unsigned int gcc1;
978
979         sc = device_get_softc(dev);
980
981         gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
982         switch (gcc1 & AGP_I830_GCC1_GMS) {
983         case AGP_I830_GCC1_GMS_STOLEN_512:
984                 sc->stolen = (512 - 132) * 1024 / 4096;
985                 sc->stolen_size = 512 * 1024;
986                 break;
987         case AGP_I830_GCC1_GMS_STOLEN_1024:
988                 sc->stolen = (1024 - 132) * 1024 / 4096;
989                 sc->stolen_size = 1024 * 1024;
990                 break;
991         case AGP_I830_GCC1_GMS_STOLEN_8192:
992                 sc->stolen = (8192 - 132) * 1024 / 4096;
993                 sc->stolen_size = 8192 * 1024;
994                 break;
995         default:
996                 sc->stolen = 0;
997                 device_printf(dev,
998                     "unknown memory configuration, disabling (GCC1 %x)\n",
999                     gcc1);
1000                 return (EINVAL);
1001         }
1002         return (0);
1003 }
1004
1005 static int
1006 agp_i915_get_stolen_size(device_t dev)
1007 {
1008         struct agp_i810_softc *sc;
1009         unsigned int gcc1, stolen, gtt_size;
1010
1011         sc = device_get_softc(dev);
1012
1013         /*
1014          * Stolen memory is set up at the beginning of the aperture by
1015          * the BIOS, consisting of the GATT followed by 4kb for the
1016          * BIOS display.
1017          */
1018         switch (sc->match->driver->chiptype) {
1019         case CHIP_I855:
1020                 gtt_size = 128;
1021                 break;
1022         case CHIP_I915:
1023                 gtt_size = 256;
1024                 break;
1025         case CHIP_I965:
1026                 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
1027                         AGP_I810_PGTBL_SIZE_MASK) {
1028                 case AGP_I810_PGTBL_SIZE_128KB:
1029                         gtt_size = 128;
1030                         break;
1031                 case AGP_I810_PGTBL_SIZE_256KB:
1032                         gtt_size = 256;
1033                         break;
1034                 case AGP_I810_PGTBL_SIZE_512KB:
1035                         gtt_size = 512;
1036                         break;
1037                 case AGP_I965_PGTBL_SIZE_1MB:
1038                         gtt_size = 1024;
1039                         break;
1040                 case AGP_I965_PGTBL_SIZE_2MB:
1041                         gtt_size = 2048;
1042                         break;
1043                 case AGP_I965_PGTBL_SIZE_1_5MB:
1044                         gtt_size = 1024 + 512;
1045                         break;
1046                 default:
1047                         device_printf(dev, "Bad PGTBL size\n");
1048                         return (EINVAL);
1049                 }
1050                 break;
1051         case CHIP_G33:
1052                 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
1053                 switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
1054                 case AGP_G33_MGGC_GGMS_SIZE_1M:
1055                         gtt_size = 1024;
1056                         break;
1057                 case AGP_G33_MGGC_GGMS_SIZE_2M:
1058                         gtt_size = 2048;
1059                         break;
1060                 default:
1061                         device_printf(dev, "Bad PGTBL size\n");
1062                         return (EINVAL);
1063                 }
1064                 break;
1065         case CHIP_IGD:
1066         case CHIP_G4X:
1067                 gtt_size = 0;
1068                 break;
1069         default:
1070                 device_printf(dev, "Bad chiptype\n");
1071                 return (EINVAL);
1072         }
1073
1074         /* GCC1 is called MGGC on i915+ */
1075         gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
1076         switch (gcc1 & AGP_I855_GCC1_GMS) {
1077         case AGP_I855_GCC1_GMS_STOLEN_1M:
1078                 stolen = 1024;
1079                 break;
1080         case AGP_I855_GCC1_GMS_STOLEN_4M:
1081                 stolen = 4 * 1024;
1082                 break;
1083         case AGP_I855_GCC1_GMS_STOLEN_8M:
1084                 stolen = 8 * 1024;
1085                 break;
1086         case AGP_I855_GCC1_GMS_STOLEN_16M:
1087                 stolen = 16 * 1024;
1088                 break;
1089         case AGP_I855_GCC1_GMS_STOLEN_32M:
1090                 stolen = 32 * 1024;
1091                 break;
1092         case AGP_I915_GCC1_GMS_STOLEN_48M:
1093                 stolen = sc->match->driver->gen > 2 ? 48 * 1024 : 0;
1094                 break;
1095         case AGP_I915_GCC1_GMS_STOLEN_64M:
1096                 stolen = sc->match->driver->gen > 2 ? 64 * 1024 : 0;
1097                 break;
1098         case AGP_G33_GCC1_GMS_STOLEN_128M:
1099                 stolen = sc->match->driver->gen > 2 ? 128 * 1024 : 0;
1100                 break;
1101         case AGP_G33_GCC1_GMS_STOLEN_256M:
1102                 stolen = sc->match->driver->gen > 2 ? 256 * 1024 : 0;
1103                 break;
1104         case AGP_G4X_GCC1_GMS_STOLEN_96M:
1105                 if (sc->match->driver->chiptype == CHIP_I965 ||
1106                     sc->match->driver->chiptype == CHIP_G4X)
1107                         stolen = 96 * 1024;
1108                 else
1109                         stolen = 0;
1110                 break;
1111         case AGP_G4X_GCC1_GMS_STOLEN_160M:
1112                 if (sc->match->driver->chiptype == CHIP_I965 ||
1113                     sc->match->driver->chiptype == CHIP_G4X)
1114                         stolen = 160 * 1024;
1115                 else
1116                         stolen = 0;
1117                 break;
1118         case AGP_G4X_GCC1_GMS_STOLEN_224M:
1119                 if (sc->match->driver->chiptype == CHIP_I965 ||
1120                     sc->match->driver->chiptype == CHIP_G4X)
1121                         stolen = 224 * 1024;
1122                 else
1123                         stolen = 0;
1124                 break;
1125         case AGP_G4X_GCC1_GMS_STOLEN_352M:
1126                 if (sc->match->driver->chiptype == CHIP_I965 ||
1127                     sc->match->driver->chiptype == CHIP_G4X)
1128                         stolen = 352 * 1024;
1129                 else
1130                         stolen = 0;
1131                 break;
1132         default:
1133                 device_printf(dev,
1134                     "unknown memory configuration, disabling (GCC1 %x)\n",
1135                     gcc1);
1136                 return (EINVAL);
1137         }
1138
1139         gtt_size += 4;
1140         sc->stolen_size = stolen * 1024;
1141         sc->stolen = (stolen - gtt_size) * 1024 / 4096;
1142
1143         return (0);
1144 }
1145
1146 static int
1147 agp_sb_get_stolen_size(device_t dev)
1148 {
1149         struct agp_i810_softc *sc;
1150         uint16_t gmch_ctl;
1151
1152         sc = device_get_softc(dev);
1153         gmch_ctl = pci_read_config(sc->bdev, AGP_SNB_GCC1, 2);
1154         switch (gmch_ctl & AGP_SNB_GMCH_GMS_STOLEN_MASK) {
1155         case AGP_SNB_GMCH_GMS_STOLEN_32M:
1156                 sc->stolen_size = 32 * 1024 * 1024;
1157                 break;
1158         case AGP_SNB_GMCH_GMS_STOLEN_64M:
1159                 sc->stolen_size = 64 * 1024 * 1024;
1160                 break;
1161         case AGP_SNB_GMCH_GMS_STOLEN_96M:
1162                 sc->stolen_size = 96 * 1024 * 1024;
1163                 break;
1164         case AGP_SNB_GMCH_GMS_STOLEN_128M:
1165                 sc->stolen_size = 128 * 1024 * 1024;
1166                 break;
1167         case AGP_SNB_GMCH_GMS_STOLEN_160M:
1168                 sc->stolen_size = 160 * 1024 * 1024;
1169                 break;
1170         case AGP_SNB_GMCH_GMS_STOLEN_192M:
1171                 sc->stolen_size = 192 * 1024 * 1024;
1172                 break;
1173         case AGP_SNB_GMCH_GMS_STOLEN_224M:
1174                 sc->stolen_size = 224 * 1024 * 1024;
1175                 break;
1176         case AGP_SNB_GMCH_GMS_STOLEN_256M:
1177                 sc->stolen_size = 256 * 1024 * 1024;
1178                 break;
1179         case AGP_SNB_GMCH_GMS_STOLEN_288M:
1180                 sc->stolen_size = 288 * 1024 * 1024;
1181                 break;
1182         case AGP_SNB_GMCH_GMS_STOLEN_320M:
1183                 sc->stolen_size = 320 * 1024 * 1024;
1184                 break;
1185         case AGP_SNB_GMCH_GMS_STOLEN_352M:
1186                 sc->stolen_size = 352 * 1024 * 1024;
1187                 break;
1188         case AGP_SNB_GMCH_GMS_STOLEN_384M:
1189                 sc->stolen_size = 384 * 1024 * 1024;
1190                 break;
1191         case AGP_SNB_GMCH_GMS_STOLEN_416M:
1192                 sc->stolen_size = 416 * 1024 * 1024;
1193                 break;
1194         case AGP_SNB_GMCH_GMS_STOLEN_448M:
1195                 sc->stolen_size = 448 * 1024 * 1024;
1196                 break;
1197         case AGP_SNB_GMCH_GMS_STOLEN_480M:
1198                 sc->stolen_size = 480 * 1024 * 1024;
1199                 break;
1200         case AGP_SNB_GMCH_GMS_STOLEN_512M:
1201                 sc->stolen_size = 512 * 1024 * 1024;
1202                 break;
1203         }
1204         sc->stolen = (sc->stolen_size - 4) / 4096;
1205         return (0);
1206 }
1207
1208 static int
1209 agp_i810_get_gtt_mappable_entries(device_t dev)
1210 {
1211         struct agp_i810_softc *sc;
1212         uint32_t ap;
1213         uint16_t miscc;
1214
1215         sc = device_get_softc(dev);
1216         miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
1217         if ((miscc & AGP_I810_MISCC_WINSIZE) == AGP_I810_MISCC_WINSIZE_32)
1218                 ap = 32;
1219         else
1220                 ap = 64;
1221         sc->gtt_mappable_entries = (ap * 1024 * 1024) >> AGP_PAGE_SHIFT;
1222         return (0);
1223 }
1224
1225 static int
1226 agp_i830_get_gtt_mappable_entries(device_t dev)
1227 {
1228         struct agp_i810_softc *sc;
1229         uint32_t ap;
1230         uint16_t gmch_ctl;
1231
1232         sc = device_get_softc(dev);
1233         gmch_ctl = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
1234         if ((gmch_ctl & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
1235                 ap = 64;
1236         else
1237                 ap = 128;
1238         sc->gtt_mappable_entries = (ap * 1024 * 1024) >> AGP_PAGE_SHIFT;
1239         return (0);
1240 }
1241
1242 static int
1243 agp_i915_get_gtt_mappable_entries(device_t dev)
1244 {
1245         struct agp_i810_softc *sc;
1246         uint32_t ap;
1247
1248         sc = device_get_softc(dev);
1249         ap = AGP_GET_APERTURE(dev);
1250         sc->gtt_mappable_entries = ap >> AGP_PAGE_SHIFT;
1251         return (0);
1252 }
1253
1254 static int
1255 agp_i810_get_gtt_total_entries(device_t dev)
1256 {
1257         struct agp_i810_softc *sc;
1258
1259         sc = device_get_softc(dev);
1260         sc->gtt_total_entries = sc->gtt_mappable_entries;
1261         return (0);
1262 }
1263
1264 static int
1265 agp_i965_get_gtt_total_entries(device_t dev)
1266 {
1267         struct agp_i810_softc *sc;
1268         uint32_t pgetbl_ctl;
1269         int error;
1270
1271         sc = device_get_softc(dev);
1272         error = 0;
1273         pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1274         switch (pgetbl_ctl & AGP_I810_PGTBL_SIZE_MASK) {
1275         case AGP_I810_PGTBL_SIZE_128KB:
1276                 sc->gtt_total_entries = 128 * 1024 / 4;
1277                 break;
1278         case AGP_I810_PGTBL_SIZE_256KB:
1279                 sc->gtt_total_entries = 256 * 1024 / 4;
1280                 break;
1281         case AGP_I810_PGTBL_SIZE_512KB:
1282                 sc->gtt_total_entries = 512 * 1024 / 4;
1283                 break;
1284         /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
1285         case AGP_I810_PGTBL_SIZE_1MB:
1286                 sc->gtt_total_entries = 1024 * 1024 / 4;
1287                 break;
1288         case AGP_I810_PGTBL_SIZE_2MB:
1289                 sc->gtt_total_entries = 2 * 1024 * 1024 / 4;
1290                 break;
1291         case AGP_I810_PGTBL_SIZE_1_5MB:
1292                 sc->gtt_total_entries = (1024 + 512) * 1024 / 4;
1293                 break;
1294         default:
1295                 device_printf(dev, "Unknown page table size\n");
1296                 error = ENXIO;
1297         }
1298         return (error);
1299 }
1300
1301 static void
1302 agp_gen5_adjust_pgtbl_size(device_t dev, uint32_t sz)
1303 {
1304         struct agp_i810_softc *sc;
1305         uint32_t pgetbl_ctl, pgetbl_ctl2;
1306
1307         sc = device_get_softc(dev);
1308
1309         /* Disable per-process page table. */
1310         pgetbl_ctl2 = bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2);
1311         pgetbl_ctl2 &= ~AGP_I810_PGTBL_ENABLED;
1312         bus_write_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2, pgetbl_ctl2);
1313
1314         /* Write the new ggtt size. */
1315         pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1316         pgetbl_ctl &= ~AGP_I810_PGTBL_SIZE_MASK;
1317         pgetbl_ctl |= sz;
1318         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgetbl_ctl);
1319 }
1320
1321 static int
1322 agp_gen5_get_gtt_total_entries(device_t dev)
1323 {
1324         struct agp_i810_softc *sc;
1325         uint16_t gcc1;
1326
1327         sc = device_get_softc(dev);
1328
1329         gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
1330         switch (gcc1 & AGP_G4x_GCC1_SIZE_MASK) {
1331         case AGP_G4x_GCC1_SIZE_1M:
1332         case AGP_G4x_GCC1_SIZE_VT_1M:
1333                 agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_1MB);
1334                 break;
1335         case AGP_G4x_GCC1_SIZE_VT_1_5M:
1336                 agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_1_5MB);
1337                 break;
1338         case AGP_G4x_GCC1_SIZE_2M:
1339         case AGP_G4x_GCC1_SIZE_VT_2M:
1340                 agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_2MB);
1341                 break;
1342         default:
1343                 device_printf(dev, "Unknown page table size\n");
1344                 return (ENXIO);
1345         }
1346
1347         return (agp_i965_get_gtt_total_entries(dev));
1348 }
1349
1350 static int
1351 agp_sb_get_gtt_total_entries(device_t dev)
1352 {
1353         struct agp_i810_softc *sc;
1354         uint16_t gcc1;
1355
1356         sc = device_get_softc(dev);
1357
1358         gcc1 = pci_read_config(sc->bdev, AGP_SNB_GCC1, 2);
1359         switch (gcc1 & AGP_SNB_GTT_SIZE_MASK) {
1360         default:
1361         case AGP_SNB_GTT_SIZE_0M:
1362                 kprintf("Bad GTT size mask: 0x%04x\n", gcc1);
1363                 return (ENXIO);
1364         case AGP_SNB_GTT_SIZE_1M:
1365                 sc->gtt_total_entries = 1024 * 1024 / 4;
1366                 break;
1367         case AGP_SNB_GTT_SIZE_2M:
1368                 sc->gtt_total_entries = 2 * 1024 * 1024 / 4;
1369                 break;
1370         }
1371         return (0);
1372 }
1373
1374 static int
1375 agp_i810_install_gatt(device_t dev)
1376 {
1377         struct agp_i810_softc *sc;
1378
1379         sc = device_get_softc(dev);
1380
1381         /* Some i810s have on-chip memory called dcache. */
1382         if ((bus_read_1(sc->sc_res[0], AGP_I810_DRT) & AGP_I810_DRT_POPULATED)
1383             != 0)
1384                 sc->dcache_size = 4 * 1024 * 1024;
1385         else
1386                 sc->dcache_size = 0;
1387
1388         /* According to the specs the gatt on the i810 must be 64k. */
1389         sc->gatt->ag_virtual = contigmalloc(64 * 1024, M_AGP, 0, 0, ~0,
1390             PAGE_SIZE, 0);
1391         if (sc->gatt->ag_virtual == NULL) {
1392                 if (bootverbose)
1393                         device_printf(dev, "contiguous allocation failed\n");
1394                 return (ENOMEM);
1395         }
1396
1397         bzero(sc->gatt->ag_virtual, sc->gatt->ag_entries * sizeof(u_int32_t));
1398         sc->gatt->ag_physical = vtophys((vm_offset_t)sc->gatt->ag_virtual);
1399         agp_flush_cache();
1400         /* Install the GATT. */
1401         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
1402             sc->gatt->ag_physical | 1);
1403         return (0);
1404 }
1405
1406 static int
1407 agp_i830_install_gatt(device_t dev)
1408 {
1409         struct agp_i810_softc *sc;
1410         uint32_t pgtblctl;
1411
1412         sc = device_get_softc(dev);
1413
1414         /*
1415          * The i830 automatically initializes the 128k gatt on boot.
1416          * GATT address is already in there, make sure it's enabled.
1417          */
1418         pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1419         pgtblctl |= 1;
1420         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
1421
1422         sc->gatt->ag_physical = pgtblctl & ~1;
1423         return (0);
1424 }
1425
1426 static int
1427 agp_i810_attach(device_t dev)
1428 {
1429         struct agp_i810_softc *sc;
1430         int error;
1431
1432         sc = device_get_softc(dev);
1433         sc->bdev = agp_i810_find_bridge(dev);
1434         if (sc->bdev == NULL)
1435                 return (ENOENT);
1436
1437         sc->match = agp_i810_match(dev);
1438
1439         agp_set_aperture_resource(dev, sc->match->driver->gen <= 2 ?
1440             AGP_APBASE : AGP_I915_GMADR);
1441         error = agp_generic_attach(dev);
1442         if (error)
1443                 return (error);
1444
1445         if (ptoa((vm_paddr_t)Maxmem) >
1446             (1ULL << sc->match->driver->busdma_addr_mask_sz) - 1) {
1447                 device_printf(dev, "agp_i810 does not support physical "
1448                     "memory above %ju.\n", (uintmax_t)(1ULL <<
1449                     sc->match->driver->busdma_addr_mask_sz) - 1);
1450                 return (ENOENT);
1451         }
1452
1453         if (bus_alloc_resources(dev, sc->match->driver->res_spec, sc->sc_res)) {
1454                 agp_generic_detach(dev);
1455                 return (ENODEV);
1456         }
1457
1458         sc->initial_aperture = AGP_GET_APERTURE(dev);
1459         sc->gatt = kmalloc(sizeof(struct agp_gatt), M_AGP, M_WAITOK);
1460         sc->gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
1461
1462         if ((error = sc->match->driver->get_stolen_size(dev)) != 0 ||
1463             (error = sc->match->driver->install_gatt(dev)) != 0 ||
1464             (error = sc->match->driver->get_gtt_mappable_entries(dev)) != 0 ||
1465             (error = sc->match->driver->get_gtt_total_entries(dev)) != 0 ||
1466             (error = sc->match->driver->chipset_flush_setup(dev)) != 0) {
1467                 bus_release_resources(dev, sc->match->driver->res_spec,
1468                     sc->sc_res);
1469                 kfree(sc->gatt, M_AGP);
1470                 agp_generic_detach(dev);
1471                 return (error);
1472         }
1473
1474         intel_agp = dev;
1475         device_printf(dev, "aperture size is %dM",
1476             sc->initial_aperture / 1024 / 1024);
1477         if (sc->stolen > 0)
1478                 kprintf(", detected %dk stolen memory\n", sc->stolen * 4);
1479         else
1480                 kprintf("\n");
1481         if (bootverbose) {
1482                 sc->match->driver->dump_regs(dev);
1483                 device_printf(dev, "Mappable GTT entries: %d\n",
1484                     sc->gtt_mappable_entries);
1485                 device_printf(dev, "Total GTT entries: %d\n",
1486                     sc->gtt_total_entries);
1487         }
1488         return (0);
1489 }
1490
1491 static void
1492 agp_i810_deinstall_gatt(device_t dev)
1493 {
1494         struct agp_i810_softc *sc;
1495
1496         sc = device_get_softc(dev);
1497         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
1498         contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
1499 }
1500
1501 static void
1502 agp_i830_deinstall_gatt(device_t dev)
1503 {
1504         struct agp_i810_softc *sc;
1505         unsigned int pgtblctl;
1506
1507         sc = device_get_softc(dev);
1508         pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1509         pgtblctl &= ~1;
1510         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
1511 }
1512
1513 static int
1514 agp_i810_detach(device_t dev)
1515 {
1516         struct agp_i810_softc *sc;
1517
1518         sc = device_get_softc(dev);
1519         agp_free_cdev(dev);
1520
1521         /* Clear the GATT base. */
1522         sc->match->driver->deinstall_gatt(dev);
1523
1524         sc->match->driver->chipset_flush_teardown(dev);
1525
1526         /* Put the aperture back the way it started. */
1527         AGP_SET_APERTURE(dev, sc->initial_aperture);
1528
1529         kfree(sc->gatt, M_AGP);
1530         bus_release_resources(dev, sc->match->driver->res_spec, sc->sc_res);
1531         agp_free_res(dev);
1532
1533         return (0);
1534 }
1535
1536 static int
1537 agp_i810_resume(device_t dev)
1538 {
1539         struct agp_i810_softc *sc;
1540         sc = device_get_softc(dev);
1541
1542         AGP_SET_APERTURE(dev, sc->initial_aperture);
1543
1544         /* Install the GATT. */
1545         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
1546         sc->gatt->ag_physical | 1);
1547
1548         return (bus_generic_resume(dev));
1549 }
1550
1551 /**
1552  * Sets the PCI resource size of the aperture on i830-class and below chipsets,
1553  * while returning failure on later chipsets when an actual change is
1554  * requested.
1555  *
1556  * This whole function is likely bogus, as the kernel would probably need to
1557  * reconfigure the placement of the AGP aperture if a larger size is requested,
1558  * which doesn't happen currently.
1559  */
1560 static int
1561 agp_i810_set_aperture(device_t dev, u_int32_t aperture)
1562 {
1563         struct agp_i810_softc *sc;
1564         u_int16_t miscc;
1565
1566         sc = device_get_softc(dev);
1567         /*
1568          * Double check for sanity.
1569          */
1570         if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
1571                 device_printf(dev, "bad aperture size %d\n", aperture);
1572                 return (EINVAL);
1573         }
1574
1575         miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
1576         miscc &= ~AGP_I810_MISCC_WINSIZE;
1577         if (aperture == 32 * 1024 * 1024)
1578                 miscc |= AGP_I810_MISCC_WINSIZE_32;
1579         else
1580                 miscc |= AGP_I810_MISCC_WINSIZE_64;
1581         
1582         pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
1583         return (0);
1584 }
1585
1586 static int
1587 agp_i830_set_aperture(device_t dev, u_int32_t aperture)
1588 {
1589         struct agp_i810_softc *sc;
1590         u_int16_t gcc1;
1591
1592         sc = device_get_softc(dev);
1593
1594         if (aperture != 64 * 1024 * 1024 &&
1595             aperture != 128 * 1024 * 1024) {
1596                 device_printf(dev, "bad aperture size %d\n", aperture);
1597                 return (EINVAL);
1598         }
1599         gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
1600         gcc1 &= ~AGP_I830_GCC1_GMASIZE;
1601         if (aperture == 64 * 1024 * 1024)
1602                 gcc1 |= AGP_I830_GCC1_GMASIZE_64;
1603         else
1604                 gcc1 |= AGP_I830_GCC1_GMASIZE_128;
1605
1606         pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
1607         return (0);
1608 }
1609
1610 static int
1611 agp_i915_set_aperture(device_t dev, u_int32_t aperture)
1612 {
1613
1614         return (agp_generic_set_aperture(dev, aperture));
1615 }
1616
1617 static int
1618 agp_i810_method_set_aperture(device_t dev, u_int32_t aperture)
1619 {
1620         struct agp_i810_softc *sc;
1621
1622         sc = device_get_softc(dev);
1623         return (sc->match->driver->set_aperture(dev, aperture));
1624 }
1625
1626 /**
1627  * Writes a GTT entry mapping the page at the given offset from the
1628  * beginning of the aperture to the given physical address.  Setup the
1629  * caching mode according to flags.
1630  *
1631  * For gen 1, 2 and 3, GTT start is located at AGP_I810_GTT offset
1632  * from corresponding BAR start. For gen 4, offset is 512KB +
1633  * AGP_I810_GTT, for gen 5 and 6 it is 2MB + AGP_I810_GTT.
1634  *
1635  * Also, the bits of the physical page address above 4GB needs to be
1636  * placed into bits 40-32 of PTE.
1637  */
1638 static void
1639 agp_i810_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1640     int flags)
1641 {
1642         uint32_t pte;
1643
1644         pte = (u_int32_t)physical | I810_PTE_VALID;
1645         if (flags == AGP_DCACHE_MEMORY)
1646                 pte |= I810_PTE_LOCAL;
1647         else if (flags == AGP_USER_CACHED_MEMORY)
1648                 pte |= I830_PTE_SYSTEM_CACHED;
1649         agp_i810_write_gtt(dev, index, pte);
1650 }
1651
1652 static void
1653 agp_i810_write_gtt(device_t dev, u_int index, uint32_t pte)
1654 {
1655         struct agp_i810_softc *sc;
1656
1657         sc = device_get_softc(dev);
1658         bus_write_4(sc->sc_res[0], AGP_I810_GTT + index * 4, pte);
1659 }
1660
1661 static void
1662 agp_i830_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1663     int flags)
1664 {
1665         uint32_t pte;
1666
1667         pte = (u_int32_t)physical | I810_PTE_VALID;
1668         if (flags == AGP_USER_CACHED_MEMORY)
1669                 pte |= I830_PTE_SYSTEM_CACHED;
1670         agp_i810_write_gtt(dev, index, pte);
1671 }
1672
1673 static void
1674 agp_i915_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1675     int flags)
1676 {
1677         uint32_t pte;
1678
1679         pte = (u_int32_t)physical | I810_PTE_VALID;
1680         if (flags == AGP_USER_CACHED_MEMORY)
1681                 pte |= I830_PTE_SYSTEM_CACHED;
1682         pte |= (physical & 0x0000000f00000000ull) >> 28;
1683         agp_i915_write_gtt(dev, index, pte);
1684 }
1685
1686 static void
1687 agp_i915_write_gtt(device_t dev, u_int index, uint32_t pte)
1688 {
1689         struct agp_i810_softc *sc;
1690
1691         sc = device_get_softc(dev);
1692         bus_write_4(sc->sc_res[1], index * 4, pte);
1693 }
1694
1695 static void
1696 agp_i965_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1697     int flags)
1698 {
1699         uint32_t pte;
1700
1701         pte = (u_int32_t)physical | I810_PTE_VALID;
1702         if (flags == AGP_USER_CACHED_MEMORY)
1703                 pte |= I830_PTE_SYSTEM_CACHED;
1704         pte |= (physical & 0x0000000f00000000ull) >> 28;
1705         agp_i965_write_gtt(dev, index, pte);
1706 }
1707
1708 static void
1709 agp_i965_write_gtt(device_t dev, u_int index, uint32_t pte)
1710 {
1711         struct agp_i810_softc *sc;
1712
1713         sc = device_get_softc(dev);
1714         bus_write_4(sc->sc_res[0], index * 4 + (512 * 1024), pte);
1715 }
1716
1717 static void
1718 agp_g4x_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1719     int flags)
1720 {
1721         uint32_t pte;
1722
1723         pte = (u_int32_t)physical | I810_PTE_VALID;
1724         if (flags == AGP_USER_CACHED_MEMORY)
1725                 pte |= I830_PTE_SYSTEM_CACHED;
1726         pte |= (physical & 0x0000000f00000000ull) >> 28;
1727         agp_g4x_write_gtt(dev, index, pte);
1728 }
1729
1730 static void
1731 agp_g4x_write_gtt(device_t dev, u_int index, uint32_t pte)
1732 {
1733         struct agp_i810_softc *sc;
1734
1735         sc = device_get_softc(dev);
1736         bus_write_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024), pte);
1737 }
1738
1739 static void
1740 agp_sb_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1741     int flags)
1742 {
1743         int type_mask, gfdt;
1744         uint32_t pte;
1745
1746         pte = (u_int32_t)physical | I810_PTE_VALID;
1747         type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1748         gfdt = (flags & AGP_USER_CACHED_MEMORY_GFDT) != 0 ? GEN6_PTE_GFDT : 0;
1749
1750         if (type_mask == AGP_USER_MEMORY)
1751                 pte |= GEN6_PTE_UNCACHED;
1752         else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)
1753                 pte |= GEN6_PTE_LLC_MLC | gfdt;
1754         else
1755                 pte |= GEN6_PTE_LLC | gfdt;
1756
1757         pte |= (physical & 0x000000ff00000000ull) >> 28;
1758         agp_sb_write_gtt(dev, index, pte);
1759 }
1760
1761 static void
1762 agp_sb_write_gtt(device_t dev, u_int index, uint32_t pte)
1763 {
1764         struct agp_i810_softc *sc;
1765
1766         sc = device_get_softc(dev);
1767         bus_write_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024), pte);
1768 }
1769
1770 static int
1771 agp_i810_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
1772 {
1773         struct agp_i810_softc *sc = device_get_softc(dev);
1774         u_int index;
1775
1776         if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
1777                 device_printf(dev, "failed: offset is 0x%08jx, "
1778                     "shift is %d, entries is %d\n", (intmax_t)offset,
1779                     AGP_PAGE_SHIFT, sc->gatt->ag_entries);
1780                 return (EINVAL);
1781         }
1782         index = offset >> AGP_PAGE_SHIFT;
1783         if (sc->stolen != 0 && index < sc->stolen) {
1784                 device_printf(dev, "trying to bind into stolen memory\n");
1785                 return (EINVAL);
1786         }
1787         sc->match->driver->install_gtt_pte(dev, index, physical, 0);
1788         return (0);
1789 }
1790
1791 static int
1792 agp_i810_unbind_page(device_t dev, vm_offset_t offset)
1793 {
1794         struct agp_i810_softc *sc;
1795         u_int index;
1796
1797         sc = device_get_softc(dev);
1798         if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
1799                 return (EINVAL);
1800         index = offset >> AGP_PAGE_SHIFT;
1801         if (sc->stolen != 0 && index < sc->stolen) {
1802                 device_printf(dev, "trying to unbind from stolen memory\n");
1803                 return (EINVAL);
1804         }
1805         sc->match->driver->install_gtt_pte(dev, index, 0, 0);
1806         return (0);
1807 }
1808
1809 static u_int32_t
1810 agp_i810_read_gtt_pte(device_t dev, u_int index)
1811 {
1812         struct agp_i810_softc *sc;
1813         u_int32_t pte;
1814
1815         sc = device_get_softc(dev);
1816         pte = bus_read_4(sc->sc_res[0], AGP_I810_GTT + index * 4);
1817         return (pte);
1818 }
1819
1820 static u_int32_t
1821 agp_i915_read_gtt_pte(device_t dev, u_int index)
1822 {
1823         struct agp_i810_softc *sc;
1824         u_int32_t pte;
1825
1826         sc = device_get_softc(dev);
1827         pte = bus_read_4(sc->sc_res[1], index * 4);
1828         return (pte);
1829 }
1830
1831 static u_int32_t
1832 agp_i965_read_gtt_pte(device_t dev, u_int index)
1833 {
1834         struct agp_i810_softc *sc;
1835         u_int32_t pte;
1836
1837         sc = device_get_softc(dev);
1838         pte = bus_read_4(sc->sc_res[0], index * 4 + (512 * 1024));
1839         return (pte);
1840 }
1841
1842 static u_int32_t
1843 agp_g4x_read_gtt_pte(device_t dev, u_int index)
1844 {
1845         struct agp_i810_softc *sc;
1846         u_int32_t pte;
1847
1848         sc = device_get_softc(dev);
1849         pte = bus_read_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024));
1850         return (pte);
1851 }
1852
1853 static vm_paddr_t
1854 agp_i810_read_gtt_pte_paddr(device_t dev, u_int index)
1855 {
1856         struct agp_i810_softc *sc;
1857         u_int32_t pte;
1858         vm_paddr_t res;
1859
1860         sc = device_get_softc(dev);
1861         pte = sc->match->driver->read_gtt_pte(dev, index);
1862         res = pte & ~PAGE_MASK;
1863         return (res);
1864 }
1865
1866 static vm_paddr_t
1867 agp_i915_read_gtt_pte_paddr(device_t dev, u_int index)
1868 {
1869         struct agp_i810_softc *sc;
1870         u_int32_t pte;
1871         vm_paddr_t res;
1872
1873         sc = device_get_softc(dev);
1874         pte = sc->match->driver->read_gtt_pte(dev, index);
1875         res = (pte & ~PAGE_MASK) | ((pte & 0xf0) << 28);
1876         return (res);
1877 }
1878
1879 static vm_paddr_t
1880 agp_sb_read_gtt_pte_paddr(device_t dev, u_int index)
1881 {
1882         struct agp_i810_softc *sc;
1883         u_int32_t pte;
1884         vm_paddr_t res;
1885
1886         sc = device_get_softc(dev);
1887         pte = sc->match->driver->read_gtt_pte(dev, index);
1888         res = (pte & ~PAGE_MASK) | ((pte & 0xff0) << 28);
1889         return (res);
1890 }
1891
1892 /*
1893  * Writing via memory mapped registers already flushes all TLBs.
1894  */
1895 static void
1896 agp_i810_flush_tlb(device_t dev)
1897 {
1898 }
1899
1900 static int
1901 agp_i810_enable(device_t dev, u_int32_t mode)
1902 {
1903
1904         return (0);
1905 }
1906
1907 static struct agp_memory *
1908 agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
1909 {
1910         struct agp_i810_softc *sc;
1911         struct agp_memory *mem;
1912         vm_page_t m;
1913
1914         sc = device_get_softc(dev);
1915
1916         if ((size & (AGP_PAGE_SIZE - 1)) != 0 ||
1917             sc->agp.as_allocated + size > sc->agp.as_maxmem)
1918                 return (0);
1919
1920         if (type == 1) {
1921                 /*
1922                  * Mapping local DRAM into GATT.
1923                  */
1924                 if (sc->match->driver->chiptype != CHIP_I810)
1925                         return (0);
1926                 if (size != sc->dcache_size)
1927                         return (0);
1928         } else if (type == 2) {
1929                 /*
1930                  * Type 2 is the contiguous physical memory type, that hands
1931                  * back a physical address.  This is used for cursors on i810.
1932                  * Hand back as many single pages with physical as the user
1933                  * wants, but only allow one larger allocation (ARGB cursor)
1934                  * for simplicity.
1935                  */
1936                 if (size != AGP_PAGE_SIZE) {
1937                         if (sc->argb_cursor != NULL)
1938                                 return (0);
1939
1940                         /* Allocate memory for ARGB cursor, if we can. */
1941                         sc->argb_cursor = contigmalloc(size, M_AGP,
1942                            0, 0, ~0, PAGE_SIZE, 0);
1943                         if (sc->argb_cursor == NULL)
1944                                 return (0);
1945                 }
1946         }
1947
1948         mem = kmalloc(sizeof *mem, M_AGP, M_INTWAIT);
1949         mem->am_id = sc->agp.as_nextid++;
1950         mem->am_size = size;
1951         mem->am_type = type;
1952         if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
1953                 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
1954                     atop(round_page(size)));
1955         else
1956                 mem->am_obj = 0;
1957
1958         if (type == 2) {
1959                 if (size == AGP_PAGE_SIZE) {
1960                         /*
1961                          * Allocate and wire down the page now so that we can
1962                          * get its physical address.
1963                          */
1964                         VM_OBJECT_LOCK(mem->am_obj);
1965                         m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NORMAL |
1966                                                          VM_ALLOC_ZERO |
1967                                                          VM_ALLOC_RETRY);
1968                         vm_page_wire(m);
1969                         VM_OBJECT_UNLOCK(mem->am_obj);
1970                         mem->am_physical = VM_PAGE_TO_PHYS(m);
1971                         vm_page_wakeup(m);
1972                 } else {
1973                         /* Our allocation is already nicely wired down for us.
1974                          * Just grab the physical address.
1975                          */
1976                         mem->am_physical = vtophys(sc->argb_cursor);
1977                 }
1978         } else
1979                 mem->am_physical = 0;
1980
1981         mem->am_offset = 0;
1982         mem->am_is_bound = 0;
1983         TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
1984         sc->agp.as_allocated += size;
1985
1986         return (mem);
1987 }
1988
1989 static int
1990 agp_i810_free_memory(device_t dev, struct agp_memory *mem)
1991 {
1992         struct agp_i810_softc *sc;
1993
1994         if (mem->am_is_bound)
1995                 return (EBUSY);
1996
1997         sc = device_get_softc(dev);
1998
1999         if (mem->am_type == 2) {
2000                 if (mem->am_size == AGP_PAGE_SIZE) {
2001                         /*
2002                          * Unwire the page which we wired in alloc_memory.
2003                          */
2004                         vm_page_t m;
2005
2006                         vm_object_hold(mem->am_obj);
2007                         m = vm_page_lookup_busy_wait(mem->am_obj, 0,
2008                                                      FALSE, "agppg");
2009                         vm_object_drop(mem->am_obj);
2010                         vm_page_unwire(m, 0);
2011                         vm_page_wakeup(m);
2012                 } else {
2013                         contigfree(sc->argb_cursor, mem->am_size, M_AGP);
2014                         sc->argb_cursor = NULL;
2015                 }
2016         }
2017
2018         sc->agp.as_allocated -= mem->am_size;
2019         TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
2020         if (mem->am_obj)
2021                 vm_object_deallocate(mem->am_obj);
2022         kfree(mem, M_AGP);
2023         return (0);
2024 }
2025
2026 static int
2027 agp_i810_bind_memory(device_t dev, struct agp_memory *mem, vm_offset_t offset)
2028 {
2029         struct agp_i810_softc *sc;
2030         vm_offset_t i;
2031
2032         /* Do some sanity checks first. */
2033         if ((offset & (AGP_PAGE_SIZE - 1)) != 0 ||
2034             offset + mem->am_size > AGP_GET_APERTURE(dev)) {
2035                 device_printf(dev, "binding memory at bad offset %#x\n",
2036                     (int)offset);
2037                 return (EINVAL);
2038         }
2039
2040         sc = device_get_softc(dev);
2041         if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
2042                 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
2043                 if (mem->am_is_bound) {
2044                         lockmgr(&sc->agp.as_lock, LK_RELEASE);
2045                         return EINVAL;
2046                 }
2047                 /* The memory's already wired down, just stick it in the GTT. */
2048                 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
2049                         sc->match->driver->install_gtt_pte(dev, (offset + i) >>
2050                             AGP_PAGE_SHIFT, mem->am_physical + i, 0);
2051                 }
2052                 agp_flush_cache();
2053                 mem->am_offset = offset;
2054                 mem->am_is_bound = 1;
2055                 lockmgr(&sc->agp.as_lock, LK_RELEASE);
2056                 return (0);
2057         }
2058
2059         if (mem->am_type != 1)
2060                 return (agp_generic_bind_memory(dev, mem, offset));
2061
2062         /*
2063          * Mapping local DRAM into GATT.
2064          */
2065         if (sc->match->driver->chiptype != CHIP_I810)
2066                 return (EINVAL);
2067         for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
2068                 bus_write_4(sc->sc_res[0],
2069                     AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
2070
2071         return (0);
2072 }
2073
2074 static int
2075 agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
2076 {
2077         struct agp_i810_softc *sc;
2078         vm_offset_t i;
2079
2080         sc = device_get_softc(dev);
2081
2082         if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
2083                 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
2084                 if (!mem->am_is_bound) {
2085                         lockmgr(&sc->agp.as_lock, LK_RELEASE);
2086                         return (EINVAL);
2087                 }
2088
2089                 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
2090                         sc->match->driver->install_gtt_pte(dev,
2091                             (mem->am_offset + i) >> AGP_PAGE_SHIFT, 0, 0);
2092                 }
2093                 agp_flush_cache();
2094                 mem->am_is_bound = 0;
2095                 lockmgr(&sc->agp.as_lock, LK_RELEASE);
2096                 return (0);
2097         }
2098
2099         if (mem->am_type != 1)
2100                 return (agp_generic_unbind_memory(dev, mem));
2101
2102         if (sc->match->driver->chiptype != CHIP_I810)
2103                 return (EINVAL);
2104         for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
2105                 sc->match->driver->install_gtt_pte(dev, i >> AGP_PAGE_SHIFT,
2106                     0, 0);
2107         }
2108         return (0);
2109 }
2110
2111 static device_method_t agp_i810_methods[] = {
2112         /* Device interface */
2113         DEVMETHOD(device_identify,      agp_i810_identify),
2114         DEVMETHOD(device_probe,         agp_i810_probe),
2115         DEVMETHOD(device_attach,        agp_i810_attach),
2116         DEVMETHOD(device_detach,        agp_i810_detach),
2117         DEVMETHOD(device_suspend,       bus_generic_suspend),
2118         DEVMETHOD(device_resume,        agp_i810_resume),
2119
2120         /* AGP interface */
2121         DEVMETHOD(agp_get_aperture,     agp_generic_get_aperture),
2122         DEVMETHOD(agp_set_aperture,     agp_i810_method_set_aperture),
2123         DEVMETHOD(agp_bind_page,        agp_i810_bind_page),
2124         DEVMETHOD(agp_unbind_page,      agp_i810_unbind_page),
2125         DEVMETHOD(agp_flush_tlb,        agp_i810_flush_tlb),
2126         DEVMETHOD(agp_enable,           agp_i810_enable),
2127         DEVMETHOD(agp_alloc_memory,     agp_i810_alloc_memory),
2128         DEVMETHOD(agp_free_memory,      agp_i810_free_memory),
2129         DEVMETHOD(agp_bind_memory,      agp_i810_bind_memory),
2130         DEVMETHOD(agp_unbind_memory,    agp_i810_unbind_memory),
2131         DEVMETHOD(agp_chipset_flush,    agp_intel_gtt_chipset_flush),
2132
2133         { 0, 0 }
2134 };
2135
2136 static driver_t agp_i810_driver = {
2137         "agp",
2138         agp_i810_methods,
2139         sizeof(struct agp_i810_softc),
2140 };
2141
2142 static devclass_t agp_devclass;
2143
2144 DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, NULL, NULL);
2145 MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
2146 MODULE_DEPEND(agp_i810, pci, 1, 1, 1);
2147
2148 extern vm_page_t bogus_page;
2149
2150 void
2151 agp_intel_gtt_clear_range(device_t dev, u_int first_entry, u_int num_entries)
2152 {
2153         struct agp_i810_softc *sc;
2154         u_int i;
2155
2156         sc = device_get_softc(dev);
2157         for (i = 0; i < num_entries; i++)
2158                 sc->match->driver->install_gtt_pte(dev, first_entry + i,
2159                     VM_PAGE_TO_PHYS(bogus_page), 0);
2160         sc->match->driver->read_gtt_pte(dev, first_entry + num_entries - 1);
2161 }
2162
2163 void
2164 agp_intel_gtt_insert_pages(device_t dev, u_int first_entry, u_int num_entries,
2165     vm_page_t *pages, u_int flags)
2166 {
2167         struct agp_i810_softc *sc;
2168         u_int i;
2169
2170         sc = device_get_softc(dev);
2171         for (i = 0; i < num_entries; i++) {
2172                 KKASSERT(pages[i]->valid == VM_PAGE_BITS_ALL);
2173                 KKASSERT(pages[i]->wire_count > 0);
2174                 sc->match->driver->install_gtt_pte(dev, first_entry + i,
2175                     VM_PAGE_TO_PHYS(pages[i]), flags);
2176         }
2177         sc->match->driver->read_gtt_pte(dev, first_entry + num_entries - 1);
2178 }
2179
2180 struct intel_gtt
2181 agp_intel_gtt_get(device_t dev)
2182 {
2183         struct agp_i810_softc *sc;
2184         struct intel_gtt res;
2185
2186         sc = device_get_softc(dev);
2187         res.stolen_size = sc->stolen_size;
2188         res.gtt_total_entries = sc->gtt_total_entries;
2189         res.gtt_mappable_entries = sc->gtt_mappable_entries;
2190         res.do_idle_maps = 0;
2191         res.scratch_page_dma = VM_PAGE_TO_PHYS(bogus_page);
2192         return (res);
2193 }
2194
2195 static int
2196 agp_i810_chipset_flush_setup(device_t dev)
2197 {
2198
2199         return (0);
2200 }
2201
2202 static void
2203 agp_i810_chipset_flush_teardown(device_t dev)
2204 {
2205
2206         /* Nothing to do. */
2207 }
2208
2209 static void
2210 agp_i810_chipset_flush(device_t dev)
2211 {
2212
2213         /* Nothing to do. */
2214 }
2215
2216 static void
2217 agp_i830_chipset_flush(device_t dev)
2218 {
2219         struct agp_i810_softc *sc;
2220         uint32_t hic;
2221         int i;
2222
2223         sc = device_get_softc(dev);
2224         cpu_wbinvd_on_all_cpus();
2225         hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC);
2226         bus_write_4(sc->sc_res[0], AGP_I830_HIC, hic | (1 << 31));
2227         for (i = 0; i < 20000 /* 1 sec */; i++) {
2228                 hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC);
2229                 if ((hic & (1 << 31)) != 0)
2230                         break;
2231                 DELAY(50);
2232         }
2233 }
2234
2235 static int
2236 agp_i915_chipset_flush_alloc_page(device_t dev, uint64_t start, uint64_t end)
2237 {
2238         struct agp_i810_softc *sc;
2239         device_t vga;
2240
2241         sc = device_get_softc(dev);
2242         vga = device_get_parent(dev);
2243         sc->sc_flush_page_rid = 100;
2244         sc->sc_flush_page_res = BUS_ALLOC_RESOURCE(device_get_parent(vga), dev,
2245             SYS_RES_MEMORY, &sc->sc_flush_page_rid, start, end, PAGE_SIZE,
2246             RF_ACTIVE, -1);
2247         if (sc->sc_flush_page_res == NULL) {
2248                 device_printf(dev, "Failed to allocate flush page at 0x%jx\n",
2249                     (uintmax_t)start);
2250                 return (EINVAL);
2251         }
2252         sc->sc_flush_page_vaddr = rman_get_virtual(sc->sc_flush_page_res);
2253         if (bootverbose) {
2254                 device_printf(dev, "Allocated flush page phys 0x%jx virt %p\n",
2255                     (uintmax_t)rman_get_start(sc->sc_flush_page_res),
2256                     sc->sc_flush_page_vaddr);
2257         }
2258         return (0);
2259 }
2260
2261 static void
2262 agp_i915_chipset_flush_free_page(device_t dev)
2263 {
2264         struct agp_i810_softc *sc;
2265         device_t vga;
2266
2267         sc = device_get_softc(dev);
2268         vga = device_get_parent(dev);
2269         if (sc->sc_flush_page_res == NULL)
2270                 return;
2271         BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev, SYS_RES_MEMORY,
2272             sc->sc_flush_page_rid, sc->sc_flush_page_res);
2273         BUS_RELEASE_RESOURCE(device_get_parent(vga), dev, SYS_RES_MEMORY,
2274             sc->sc_flush_page_rid, sc->sc_flush_page_res);
2275 }
2276
2277 static int
2278 agp_i915_chipset_flush_setup(device_t dev)
2279 {
2280         struct agp_i810_softc *sc;
2281         uint32_t temp;
2282         int error;
2283
2284         sc = device_get_softc(dev);
2285         temp = pci_read_config(sc->bdev, AGP_I915_IFPADDR, 4);
2286         if ((temp & 1) != 0) {
2287                 temp &= ~1;
2288                 if (bootverbose)
2289                         device_printf(dev,
2290                             "Found already configured flush page at 0x%jx\n",
2291                             (uintmax_t)temp);
2292                 sc->sc_bios_allocated_flush_page = 1;
2293                 /*
2294                  * In the case BIOS initialized the flush pointer (?)
2295                  * register, expect that BIOS also set up the resource
2296                  * for the page.
2297                  */
2298                 error = agp_i915_chipset_flush_alloc_page(dev, temp,
2299                     temp + PAGE_SIZE - 1);
2300                 if (error != 0)
2301                         return (error);
2302         } else {
2303                 sc->sc_bios_allocated_flush_page = 0;
2304                 error = agp_i915_chipset_flush_alloc_page(dev, 0, 0xffffffff);
2305                 if (error != 0)
2306                         return (error);
2307                 temp = rman_get_start(sc->sc_flush_page_res);
2308                 pci_write_config(sc->bdev, AGP_I915_IFPADDR, temp | 1, 4);
2309         }
2310         return (0);
2311 }
2312
2313 static void
2314 agp_i915_chipset_flush_teardown(device_t dev)
2315 {
2316         struct agp_i810_softc *sc;
2317         uint32_t temp;
2318
2319         sc = device_get_softc(dev);
2320         if (sc->sc_flush_page_res == NULL)
2321                 return;
2322         if (!sc->sc_bios_allocated_flush_page) {
2323                 temp = pci_read_config(sc->bdev, AGP_I915_IFPADDR, 4);
2324                 temp &= ~1;
2325                 pci_write_config(sc->bdev, AGP_I915_IFPADDR, temp, 4);
2326         }
2327         agp_i915_chipset_flush_free_page(dev);
2328 }
2329
2330 static int
2331 agp_i965_chipset_flush_setup(device_t dev)
2332 {
2333         struct agp_i810_softc *sc;
2334         uint64_t temp;
2335         uint32_t temp_hi, temp_lo;
2336         int error;
2337
2338         sc = device_get_softc(dev);
2339
2340         temp_hi = pci_read_config(sc->bdev, AGP_I965_IFPADDR + 4, 4);
2341         temp_lo = pci_read_config(sc->bdev, AGP_I965_IFPADDR, 4);
2342
2343         if ((temp_lo & 1) != 0) {
2344                 temp = ((uint64_t)temp_hi << 32) | (temp_lo & ~1);
2345                 if (bootverbose)
2346                         device_printf(dev,
2347                             "Found already configured flush page at 0x%jx\n",
2348                             (uintmax_t)temp);
2349                 sc->sc_bios_allocated_flush_page = 1;
2350                 /*
2351                  * In the case BIOS initialized the flush pointer (?)
2352                  * register, expect that BIOS also set up the resource
2353                  * for the page.
2354                  */
2355                 error = agp_i915_chipset_flush_alloc_page(dev, temp,
2356                     temp + PAGE_SIZE - 1);
2357                 if (error != 0)
2358                         return (error);
2359         } else {
2360                 sc->sc_bios_allocated_flush_page = 0;
2361                 error = agp_i915_chipset_flush_alloc_page(dev, 0, ~0);
2362                 if (error != 0)
2363                         return (error);
2364                 temp = rman_get_start(sc->sc_flush_page_res);
2365                 pci_write_config(sc->bdev, AGP_I965_IFPADDR + 4,
2366                     (temp >> 32) & UINT32_MAX, 4);
2367                 pci_write_config(sc->bdev, AGP_I965_IFPADDR,
2368                     (temp & UINT32_MAX) | 1, 4);
2369         }
2370         return (0);
2371 }
2372
2373 static void
2374 agp_i965_chipset_flush_teardown(device_t dev)
2375 {
2376         struct agp_i810_softc *sc;
2377         uint32_t temp_lo;
2378
2379         sc = device_get_softc(dev);
2380         if (sc->sc_flush_page_res == NULL)
2381                 return;
2382         if (!sc->sc_bios_allocated_flush_page) {
2383                 temp_lo = pci_read_config(sc->bdev, AGP_I965_IFPADDR, 4);
2384                 temp_lo &= ~1;
2385                 pci_write_config(sc->bdev, AGP_I965_IFPADDR, temp_lo, 4);
2386         }
2387         agp_i915_chipset_flush_free_page(dev);
2388 }
2389
2390 static void
2391 agp_i915_chipset_flush(device_t dev)
2392 {
2393         struct agp_i810_softc *sc;
2394
2395         sc = device_get_softc(dev);
2396         *(uint32_t *)sc->sc_flush_page_vaddr = 1;
2397 }
2398
2399 int
2400 agp_intel_gtt_chipset_flush(device_t dev)
2401 {
2402         struct agp_i810_softc *sc;
2403
2404         sc = device_get_softc(dev);
2405         sc->match->driver->chipset_flush(dev);
2406         return (0);
2407 }
2408
2409 void
2410 agp_intel_gtt_unmap_memory(device_t dev, struct sglist *sg_list)
2411 {
2412 }
2413
2414 int
2415 agp_intel_gtt_map_memory(device_t dev, vm_page_t *pages, u_int num_entries,
2416     struct sglist **sg_list)
2417 {
2418         struct agp_i810_softc *sc;
2419         struct sglist *sg;
2420         int i;
2421 #if 0
2422         int error;
2423         bus_dma_tag_t dmat;
2424 #endif
2425
2426         if (*sg_list != NULL)
2427                 return (0);
2428         sc = device_get_softc(dev);
2429         sg = sglist_alloc(num_entries, M_WAITOK /* XXXKIB */);
2430         for (i = 0; i < num_entries; i++) {
2431                 sg->sg_segs[i].ss_paddr = VM_PAGE_TO_PHYS(pages[i]);
2432                 sg->sg_segs[i].ss_len = PAGE_SIZE;
2433         }
2434
2435 #if 0
2436         error = bus_dma_tag_create(bus_get_dma_tag(dev),
2437             1 /* alignment */, 0 /* boundary */,
2438             1ULL << sc->match->busdma_addr_mask_sz /* lowaddr */,
2439             BUS_SPACE_MAXADDR /* highaddr */,
2440             NULL /* filtfunc */, NULL /* filtfuncarg */,
2441             BUS_SPACE_MAXADDR /* maxsize */,
2442             BUS_SPACE_UNRESTRICTED /* nsegments */,
2443             BUS_SPACE_MAXADDR /* maxsegsz */,
2444             0 /* flags */, NULL /* lockfunc */, NULL /* lockfuncarg */,
2445             &dmat);
2446         if (error != 0) {
2447                 sglist_free(sg);
2448                 return (error);
2449         }
2450         /* XXXKIB */
2451 #endif
2452         *sg_list = sg;
2453         return (0);
2454 }
2455
2456 void
2457 agp_intel_gtt_insert_sg_entries(device_t dev, struct sglist *sg_list,
2458     u_int first_entry, u_int flags)
2459 {
2460         struct agp_i810_softc *sc;
2461         vm_paddr_t spaddr;
2462         size_t slen;
2463         u_int i, j;
2464
2465         sc = device_get_softc(dev);
2466         for (i = j = 0; j < sg_list->sg_nseg; j++) {
2467                 spaddr = sg_list->sg_segs[i].ss_paddr;
2468                 slen = sg_list->sg_segs[i].ss_len;
2469                 for (; slen > 0; i++) {
2470                         sc->match->driver->install_gtt_pte(dev, first_entry + i,
2471                             spaddr, flags);
2472                         spaddr += AGP_PAGE_SIZE;
2473                         slen -= AGP_PAGE_SIZE;
2474                 }
2475         }
2476         sc->match->driver->read_gtt_pte(dev, first_entry + i - 1);
2477 }
2478
2479 void
2480 intel_gtt_clear_range(u_int first_entry, u_int num_entries)
2481 {
2482
2483         agp_intel_gtt_clear_range(intel_agp, first_entry, num_entries);
2484 }
2485
2486 void
2487 intel_gtt_insert_pages(u_int first_entry, u_int num_entries, vm_page_t *pages,
2488     u_int flags)
2489 {
2490
2491         agp_intel_gtt_insert_pages(intel_agp, first_entry, num_entries,
2492             pages, flags);
2493 }
2494
2495 struct intel_gtt
2496 intel_gtt_get(void)
2497 {
2498
2499         return (agp_intel_gtt_get(intel_agp));
2500 }
2501
2502 int
2503 intel_gtt_chipset_flush(void)
2504 {
2505
2506         return (agp_intel_gtt_chipset_flush(intel_agp));
2507 }
2508
2509 void
2510 intel_gtt_unmap_memory(struct sglist *sg_list)
2511 {
2512
2513         agp_intel_gtt_unmap_memory(intel_agp, sg_list);
2514 }
2515
2516 int
2517 intel_gtt_map_memory(vm_page_t *pages, u_int num_entries,
2518     struct sglist **sg_list)
2519 {
2520
2521         return (agp_intel_gtt_map_memory(intel_agp, pages, num_entries,
2522             sg_list));
2523 }
2524
2525 void
2526 intel_gtt_insert_sg_entries(struct sglist *sg_list, u_int first_entry,
2527     u_int flags)
2528 {
2529
2530         agp_intel_gtt_insert_sg_entries(intel_agp, sg_list, first_entry, flags);
2531 }
2532
2533 device_t
2534 intel_gtt_get_bridge_device(void)
2535 {
2536         struct agp_i810_softc *sc;
2537
2538         sc = device_get_softc(intel_agp);
2539         return (sc->bdev);
2540 }
2541
2542 vm_paddr_t
2543 intel_gtt_read_pte_paddr(u_int entry)
2544 {
2545         struct agp_i810_softc *sc;
2546
2547         sc = device_get_softc(intel_agp);
2548         return (sc->match->driver->read_gtt_pte_paddr(intel_agp, entry));
2549 }
2550
2551 u_int32_t
2552 intel_gtt_read_pte(u_int entry)
2553 {
2554         struct agp_i810_softc *sc;
2555
2556         sc = device_get_softc(intel_agp);
2557         return (sc->match->driver->read_gtt_pte(intel_agp, entry));
2558 }
2559
2560 void
2561 intel_gtt_write(u_int entry, uint32_t val)
2562 {
2563         struct agp_i810_softc *sc;
2564
2565         sc = device_get_softc(intel_agp);
2566         return (sc->match->driver->write_gtt(intel_agp, entry, val));
2567 }