2 * Copyright (c) 2011 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/bitops.h>
42 #include <bus/pci/pcivar.h>
43 #include <bus/pci/pcireg.h>
44 #include <bus/pci/pcibus.h>
45 #include <bus/pci/pci_cfgreg.h>
46 #include <bus/pci/pcib_private.h>
52 #include <dev/misc/ecc/ecc_e31200_reg.h>
54 #define ECC_E31200_VER_1 1 /* Sandy Bridge */
55 #define ECC_E31200_VER_2 2 /* Ivy Bridge */
56 #define ECC_E31200_VER_3 3 /* Haswell */
58 struct ecc_e31200_memctrl {
62 int ver; /* ECC_E31200_VER_ */
65 struct ecc_e31200_softc {
68 struct callout ecc_callout;
69 int ecc_ver; /* ECC_E31200_VER_ */
70 volatile uint8_t *ecc_addr;
73 #define CSR_READ_4(sc, ofs) (*(volatile uint32_t *)((sc)->ecc_addr + (ofs)))
75 #define ecc_printf(sc, fmt, arg...) \
76 device_printf((sc)->ecc_mydev, fmt , ##arg)
78 static int ecc_e31200_probe(device_t);
79 static int ecc_e31200_attach(device_t);
81 static void ecc_e31200_chaninfo(struct ecc_e31200_softc *, uint32_t,
83 static void ecc_e31200_status(struct ecc_e31200_softc *);
84 static void ecc_e31200_callout(void *);
85 static void ecc_e31200_errlog(struct ecc_e31200_softc *);
86 static void ecc_e31200_errlog_ch(struct ecc_e31200_softc *, int, int,
89 static const struct ecc_e31200_memctrl ecc_memctrls[] = {
90 { 0x8086, 0x0108, "Intel E3-1200 memory controller",
92 { 0x8086, 0x0158, "Intel E3-1200 v2 memory controller",
94 { 0x8086, 0x0c08, "Intel E3-1200 v3 memory controller",
96 { 0, 0, NULL } /* required last entry */
99 static device_method_t ecc_e31200_methods[] = {
100 /* Device interface */
101 DEVMETHOD(device_probe, ecc_e31200_probe),
102 DEVMETHOD(device_attach, ecc_e31200_attach),
103 DEVMETHOD(device_shutdown, bus_generic_shutdown),
104 DEVMETHOD(device_suspend, bus_generic_suspend),
105 DEVMETHOD(device_resume, bus_generic_resume),
109 static driver_t ecc_e31200_driver = {
112 sizeof(struct ecc_e31200_softc)
114 static devclass_t ecc_devclass;
115 DRIVER_MODULE(ecc_e31200, hostb, ecc_e31200_driver, ecc_devclass, NULL, NULL);
116 MODULE_DEPEND(ecc_e31200, pci, 1, 1, 1);
119 ecc_e31200_probe(device_t dev)
121 const struct ecc_e31200_memctrl *mc;
124 vid = pci_get_vendor(dev);
125 did = pci_get_device(dev);
127 for (mc = ecc_memctrls; mc->desc != NULL; ++mc) {
128 if (mc->vid == vid && mc->did == did) {
129 struct ecc_e31200_softc *sc = device_get_softc(dev);
131 device_set_desc(dev, mc->desc);
133 sc->ecc_device = device_get_parent(dev);
134 sc->ecc_ver = mc->ver;
142 ecc_e31200_attach(device_t dev)
144 struct ecc_e31200_softc *sc = device_get_softc(dev);
145 uint32_t capa, dmfc, mch_barlo, mch_barhi;
147 int bus, slot, dmfc_parsed = 1;
149 dev = sc->ecc_device; /* XXX */
151 bus = pci_get_bus(dev);
152 slot = pci_get_slot(dev);
154 capa = pcib_read_config(dev, bus, slot, 0, PCI_E31200_CAPID0_A, 4);
156 if (sc->ecc_ver == ECC_E31200_VER_1) {
157 dmfc = __SHIFTOUT(capa, PCI_E31200_CAPID0_A_DMFC);
161 capb = pcib_read_config(dev, bus, slot, 0,
162 PCI_E31200_CAPID0_B, 4);
163 dmfc = __SHIFTOUT(capb, PCI_E31200_CAPID0_B_DMFC);
166 if (dmfc == PCI_E31200_CAPID0_DMFC_1067) {
167 ecc_printf(sc, "CAP DDR3 1067 ");
168 } else if (dmfc == PCI_E31200_CAPID0_DMFC_1333) {
169 ecc_printf(sc, "CAP DDR3 1333 ");
171 if (sc->ecc_ver == ECC_E31200_VER_1) {
172 if (dmfc == PCI_E31200_CAPID0_DMFC_V1_ALL)
173 ecc_printf(sc, "no CAP ");
177 if (dmfc == PCI_E31200_CAPID0_DMFC_1600)
178 ecc_printf(sc, "CAP DDR3 1600 ");
179 else if (dmfc == PCI_E31200_CAPID0_DMFC_1867)
180 ecc_printf(sc, "CAP DDR3 1867 ");
181 else if (dmfc == PCI_E31200_CAPID0_DMFC_2133)
182 ecc_printf(sc, "CAP DDR3 2133 ");
183 else if (dmfc == PCI_E31200_CAPID0_DMFC_2400)
184 ecc_printf(sc, "CAP DDR3 2400 ");
185 else if (dmfc == PCI_E31200_CAPID0_DMFC_2667)
186 ecc_printf(sc, "CAP DDR3 2667 ");
187 else if (dmfc == PCI_E31200_CAPID0_DMFC_2933)
188 ecc_printf(sc, "CAP DDR3 2933 ");
194 ecc_printf(sc, "unknown DMFC %#x\n", dmfc);
198 if (capa & PCI_E31200_CAPID0_A_ECCDIS) {
199 kprintf("NON-ECC\n");
205 mch_barlo = pcib_read_config(dev, bus, slot, 0,
206 PCI_E31200_MCHBAR_LO, 4);
207 mch_barhi = pcib_read_config(dev, bus, slot, 0,
208 PCI_E31200_MCHBAR_HI, 4);
210 mch_bar = (uint64_t)mch_barlo | (((uint64_t)mch_barhi) << 32);
212 ecc_printf(sc, "MCHBAR %jx\n", (uintmax_t)mch_bar);
214 if (mch_bar & PCI_E31200_MCHBAR_LO_EN) {
215 uint64_t map_addr = mch_bar & PCI_E31200_MCHBAR_ADDRMASK;
216 uint32_t dimm_ch0, dimm_ch1;
219 sc->ecc_addr = pmap_mapdev_uncacheable(map_addr,
223 ecc_printf(sc, "LOG0_C0 %#x\n",
224 CSR_READ_4(sc, MCH_E31200_ERRLOG0_C0));
225 ecc_printf(sc, "LOG0_C1 %#x\n",
226 CSR_READ_4(sc, MCH_E31200_ERRLOG0_C1));
229 dimm_ch0 = CSR_READ_4(sc, MCH_E31200_DIMM_CH0);
230 dimm_ch1 = CSR_READ_4(sc, MCH_E31200_DIMM_CH1);
233 ecc_e31200_chaninfo(sc, dimm_ch0, "channel0");
234 ecc_e31200_chaninfo(sc, dimm_ch1, "channel1");
238 if (sc->ecc_ver == ECC_E31200_VER_1 ||
239 sc->ecc_ver == ECC_E31200_VER_2) {
240 if (((dimm_ch0 | dimm_ch1) & MCH_E31200_DIMM_ECC) ==
241 MCH_E31200_DIMM_ECC_NONE) {
243 ecc_printf(sc, "No ECC active\n");
246 uint32_t ecc_mode0, ecc_mode1;
248 ecc_mode0 = __SHIFTOUT(dimm_ch0, MCH_E31200_DIMM_ECC);
249 ecc_mode1 = __SHIFTOUT(dimm_ch1, MCH_E31200_DIMM_ECC);
252 * Only active ALL/NONE is supported
255 if (ecc_mode0 != MCH_E31200_DIMM_ECC_NONE &&
256 ecc_mode0 != MCH_E31200_DIMM_ECC_ALL) {
258 ecc_printf(sc, "channel0, invalid ECC "
259 "active 0x%x\n", ecc_mode0);
261 if (ecc_mode1 != MCH_E31200_DIMM_ECC_NONE &&
262 ecc_mode1 != MCH_E31200_DIMM_ECC_ALL) {
264 ecc_printf(sc, "channel1, invalid ECC "
265 "active 0x%x\n", ecc_mode1);
268 if (ecc_mode0 == MCH_E31200_DIMM_ECC_NONE &&
269 ecc_mode1 == MCH_E31200_DIMM_ECC_NONE) {
271 ecc_printf(sc, "No ECC active\n");
276 pmap_unmapdev((vm_offset_t)sc->ecc_addr,
281 ecc_printf(sc, "MCHBAR is not enabled\n");
284 ecc_e31200_status(sc);
285 callout_init_mp(&sc->ecc_callout);
286 callout_reset(&sc->ecc_callout, hz, ecc_e31200_callout, sc);
292 ecc_e31200_callout(void *xsc)
294 struct ecc_e31200_softc *sc = xsc;
296 ecc_e31200_status(sc);
297 callout_reset(&sc->ecc_callout, hz, ecc_e31200_callout, sc);
301 ecc_e31200_status(struct ecc_e31200_softc *sc)
303 device_t dev = sc->ecc_device;
307 bus = pci_get_bus(dev);
308 slot = pci_get_slot(dev);
310 errsts = pcib_read_config(dev, bus, slot, 0, PCI_E31200_ERRSTS, 2);
311 if (errsts & PCI_E31200_ERRSTS_DMERR)
312 ecc_printf(sc, "Uncorrectable multilple-bit ECC error\n");
313 else if (errsts & PCI_E31200_ERRSTS_DSERR)
314 ecc_printf(sc, "Correctable single-bit ECC error\n");
316 if (errsts & (PCI_E31200_ERRSTS_DSERR | PCI_E31200_ERRSTS_DMERR)) {
317 if (sc->ecc_addr != NULL)
318 ecc_e31200_errlog(sc);
320 /* Clear pending errors */
321 pcib_write_config(dev, bus, slot, 0, PCI_E31200_ERRSTS,
327 ecc_e31200_chaninfo(struct ecc_e31200_softc *sc, uint32_t dimm_ch,
330 int size_a, size_b, ecc;
332 size_a = __SHIFTOUT(dimm_ch, MCH_E31200_DIMM_A_SIZE);
334 ecc_printf(sc, "%s, DIMM A %dMB %s %s\n", desc,
335 size_a * MCH_E31200_DIMM_SIZE_UNIT,
336 (dimm_ch & MCH_E31200_DIMM_A_X16) ? "X16" : "X8",
337 (dimm_ch & MCH_E31200_DIMM_A_DUAL_RANK) ?
341 size_b = __SHIFTOUT(dimm_ch, MCH_E31200_DIMM_B_SIZE);
343 ecc_printf(sc, "%s, DIMM B %dMB %s %s\n", desc,
344 size_b * MCH_E31200_DIMM_SIZE_UNIT,
345 (dimm_ch & MCH_E31200_DIMM_B_X16) ? "X16" : "X8",
346 (dimm_ch & MCH_E31200_DIMM_B_DUAL_RANK) ?
350 if (size_a == 0 && size_b == 0)
353 ecc = __SHIFTOUT(dimm_ch, MCH_E31200_DIMM_ECC);
354 if (ecc == MCH_E31200_DIMM_ECC_NONE) {
355 ecc_printf(sc, "%s, no ECC active\n", desc);
356 } else if (ecc == MCH_E31200_DIMM_ECC_ALL) {
357 ecc_printf(sc, "%s, ECC active IO/logic\n", desc);
359 if (sc->ecc_ver == ECC_E31200_VER_1 ||
360 sc->ecc_ver == ECC_E31200_VER_2) {
361 if (ecc == MCH_E31200_DIMM_ECC_IO)
362 ecc_printf(sc, "%s, ECC active IO\n", desc);
364 ecc_printf(sc, "%s, ECC active logic\n", desc);
366 ecc_printf(sc, "%s, invalid ECC active 0x%x\n",
371 if (sc->ecc_ver == ECC_E31200_VER_1 ||
372 sc->ecc_ver == ECC_E31200_VER_2) {
373 /* This bit is V3 only */
374 dimm_ch &= ~MCH_E31200_DIMM_HORI;
376 if (dimm_ch & (MCH_E31200_DIMM_ENHI | MCH_E31200_DIMM_RI |
377 MCH_E31200_DIMM_HORI)) {
378 ecc_printf(sc, "%s", desc);
379 if (dimm_ch & MCH_E31200_DIMM_RI)
380 kprintf(", rank interleave");
381 if (dimm_ch & MCH_E31200_DIMM_ENHI)
382 kprintf(", enhanced interleave");
383 if (dimm_ch & MCH_E31200_DIMM_HORI)
384 kprintf(", high order rank interleave");
390 ecc_e31200_errlog(struct ecc_e31200_softc *sc)
392 ecc_e31200_errlog_ch(sc, MCH_E31200_ERRLOG0_C0, MCH_E31200_ERRLOG1_C0,
394 ecc_e31200_errlog_ch(sc, MCH_E31200_ERRLOG0_C1, MCH_E31200_ERRLOG1_C1,
399 ecc_e31200_errlog_ch(struct ecc_e31200_softc *sc,
400 int err0_ofs, int err1_ofs, const char *desc)
404 err0 = CSR_READ_4(sc, err0_ofs);
405 if ((err0 & (MCH_E31200_ERRLOG0_CERRSTS | MCH_E31200_ERRLOG0_MERRSTS))
409 err1 = CSR_READ_4(sc, err1_ofs);
411 ecc_printf(sc, "%s error @bank %d, rank %d, chunk %d, syndrome %d, "
412 "row %d, col %d\n", desc,
413 __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRBANK),
414 __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRRANK),
415 __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRCHUNK),
416 __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRSYND),
417 __SHIFTOUT(err1, MCH_E31200_ERRLOG1_ERRROW),
418 __SHIFTOUT(err1, MCH_E31200_ERRLOG1_ERRCOL));