1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <sys/eventhandler.h>
35 #include <dev/agp/agp_i810.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include <linux/completion.h>
40 #include <linux/workqueue.h>
42 /* General customization:
45 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
47 #define DRIVER_NAME "i915"
48 #define DRIVER_DESC "Intel Graphics"
49 #define DRIVER_DATE "20080730"
51 MALLOC_DECLARE(DRM_I915_GEM);
59 #define pipe_name(p) ((p) + 'A')
60 #define I915_NUM_PIPE 2
68 #define transcoder_name(t) ((t) + 'A')
75 #define plane_name(p) ((p) + 'A')
85 #define port_name(p) ((p) + 'A')
87 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
89 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
91 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
92 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
93 if ((intel_encoder)->base.crtc == (__crtc))
95 struct intel_pch_pll {
96 int refcount; /* count of number of CRTCs sharing this PLL */
97 int active; /* count of number of active CRTCs (i.e. DPMS on) */
98 bool on; /* is the PLL actually active? Disabled during modeset */
103 #define I915_NUM_PLLS 2
105 struct intel_ddi_plls {
111 /* Interface history:
114 * 1.2: Add Power Management
115 * 1.3: Add vblank support
116 * 1.4: Fix cmdbuffer path, add heap destroy
117 * 1.5: Add vblank pipe configuration
118 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
119 * - Support vertical blank on secondary display pipe
121 #define DRIVER_MAJOR 1
122 #define DRIVER_MINOR 6
123 #define DRIVER_PATCHLEVEL 0
125 #define WATCH_COHERENCY 0
126 #define WATCH_LISTS 0
129 #define I915_GEM_PHYS_CURSOR_0 1
130 #define I915_GEM_PHYS_CURSOR_1 2
131 #define I915_GEM_PHYS_OVERLAY_REGS 3
132 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
134 struct drm_i915_gem_phys_object {
136 drm_dma_handle_t *handle;
137 struct drm_i915_gem_object *cur_obj;
140 struct opregion_header;
141 struct opregion_acpi;
142 struct opregion_swsci;
143 struct opregion_asle;
144 struct drm_i915_private;
146 struct intel_opregion {
147 struct opregion_header __iomem *header;
148 struct opregion_acpi __iomem *acpi;
149 struct opregion_swsci __iomem *swsci;
150 struct opregion_asle __iomem *asle;
152 u32 __iomem *lid_state;
154 #define OPREGION_SIZE (8*1024)
156 struct intel_overlay;
157 struct intel_overlay_error_state;
159 struct drm_i915_master_private {
160 drm_local_map_t *sarea;
161 struct _drm_i915_sarea *sarea_priv;
163 #define I915_FENCE_REG_NONE -1
164 #define I915_MAX_NUM_FENCES 16
165 /* 16 fences + sign bit for FENCE_REG_NONE */
166 #define I915_MAX_NUM_FENCE_BITS 5
168 struct drm_i915_fence_reg {
169 struct list_head lru_list;
170 struct drm_i915_gem_object *obj;
174 struct sdvo_device_mapping {
183 struct drm_i915_error_state {
187 bool waiting[I915_NUM_RINGS];
188 u32 pipestat[I915_MAX_PIPES];
189 u32 tail[I915_NUM_RINGS];
190 u32 head[I915_NUM_RINGS];
191 u32 ipeir[I915_NUM_RINGS];
192 u32 ipehr[I915_NUM_RINGS];
193 u32 instdone[I915_NUM_RINGS];
194 u32 acthd[I915_NUM_RINGS];
195 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
196 /* our own tracking of ring head and tail */
197 u32 cpu_ring_head[I915_NUM_RINGS];
198 u32 cpu_ring_tail[I915_NUM_RINGS];
199 u32 error; /* gen6+ */
200 u32 instpm[I915_NUM_RINGS];
201 u32 instps[I915_NUM_RINGS];
203 u32 seqno[I915_NUM_RINGS];
205 u32 fault_reg[I915_NUM_RINGS];
207 u32 faddr[I915_NUM_RINGS];
208 u64 fence[I915_MAX_NUM_FENCES];
210 struct drm_i915_error_ring {
211 struct drm_i915_error_object {
215 } *ringbuffer, *batchbuffer;
216 struct drm_i915_error_request {
222 } ring[I915_NUM_RINGS];
223 struct drm_i915_error_buffer {
230 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
237 } *active_bo, *pinned_bo;
238 u32 active_bo_count, pinned_bo_count;
239 struct intel_overlay_error_state *overlay;
240 struct intel_display_error_state *display;
243 struct drm_i915_display_funcs {
244 bool (*fbc_enabled)(struct drm_device *dev);
245 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
246 void (*disable_fbc)(struct drm_device *dev);
247 int (*get_display_clock_speed)(struct drm_device *dev);
248 int (*get_fifo_size)(struct drm_device *dev, int plane);
249 void (*update_wm)(struct drm_device *dev);
250 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
251 uint32_t sprite_width, int pixel_size);
252 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
253 struct drm_display_mode *mode);
254 void (*modeset_global_resources)(struct drm_device *dev);
255 int (*crtc_mode_set)(struct drm_crtc *crtc,
256 struct drm_display_mode *mode,
257 struct drm_display_mode *adjusted_mode,
259 struct drm_framebuffer *old_fb);
260 void (*crtc_enable)(struct drm_crtc *crtc);
261 void (*crtc_disable)(struct drm_crtc *crtc);
262 void (*off)(struct drm_crtc *crtc);
263 void (*write_eld)(struct drm_connector *connector,
264 struct drm_crtc *crtc);
265 void (*fdi_link_train)(struct drm_crtc *crtc);
266 void (*init_clock_gating)(struct drm_device *dev);
267 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
268 struct drm_framebuffer *fb,
269 struct drm_i915_gem_object *obj);
270 void (*force_wake_get)(struct drm_i915_private *dev_priv);
271 void (*force_wake_put)(struct drm_i915_private *dev_priv);
272 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
274 /* clock updates for mode set */
276 /* render clock increase/decrease */
277 /* display clock increase/decrease */
278 /* pll clock increase/decrease */
281 struct drm_i915_gt_funcs {
282 void (*force_wake_get)(struct drm_i915_private *dev_priv);
283 void (*force_wake_put)(struct drm_i915_private *dev_priv);
286 #define DEV_INFO_FLAGS \
287 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
288 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
289 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
290 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
291 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
292 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
293 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
294 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
295 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
296 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
297 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
298 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
299 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
300 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
301 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
302 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
303 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
304 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
305 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
306 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
307 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
308 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
309 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
310 DEV_INFO_FLAG(has_llc)
312 struct intel_device_info {
331 u8 cursor_needs_physical:1;
333 u8 overlay_needs_physical:1;
340 #define I915_PPGTT_PD_ENTRIES 512
341 #define I915_PPGTT_PT_ENTRIES 1024
342 struct i915_hw_ppgtt {
343 unsigned num_pd_entries;
346 vm_paddr_t *pt_dma_addr;
347 vm_paddr_t scratch_page_dma_addr;
351 FBC_NO_OUTPUT, /* no outputs enabled to compress */
352 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
353 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
354 FBC_MODE_TOO_LARGE, /* mode too large for compression */
355 FBC_BAD_PLANE, /* fbc not supported on plane */
356 FBC_NOT_TILED, /* buffer not tiled */
357 FBC_MULTIPLE_PIPES, /* more than one pipe active */
361 /* defined intel_pm.c */
362 extern struct lock mchdev_lock;
364 struct opregion_header;
365 struct opregion_acpi;
366 struct opregion_swsci;
367 struct opregion_asle;
369 #define I915_FENCE_REG_NONE -1
370 #define I915_MAX_NUM_FENCES 16
371 /* 16 fences + sign bit for FENCE_REG_NONE */
372 #define I915_MAX_NUM_FENCE_BITS 5
375 PCH_NONE = 0, /* No PCH present */
376 PCH_IBX, /* Ibexpeak PCH */
377 PCH_CPT, /* Cougarpoint PCH */
378 PCH_LPT, /* Lynxpoint PCH */
381 enum intel_sbi_destination {
386 #define QUIRK_PIPEA_FORCE (1<<0)
387 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
388 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
391 struct intel_fbc_work;
397 struct drm_i915_private *dev_priv;
400 struct intel_iic_softc {
401 struct drm_device *drm_dev;
409 struct i915_suspend_saved_registers {
430 u32 saveTRANS_HTOTAL_A;
431 u32 saveTRANS_HBLANK_A;
432 u32 saveTRANS_HSYNC_A;
433 u32 saveTRANS_VTOTAL_A;
434 u32 saveTRANS_VBLANK_A;
435 u32 saveTRANS_VSYNC_A;
443 u32 savePFIT_PGM_RATIOS;
444 u32 saveBLC_HIST_CTL;
446 u32 saveBLC_PWM_CTL2;
447 u32 saveBLC_CPU_PWM_CTL;
448 u32 saveBLC_CPU_PWM_CTL2;
461 u32 saveTRANS_HTOTAL_B;
462 u32 saveTRANS_HBLANK_B;
463 u32 saveTRANS_HSYNC_B;
464 u32 saveTRANS_VTOTAL_B;
465 u32 saveTRANS_VBLANK_B;
466 u32 saveTRANS_VSYNC_B;
480 u32 savePP_ON_DELAYS;
481 u32 savePP_OFF_DELAYS;
489 u32 savePFIT_CONTROL;
490 u32 save_palette_a[256];
491 u32 save_palette_b[256];
492 u32 saveDPFC_CB_BASE;
493 u32 saveFBC_CFB_BASE;
496 u32 saveFBC_CONTROL2;
506 u32 saveCACHE_MODE_0;
507 u32 saveMI_ARB_STATE;
518 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
529 u32 savePIPEA_GMCH_DATA_M;
530 u32 savePIPEB_GMCH_DATA_M;
531 u32 savePIPEA_GMCH_DATA_N;
532 u32 savePIPEB_GMCH_DATA_N;
533 u32 savePIPEA_DP_LINK_M;
534 u32 savePIPEB_DP_LINK_M;
535 u32 savePIPEA_DP_LINK_N;
536 u32 savePIPEB_DP_LINK_N;
547 u32 savePCH_DREF_CONTROL;
548 u32 saveDISP_ARB_CTL;
549 u32 savePIPEA_DATA_M1;
550 u32 savePIPEA_DATA_N1;
551 u32 savePIPEA_LINK_M1;
552 u32 savePIPEA_LINK_N1;
553 u32 savePIPEB_DATA_M1;
554 u32 savePIPEB_DATA_N1;
555 u32 savePIPEB_LINK_M1;
556 u32 savePIPEB_LINK_N1;
557 u32 saveMCHBAR_RENDER_STANDBY;
558 u32 savePCH_PORT_HOTPLUG;
561 struct intel_gen6_power_mgmt {
562 struct work_struct work;
564 /* lock - irqsave spinlock that protectects the work_struct and
566 struct spinlock lock;
568 /* The below variables an all the rps hw state are protected by
569 * dev->struct mutext. */
574 struct delayed_work delayed_resume_work;
577 * Protects RPS/RC6 register access and PCU communication.
578 * Must be taken after struct_mutex if nested.
583 struct intel_ilk_power_mgmt {
591 unsigned long last_time1;
592 unsigned long chipset_power;
594 struct timespec last_time2;
595 unsigned long gfx_power;
601 struct drm_i915_gem_object *pwrctx;
602 struct drm_i915_gem_object *renderctx;
605 struct i915_dri1_state {
606 unsigned allow_batchbuffer : 1;
607 u32 __iomem *gfx_hws_cpu_addr;
618 struct intel_l3_parity {
620 struct work_struct error_work;
623 typedef struct drm_i915_private {
624 struct drm_device *dev;
626 const struct intel_device_info *info;
628 int relative_constants_mode;
630 device_t *gmbus_bridge;
631 device_t *bbbus_bridge;
635 drm_local_map_t *sarea;
636 drm_local_map_t *mmio_map;
638 struct drm_i915_gt_funcs gt;
639 /** gt_fifo_count and the subsequent register write are synchronized
640 * with dev->struct_mutex. */
641 unsigned gt_fifo_count;
642 /** forcewake_count is protected by gt_lock */
643 unsigned forcewake_count;
644 /** gt_lock is also taken in irq contexts. */
647 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
648 * controller on different i2c buses. */
649 struct lock gmbus_mutex;
651 drm_i915_sarea_t *sarea_priv;
652 struct intel_ring_buffer ring[I915_NUM_RINGS];
655 drm_dma_handle_t *status_page_dmah;
656 struct resource *mch_res;
658 void *hw_status_page;
659 dma_addr_t dma_status_page;
660 unsigned int status_gfx_addr;
661 drm_local_map_t hws_map;
662 struct drm_gem_object *hws_obj;
670 atomic_t irq_received;
673 /* DPIO indirect register protection */
674 struct spinlock dpio_lock;
676 /** Cached value of IER to avoid reads in updating the bitfield */
681 struct lock irq_lock;
683 u32 hotplug_supported_mask;
684 struct work_struct hotplug_work;
686 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
692 /* For hangcheck timer */
693 #define DRM_I915_HANGCHECK_PERIOD ((1500 /* in ms */ * hz) / 1000)
694 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
695 struct timer_list hangcheck_timer;
697 uint32_t last_acthd[I915_NUM_RINGS];
698 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
700 uint32_t last_acthd_bsd;
701 uint32_t last_acthd_blt;
702 uint32_t last_instdone;
703 uint32_t last_instdone1;
705 unsigned int stop_rings;
707 struct intel_opregion opregion;
710 struct intel_overlay *overlay;
711 bool sprite_scaling_enabled;
714 int backlight_level; /* restore backlight to this value */
715 bool backlight_enabled;
716 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
717 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
719 /* Feature bits from the VBIOS */
720 unsigned int int_tv_support:1;
721 unsigned int lvds_dither:1;
722 unsigned int lvds_vbt:1;
723 unsigned int int_crt_support:1;
724 unsigned int lvds_use_ssc:1;
725 unsigned int display_clock_mode:1;
726 unsigned int fdi_rx_polarity_inverted:1;
728 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
729 unsigned int lvds_val; /* used for checking LVDS channel mode */
739 struct edp_power_seq pps;
741 bool no_aux_handshake;
744 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
745 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
746 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
748 unsigned int fsb_freq, mem_freq, is_ddr3;
750 /* Display functions */
751 struct drm_i915_display_funcs display;
753 /* PCH chipset type */
754 enum intel_pch pch_type;
755 unsigned short pch_id;
757 unsigned long quirks;
763 /** Bridge to intel-gtt-ko */
764 const struct intel_gtt *gtt;
765 /** Memory allocator for GTT stolen memory */
766 struct drm_mm stolen;
767 /** Memory allocator for GTT */
768 struct drm_mm gtt_space;
769 /** List of all objects in gtt_space. Used to restore gtt
770 * mappings on resume */
771 struct list_head gtt_list;
773 /** Usable portion of the GTT for GEM */
774 unsigned long gtt_start;
775 unsigned long gtt_mappable_end;
776 unsigned long gtt_end;
778 /** PPGTT used for aliasing the PPGTT with the GTT */
779 struct i915_hw_ppgtt *aliasing_ppgtt;
781 bool shrinker_no_lock_stealing;
784 * List of objects currently involved in rendering from the
787 * Includes buffers having the contents of their GPU caches
788 * flushed, not necessarily primitives. last_rendering_seqno
789 * represents when the rendering involved will be completed.
791 * A reference is held on the buffer while on this list.
793 struct list_head active_list;
796 * LRU list of objects which are not in the ringbuffer and
797 * are ready to unbind, but are still in the GTT.
799 * last_rendering_seqno is 0 while an object is in this list.
801 * A reference is not held on the buffer while on this list,
802 * as merely being GTT-bound shouldn't prevent its being
803 * freed, and we'll pull it off the list in the free path.
805 struct list_head inactive_list;
807 /** LRU list of objects with fence regs on them. */
808 struct list_head fence_list;
811 * We leave the user IRQ off as much as possible,
812 * but this means that requests will finish and never
813 * be retired once the system goes idle. Set a timer to
814 * fire periodically while the ring is running. When it
815 * fires, go retire requests.
817 struct delayed_work retire_work;
820 * Are we in a non-interruptible section of code like
825 uint32_t next_gem_seqno;
828 * Waiting sequence number, if any
830 uint32_t waiting_gem_seqno;
833 * Last seq seen at irq time
835 uint32_t irq_gem_seqno;
838 * Flag if the X Server, and thus DRM, is not currently in
839 * control of the device.
841 * This is set between LeaveVT and EnterVT. It needs to be
842 * replaced with a semaphore. It also needs to be
843 * transitioned away from for kernel modesetting.
848 * Flag if the hardware appears to be wedged.
850 * This is set when attempts to idle the device timeout.
851 * It prevents command submission from occuring and makes
852 * every pending request fail
856 /** Bit 6 swizzling required for X tiling */
857 uint32_t bit_6_swizzle_x;
858 /** Bit 6 swizzling required for Y tiling */
859 uint32_t bit_6_swizzle_y;
861 /* storage for physical objects */
862 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
864 /* accounting, useful for userland debugging */
866 size_t mappable_gtt_total;
867 size_t object_memory;
870 eventhandler_tag i915_lowmem;
873 /* Kernel Modesetting */
875 struct sdvo_device_mapping sdvo_mappings[2];
876 /* indicate whether the LVDS_BORDER should be enabled or not */
877 unsigned int lvds_border_bits;
878 /* Panel fitter placement and size for Ironlake+ */
879 u32 pch_pf_pos, pch_pf_size;
881 struct drm_crtc *plane_to_crtc_mapping[3];
882 struct drm_crtc *pipe_to_crtc_mapping[3];
883 wait_queue_head_t pending_flip_queue;
885 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
886 struct intel_ddi_plls ddi_plls;
888 /* Reclocking support */
889 bool render_reclock_avail;
890 bool lvds_downclock_avail;
891 /* indicates the reduced downclock for LVDS*/
895 struct child_device_config *child_dev;
896 struct drm_connector *int_lvds_connector;
897 struct drm_connector *int_edp_connector;
900 bool mchbar_need_disable;
902 struct intel_l3_parity l3_parity;
906 /* gen6+ rps state */
907 struct intel_gen6_power_mgmt rps;
909 /* ilk-only ips/rps state. Everything in here is protected by the global
910 * mchdev_lock in intel_pm.c */
911 struct intel_ilk_power_mgmt ips;
913 enum no_fbc_reason no_fbc_reason;
915 struct lock *mchdev_lock;
917 unsigned long cfb_size;
921 struct intel_fbc_work *fbc_work;
923 struct lock error_lock;
924 /* Protected by dev->error_lock. */
925 struct drm_i915_error_state *first_error;
926 struct work_struct error_work;
927 struct completion error_completion;
928 struct workqueue_struct *wq;
930 unsigned long last_gpu_reset;
932 struct intel_fbdev *fbdev;
934 struct drm_property *broadcast_rgb_property;
935 struct drm_property *force_audio_property;
939 struct i915_suspend_saved_registers regfile;
941 /* Old dri1 support infrastructure, beware the dragons ya fools entering
943 struct i915_dri1_state dri1;
944 } drm_i915_private_t;
946 /* Iterate over initialised rings */
947 #define for_each_ring(ring__, dev_priv__, i__) \
948 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
949 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
951 enum hdmi_force_audio {
952 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
953 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
954 HDMI_AUDIO_AUTO, /* trust EDID */
955 HDMI_AUDIO_ON, /* force turn on HDMI audio */
958 enum i915_cache_level {
961 I915_CACHE_LLC_MLC, /* gen6+ */
964 enum intel_chip_family {
971 /** driver private structure attached to each drm_gem_object */
972 struct drm_i915_gem_object {
973 struct drm_gem_object base;
975 /** Current space allocated to this object in the GTT, if any. */
976 struct drm_mm_node *gtt_space;
977 struct list_head gtt_list;
978 /** This object's place on the active/inactive lists */
979 struct list_head ring_list;
980 struct list_head mm_list;
981 /** This object's place on GPU write list */
982 struct list_head gpu_write_list;
983 /** This object's place in the batchbuffer or on the eviction list */
984 struct list_head exec_list;
987 * This is set if the object is on the active lists (has pending
988 * rendering and so a non-zero seqno), and is not set if it i s on
989 * inactive (ready to be unbound) list.
991 unsigned int active:1;
994 * This is set if the object has been written to since last bound
997 unsigned int dirty:1;
1000 * Fence register bits (if any) for this object. Will be set
1001 * as needed when mapped into the GTT.
1002 * Protected by dev->struct_mutex.
1004 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1007 * Advice: are the backing pages purgeable?
1009 unsigned int madv:2;
1012 * Current tiling mode for the object.
1014 unsigned int tiling_mode:2;
1016 * Whether the tiling parameters for the currently associated fence
1017 * register have changed. Note that for the purposes of tracking
1018 * tiling changes we also treat the unfenced register, the register
1019 * slot that the object occupies whilst it executes a fenced
1020 * command (such as BLT on gen2/3), as a "fence".
1022 unsigned int fence_dirty:1;
1024 /** How many users have pinned this object in GTT space. The following
1025 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1026 * (via user_pin_count), execbuffer (objects are not allowed multiple
1027 * times for the same batchbuffer), and the framebuffer code. When
1028 * switching/pageflipping, the framebuffer code has at most two buffers
1031 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1032 * bits with absolutely no headroom. So use 4 bits. */
1033 unsigned int pin_count:4;
1034 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1037 * Is the object at the current location in the gtt mappable and
1038 * fenceable? Used to avoid costly recalculations.
1040 unsigned int map_and_fenceable:1;
1043 * Whether the current gtt mapping needs to be mappable (and isn't just
1044 * mappable by accident). Track pin and fault separate for a more
1045 * accurate mappable working set.
1047 unsigned int fault_mappable:1;
1048 unsigned int pin_mappable:1;
1051 * Is the GPU currently using a fence to access this buffer,
1053 unsigned int pending_fenced_gpu_access:1;
1054 unsigned int fenced_gpu_access:1;
1056 unsigned int cache_level:2;
1058 unsigned int has_aliasing_ppgtt_mapping:1;
1059 unsigned int has_global_gtt_mapping:1;
1064 * Used for performing relocations during execbuffer insertion.
1066 struct hlist_node exec_node;
1067 unsigned long exec_handle;
1068 struct drm_i915_gem_exec_object2 *exec_entry;
1071 * Current offset of the object in GTT space.
1073 * This is the same as gtt_space->start
1075 uint32_t gtt_offset;
1077 struct intel_ring_buffer *ring;
1079 /** Breadcrumb of last rendering to the buffer. */
1080 uint32_t last_read_seqno;
1081 uint32_t last_write_seqno;
1083 /** Breadcrumb of last fenced GPU access to the buffer. */
1084 uint32_t last_fenced_seqno;
1086 /** Current tiling stride for the object, if it's tiled. */
1089 /** Record of address bit 17 of each page at last unbind. */
1090 unsigned long *bit_17;
1092 /** User space pin count and filp owning the pin */
1093 uint32_t user_pin_count;
1094 struct drm_file *pin_filp;
1096 /** for phy allocated objects */
1097 struct drm_i915_gem_phys_object *phys_obj;
1100 * Number of crtcs where this object is currently the fb, but
1101 * will be page flipped away on the next vblank. When it
1102 * reaches 0, dev_priv->pending_flip_queue will be woken up.
1104 atomic_t pending_flip;
1106 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1108 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1111 * Request queue structure.
1113 * The request queue allows us to note sequence numbers that have been emitted
1114 * and may be associated with active buffers to be retired.
1116 * By keeping this list, we can avoid having to do questionable
1117 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1118 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1120 struct drm_i915_gem_request {
1121 /** On Which ring this request was generated */
1122 struct intel_ring_buffer *ring;
1124 /** GEM sequence number associated with this request. */
1127 /** Postion in the ringbuffer of the end of the request */
1130 /** Time at which this request was emitted, in jiffies. */
1131 unsigned long emitted_jiffies;
1133 /** global list entry for this request */
1134 struct list_head list;
1136 struct drm_i915_file_private *file_priv;
1137 /** file_priv list entry for this request */
1138 struct list_head client_list;
1141 struct drm_i915_file_private {
1143 struct spinlock lock;
1144 struct list_head request_list;
1148 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1150 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1151 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1152 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1153 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1154 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1155 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1156 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1157 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1158 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1159 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1160 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1161 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1162 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1163 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1164 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1165 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1166 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1167 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1168 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1169 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1170 (dev)->pci_device == 0x0152 || \
1171 (dev)->pci_device == 0x015a)
1172 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1173 (dev)->pci_device == 0x0106 || \
1174 (dev)->pci_device == 0x010A)
1175 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1176 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1177 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1178 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1179 ((dev)->pci_device & 0xFF00) == 0x0A00)
1182 * The genX designation typically refers to the render engine, so render
1183 * capability related checks should use IS_GEN, while display and other checks
1184 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1187 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1188 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1189 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1190 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1191 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1192 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1194 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1195 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1196 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1197 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1199 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1200 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1202 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1203 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1205 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1206 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1208 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1209 * rows, which changed the alignment requirements and fence programming.
1211 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1213 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1214 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1215 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1216 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1217 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1218 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1219 /* dsparb controlled by hw only */
1220 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1222 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1223 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1224 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1226 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1228 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1229 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1230 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1231 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1232 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1233 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1235 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1236 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1237 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1238 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1239 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1241 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1243 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1245 #define GT_FREQUENCY_MULTIPLIER 50
1248 * RC6 is a special power stage which allows the GPU to enter an very
1249 * low-voltage mode when idle, using down to 0V while at this stage. This
1250 * stage is entered automatically when the GPU is idle when RC6 support is
1251 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1253 * There are different RC6 modes available in Intel GPU, which differentiate
1254 * among each other with the latency required to enter and leave RC6 and
1255 * voltage consumed by the GPU in different states.
1257 * The combination of the following flags define which states GPU is allowed
1258 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1259 * RC6pp is deepest RC6. Their support by hardware varies according to the
1260 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1261 * which brings the most power savings; deeper states save more power, but
1262 * require higher latency to switch to and wake up.
1264 #define INTEL_RC6_ENABLE (1<<0)
1265 #define INTEL_RC6p_ENABLE (1<<1)
1266 #define INTEL_RC6pp_ENABLE (1<<2)
1268 extern int intel_iommu_enabled;
1269 extern struct drm_ioctl_desc i915_ioctls[];
1270 extern struct drm_driver i915_driver_info;
1271 extern struct cdev_pager_ops i915_gem_pager_ops;
1272 extern int i915_panel_ignore_lid;
1273 extern unsigned int i915_powersave;
1274 extern int i915_semaphores;
1275 extern unsigned int i915_lvds_downclock;
1276 extern int i915_lvds_channel_mode __read_mostly;
1277 extern int i915_panel_use_ssc;
1278 extern int i915_vbt_sdvo_panel_type;
1279 extern int i915_enable_rc6;
1280 extern int i915_enable_fbc;
1281 extern int i915_enable_ppgtt;
1282 extern int i915_enable_hangcheck;
1284 void i915_sysctl_cleanup(struct drm_device *dev);
1287 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1288 extern void i915_kernel_lost_context(struct drm_device * dev);
1289 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1290 extern int i915_driver_unload(struct drm_device *);
1291 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1292 extern void i915_driver_lastclose(struct drm_device * dev);
1293 extern void i915_driver_preclose(struct drm_device *dev,
1294 struct drm_file *file_priv);
1295 extern void i915_driver_postclose(struct drm_device *dev,
1296 struct drm_file *file_priv);
1297 extern int i915_driver_device_is_agp(struct drm_device * dev);
1298 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1300 extern int i915_emit_box(struct drm_device *dev,
1301 struct drm_clip_rect __user *boxes,
1302 int i, int DR1, int DR4);
1303 int i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box,
1305 extern int intel_gpu_reset(struct drm_device *dev);
1306 extern int i915_reset(struct drm_device *dev);
1307 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1308 unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1309 void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1310 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1313 extern int i915_irq_emit(struct drm_device *dev, void *data,
1314 struct drm_file *file_priv);
1315 extern int i915_irq_wait(struct drm_device *dev, void *data,
1316 struct drm_file *file_priv);
1318 extern void intel_irq_init(struct drm_device *dev);
1319 extern void intel_gt_init(struct drm_device *dev);
1320 extern void intel_gt_reset(struct drm_device *dev);
1322 void intel_enable_asle(struct drm_device *dev);
1323 void i915_hangcheck_elapsed(unsigned long data);
1324 void i915_handle_error(struct drm_device *dev, bool wedged);
1326 void i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1327 void i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1329 #ifdef CONFIG_DEBUG_FS
1330 extern void i915_destroy_error_state(struct drm_device *dev);
1332 #define i915_destroy_error_state(x)
1336 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1337 struct drm_file *file_priv);
1338 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1339 struct drm_file *file_priv);
1340 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1341 struct drm_file *file_priv);
1342 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1343 struct drm_file *file_priv);
1344 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1345 struct drm_file *file_priv);
1346 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1347 struct drm_file *file_priv);
1348 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1349 struct drm_file *file_priv);
1350 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1351 struct drm_file *file_priv);
1352 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1353 struct drm_file *file_priv);
1354 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1355 struct drm_file *file_priv);
1356 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1357 struct drm_file *file_priv);
1358 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1359 struct drm_file *file_priv);
1360 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1361 struct drm_file *file_priv);
1362 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1363 struct drm_file *file_priv);
1364 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1365 struct drm_file *file_priv);
1366 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1367 struct drm_file *file_priv);
1368 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1369 struct drm_file *file_priv);
1370 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1371 struct drm_file *file_priv);
1372 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1373 struct drm_file *file_priv);
1374 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1375 struct drm_file *file_priv);
1376 void i915_gem_load(struct drm_device *dev);
1377 void i915_gem_unload(struct drm_device *dev);
1378 int i915_gem_init_object(struct drm_gem_object *obj);
1379 void i915_gem_free_object(struct drm_gem_object *obj);
1380 int i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment,
1381 bool map_and_fenceable);
1382 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1383 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1384 void i915_gem_lastclose(struct drm_device *dev);
1385 uint32_t i915_get_gem_seqno(struct drm_device *dev);
1388 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1390 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1391 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1392 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1397 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1399 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1400 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1401 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1405 void i915_gem_retire_requests(struct drm_device *dev);
1406 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1407 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1408 bool interruptible);
1410 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1411 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1413 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
1414 unsigned long mappable_end, unsigned long end);
1415 uint32_t i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1416 uint32_t size, int tiling_mode);
1417 int i915_mutex_lock_interruptible(struct drm_device *dev);
1418 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1419 struct intel_ring_buffer *to);
1421 int i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1424 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1426 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1428 struct intel_ring_buffer *pipelined);
1429 int i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1430 int __must_check i915_gem_init(struct drm_device *dev);
1431 int i915_gem_flush_ring(struct intel_ring_buffer *ring,
1432 uint32_t invalidate_domains, uint32_t flush_domains);
1433 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1434 int i915_gem_idle(struct drm_device *dev);
1435 int i915_gem_init_hw(struct drm_device *dev);
1436 void i915_gem_l3_remap(struct drm_device *dev);
1437 void i915_gem_init_swizzling(struct drm_device *dev);
1438 void i915_gem_init_ppgtt(struct drm_device *dev);
1439 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1440 int __must_check i915_gpu_idle(struct drm_device *dev);
1441 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1442 struct intel_ring_buffer *ring);
1443 int i915_add_request(struct intel_ring_buffer *ring,
1444 struct drm_file *file,
1446 int i915_wait_seqno(struct intel_ring_buffer *ring,
1448 void i915_gem_reset(struct drm_device *dev);
1449 int i915_gem_mmap(struct drm_device *dev, uint64_t offset, int prot);
1450 int i915_gem_fault(struct drm_device *dev, uint64_t offset, int prot,
1452 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1453 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1454 enum i915_cache_level cache_level);
1456 void i915_gem_free_all_phys_object(struct drm_device *dev);
1457 void i915_gem_detach_phys_object(struct drm_device *dev,
1458 struct drm_i915_gem_object *obj);
1459 int i915_gem_attach_phys_object(struct drm_device *dev,
1460 struct drm_i915_gem_object *obj, int id, int align);
1462 int i915_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev,
1463 struct drm_mode_create_dumb *args);
1464 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1465 uint32_t handle, uint64_t *offset);
1466 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1469 /* i915_gem_tiling.c */
1470 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1471 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1472 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1474 /* i915_gem_debug.c */
1476 int i915_verify_lists(struct drm_device *dev);
1478 #define i915_verify_lists(dev) 0
1481 /* i915_gem_evict.c */
1482 int i915_gem_evict_something(struct drm_device *dev, int min_size,
1483 unsigned alignment, bool mappable);
1484 int i915_gem_evict_everything(struct drm_device *dev);
1486 /* i915_suspend.c */
1487 extern int i915_save_state(struct drm_device *dev);
1488 extern int i915_restore_state(struct drm_device *dev);
1491 extern int intel_setup_gmbus(struct drm_device *dev);
1492 extern void intel_teardown_gmbus(struct drm_device *dev);
1493 static inline bool intel_gmbus_is_port_valid(unsigned port)
1495 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1498 extern struct device *intel_gmbus_get_adapter(
1499 struct drm_i915_private *dev_priv, unsigned port);
1500 extern void intel_gmbus_set_speed(device_t idev, int speed);
1501 extern void intel_gmbus_force_bit(device_t idev, bool force_bit);
1502 static inline bool intel_gmbus_is_forced_bit(struct device *adapter)
1504 struct intel_iic_softc *sc;
1505 sc = device_get_softc(device_get_parent(adapter));
1507 return sc->force_bit_dev;
1509 extern void intel_iic_reset(struct drm_device *dev);
1511 /* i915_gem_context.c */
1512 void i915_gem_context_init(struct drm_device *dev);
1514 /* i915_gem_gtt.c */
1515 int i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1516 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1517 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1518 struct drm_i915_gem_object *obj, enum i915_cache_level cache_level);
1519 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1520 struct drm_i915_gem_object *obj);
1522 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1523 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1524 enum i915_cache_level cache_level);
1525 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1526 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1528 /* intel_opregion.c */
1529 extern int intel_opregion_setup(struct drm_device *dev);
1531 extern void intel_opregion_init(struct drm_device *dev);
1532 extern void intel_opregion_fini(struct drm_device *dev);
1533 extern void intel_opregion_asle_intr(struct drm_device *dev);
1534 extern void intel_opregion_gse_intr(struct drm_device *dev);
1535 extern void intel_opregion_enable_asle(struct drm_device *dev);
1537 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1538 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1539 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1540 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1541 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1545 extern void intel_modeset_init_hw(struct drm_device *dev);
1546 extern void intel_modeset_init(struct drm_device *dev);
1547 extern void intel_modeset_gem_init(struct drm_device *dev);
1548 extern void intel_modeset_cleanup(struct drm_device *dev);
1549 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1550 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1551 bool force_restore);
1552 extern void intel_disable_fbc(struct drm_device *dev);
1553 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1554 extern void intel_init_pch_refclk(struct drm_device *dev);
1555 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1556 extern void intel_detect_pch(struct drm_device *dev);
1557 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1558 extern int intel_enable_rc6(const struct drm_device *dev);
1560 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1562 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(
1563 struct drm_device *dev);
1564 extern void intel_overlay_print_error_state(struct sbuf *m,
1565 struct intel_overlay_error_state *error);
1566 extern struct intel_display_error_state *intel_display_capture_error_state(
1567 struct drm_device *dev);
1568 extern void intel_display_print_error_state(struct sbuf *m,
1569 struct drm_device *dev, struct intel_display_error_state *error);
1572 trace_i915_reg_rw(boolean_t rw, int reg, uint64_t val, int sz)
1577 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1579 #define BEGIN_LP_RING(n) \
1580 intel_ring_begin(LP_RING(dev_priv), (n))
1582 #define OUT_RING(x) \
1583 intel_ring_emit(LP_RING(dev_priv), x)
1585 #define ADVANCE_LP_RING() \
1586 intel_ring_advance(LP_RING(dev_priv))
1588 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1589 if (LP_RING(dev->dev_private)->obj == NULL) \
1590 LOCK_TEST_WITH_RETURN(dev, file); \
1593 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
1594 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1595 #define I915_GEM_HWS_INDEX 0x20
1596 #define I915_BREADCRUMB_INDEX 0x21
1598 const struct intel_device_info *i915_get_device_id(int device);
1601 int i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx,
1602 struct sysctl_oid *top);
1605 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1608 return ((int32_t)(seq1 - seq2) >= 0);
1611 extern int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1613 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1614 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1616 /* On SNB platform, before reading ring registers forcewake bit
1617 * must be set to prevent GT core from power down and stale values being
1620 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1621 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1622 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1624 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1625 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1627 #define __i915_read(x, y) \
1628 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1636 #define __i915_write(x, y) \
1637 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1640 __i915_write(16, 16)
1641 __i915_write(32, 32)
1642 __i915_write(64, 64)
1645 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1646 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1648 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1649 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1650 #define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->mmio_map, (reg))
1651 #define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
1653 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1654 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1655 #define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->mmio_map, (reg))
1656 #define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
1658 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1659 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1661 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1662 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)