sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/async.h>
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include <drm/drm_legacy.h>
  33 #include "i915_drv.h"
  34 #include "intel_drv.h"
  35 #include "intel_ringbuffer.h"
  36 #include <linux/workqueue.h>
  37
  38 extern struct drm_i915_private *i915_mch_dev;
  39
  40 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  41
  42 #define BEGIN_LP_RING(n) \
  43         intel_ring_begin(LP_RING(dev_priv), (n))
  44
  45 #define OUT_RING(x) \
  46         intel_ring_emit(LP_RING(dev_priv), x)
  47
  48 #define ADVANCE_LP_RING() \
  49         __intel_ring_advance(LP_RING(dev_priv))
  50
  51 /**
  52  * Lock test for when it's just for synchronization of ring access.
  53  *
  54  * In that case, we don't need to do it when GEM is initialized as nobody else
  55  * has access to the ring.
  56  */
  57 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  58         if (LP_RING(dev->dev_private)->buffer->obj == NULL)                     \
  59                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  60 } while (0)
  61
  62 static inline u32
  63 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  64 {
  65         if (I915_NEED_GFX_HWS(dev_priv->dev))
  66                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  67         else
  68                 return intel_read_status_page(LP_RING(dev_priv), reg);
  69 }
  70
  71 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  72 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  73 #define I915_BREADCRUMB_INDEX           0x21
  74
  75 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  76 {
  77         /* XXX: We don't care about dri1 */
  78         return;
  79 }
  80
  81 static void i915_write_hws_pga(struct drm_device *dev)
  82 {
  83         struct drm_i915_private *dev_priv = dev->dev_private;
  84         u32 addr;
  85
  86         addr = dev_priv->status_page_dmah->busaddr;
  87         if (INTEL_INFO(dev)->gen >= 4)
  88                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  89         I915_WRITE(HWS_PGA, addr);
  90 }
  91
  92 /**
  93  * Frees the hardware status page, whether it's a physical address or a virtual
  94  * address set up by the X Server.
  95  */
  96 static void i915_free_hws(struct drm_device *dev)
  97 {
  98         struct drm_i915_private *dev_priv = dev->dev_private;
  99         struct intel_engine_cs *ring = LP_RING(dev_priv);
 100
 101         if (dev_priv->status_page_dmah) {
 102                 drm_pci_free(dev, dev_priv->status_page_dmah);
 103                 dev_priv->status_page_dmah = NULL;
 104         }
 105
 106         if (ring->status_page.gfx_addr) {
 107                 ring->status_page.gfx_addr = 0;
 108 #if 0   /* We don't care about dri1 */
 109                 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
 110 #endif
 111         }
 112
 113         /* Need to rewrite hardware status page */
 114         I915_WRITE(HWS_PGA, 0x1ffff000);
 115 }
 116
 117 void i915_kernel_lost_context(struct drm_device *dev)
 118 {
 119         struct drm_i915_private *dev_priv = dev->dev_private;
 120         struct drm_i915_private *master_priv = dev_priv;
 121         struct intel_engine_cs *ring = LP_RING(dev_priv);
 122         struct intel_ringbuffer *ringbuf = ring->buffer;
 123
 124         /*
 125          * We should never lose context on the ring with modesetting
 126          * as we don't expose it to userspace
 127          */
 128         if (drm_core_check_feature(dev, DRIVER_MODESET))
 129                 return;
 130
 131         ringbuf->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 132         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 133         ringbuf->space = ringbuf->head - (ringbuf->tail + I915_RING_FREE_SPACE);
 134         if (ringbuf->space < 0)
 135                 ringbuf->space += ringbuf->size;
 136
 137 #if 0
 138         if (!dev->primary->master)
 139                 return;
 140
 141         master_priv = dev->primary->master->driver_priv;
 142 #endif
 143         if (ringbuf->head == ringbuf->tail && master_priv->sarea_priv)
 144                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 145 }
 146
 147 static int i915_dma_cleanup(struct drm_device *dev)
 148 {
 149         struct drm_i915_private *dev_priv = dev->dev_private;
 150         int i;
 151
 152         /* Make sure interrupts are disabled here because the uninstall ioctl
 153          * may not have been called from userspace and after dev_private
 154          * is freed, it's too late.
 155          */
 156         if (dev->irq_enabled)
 157                 drm_irq_uninstall(dev);
 158
 159         mutex_lock(&dev->struct_mutex);
 160         for (i = 0; i < I915_NUM_RINGS; i++)
 161                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 162         mutex_unlock(&dev->struct_mutex);
 163
 164         /* Clear the HWS virtual address at teardown */
 165         if (I915_NEED_GFX_HWS(dev))
 166                 i915_free_hws(dev);
 167
 168         return 0;
 169 }
 170
 171 static int i915_initialize(struct drm_device *dev, drm_i915_init_t *init)
 172 {
 173         struct drm_i915_private *dev_priv = dev->dev_private;
 174         int ret;
 175
 176         dev_priv->sarea = drm_legacy_getsarea(dev);
 177         if (!dev_priv->sarea) {
 178                 DRM_ERROR("can not find sarea!\n");
 179                 i915_dma_cleanup(dev);
 180                 return -EINVAL;
 181         }
 182
 183         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 184             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 185
 186         if (init->ring_size != 0) {
 187                 if (LP_RING(dev_priv)->buffer->obj != NULL) {
 188                         i915_dma_cleanup(dev);
 189                         DRM_ERROR("Client tried to initialize ringbuffer in "
 190                                   "GEM mode\n");
 191                         return -EINVAL;
 192                 }
 193
 194                 ret = intel_render_ring_init_dri(dev,
 195                                                  init->ring_start,
 196                                                  init->ring_size);
 197                 if (ret) {
 198                         i915_dma_cleanup(dev);
 199                         return ret;
 200                 }
 201         }
 202
 203         dev_priv->dri1.cpp = init->cpp;
 204         dev_priv->dri1.back_offset = init->back_offset;
 205         dev_priv->dri1.front_offset = init->front_offset;
 206         dev_priv->dri1.current_page = 0;
 207         dev_priv->sarea_priv->pf_current_page = 0;
 208
 209
 210         /* Allow hardware batchbuffers unless told otherwise.
 211          */
 212         dev_priv->dri1.allow_batchbuffer = 1;
 213
 214         return 0;
 215 }
 216
 217 static int i915_dma_resume(struct drm_device *dev)
 218 {
 219         struct drm_i915_private *dev_priv = dev->dev_private;
 220         struct intel_engine_cs *ring = LP_RING(dev_priv);
 221
 222         DRM_DEBUG_DRIVER("%s\n", __func__);
 223
 224         if (ring->buffer->virtual_start == NULL) {
 225                 DRM_ERROR("can not ioremap virtual address for"
 226                           " ring buffer\n");
 227                 return -ENOMEM;
 228         }
 229
 230         /* Program Hardware Status Page */
 231         if (!ring->status_page.page_addr) {
 232                 DRM_ERROR("Can not find hardware status page\n");
 233                 return -EINVAL;
 234         }
 235         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 236                                 ring->status_page.page_addr);
 237         if (ring->status_page.gfx_addr != 0)
 238                 intel_ring_setup_status_page(ring);
 239         else
 240                 i915_write_hws_pga(dev);
 241
 242         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 243
 244         return 0;
 245 }
 246
 247 static int i915_dma_init(struct drm_device *dev, void *data,
 248                          struct drm_file *file_priv)
 249 {
 250         drm_i915_init_t *init = data;
 251         int retcode = 0;
 252
 253         if (drm_core_check_feature(dev, DRIVER_MODESET))
 254                 return -ENODEV;
 255
 256         switch (init->func) {
 257         case I915_INIT_DMA:
 258                 retcode = i915_initialize(dev, init);
 259                 break;
 260         case I915_CLEANUP_DMA:
 261                 retcode = i915_dma_cleanup(dev);
 262                 break;
 263         case I915_RESUME_DMA:
 264                 retcode = i915_dma_resume(dev);
 265                 break;
 266         default:
 267                 retcode = -EINVAL;
 268                 break;
 269         }
 270
 271         return retcode;
 272 }
 273
 274 /* Implement basically the same security restrictions as hardware does
 275  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 276  *
 277  * Most of the calculations below involve calculating the size of a
 278  * particular instruction.  It's important to get the size right as
 279  * that tells us where the next instruction to check is.  Any illegal
 280  * instruction detected will be given a size of zero, which is a
 281  * signal to abort the rest of the buffer.
 282  */
 283 static int validate_cmd(int cmd)
 284 {
 285         switch (((cmd >> 29) & 0x7)) {
 286         case 0x0:
 287                 switch ((cmd >> 23) & 0x3f) {
 288                 case 0x0:
 289                         return 1;       /* MI_NOOP */
 290                 case 0x4:
 291                         return 1;       /* MI_FLUSH */
 292                 default:
 293                         return 0;       /* disallow everything else */
 294                 }
 295                 break;
 296         case 0x1:
 297                 return 0;       /* reserved */
 298         case 0x2:
 299                 return (cmd & 0xff) + 2;        /* 2d commands */
 300         case 0x3:
 301                 if (((cmd >> 24) & 0x1f) <= 0x18)
 302                         return 1;
 303
 304                 switch ((cmd >> 24) & 0x1f) {
 305                 case 0x1c:
 306                         return 1;
 307                 case 0x1d:
 308                         switch ((cmd >> 16) & 0xff) {
 309                         case 0x3:
 310                                 return (cmd & 0x1f) + 2;
 311                         case 0x4:
 312                                 return (cmd & 0xf) + 2;
 313                         default:
 314                                 return (cmd & 0xffff) + 2;
 315                         }
 316                 case 0x1e:
 317                         if (cmd & (1 << 23))
 318                                 return (cmd & 0xffff) + 1;
 319                         else
 320                                 return 1;
 321                 case 0x1f:
 322                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 323                                 return (cmd & 0x1ffff) + 2;
 324                         else if (cmd & (1 << 17))       /* indirect random */
 325                                 if ((cmd & 0xffff) == 0)
 326                                         return 0;       /* unknown length, too hard */
 327                                 else
 328                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 329                         else
 330                                 return 2;       /* indirect sequential */
 331                 default:
 332                         return 0;
 333                 }
 334         default:
 335                 return 0;
 336         }
 337
 338         return 0;
 339 }
 340
 341 static int i915_emit_cmds(struct drm_device *dev, int *buffer, int dwords)
 342 {
 343         struct drm_i915_private *dev_priv = dev->dev_private;
 344         int i, ret;
 345
 346         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->buffer->size - 8)
 347                 return -EINVAL;
 348
 349         for (i = 0; i < dwords;) {
 350                 int sz = validate_cmd(buffer[i]);
 351
 352                 if (sz == 0 || i + sz > dwords)
 353                         return -EINVAL;
 354                 i += sz;
 355         }
 356
 357         ret = BEGIN_LP_RING((dwords+1)&~1);
 358         if (ret)
 359                 return ret;
 360
 361         for (i = 0; i < dwords; i++)
 362                 OUT_RING(buffer[i]);
 363         if (dwords & 1)
 364                 OUT_RING(0);
 365
 366         ADVANCE_LP_RING();
 367
 368         return 0;
 369 }
 370
 371 int
 372 i915_emit_box(struct drm_device *dev,
 373               struct drm_clip_rect *box,
 374               int DR1, int DR4)
 375 {
 376         struct drm_i915_private *dev_priv = dev->dev_private;
 377         int ret;
 378
 379         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 380             box->y2 <= 0 || box->x2 <= 0) {
 381                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 382                           box->x1, box->y1, box->x2, box->y2);
 383                 return -EINVAL;
 384         }
 385
 386         if (INTEL_INFO(dev)->gen >= 4) {
 387                 ret = BEGIN_LP_RING(4);
 388                 if (ret)
 389                         return ret;
 390
 391                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 392                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 393                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 394                 OUT_RING(DR4);
 395         } else {
 396                 ret = BEGIN_LP_RING(6);
 397                 if (ret)
 398                         return ret;
 399
 400                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 401                 OUT_RING(DR1);
 402                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 403                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 404                 OUT_RING(DR4);
 405                 OUT_RING(0);
 406         }
 407         ADVANCE_LP_RING();
 408
 409         return 0;
 410 }
 411
 412 /* XXX: Emitting the counter should really be moved to part of the IRQ
 413  * emit. For now, do it in both places:
 414  */
 415
 416 static void i915_emit_breadcrumb(struct drm_device *dev)
 417 {
 418         struct drm_i915_private *dev_priv = dev->dev_private;
 419
 420         dev_priv->dri1.counter++;
 421         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 422                 dev_priv->dri1.counter = 0;
 423         if (dev_priv->sarea_priv)
 424                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 425
 426         if (BEGIN_LP_RING(4) == 0) {
 427                 OUT_RING(MI_STORE_DWORD_INDEX);
 428                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 429                 OUT_RING(dev_priv->dri1.counter);
 430                 OUT_RING(0);
 431                 ADVANCE_LP_RING();
 432         }
 433 }
 434
 435 static int i915_dispatch_cmdbuffer(struct drm_device *dev,
 436                                    drm_i915_cmdbuffer_t *cmd,
 437                                    struct drm_clip_rect *cliprects,
 438                                    void *cmdbuf)
 439 {
 440         int nbox = cmd->num_cliprects;
 441         int i = 0, count, ret;
 442
 443         if (cmd->sz & 0x3) {
 444                 DRM_ERROR("alignment");
 445                 return -EINVAL;
 446         }
 447
 448         i915_kernel_lost_context(dev);
 449
 450         count = nbox ? nbox : 1;
 451
 452         for (i = 0; i < count; i++) {
 453                 if (i < nbox) {
 454                         ret = i915_emit_box(dev, &cliprects[i],
 455                                             cmd->DR1, cmd->DR4);
 456                         if (ret)
 457                                 return ret;
 458                 }
 459
 460                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 461                 if (ret)
 462                         return ret;
 463         }
 464
 465         i915_emit_breadcrumb(dev);
 466         return 0;
 467 }
 468
 469 static int i915_dispatch_batchbuffer(struct drm_device *dev,
 470                                      drm_i915_batchbuffer_t *batch,
 471                                      struct drm_clip_rect *cliprects)
 472 {
 473         struct drm_i915_private *dev_priv = dev->dev_private;
 474         int nbox = batch->num_cliprects;
 475         int i, count, ret;
 476
 477         if ((batch->start | batch->used) & 0x7) {
 478                 DRM_ERROR("alignment");
 479                 return -EINVAL;
 480         }
 481
 482         i915_kernel_lost_context(dev);
 483
 484         count = nbox ? nbox : 1;
 485         for (i = 0; i < count; i++) {
 486                 if (i < nbox) {
 487                         ret = i915_emit_box(dev, &cliprects[i],
 488                                             batch->DR1, batch->DR4);
 489                         if (ret)
 490                                 return ret;
 491                 }
 492
 493                 if (!IS_I830(dev) && !IS_845G(dev)) {
 494                         ret = BEGIN_LP_RING(2);
 495                         if (ret)
 496                                 return ret;
 497
 498                         if (INTEL_INFO(dev)->gen >= 4) {
 499                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 500                                 OUT_RING(batch->start);
 501                         } else {
 502                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 503                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 504                         }
 505                 } else {
 506                         ret = BEGIN_LP_RING(4);
 507                         if (ret)
 508                                 return ret;
 509
 510                         OUT_RING(MI_BATCH_BUFFER);
 511                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 512                         OUT_RING(batch->start + batch->used - 4);
 513                         OUT_RING(0);
 514                 }
 515                 ADVANCE_LP_RING();
 516         }
 517
 518
 519         if (IS_G4X(dev) || IS_GEN5(dev)) {
 520                 if (BEGIN_LP_RING(2) == 0) {
 521                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 522                         OUT_RING(MI_NOOP);
 523                         ADVANCE_LP_RING();
 524                 }
 525         }
 526
 527         i915_emit_breadcrumb(dev);
 528         return 0;
 529 }
 530
 531 static int i915_dispatch_flip(struct drm_device *dev)
 532 {
 533         struct drm_i915_private *dev_priv = dev->dev_private;
 534         int ret;
 535
 536         if (!dev_priv->sarea_priv)
 537                 return -EINVAL;
 538
 539         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 540                           __func__,
 541                          dev_priv->dri1.current_page,
 542                          dev_priv->sarea_priv->pf_current_page);
 543
 544         i915_kernel_lost_context(dev);
 545
 546         ret = BEGIN_LP_RING(10);
 547         if (ret)
 548                 return ret;
 549
 550         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 551         OUT_RING(0);
 552
 553         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 554         OUT_RING(0);
 555         if (dev_priv->dri1.current_page == 0) {
 556                 OUT_RING(dev_priv->dri1.back_offset);
 557                 dev_priv->dri1.current_page = 1;
 558         } else {
 559                 OUT_RING(dev_priv->dri1.front_offset);
 560                 dev_priv->dri1.current_page = 0;
 561         }
 562         OUT_RING(0);
 563
 564         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 565         OUT_RING(0);
 566
 567         ADVANCE_LP_RING();
 568
 569         dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 570
 571         if (BEGIN_LP_RING(4) == 0) {
 572                 OUT_RING(MI_STORE_DWORD_INDEX);
 573                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 574                 OUT_RING(dev_priv->dri1.counter);
 575                 OUT_RING(0);
 576                 ADVANCE_LP_RING();
 577         }
 578
 579         dev_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 580         return 0;
 581 }
 582
 583 static int i915_quiescent(struct drm_device *dev)
 584 {
 585         i915_kernel_lost_context(dev);
 586         return intel_ring_idle(LP_RING(dev->dev_private));
 587 }
 588
 589 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 590                             struct drm_file *file_priv)
 591 {
 592         int ret;
 593
 594         if (drm_core_check_feature(dev, DRIVER_MODESET))
 595                 return -ENODEV;
 596
 597         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 598
 599         mutex_lock(&dev->struct_mutex);
 600         ret = i915_quiescent(dev);
 601         mutex_unlock(&dev->struct_mutex);
 602
 603         return ret;
 604 }
 605
 606 static int i915_batchbuffer(struct drm_device *dev, void *data,
 607                             struct drm_file *file_priv)
 608 {
 609         struct drm_i915_private *dev_priv = dev->dev_private;
 610         drm_i915_sarea_t *sarea_priv;
 611         drm_i915_batchbuffer_t *batch = data;
 612         int ret;
 613         struct drm_clip_rect *cliprects = NULL;
 614
 615         if (drm_core_check_feature(dev, DRIVER_MODESET))
 616                 return -ENODEV;
 617
 618         sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv;
 619
 620         if (!dev_priv->dri1.allow_batchbuffer) {
 621                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 622                 return -EINVAL;
 623         }
 624
 625         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 626                         batch->start, batch->used, batch->num_cliprects);
 627
 628         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 629
 630         if (batch->num_cliprects < 0)
 631                 return -EINVAL;
 632
 633         if (batch->num_cliprects) {
 634                 cliprects = kcalloc(batch->num_cliprects,
 635                                     sizeof(*cliprects),
 636                                     GFP_KERNEL);
 637                 if (cliprects == NULL)
 638                         return -ENOMEM;
 639
 640                 ret = copy_from_user(cliprects, batch->cliprects,
 641                                      batch->num_cliprects *
 642                                      sizeof(struct drm_clip_rect));
 643                 if (ret != 0) {
 644                         ret = -EFAULT;
 645                         goto fail_free;
 646                 }
 647         }
 648
 649         mutex_lock(&dev->struct_mutex);
 650         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 651         mutex_unlock(&dev->struct_mutex);
 652
 653         if (sarea_priv)
 654                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 655
 656 fail_free:
 657         kfree(cliprects);
 658
 659         return ret;
 660 }
 661
 662 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 663                           struct drm_file *file_priv)
 664 {
 665         struct drm_i915_private *dev_priv = dev->dev_private;
 666         drm_i915_sarea_t *sarea_priv;
 667         drm_i915_cmdbuffer_t *cmdbuf = data;
 668         struct drm_clip_rect *cliprects = NULL;
 669         void *batch_data;
 670         int ret;
 671
 672         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 673                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 674
 675         if (drm_core_check_feature(dev, DRIVER_MODESET))
 676                 return -ENODEV;
 677
 678         sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv;
 679
 680         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 681
 682         if (cmdbuf->num_cliprects < 0)
 683                 return -EINVAL;
 684
 685         batch_data = kmalloc(cmdbuf->sz, M_DRM, M_WAITOK);
 686         if (batch_data == NULL)
 687                 return -ENOMEM;
 688
 689         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 690         if (ret != 0) {
 691                 ret = -EFAULT;
 692                 goto fail_batch_free;
 693         }
 694
 695         if (cmdbuf->num_cliprects) {
 696                 cliprects = kcalloc(cmdbuf->num_cliprects,
 697                                     sizeof(*cliprects), GFP_KERNEL);
 698                 if (cliprects == NULL) {
 699                         ret = -ENOMEM;
 700                         goto fail_batch_free;
 701                 }
 702
 703                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 704                                      cmdbuf->num_cliprects *
 705                                      sizeof(struct drm_clip_rect));
 706                 if (ret != 0) {
 707                         ret = -EFAULT;
 708                         goto fail_clip_free;
 709                 }
 710         }
 711
 712         mutex_lock(&dev->struct_mutex);
 713         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 714         mutex_unlock(&dev->struct_mutex);
 715         if (ret) {
 716                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 717                 goto fail_clip_free;
 718         }
 719
 720         if (sarea_priv)
 721                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 722
 723 fail_clip_free:
 724         kfree(cliprects);
 725 fail_batch_free:
 726         kfree(batch_data);
 727
 728         return ret;
 729 }
 730
 731 static int i915_emit_irq(struct drm_device *dev)
 732 {
 733         struct drm_i915_private *dev_priv = dev->dev_private;
 734 #if 0
 735         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 736 #endif
 737
 738         i915_kernel_lost_context(dev);
 739
 740         DRM_DEBUG_DRIVER("\n");
 741
 742         dev_priv->dri1.counter++;
 743         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 744                 dev_priv->dri1.counter = 1;
 745         if (dev_priv->sarea_priv)
 746                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 747
 748         if (BEGIN_LP_RING(4) == 0) {
 749                 OUT_RING(MI_STORE_DWORD_INDEX);
 750                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 751                 OUT_RING(dev_priv->dri1.counter);
 752                 OUT_RING(MI_USER_INTERRUPT);
 753                 ADVANCE_LP_RING();
 754         }
 755
 756         return dev_priv->dri1.counter;
 757 }
 758
 759 static int i915_wait_irq(struct drm_device *dev, int irq_nr)
 760 {
 761         struct drm_i915_private *dev_priv = dev->dev_private;
 762 #if 0
 763         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 764 #endif
 765         int ret = 0;
 766         struct intel_engine_cs *ring = LP_RING(dev_priv);
 767
 768         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 769                   READ_BREADCRUMB(dev_priv));
 770
 771 #if 0
 772         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 773                 if (master_priv->sarea_priv)
 774                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 775                 return 0;
 776         }
 777
 778         if (master_priv->sarea_priv)
 779                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 780 #else
 781         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 782                 if (dev_priv->sarea_priv) {
 783                         dev_priv->sarea_priv->last_dispatch =
 784                                 READ_BREADCRUMB(dev_priv);
 785                 }
 786                 return 0;
 787         }
 788
 789         if (dev_priv->sarea_priv)
 790                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 791 #endif
 792
 793         if (ring->irq_get(ring)) {
 794                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ,
 795                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 796                 ring->irq_put(ring);
 797         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 798                 ret = -EBUSY;
 799
 800         if (ret == -EBUSY) {
 801                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 802                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 803         }
 804
 805         return ret;
 806 }
 807
 808 /* Needs the lock as it touches the ring.
 809  */
 810 static int i915_irq_emit(struct drm_device *dev, void *data,
 811                          struct drm_file *file_priv)
 812 {
 813         struct drm_i915_private *dev_priv = dev->dev_private;
 814         drm_i915_irq_emit_t *emit = data;
 815         int result;
 816
 817         if (drm_core_check_feature(dev, DRIVER_MODESET))
 818                 return -ENODEV;
 819
 820         if (!dev_priv || !LP_RING(dev_priv)->buffer->virtual_start) {
 821                 DRM_ERROR("called with no initialization\n");
 822                 return -EINVAL;
 823         }
 824
 825         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 826
 827         mutex_lock(&dev->struct_mutex);
 828         result = i915_emit_irq(dev);
 829         mutex_unlock(&dev->struct_mutex);
 830
 831         if (copy_to_user(emit->irq_seq, &result, sizeof(int))) {
 832                 DRM_ERROR("copy_to_user\n");
 833                 return -EFAULT;
 834         }
 835
 836         return 0;
 837 }
 838
 839 /* Doesn't need the hardware lock.
 840  */
 841 static int i915_irq_wait(struct drm_device *dev, void *data,
 842                          struct drm_file *file_priv)
 843 {
 844         struct drm_i915_private *dev_priv = dev->dev_private;
 845         drm_i915_irq_wait_t *irqwait = data;
 846
 847         if (drm_core_check_feature(dev, DRIVER_MODESET))
 848                 return -ENODEV;
 849
 850         if (!dev_priv) {
 851                 DRM_ERROR("called with no initialization\n");
 852                 return -EINVAL;
 853         }
 854
 855         return i915_wait_irq(dev, irqwait->irq_seq);
 856 }
 857
 858 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 859                          struct drm_file *file_priv)
 860 {
 861         struct drm_i915_private *dev_priv = dev->dev_private;
 862         drm_i915_vblank_pipe_t *pipe = data;
 863
 864         if (drm_core_check_feature(dev, DRIVER_MODESET))
 865                 return -ENODEV;
 866
 867         if (!dev_priv) {
 868                 DRM_ERROR("called with no initialization\n");
 869                 return -EINVAL;
 870         }
 871
 872         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 873
 874         return 0;
 875 }
 876
 877 /**
 878  * Schedule buffer swap at given vertical blank.
 879  */
 880 static int i915_vblank_swap(struct drm_device *dev, void *data,
 881                      struct drm_file *file_priv)
 882 {
 883         /* The delayed swap mechanism was fundamentally racy, and has been
 884          * removed.  The model was that the client requested a delayed flip/swap
 885          * from the kernel, then waited for vblank before continuing to perform
 886          * rendering.  The problem was that the kernel might wake the client
 887          * up before it dispatched the vblank swap (since the lock has to be
 888          * held while touching the ringbuffer), in which case the client would
 889          * clear and start the next frame before the swap occurred, and
 890          * flicker would occur in addition to likely missing the vblank.
 891          *
 892          * In the absence of this ioctl, userland falls back to a correct path
 893          * of waiting for a vblank, then dispatching the swap on its own.
 894          * Context switching to userland and back is plenty fast enough for
 895          * meeting the requirements of vblank swapping.
 896          */
 897         return -EINVAL;
 898 }
 899
 900 static int i915_flip_bufs(struct drm_device *dev, void *data,
 901                           struct drm_file *file_priv)
 902 {
 903         int ret;
 904
 905         if (drm_core_check_feature(dev, DRIVER_MODESET))
 906                 return -ENODEV;
 907
 908         DRM_DEBUG_DRIVER("%s\n", __func__);
 909
 910         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 911
 912         mutex_lock(&dev->struct_mutex);
 913         ret = i915_dispatch_flip(dev);
 914         mutex_unlock(&dev->struct_mutex);
 915
 916         return ret;
 917 }
 918
 919 static int i915_getparam(struct drm_device *dev, void *data,
 920                          struct drm_file *file_priv)
 921 {
 922         struct drm_i915_private *dev_priv = dev->dev_private;
 923         drm_i915_getparam_t *param = data;
 924         int value;
 925
 926         if (!dev_priv) {
 927                 DRM_ERROR("called with no initialization\n");
 928                 return -EINVAL;
 929         }
 930
 931         switch (param->param) {
 932         case I915_PARAM_IRQ_ACTIVE:
 933                 value = dev->irq_enabled ? 1 : 0;
 934                 break;
 935         case I915_PARAM_ALLOW_BATCHBUFFER:
 936                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 937                 break;
 938         case I915_PARAM_LAST_DISPATCH:
 939                 value = READ_BREADCRUMB(dev_priv);
 940                 break;
 941         case I915_PARAM_CHIPSET_ID:
 942                 value = dev->pdev->device;
 943                 break;
 944         case I915_PARAM_HAS_GEM:
 945                 value = 1;
 946                 break;
 947         case I915_PARAM_NUM_FENCES_AVAIL:
 948                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 949                 break;
 950         case I915_PARAM_HAS_OVERLAY:
 951                 value = dev_priv->overlay ? 1 : 0;
 952                 break;
 953         case I915_PARAM_HAS_PAGEFLIPPING:
 954                 value = 1;
 955                 break;
 956         case I915_PARAM_HAS_EXECBUF2:
 957                 /* depends on GEM */
 958                 value = 1;
 959                 break;
 960         case I915_PARAM_HAS_BSD:
 961                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 962                 break;
 963         case I915_PARAM_HAS_BLT:
 964                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 965                 break;
 966         case I915_PARAM_HAS_VEBOX:
 967                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
 968                 break;
 969         case I915_PARAM_HAS_RELAXED_FENCING:
 970                 value = 1;
 971                 break;
 972         case I915_PARAM_HAS_COHERENT_RINGS:
 973                 value = 1;
 974                 break;
 975         case I915_PARAM_HAS_EXEC_CONSTANTS:
 976                 value = INTEL_INFO(dev)->gen >= 4;
 977                 break;
 978         case I915_PARAM_HAS_RELAXED_DELTA:
 979                 value = 1;
 980                 break;
 981         case I915_PARAM_HAS_GEN7_SOL_RESET:
 982                 value = 1;
 983                 break;
 984         case I915_PARAM_HAS_LLC:
 985                 value = HAS_LLC(dev);
 986                 break;
 987         case I915_PARAM_HAS_WT:
 988                 value = HAS_WT(dev);
 989                 break;
 990         case I915_PARAM_HAS_ALIASING_PPGTT:
 991                 value = USES_PPGTT(dev);
 992                 break;
 993         case I915_PARAM_HAS_WAIT_TIMEOUT:
 994                 value = 1;
 995                 break;
 996         case I915_PARAM_HAS_SEMAPHORES:
 997                 value = i915_semaphore_is_enabled(dev);
 998                 break;
 999         case I915_PARAM_HAS_PINNED_BATCHES:
1000                 value = 1;
1001                 break;
1002         case I915_PARAM_HAS_EXEC_NO_RELOC:
1003                 value = 1;
1004                 break;
1005         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1006                 value = 1;
1007                 break;
1008         case I915_PARAM_CMD_PARSER_VERSION:
1009                 value = i915_cmd_parser_get_version();
1010                 break;
1011         default:
1012                 DRM_DEBUG("Unknown parameter %d\n", param->param);
1013                 return -EINVAL;
1014         }
1015
1016         if (copy_to_user(param->value, &value, sizeof(int))) {
1017                 DRM_ERROR("copy_to_user failed\n");
1018                 return -EFAULT;
1019         }
1020
1021         return 0;
1022 }
1023
1024 static int i915_setparam(struct drm_device *dev, void *data,
1025                          struct drm_file *file_priv)
1026 {
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028         drm_i915_setparam_t *param = data;
1029
1030         if (!dev_priv) {
1031                 DRM_ERROR("called with no initialization\n");
1032                 return -EINVAL;
1033         }
1034
1035         switch (param->param) {
1036         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1037                 break;
1038         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1039                 break;
1040         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1041                 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1042                 break;
1043         case I915_SETPARAM_NUM_USED_FENCES:
1044                 if (param->value > dev_priv->num_fence_regs ||
1045                     param->value < 0)
1046                         return -EINVAL;
1047                 /* Userspace can use first N regs */
1048                 dev_priv->fence_reg_start = param->value;
1049                 break;
1050         default:
1051                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1052                                         param->param);
1053                 return -EINVAL;
1054         }
1055
1056         return 0;
1057 }
1058
1059 static int i915_set_status_page(struct drm_device *dev, void *data,
1060                                 struct drm_file *file_priv)
1061 {
1062 #if 0   /* We don't care about dri1 */
1063         struct drm_i915_private *dev_priv = dev->dev_private;
1064         drm_i915_hws_addr_t *hws = data;
1065         struct intel_engine_cs *ring;
1066
1067         if (drm_core_check_feature(dev, DRIVER_MODESET))
1068                 return -ENODEV;
1069
1070         if (!I915_NEED_GFX_HWS(dev))
1071                 return -EINVAL;
1072
1073         if (!dev_priv) {
1074                 DRM_ERROR("called with no initialization\n");
1075                 return -EINVAL;
1076         }
1077
1078         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1079                 WARN(1, "tried to set status page when mode setting active\n");
1080                 return 0;
1081         }
1082
1083         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1084
1085         ring = LP_RING(dev_priv);
1086         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1087
1088         dev_priv->dri1.gfx_hws_cpu_addr =
1089                 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1090         if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1091                 i915_dma_cleanup(dev);
1092                 ring->status_page.gfx_addr = 0;
1093                 DRM_ERROR("can not ioremap virtual address for"
1094                                 " G33 hw status page\n");
1095                 return -ENOMEM;
1096         }
1097
1098         memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1099         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1100
1101         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1102                          ring->status_page.gfx_addr);
1103         DRM_DEBUG_DRIVER("load hws at %p\n",
1104                          ring->status_page.page_addr);
1105         return 0;
1106 #endif
1107         return -EINVAL;
1108 }
1109
1110 static int i915_get_bridge_dev(struct drm_device *dev)
1111 {
1112         struct drm_i915_private *dev_priv = dev->dev_private;
1113         static struct pci_dev i915_bridge_dev;
1114
1115         i915_bridge_dev.dev = pci_find_dbsf(0, 0, 0, 0);
1116         if (!i915_bridge_dev.dev) {
1117                 DRM_ERROR("bridge device not found\n");
1118                 return -1;
1119         }
1120
1121         dev_priv->bridge_dev = &i915_bridge_dev;
1122         return 0;
1123 }
1124
1125 #define MCHBAR_I915 0x44
1126 #define MCHBAR_I965 0x48
1127 #define MCHBAR_SIZE (4*4096)
1128
1129 #define DEVEN_REG 0x54
1130 #define   DEVEN_MCHBAR_EN (1 << 28)
1131
1132 /* Allocate space for the MCH regs if needed, return nonzero on error */
1133 static int
1134 intel_alloc_mchbar_resource(struct drm_device *dev)
1135 {
1136         struct drm_i915_private *dev_priv = dev->dev_private;
1137         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1138         device_t vga;
1139         u32 temp_lo, temp_hi = 0;
1140         u64 mchbar_addr;
1141
1142         if (INTEL_INFO(dev)->gen >= 4)
1143                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1144         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1145         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1146
1147         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1148 #ifdef CONFIG_PNP
1149         if (mchbar_addr &&
1150             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1151                 return 0;
1152 #endif
1153
1154         /* Get some space for it */
1155         vga = device_get_parent(dev->dev);
1156         dev_priv->mch_res_rid = 0x100;
1157         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1158             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1159             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1160         if (dev_priv->mch_res == NULL) {
1161                 DRM_ERROR("failed mchbar resource alloc\n");
1162                 return (-ENOMEM);
1163         }
1164
1165         if (INTEL_INFO(dev)->gen >= 4)
1166                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1167                                        upper_32_bits(rman_get_start(dev_priv->mch_res)));
1168
1169         pci_write_config_dword(dev_priv->bridge_dev, reg,
1170                                lower_32_bits(rman_get_start(dev_priv->mch_res)));
1171         return 0;
1172 }
1173
1174 /* Setup MCHBAR if possible, return true if we should disable it again */
1175 static void
1176 intel_setup_mchbar(struct drm_device *dev)
1177 {
1178         struct drm_i915_private *dev_priv = dev->dev_private;
1179         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1180         u32 temp;
1181         bool enabled;
1182
1183         if (IS_VALLEYVIEW(dev))
1184                 return;
1185
1186         dev_priv->mchbar_need_disable = false;
1187
1188         if (IS_I915G(dev) || IS_I915GM(dev)) {
1189                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1190                 enabled = !!(temp & DEVEN_MCHBAR_EN);
1191         } else {
1192                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1193                 enabled = temp & 1;
1194         }
1195
1196         /* If it's already enabled, don't have to do anything */
1197         if (enabled)
1198                 return;
1199
1200         if (intel_alloc_mchbar_resource(dev))
1201                 return;
1202
1203         dev_priv->mchbar_need_disable = true;
1204
1205         /* Space is allocated or reserved, so enable it. */
1206         if (IS_I915G(dev) || IS_I915GM(dev)) {
1207                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1208                                        temp | DEVEN_MCHBAR_EN);
1209         } else {
1210                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1211                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1212         }
1213 }
1214
1215 static void
1216 intel_teardown_mchbar(struct drm_device *dev)
1217 {
1218         struct drm_i915_private *dev_priv = dev->dev_private;
1219         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1220         device_t vga;
1221         u32 temp;
1222
1223         if (dev_priv->mchbar_need_disable) {
1224                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1225                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1226                         temp &= ~DEVEN_MCHBAR_EN;
1227                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1228                 } else {
1229                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1230                         temp &= ~1;
1231                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1232                 }
1233         }
1234
1235         if (dev_priv->mch_res != NULL) {
1236                 vga = device_get_parent(dev->dev);
1237                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1238                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1239                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1240                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1241                 dev_priv->mch_res = NULL;
1242         }
1243 }
1244
1245 #if 0
1246 /* true = enable decode, false = disable decoder */
1247 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1248 {
1249         struct drm_device *dev = cookie;
1250
1251         intel_modeset_vga_set_state(dev, state);
1252         if (state)
1253                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1254                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1255         else
1256                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1257 }
1258
1259 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1260 {
1261         struct drm_device *dev = pci_get_drvdata(pdev);
1262         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1263
1264         if (state == VGA_SWITCHEROO_ON) {
1265                 pr_info("switched on\n");
1266                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1267                 /* i915 resume handler doesn't set to D0 */
1268                 pci_set_power_state(dev->pdev, PCI_D0);
1269                 i915_resume(dev);
1270                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1271         } else {
1272                 pr_err("switched off\n");
1273                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1274                 i915_suspend(dev, pmm);
1275                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1276         }
1277 }
1278
1279 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1280 {
1281         struct drm_device *dev = pci_get_drvdata(pdev);
1282
1283         /*
1284          * FIXME: open_count is protected by drm_global_mutex but that would lead to
1285          * locking inversion with the driver load path. And the access here is
1286          * completely racy anyway. So don't bother with locking for now.
1287          */
1288         return dev->open_count == 0;
1289 }
1290
1291 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1292         .set_gpu_state = i915_switcheroo_set_state,
1293         .reprobe = NULL,
1294         .can_switch = i915_switcheroo_can_switch,
1295 };
1296 #endif
1297
1298 static int i915_load_modeset_init(struct drm_device *dev)
1299 {
1300         struct drm_i915_private *dev_priv = dev->dev_private;
1301         int ret;
1302
1303         ret = intel_parse_bios(dev);
1304         if (ret)
1305                 DRM_INFO("failed to find VBIOS tables\n");
1306
1307 #if 0
1308         /* If we have > 1 VGA cards, then we need to arbitrate access
1309          * to the common VGA resources.
1310          *
1311          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1312          * then we do not take part in VGA arbitration and the
1313          * vga_client_register() fails with -ENODEV.
1314          */
1315         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1316         if (ret && ret != -ENODEV)
1317                 goto out;
1318
1319         intel_register_dsm_handler();
1320
1321         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
1322         if (ret)
1323                 goto cleanup_vga_client;
1324
1325         /* Initialise stolen first so that we may reserve preallocated
1326          * objects for the BIOS to KMS transition.
1327          */
1328         ret = i915_gem_init_stolen(dev);
1329         if (ret)
1330                 goto cleanup_vga_switcheroo;
1331 #endif
1332
1333         intel_power_domains_init_hw(dev_priv);
1334
1335         /*
1336          * We enable some interrupt sources in our postinstall hooks, so mark
1337          * interrupts as enabled _before_ actually enabling them to avoid
1338          * special cases in our ordering checks.
1339          */
1340         dev_priv->pm._irqs_disabled = false;
1341
1342         ret = drm_irq_install(dev, dev->irq);
1343         if (ret)
1344                 goto cleanup_gem_stolen;
1345
1346         /* Important: The output setup functions called by modeset_init need
1347          * working irqs for e.g. gmbus and dp aux transfers. */
1348         intel_modeset_init(dev);
1349
1350         ret = i915_gem_init(dev);
1351         if (ret)
1352                 goto cleanup_irq;
1353
1354         intel_modeset_gem_init(dev);
1355
1356         /* Always safe in the mode setting case. */
1357         /* FIXME: do pre/post-mode set stuff in core KMS code */
1358         dev->vblank_disable_allowed = 1;
1359         if (INTEL_INFO(dev)->num_pipes == 0) {
1360                 return 0;
1361         }
1362
1363         ret = intel_fbdev_init(dev);
1364         if (ret)
1365                 goto cleanup_gem;
1366
1367         /* Only enable hotplug handling once the fbdev is fully set up. */
1368         intel_hpd_init(dev);
1369
1370         /*
1371          * Some ports require correctly set-up hpd registers for detection to
1372          * work properly (leading to ghost connected connector status), e.g. VGA
1373          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1374          * irqs are fully enabled. Now we should scan for the initial config
1375          * only once hotplug handling is enabled, but due to screwed-up locking
1376          * around kms/fbdev init we can't protect the fdbev initial config
1377          * scanning against hotplug events. Hence do this first and ignore the
1378          * tiny window where we will loose hotplug notifactions.
1379          */
1380         async_schedule(intel_fbdev_initial_config, dev_priv);
1381
1382         drm_kms_helper_poll_init(dev);
1383
1384         return 0;
1385
1386 cleanup_gem:
1387         mutex_lock(&dev->struct_mutex);
1388         i915_gem_cleanup_ringbuffer(dev);
1389         i915_gem_context_fini(dev);
1390         mutex_unlock(&dev->struct_mutex);
1391 cleanup_irq:
1392         drm_irq_uninstall(dev);
1393 cleanup_gem_stolen:
1394 #if 0
1395         i915_gem_cleanup_stolen(dev);
1396 cleanup_vga_switcheroo:
1397         vga_switcheroo_unregister_client(dev->pdev);
1398 cleanup_vga_client:
1399         vga_client_register(dev->pdev, NULL, NULL, NULL);
1400 out:
1401 #endif
1402         return ret;
1403 }
1404
1405 #if 0
1406 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1407 {
1408         struct drm_i915_master_private *master_priv;
1409
1410         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1411         if (!master_priv)
1412                 return -ENOMEM;
1413
1414         master->driver_priv = master_priv;
1415         return 0;
1416 }
1417
1418 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1419 {
1420         struct drm_i915_master_private *master_priv = master->driver_priv;
1421
1422         if (!master_priv)
1423                 return;
1424
1425         kfree(master_priv);
1426
1427         master->driver_priv = NULL;
1428 }
1429 #endif
1430
1431 #if IS_ENABLED(CONFIG_FB)
1432 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1433 {
1434         struct apertures_struct *ap;
1435         struct pci_dev *pdev = dev_priv->dev->pdev;
1436         bool primary;
1437         int ret;
1438
1439         ap = alloc_apertures(1);
1440         if (!ap)
1441                 return -ENOMEM;
1442
1443         ap->ranges[0].base = dev_priv->gtt.mappable_base;
1444         ap->ranges[0].size = dev_priv->gtt.mappable_end;
1445
1446         primary =
1447                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1448
1449         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1450
1451         kfree(ap);
1452
1453         return ret;
1454 }
1455 #else
1456 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1457 {
1458         return 0;
1459 }
1460 #endif
1461
1462 #if !defined(CONFIG_VGA_CONSOLE)
1463 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1464 {
1465         return 0;
1466 }
1467 #elif !defined(CONFIG_DUMMY_CONSOLE)
1468 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1469 {
1470         return -ENODEV;
1471 }
1472 #else
1473 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1474 {
1475         int ret = 0;
1476
1477         DRM_INFO("Replacing VGA console driver\n");
1478
1479         console_lock();
1480         if (con_is_bound(&vga_con))
1481                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
1482         if (ret == 0) {
1483                 ret = do_unregister_con_driver(&vga_con);
1484
1485                 /* Ignore "already unregistered". */
1486                 if (ret == -ENODEV)
1487                         ret = 0;
1488         }
1489         console_unlock();
1490
1491         return ret;
1492 }
1493 #endif
1494
1495 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1496 {
1497 #if 0
1498         const struct intel_device_info *info = &dev_priv->info;
1499
1500 #define PRINT_S(name) "%s"
1501 #define SEP_EMPTY
1502 #define PRINT_FLAG(name) info->name ? #name "," : ""
1503 #define SEP_COMMA ,
1504         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
1505                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1506                          info->gen,
1507                          dev_priv->dev->pdev->device,
1508                          dev_priv->dev->pdev->revision,
1509                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1510 #undef PRINT_S
1511 #undef SEP_EMPTY
1512 #undef PRINT_FLAG
1513 #undef SEP_COMMA
1514 #endif
1515 }
1516
1517 /*
1518  * Determine various intel_device_info fields at runtime.
1519  *
1520  * Use it when either:
1521  *   - it's judged too laborious to fill n static structures with the limit
1522  *     when a simple if statement does the job,
1523  *   - run-time checks (eg read fuse/strap registers) are needed.
1524  *
1525  * This function needs to be called:
1526  *   - after the MMIO has been setup as we are reading registers,
1527  *   - after the PCH has been detected,
1528  *   - before the first usage of the fields it can tweak.
1529  */
1530 static void intel_device_info_runtime_init(struct drm_device *dev)
1531 {
1532         struct drm_i915_private *dev_priv = dev->dev_private;
1533         struct intel_device_info *info;
1534         enum i915_pipe pipe;
1535
1536         info = (struct intel_device_info *)&dev_priv->info;
1537
1538         if (IS_VALLEYVIEW(dev))
1539                 for_each_pipe(dev_priv, pipe)
1540                         info->num_sprites[pipe] = 2;
1541         else
1542                 for_each_pipe(dev_priv, pipe)
1543                         info->num_sprites[pipe] = 1;
1544
1545         if (i915.disable_display) {
1546                 DRM_INFO("Display disabled (module parameter)\n");
1547                 info->num_pipes = 0;
1548         } else if (info->num_pipes > 0 &&
1549                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
1550                    !IS_VALLEYVIEW(dev)) {
1551                 u32 fuse_strap = I915_READ(FUSE_STRAP);
1552                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
1553
1554                 /*
1555                  * SFUSE_STRAP is supposed to have a bit signalling the display
1556                  * is fused off. Unfortunately it seems that, at least in
1557                  * certain cases, fused off display means that PCH display
1558                  * reads don't land anywhere. In that case, we read 0s.
1559                  *
1560                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1561                  * should be set when taking over after the firmware.
1562                  */
1563                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1564                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1565                     (dev_priv->pch_type == PCH_CPT &&
1566                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1567                         DRM_INFO("Display fused off, disabling\n");
1568                         info->num_pipes = 0;
1569                 }
1570         }
1571 }
1572
1573 /**
1574  * i915_driver_load - setup chip and create an initial config
1575  * @dev: DRM device
1576  * @flags: startup flags
1577  *
1578  * The driver load routine has to do several things:
1579  *   - drive output discovery via intel_modeset_init()
1580  *   - initialize the memory manager
1581  *   - allocate initial config memory
1582  *   - setup the DRM framebuffer with the allocated memory
1583  */
1584 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1585 {
1586         struct drm_i915_private *dev_priv = dev->dev_private;
1587         struct intel_device_info *info, *device_info;
1588         unsigned long base, size;
1589         int ret = 0, mmio_bar, mmio_size;
1590         uint32_t aperture_size;
1591         static struct pci_dev i915_pdev;
1592
1593         /* XXX: dev->pci_device not present in Linux drm */
1594         info = i915_get_device_id(dev->pci_device);
1595
1596         /* XXX: struct pci_dev */
1597         i915_pdev.dev = dev->dev;
1598         dev->pdev = &i915_pdev;
1599         dev->pdev->device = dev->pci_device;
1600
1601         /* Refuse to load on gen6+ without kms enabled. */
1602         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
1603                 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
1604                 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
1605                 return -ENODEV;
1606         }
1607
1608         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1609         if (dev_priv == NULL)
1610                 return -ENOMEM;
1611
1612         dev->dev_private = dev_priv;
1613         dev_priv->dev = dev;
1614
1615         /* Setup the write-once "constant" device info */
1616         device_info = (struct intel_device_info *)&dev_priv->info;
1617         memcpy(device_info, info, sizeof(dev_priv->info));
1618         device_info->device_id = dev->pdev->device;
1619
1620         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1621         lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
1622         spin_init(&dev_priv->backlight_lock, "i915bl");
1623         lockinit(&dev_priv->uncore.lock, "915gt", 0, LK_CANRECURSE);
1624         spin_init(&dev_priv->mm.object_stat_lock, "i915osl");
1625         spin_init(&dev_priv->mmio_flip_lock, "i915mfl");
1626         lockinit(&dev_priv->dpio_lock, "i915dpio", 0, LK_CANRECURSE);
1627         lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
1628
1629         intel_pm_setup(dev);
1630
1631         intel_display_crc_init(dev);
1632
1633         i915_dump_device_info(dev_priv);
1634
1635         /* Not all pre-production machines fall into this category, only the
1636          * very first ones. Almost everything should work, except for maybe
1637          * suspend/resume. And we don't implement workarounds that affect only
1638          * pre-production machines. */
1639         if (IS_HSW_EARLY_SDV(dev))
1640                 DRM_INFO("This is an early pre-production Haswell machine. "
1641                          "It may not be fully functional.\n");
1642
1643         if (i915_get_bridge_dev(dev)) {
1644                 ret = -EIO;
1645                 goto free_priv;
1646         }
1647
1648         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1649         /* Before gen4, the registers and the GTT are behind different BARs.
1650          * However, from gen4 onwards, the registers and the GTT are shared
1651          * in the same BAR, so we want to restrict this ioremap from
1652          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1653          * the register BAR remains the same size for all the earlier
1654          * generations up to Ironlake.
1655          */
1656         if (info->gen < 5)
1657                 mmio_size = 512*1024;
1658         else
1659                 mmio_size = 2*1024*1024;
1660
1661 #if 0
1662         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1663         if (!dev_priv->regs) {
1664                 DRM_ERROR("failed to map registers\n");
1665                 ret = -EIO;
1666                 goto put_bridge;
1667         }
1668 #else
1669         base = drm_get_resource_start(dev, mmio_bar);
1670         size = drm_get_resource_len(dev, mmio_bar);
1671
1672         ret = drm_legacy_addmap(dev, base, size, _DRM_REGISTERS,
1673             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1674 #endif
1675
1676         /* This must be called before any calls to HAS_PCH_* */
1677         intel_detect_pch(dev);
1678
1679         intel_uncore_init(dev);
1680
1681         ret = i915_gem_gtt_init(dev);
1682         if (ret)
1683                 goto out_regs;
1684
1685         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1686                 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1687                  * otherwise the vga fbdev driver falls over. */
1688                 ret = i915_kick_out_firmware_fb(dev_priv);
1689                 if (ret) {
1690                         DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1691                         goto out_gtt;
1692                 }
1693
1694                 ret = i915_kick_out_vgacon(dev_priv);
1695                 if (ret) {
1696                         DRM_ERROR("failed to remove conflicting VGA console\n");
1697                         goto out_gtt;
1698                 }
1699         }
1700
1701 #if 0
1702         pci_set_master(dev->pdev);
1703
1704         /* overlay on gen2 is broken and can't address above 1G */
1705         if (IS_GEN2(dev))
1706                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1707
1708         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1709          * using 32bit addressing, overwriting memory if HWS is located
1710          * above 4GB.
1711          *
1712          * The documentation also mentions an issue with undefined
1713          * behaviour if any general state is accessed within a page above 4GB,
1714          * which also needs to be handled carefully.
1715          */
1716         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1717                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1718 #endif
1719
1720         aperture_size = dev_priv->gtt.mappable_end;
1721
1722         dev_priv->gtt.mappable =
1723                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1724                                      aperture_size);
1725         if (dev_priv->gtt.mappable == NULL) {
1726                 ret = -EIO;
1727                 goto out_gtt;
1728         }
1729
1730         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1731                                               aperture_size);
1732
1733         /* The i915 workqueue is primarily used for batched retirement of
1734          * requests (and thus managing bo) once the task has been completed
1735          * by the GPU. i915_gem_retire_requests() is called directly when we
1736          * need high-priority retirement, such as waiting for an explicit
1737          * bo.
1738          *
1739          * It is also used for periodic low-priority events, such as
1740          * idle-timers and recording error state.
1741          *
1742          * All tasks on the workqueue are expected to acquire the dev mutex
1743          * so there is no point in running more than one instance of the
1744          * workqueue at any time.  Use an ordered one.
1745          */
1746         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1747         if (dev_priv->wq == NULL) {
1748                 DRM_ERROR("Failed to create our workqueue.\n");
1749                 ret = -ENOMEM;
1750                 goto out_mtrrfree;
1751         }
1752
1753         dev_priv->dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1754         if (dev_priv->dp_wq == NULL) {
1755                 DRM_ERROR("Failed to create our dp workqueue.\n");
1756                 ret = -ENOMEM;
1757                 goto out_freewq;
1758         }
1759
1760         intel_irq_init(dev);
1761         intel_uncore_sanitize(dev);
1762
1763         /* Try to make sure MCHBAR is enabled before poking at it */
1764         intel_setup_mchbar(dev);
1765         intel_setup_gmbus(dev);
1766         intel_opregion_setup(dev);
1767
1768         intel_setup_bios(dev);
1769
1770         i915_gem_load(dev);
1771
1772         /* On the 945G/GM, the chipset reports the MSI capability on the
1773          * integrated graphics even though the support isn't actually there
1774          * according to the published specs.  It doesn't appear to function
1775          * correctly in testing on 945G.
1776          * This may be a side effect of MSI having been made available for PEG
1777          * and the registers being closely associated.
1778          *
1779          * According to chipset errata, on the 965GM, MSI interrupts may
1780          * be lost or delayed, but we use them anyways to avoid
1781          * stuck interrupts on some machines.
1782          */
1783 #if 0
1784         if (!IS_I945G(dev) && !IS_I945GM(dev))
1785                 pci_enable_msi(dev->pdev);
1786 #endif
1787
1788         intel_device_info_runtime_init(dev);
1789
1790         if (INTEL_INFO(dev)->num_pipes) {
1791                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1792                 if (ret)
1793                         goto out_gem_unload;
1794         }
1795
1796         intel_power_domains_init(dev_priv);
1797
1798         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1799                 ret = i915_load_modeset_init(dev);
1800                 if (ret < 0) {
1801                         DRM_ERROR("failed to init modeset\n");
1802                         goto out_power_well;
1803                 }
1804         } else {
1805                 /* Start out suspended in ums mode. */
1806                 dev_priv->ums.mm_suspended = 1;
1807         }
1808
1809 #if 0
1810         i915_setup_sysfs(dev);
1811 #endif
1812
1813         if (INTEL_INFO(dev)->num_pipes) {
1814                 /* Must be done after probing outputs */
1815                 intel_opregion_init(dev);
1816 #if 0
1817                 acpi_video_register();
1818 #endif
1819         }
1820
1821         if (IS_GEN5(dev))
1822                 intel_gpu_ips_init(dev_priv);
1823
1824         intel_init_runtime_pm(dev_priv);
1825
1826         return 0;
1827
1828 out_power_well:
1829         intel_power_domains_remove(dev_priv);
1830         drm_vblank_cleanup(dev);
1831 out_gem_unload:
1832
1833         intel_teardown_gmbus(dev);
1834         intel_teardown_mchbar(dev);
1835         pm_qos_remove_request(&dev_priv->pm_qos);
1836         destroy_workqueue(dev_priv->dp_wq);
1837 out_freewq:
1838         destroy_workqueue(dev_priv->wq);
1839 out_mtrrfree:
1840         arch_phys_wc_del(dev_priv->gtt.mtrr);
1841 #if 0
1842         io_mapping_free(dev_priv->gtt.mappable);
1843 #endif
1844 out_gtt:
1845         i915_global_gtt_cleanup(dev);
1846 out_regs:
1847         intel_uncore_fini(dev);
1848 free_priv:
1849         kfree(dev_priv);
1850         return ret;
1851 }
1852
1853 int i915_driver_unload(struct drm_device *dev)
1854 {
1855         struct drm_i915_private *dev_priv = dev->dev_private;
1856         int ret;
1857
1858         ret = i915_gem_suspend(dev);
1859         if (ret) {
1860                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1861                 return ret;
1862         }
1863
1864         intel_fini_runtime_pm(dev_priv);
1865
1866         intel_gpu_ips_teardown();
1867
1868         /* The i915.ko module is still not prepared to be loaded when
1869          * the power well is not enabled, so just enable it in case
1870          * we're going to unload/reload. */
1871         intel_display_set_init_power(dev_priv, true);
1872         intel_power_domains_remove(dev_priv);
1873
1874 #if 0
1875         i915_teardown_sysfs(dev);
1876
1877         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1878         unregister_shrinker(&dev_priv->mm.shrinker);
1879
1880         io_mapping_free(dev_priv->gtt.mappable);
1881 #endif
1882         arch_phys_wc_del(dev_priv->gtt.mtrr);
1883
1884 #if 0
1885         acpi_video_unregister();
1886 #endif
1887
1888         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1889                 intel_fbdev_fini(dev);
1890                 intel_modeset_cleanup(dev);
1891
1892                 /*
1893                  * free the memory space allocated for the child device
1894                  * config parsed from VBT
1895                  */
1896                 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1897                         kfree(dev_priv->vbt.child_dev);
1898                         dev_priv->vbt.child_dev = NULL;
1899                         dev_priv->vbt.child_dev_num = 0;
1900                 }
1901
1902         }
1903
1904         /* Free error state after interrupts are fully disabled. */
1905         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1906         cancel_work_sync(&dev_priv->gpu_error.work);
1907 #if 0
1908         i915_destroy_error_state(dev);
1909 #endif
1910
1911         intel_opregion_fini(dev);
1912
1913         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1914                 /* Flush any outstanding unpin_work. */
1915                 flush_workqueue(dev_priv->wq);
1916
1917                 mutex_lock(&dev->struct_mutex);
1918                 i915_gem_cleanup_ringbuffer(dev);
1919                 i915_gem_context_fini(dev);
1920                 mutex_unlock(&dev->struct_mutex);
1921 #if 0
1922                 i915_gem_cleanup_stolen(dev);
1923 #endif
1924
1925                 if (!I915_NEED_GFX_HWS(dev))
1926                         i915_free_hws(dev);
1927         }
1928
1929         drm_vblank_cleanup(dev);
1930
1931         intel_teardown_gmbus(dev);
1932         intel_teardown_mchbar(dev);
1933
1934         bus_generic_detach(dev->dev);
1935         drm_legacy_rmmap(dev, dev_priv->mmio_map);
1936
1937         destroy_workqueue(dev_priv->dp_wq);
1938         destroy_workqueue(dev_priv->wq);
1939         pm_qos_remove_request(&dev_priv->pm_qos);
1940
1941         i915_global_gtt_cleanup(dev);
1942
1943         intel_uncore_fini(dev);
1944 #if 0
1945         if (dev_priv->regs != NULL)
1946                 pci_iounmap(dev->pdev, dev_priv->regs);
1947 #endif
1948
1949         pci_dev_put(dev_priv->bridge_dev);
1950         kfree(dev_priv);
1951
1952         return 0;
1953 }
1954
1955 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1956 {
1957         int ret;
1958
1959         ret = i915_gem_open(dev, file);
1960         if (ret)
1961                 return ret;
1962
1963         return 0;
1964 }
1965
1966 /**
1967  * i915_driver_lastclose - clean up after all DRM clients have exited
1968  * @dev: DRM device
1969  *
1970  * Take care of cleaning up after all DRM clients have exited.  In the
1971  * mode setting case, we want to restore the kernel's initial mode (just
1972  * in case the last client left us in a bad state).
1973  *
1974  * Additionally, in the non-mode setting case, we'll tear down the GTT
1975  * and DMA structures, since the kernel won't be using them, and clea
1976  * up any GEM state.
1977  */
1978 void i915_driver_lastclose(struct drm_device *dev)
1979 {
1980         struct drm_i915_private *dev_priv = dev->dev_private;
1981
1982         /* On gen6+ we refuse to init without kms enabled, but then the drm core
1983          * goes right around and calls lastclose. Check for this and don't clean
1984          * up anything. */
1985         if (!dev_priv)
1986                 return;
1987
1988         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1989 #if 0
1990                 intel_fbdev_restore_mode(dev);
1991                 vga_switcheroo_process_delayed_switch();
1992 #endif
1993                 return;
1994         }
1995
1996         i915_gem_lastclose(dev);
1997
1998         i915_dma_cleanup(dev);
1999 }
2000
2001 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
2002 {
2003         mutex_lock(&dev->struct_mutex);
2004         i915_gem_context_close(dev, file);
2005         i915_gem_release(dev, file);
2006         mutex_unlock(&dev->struct_mutex);
2007
2008         if (drm_core_check_feature(dev, DRIVER_MODESET))
2009                 intel_modeset_preclose(dev, file);
2010 }
2011
2012 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2013 {
2014         struct drm_i915_file_private *file_priv = file->driver_priv;
2015
2016         if (file_priv && file_priv->bsd_ring)
2017                 file_priv->bsd_ring = NULL;
2018         kfree(file_priv);
2019 }
2020
2021 const struct drm_ioctl_desc i915_ioctls[] = {
2022         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2023         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2024         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2025         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2026         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2027         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2028         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2029         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2030         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2031         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2032         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2033         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2034         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2035         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2036         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
2037         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2038         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2039         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2040         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2041         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2042         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2043         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2044         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2045         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2046         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2047         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2048         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2049         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2050         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2051         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2052         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2053         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2054         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2055         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2056         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2057         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2058         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2059         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2060         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2061         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2062         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2063         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2064         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2065         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2066         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2067         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2068         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2069         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2070         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2071 #if 0
2072         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2073 #endif
2074 };
2075
2076 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
2077
2078 /*
2079  * This is really ugly: Because old userspace abused the linux agp interface to
2080  * manage the gtt, we need to claim that all intel devices are agp.  For
2081  * otherwise the drm core refuses to initialize the agp support code.
2082  */
2083 int i915_driver_device_is_agp(struct drm_device *dev)
2084 {
2085         return 1;
2086 }