1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
31 * ------------------------ This file is DEPRECATED! -------------------------
33 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_cp.c 254885 2013-08-25 19:37:15Z dumbbell $
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/linker.h>
39 #include <sys/firmware.h>
40 #include <linux/module.h>
43 #include <uapi_drm/radeon_drm.h>
44 #include "radeon_drv.h"
47 #define RADEON_FIFO_DEBUG 0
50 #define FIRMWARE_R100 "radeonkmsfw_R100_cp"
51 #define FIRMWARE_R200 "radeonkmsfw_R200_cp"
52 #define FIRMWARE_R300 "radeonkmsfw_R300_cp"
53 #define FIRMWARE_R420 "radeonkmsfw_R420_cp"
54 #define FIRMWARE_RS690 "radeonkmsfw_RS690_cp"
55 #define FIRMWARE_RS600 "radeonkmsfw_RS600_cp"
56 #define FIRMWARE_R520 "radeonkmsfw_R520_cp"
58 MODULE_FIRMWARE(FIRMWARE_R100);
59 MODULE_FIRMWARE(FIRMWARE_R200);
60 MODULE_FIRMWARE(FIRMWARE_R300);
61 MODULE_FIRMWARE(FIRMWARE_R420);
62 MODULE_FIRMWARE(FIRMWARE_RS690);
63 MODULE_FIRMWARE(FIRMWARE_RS600);
64 MODULE_FIRMWARE(FIRMWARE_R520);
66 static int radeon_do_cleanup_cp(struct drm_device * dev);
67 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
69 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
73 if (dev_priv->flags & RADEON_IS_AGP) {
74 val = DRM_READ32(dev_priv->ring_rptr, off);
76 val = *(((volatile u32 *)
77 dev_priv->ring_rptr->handle) +
79 val = le32_to_cpu(val);
84 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
86 if (dev_priv->writeback_works)
87 return radeon_read_ring_rptr(dev_priv, 0);
89 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
90 return RADEON_READ(R600_CP_RB_RPTR);
92 return RADEON_READ(RADEON_CP_RB_RPTR);
96 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
98 if (dev_priv->flags & RADEON_IS_AGP)
99 DRM_WRITE32(dev_priv->ring_rptr, off, val);
101 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
102 (off / sizeof(u32))) = cpu_to_le32(val);
105 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
107 radeon_write_ring_rptr(dev_priv, 0, val);
110 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
112 if (dev_priv->writeback_works) {
113 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
114 return radeon_read_ring_rptr(dev_priv,
115 R600_SCRATCHOFF(index));
117 return radeon_read_ring_rptr(dev_priv,
118 RADEON_SCRATCHOFF(index));
120 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
121 return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
123 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
127 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
130 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
131 ret = RADEON_READ(R520_MC_IND_DATA);
132 RADEON_WRITE(R520_MC_IND_INDEX, 0);
136 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
139 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
140 ret = RADEON_READ(RS480_NB_MC_DATA);
141 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
145 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
148 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
149 ret = RADEON_READ(RS690_MC_DATA);
150 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
154 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
157 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
158 RS600_MC_IND_CITF_ARB0));
159 ret = RADEON_READ(RS600_MC_DATA);
163 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
165 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
166 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
167 return RS690_READ_MCIND(dev_priv, addr);
168 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
169 return RS600_READ_MCIND(dev_priv, addr);
171 return RS480_READ_MCIND(dev_priv, addr);
174 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
177 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
178 return RADEON_READ(R700_MC_VM_FB_LOCATION);
179 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
180 return RADEON_READ(R600_MC_VM_FB_LOCATION);
181 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
182 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
183 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
184 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
185 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
186 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
187 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
188 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
189 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
191 return RADEON_READ(RADEON_MC_FB_LOCATION);
194 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
196 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
197 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
198 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
199 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
200 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
201 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
202 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
203 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
204 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
205 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
206 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
207 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
208 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
210 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
213 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
215 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
216 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
217 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
218 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
219 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
220 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
221 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
222 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
223 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
224 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
225 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
226 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
227 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
228 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
229 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
230 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
232 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
235 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
237 u32 agp_base_hi = upper_32_bits(agp_base);
238 u32 agp_base_lo = agp_base & 0xffffffff;
239 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
241 /* R6xx/R7xx must be aligned to a 4MB boundary */
242 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
243 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
244 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
245 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
246 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
247 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
248 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
249 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
250 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
251 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
252 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
253 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
254 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
255 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
256 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
257 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
258 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
259 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
260 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
261 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
262 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
264 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
265 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
266 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
270 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
273 /* Turn on bus mastering */
274 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
275 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
276 /* rs600/rs690/rs740 */
277 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
278 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
279 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
280 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
281 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
282 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
283 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
284 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
285 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
286 } /* PCIE cards appears to not need this */
289 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
291 drm_radeon_private_t *dev_priv = dev->dev_private;
293 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
294 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
297 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
299 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
300 return RADEON_READ(RADEON_PCIE_DATA);
303 #if RADEON_FIFO_DEBUG
304 static void radeon_status(drm_radeon_private_t * dev_priv)
306 printk("%s:\n", __func__);
307 printk("RBBM_STATUS = 0x%08x\n",
308 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
309 printk("CP_RB_RTPR = 0x%08x\n",
310 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
311 printk("CP_RB_WTPR = 0x%08x\n",
312 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
313 printk("AIC_CNTL = 0x%08x\n",
314 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
315 printk("AIC_STAT = 0x%08x\n",
316 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
317 printk("AIC_PT_BASE = 0x%08x\n",
318 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
319 printk("TLB_ADDR = 0x%08x\n",
320 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
321 printk("TLB_DATA = 0x%08x\n",
322 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
326 /* ================================================================
327 * Engine, FIFO control
330 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
335 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
337 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
338 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
339 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
340 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
342 for (i = 0; i < dev_priv->usec_timeout; i++) {
343 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
344 & RADEON_RB3D_DC_BUSY)) {
350 /* don't flush or purge cache here or lockup */
354 #if RADEON_FIFO_DEBUG
355 DRM_ERROR("failed!\n");
356 radeon_status(dev_priv);
361 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
365 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
367 for (i = 0; i < dev_priv->usec_timeout; i++) {
368 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
369 & RADEON_RBBM_FIFOCNT_MASK);
370 if (slots >= entries)
374 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
375 RADEON_READ(RADEON_RBBM_STATUS),
376 RADEON_READ(R300_VAP_CNTL_STATUS));
378 #if RADEON_FIFO_DEBUG
379 DRM_ERROR("failed!\n");
380 radeon_status(dev_priv);
385 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
389 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
391 ret = radeon_do_wait_for_fifo(dev_priv, 64);
395 for (i = 0; i < dev_priv->usec_timeout; i++) {
396 if (!(RADEON_READ(RADEON_RBBM_STATUS)
397 & RADEON_RBBM_ACTIVE)) {
398 radeon_do_pixcache_flush(dev_priv);
403 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
404 RADEON_READ(RADEON_RBBM_STATUS),
405 RADEON_READ(R300_VAP_CNTL_STATUS));
407 #if RADEON_FIFO_DEBUG
408 DRM_ERROR("failed!\n");
409 radeon_status(dev_priv);
414 static void radeon_init_pipes(struct drm_device *dev)
416 drm_radeon_private_t *dev_priv = dev->dev_private;
417 uint32_t gb_tile_config, gb_pipe_sel = 0;
419 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
420 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
421 if ((z_pipe_sel & 3) == 3)
422 dev_priv->num_z_pipes = 2;
424 dev_priv->num_z_pipes = 1;
426 dev_priv->num_z_pipes = 1;
428 /* RS4xx/RS6xx/R4xx/R5xx */
429 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
430 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
431 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
432 /* SE cards have 1 pipe */
433 if ((dev->pdev->device == 0x5e4c) ||
434 (dev->pdev->device == 0x5e4f))
435 dev_priv->num_gb_pipes = 1;
438 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
439 dev->pdev->device != 0x4144) ||
440 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 &&
441 dev->pdev->device != 0x4148)) {
442 dev_priv->num_gb_pipes = 2;
444 /* RV3xx/R300 AD/R350 AH */
445 dev_priv->num_gb_pipes = 1;
448 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
450 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
452 switch (dev_priv->num_gb_pipes) {
453 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
454 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
455 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
457 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
460 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
461 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
462 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
464 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
465 radeon_do_wait_for_idle(dev_priv);
466 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
467 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
468 R300_DC_AUTOFLUSH_ENABLE |
469 R300_DC_DC_DISABLE_IGNORE_PE));
474 /* ================================================================
475 * CP control, initialization
478 /* Load the microcode for the CP */
479 static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
481 struct platform_device *pdev;
482 const char *fw_name = NULL;
487 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
488 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
489 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
490 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
491 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
492 DRM_INFO("Loading R100 Microcode\n");
493 fw_name = FIRMWARE_R100;
494 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
495 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
496 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
497 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
498 DRM_INFO("Loading R200 Microcode\n");
499 fw_name = FIRMWARE_R200;
500 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
501 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
502 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
503 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
504 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
505 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
506 DRM_INFO("Loading R300 Microcode\n");
507 fw_name = FIRMWARE_R300;
508 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
509 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
510 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
511 DRM_INFO("Loading R400 Microcode\n");
512 fw_name = FIRMWARE_R420;
513 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
514 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
515 DRM_INFO("Loading RS690/RS740 Microcode\n");
516 fw_name = FIRMWARE_RS690;
517 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
518 DRM_INFO("Loading RS600 Microcode\n");
519 fw_name = FIRMWARE_RS600;
520 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
521 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
522 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
523 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
524 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
525 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
526 DRM_INFO("Loading R500 Microcode\n");
527 fw_name = FIRMWARE_R520;
530 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
532 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
534 } else if (dev_priv->me_fw->datasize % 8) {
536 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
537 dev_priv->me_fw->datasize, fw_name);
539 release_firmware(dev_priv->me_fw);
540 dev_priv->me_fw = NULL;
545 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
547 const __be32 *fw_data;
550 radeon_do_wait_for_idle(dev_priv);
552 if (dev_priv->me_fw) {
553 size = dev_priv->me_fw->datasize / 4;
554 fw_data = (const __be32 *)dev_priv->me_fw->data;
555 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
556 for (i = 0; i < size; i += 2) {
557 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
558 be32_to_cpup(&fw_data[i]));
559 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
560 be32_to_cpup(&fw_data[i + 1]));
565 /* Flush any pending commands to the CP. This should only be used just
566 * prior to a wait for idle, as it informs the engine that the command
569 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
575 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
576 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
580 /* Wait for the CP to go idle.
582 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
589 RADEON_PURGE_CACHE();
590 RADEON_PURGE_ZCACHE();
591 RADEON_WAIT_UNTIL_IDLE();
596 return radeon_do_wait_for_idle(dev_priv);
599 /* Start the Command Processor.
601 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
606 radeon_do_wait_for_idle(dev_priv);
608 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
610 dev_priv->cp_running = 1;
612 /* on r420, any DMA from CP to system memory while 2D is active
613 * can cause a hang. workaround is to queue a CP RESYNC token
615 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
617 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
618 OUT_RING(5); /* scratch reg 5 */
619 OUT_RING(0xdeadbeef);
625 /* isync can only be written through cp on r5xx write it here */
626 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
627 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
628 RADEON_ISYNC_ANY3D_IDLE2D |
629 RADEON_ISYNC_WAIT_IDLEGUI |
630 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
631 RADEON_PURGE_CACHE();
632 RADEON_PURGE_ZCACHE();
633 RADEON_WAIT_UNTIL_IDLE();
637 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
640 /* Reset the Command Processor. This will not flush any pending
641 * commands, so you must wait for the CP command stream to complete
642 * before calling this routine.
644 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
649 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
650 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
651 SET_RING_HEAD(dev_priv, cur_read_ptr);
652 dev_priv->ring.tail = cur_read_ptr;
655 /* Stop the Command Processor. This will not flush any pending
656 * commands, so you must flush the command stream and wait for the CP
657 * to go idle before calling this routine.
659 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
664 /* finish the pending CP_RESYNC token */
665 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
667 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
668 OUT_RING(R300_RB3D_DC_FINISH);
671 radeon_do_wait_for_idle(dev_priv);
674 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
676 dev_priv->cp_running = 0;
679 /* Reset the engine. This will stop the CP if it is running.
681 static int radeon_do_engine_reset(struct drm_device * dev)
683 drm_radeon_private_t *dev_priv = dev->dev_private;
684 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
687 radeon_do_pixcache_flush(dev_priv);
689 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
690 /* may need something similar for newer chips */
691 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
692 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
694 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
695 RADEON_FORCEON_MCLKA |
696 RADEON_FORCEON_MCLKB |
697 RADEON_FORCEON_YCLKA |
698 RADEON_FORCEON_YCLKB |
700 RADEON_FORCEON_AIC));
703 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
705 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
706 RADEON_SOFT_RESET_CP |
707 RADEON_SOFT_RESET_HI |
708 RADEON_SOFT_RESET_SE |
709 RADEON_SOFT_RESET_RE |
710 RADEON_SOFT_RESET_PP |
711 RADEON_SOFT_RESET_E2 |
712 RADEON_SOFT_RESET_RB));
713 RADEON_READ(RADEON_RBBM_SOFT_RESET);
714 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
715 ~(RADEON_SOFT_RESET_CP |
716 RADEON_SOFT_RESET_HI |
717 RADEON_SOFT_RESET_SE |
718 RADEON_SOFT_RESET_RE |
719 RADEON_SOFT_RESET_PP |
720 RADEON_SOFT_RESET_E2 |
721 RADEON_SOFT_RESET_RB)));
722 RADEON_READ(RADEON_RBBM_SOFT_RESET);
724 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
725 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
726 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
727 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
730 /* setup the raster pipes */
731 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
732 radeon_init_pipes(dev);
734 /* Reset the CP ring */
735 radeon_do_cp_reset(dev_priv);
737 /* The CP is no longer running after an engine reset */
738 dev_priv->cp_running = 0;
740 /* Reset any pending vertex, indirect buffers */
741 radeon_freelist_reset(dev);
746 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
747 drm_radeon_private_t *dev_priv,
748 struct drm_file *file_priv)
750 struct drm_radeon_master_private *master_priv;
751 u32 ring_start, cur_read_ptr;
753 /* Initialize the memory controller. With new memory map, the fb location
754 * is not changed, it should have been properly initialized already. Part
755 * of the problem is that the code below is bogus, assuming the GART is
756 * always appended to the fb which is not necessarily the case
758 if (!dev_priv->new_memmap)
759 radeon_write_fb_location(dev_priv,
760 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
761 | (dev_priv->fb_location >> 16));
764 if (dev_priv->flags & RADEON_IS_AGP) {
765 radeon_write_agp_base(dev_priv, dev->agp->base);
767 radeon_write_agp_location(dev_priv,
768 (((dev_priv->gart_vm_start - 1 +
769 dev_priv->gart_size) & 0xffff0000) |
770 (dev_priv->gart_vm_start >> 16)));
772 ring_start = (dev_priv->cp_ring->offset
774 + dev_priv->gart_vm_start);
777 ring_start = (dev_priv->cp_ring->offset
778 - (unsigned long)dev->sg->vaddr
779 + dev_priv->gart_vm_start);
781 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
783 /* Set the write pointer delay */
784 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
786 /* Initialize the ring buffer's read and write pointers */
787 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
788 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
789 SET_RING_HEAD(dev_priv, cur_read_ptr);
790 dev_priv->ring.tail = cur_read_ptr;
793 if (dev_priv->flags & RADEON_IS_AGP) {
794 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
795 dev_priv->ring_rptr->offset
796 - dev->agp->base + dev_priv->gart_vm_start);
800 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
801 dev_priv->ring_rptr->offset
802 - ((unsigned long) dev->sg->vaddr)
803 + dev_priv->gart_vm_start);
806 /* Set ring buffer size */
808 RADEON_WRITE(RADEON_CP_RB_CNTL,
809 RADEON_BUF_SWAP_32BIT |
810 (dev_priv->ring.fetch_size_l2ow << 18) |
811 (dev_priv->ring.rptr_update_l2qw << 8) |
812 dev_priv->ring.size_l2qw);
814 RADEON_WRITE(RADEON_CP_RB_CNTL,
815 (dev_priv->ring.fetch_size_l2ow << 18) |
816 (dev_priv->ring.rptr_update_l2qw << 8) |
817 dev_priv->ring.size_l2qw);
821 /* Initialize the scratch register pointer. This will cause
822 * the scratch register values to be written out to memory
823 * whenever they are updated.
825 * We simply put this behind the ring read pointer, this works
826 * with PCI GART as well as (whatever kind of) AGP GART
828 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
829 + RADEON_SCRATCH_REG_OFFSET);
831 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
833 radeon_enable_bm(dev_priv);
835 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
836 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
838 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
839 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
841 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
842 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
844 /* reset sarea copies of these */
845 master_priv = file_priv->masterp->driver_priv;
846 if (master_priv->sarea_priv) {
847 master_priv->sarea_priv->last_frame = 0;
848 master_priv->sarea_priv->last_dispatch = 0;
849 master_priv->sarea_priv->last_clear = 0;
852 radeon_do_wait_for_idle(dev_priv);
854 /* Sync everything up */
855 RADEON_WRITE(RADEON_ISYNC_CNTL,
856 (RADEON_ISYNC_ANY2D_IDLE3D |
857 RADEON_ISYNC_ANY3D_IDLE2D |
858 RADEON_ISYNC_WAIT_IDLEGUI |
859 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
863 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
867 /* Start with assuming that writeback doesn't work */
868 dev_priv->writeback_works = 0;
870 /* Writeback doesn't seem to work everywhere, test it here and possibly
871 * enable it if it appears to work
873 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
875 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
877 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
880 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
881 if (val == 0xdeadbeef)
886 if (tmp < dev_priv->usec_timeout) {
887 dev_priv->writeback_works = 1;
888 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
890 dev_priv->writeback_works = 0;
891 DRM_INFO("writeback test failed\n");
893 if (radeon_no_wb == 1) {
894 dev_priv->writeback_works = 0;
895 DRM_INFO("writeback forced off\n");
898 if (!dev_priv->writeback_works) {
899 /* Disable writeback to avoid unnecessary bus master transfer */
900 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
901 RADEON_RB_NO_UPDATE);
902 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
906 /* Enable or disable IGP GART on the chip */
907 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
912 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
913 dev_priv->gart_vm_start,
914 (long)dev_priv->gart_info.bus_addr,
915 dev_priv->gart_size);
917 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
918 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
919 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
920 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
921 RS690_BLOCK_GFX_D3_EN));
923 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
925 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
926 RS480_VA_SIZE_32MB));
928 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
929 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
934 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
935 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
936 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
938 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
939 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
940 RS480_REQ_TYPE_SNOOP_DIS));
942 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
944 dev_priv->gart_size = 32*1024*1024;
945 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
946 0xffff0000) | (dev_priv->gart_vm_start >> 16));
948 radeon_write_agp_location(dev_priv, temp);
950 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
951 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
952 RS480_VA_SIZE_32MB));
955 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
956 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
961 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
962 RS480_GART_CACHE_INVALIDATE);
965 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
966 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
971 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
973 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
977 /* Enable or disable IGP GART on the chip */
978 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
984 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
985 dev_priv->gart_vm_start,
986 (long)dev_priv->gart_info.bus_addr,
987 dev_priv->gart_size);
989 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
990 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
992 for (i = 0; i < 19; i++)
993 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
994 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
995 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
996 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
997 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
998 RS600_ENABLE_FRAGMENT_PROCESSING |
999 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
1001 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
1002 RS600_PAGE_TABLE_TYPE_FLAT));
1004 /* disable all other contexts */
1005 for (i = 1; i < 8; i++)
1006 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
1008 /* setup the page table aperture */
1009 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
1010 dev_priv->gart_info.bus_addr);
1011 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
1012 dev_priv->gart_vm_start);
1013 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
1014 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1015 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
1017 /* setup the system aperture */
1018 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
1019 dev_priv->gart_vm_start);
1020 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
1021 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1023 /* enable page tables */
1024 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1025 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1027 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1028 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1030 /* invalidate the cache */
1031 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1033 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1034 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1035 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1037 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1038 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1039 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1041 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1042 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1043 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1046 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1047 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1048 temp &= ~RS600_ENABLE_PAGE_TABLES;
1049 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1053 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1055 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1058 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1059 dev_priv->gart_vm_start,
1060 (long)dev_priv->gart_info.bus_addr,
1061 dev_priv->gart_size);
1062 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1063 dev_priv->gart_vm_start);
1064 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1065 dev_priv->gart_info.bus_addr);
1066 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1067 dev_priv->gart_vm_start);
1068 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1069 dev_priv->gart_vm_start +
1070 dev_priv->gart_size - 1);
1072 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1074 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1075 RADEON_PCIE_TX_GART_EN);
1077 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1078 tmp & ~RADEON_PCIE_TX_GART_EN);
1082 /* Enable or disable PCI GART on the chip */
1083 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1087 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1088 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1089 (dev_priv->flags & RADEON_IS_IGPGART)) {
1090 radeon_set_igpgart(dev_priv, on);
1094 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1095 rs600_set_igpgart(dev_priv, on);
1099 if (dev_priv->flags & RADEON_IS_PCIE) {
1100 radeon_set_pciegart(dev_priv, on);
1104 tmp = RADEON_READ(RADEON_AIC_CNTL);
1107 RADEON_WRITE(RADEON_AIC_CNTL,
1108 tmp | RADEON_PCIGART_TRANSLATE_EN);
1110 /* set PCI GART page-table base address
1112 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1114 /* set address range for PCI address translate
1116 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1117 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1118 + dev_priv->gart_size - 1);
1120 /* Turn off AGP aperture -- is this required for PCI GART?
1122 radeon_write_agp_location(dev_priv, 0xffffffc0);
1123 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1125 RADEON_WRITE(RADEON_AIC_CNTL,
1126 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1130 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1132 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1133 struct radeon_virt_surface *vp;
1136 for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1137 if (!dev_priv->virt_surfaces[i].file_priv ||
1138 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1141 if (i >= 2 * RADEON_MAX_SURFACES)
1143 vp = &dev_priv->virt_surfaces[i];
1145 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1146 struct radeon_surface *sp = &dev_priv->surfaces[i];
1150 vp->surface_index = i;
1151 vp->lower = gart_info->bus_addr;
1152 vp->upper = vp->lower + gart_info->table_size;
1154 vp->file_priv = PCIGART_FILE_PRIV;
1157 sp->lower = vp->lower;
1158 sp->upper = vp->upper;
1161 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1162 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1163 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1170 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1171 struct drm_file *file_priv)
1173 drm_radeon_private_t *dev_priv = dev->dev_private;
1174 struct drm_radeon_master_private *master_priv = file_priv->masterp->driver_priv;
1178 /* if we require new memory map but we don't have it fail */
1179 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1180 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1181 radeon_do_cleanup_cp(dev);
1185 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1186 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1187 dev_priv->flags &= ~RADEON_IS_AGP;
1188 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1190 DRM_DEBUG("Restoring AGP flag\n");
1191 dev_priv->flags |= RADEON_IS_AGP;
1194 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1195 DRM_ERROR("PCI GART memory not allocated!\n");
1196 radeon_do_cleanup_cp(dev);
1200 dev_priv->usec_timeout = init->usec_timeout;
1201 if (dev_priv->usec_timeout < 1 ||
1202 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1203 DRM_DEBUG("TIMEOUT problem!\n");
1204 radeon_do_cleanup_cp(dev);
1208 /* Enable vblank on CRTC1 for older X servers
1210 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1212 switch(init->func) {
1213 case RADEON_INIT_R200_CP:
1214 dev_priv->microcode_version = UCODE_R200;
1216 case RADEON_INIT_R300_CP:
1217 dev_priv->microcode_version = UCODE_R300;
1220 dev_priv->microcode_version = UCODE_R100;
1223 dev_priv->do_boxes = 0;
1224 dev_priv->cp_mode = init->cp_mode;
1226 /* We don't support anything other than bus-mastering ring mode,
1227 * but the ring can be in either AGP or PCI space for the ring
1230 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1231 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1232 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1233 radeon_do_cleanup_cp(dev);
1237 switch (init->fb_bpp) {
1239 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1243 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1246 dev_priv->front_offset = init->front_offset;
1247 dev_priv->front_pitch = init->front_pitch;
1248 dev_priv->back_offset = init->back_offset;
1249 dev_priv->back_pitch = init->back_pitch;
1251 switch (init->depth_bpp) {
1253 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1257 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1260 dev_priv->depth_offset = init->depth_offset;
1261 dev_priv->depth_pitch = init->depth_pitch;
1263 /* Hardware state for depth clears. Remove this if/when we no
1264 * longer clear the depth buffer with a 3D rectangle. Hard-code
1265 * all values to prevent unwanted 3D state from slipping through
1266 * and screwing with the clear operation.
1268 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1269 (dev_priv->color_fmt << 10) |
1270 (dev_priv->microcode_version ==
1271 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1273 dev_priv->depth_clear.rb3d_zstencilcntl =
1274 (dev_priv->depth_fmt |
1275 RADEON_Z_TEST_ALWAYS |
1276 RADEON_STENCIL_TEST_ALWAYS |
1277 RADEON_STENCIL_S_FAIL_REPLACE |
1278 RADEON_STENCIL_ZPASS_REPLACE |
1279 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1281 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1282 RADEON_BFACE_SOLID |
1283 RADEON_FFACE_SOLID |
1284 RADEON_FLAT_SHADE_VTX_LAST |
1285 RADEON_DIFFUSE_SHADE_FLAT |
1286 RADEON_ALPHA_SHADE_FLAT |
1287 RADEON_SPECULAR_SHADE_FLAT |
1288 RADEON_FOG_SHADE_FLAT |
1289 RADEON_VTX_PIX_CENTER_OGL |
1290 RADEON_ROUND_MODE_TRUNC |
1291 RADEON_ROUND_PREC_8TH_PIX);
1294 dev_priv->ring_offset = init->ring_offset;
1295 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1296 dev_priv->buffers_offset = init->buffers_offset;
1297 dev_priv->gart_textures_offset = init->gart_textures_offset;
1299 master_priv->sarea = drm_legacy_getsarea(dev);
1300 if (!master_priv->sarea) {
1301 DRM_ERROR("could not find sarea!\n");
1302 radeon_do_cleanup_cp(dev);
1306 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1307 if (!dev_priv->cp_ring) {
1308 DRM_ERROR("could not find cp ring region!\n");
1309 radeon_do_cleanup_cp(dev);
1312 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1313 if (!dev_priv->ring_rptr) {
1314 DRM_ERROR("could not find ring read pointer!\n");
1315 radeon_do_cleanup_cp(dev);
1318 dev->agp_buffer_token = init->buffers_offset;
1319 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1320 if (!dev->agp_buffer_map) {
1321 DRM_ERROR("could not find dma buffer region!\n");
1322 radeon_do_cleanup_cp(dev);
1326 if (init->gart_textures_offset) {
1327 dev_priv->gart_textures =
1328 drm_core_findmap(dev, init->gart_textures_offset);
1329 if (!dev_priv->gart_textures) {
1330 DRM_ERROR("could not find GART texture region!\n");
1331 radeon_do_cleanup_cp(dev);
1337 if (dev_priv->flags & RADEON_IS_AGP) {
1338 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1339 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1340 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1341 if (!dev_priv->cp_ring->handle ||
1342 !dev_priv->ring_rptr->handle ||
1343 !dev->agp_buffer_map->handle) {
1344 DRM_ERROR("could not find ioremap agp regions!\n");
1345 radeon_do_cleanup_cp(dev);
1351 dev_priv->cp_ring->handle =
1352 (void *)(unsigned long)dev_priv->cp_ring->offset;
1353 dev_priv->ring_rptr->handle =
1354 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1355 dev->agp_buffer_map->handle =
1356 (void *)(unsigned long)dev->agp_buffer_map->offset;
1358 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1359 dev_priv->cp_ring->handle);
1360 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1361 dev_priv->ring_rptr->handle);
1362 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1363 dev->agp_buffer_map->handle);
1366 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1368 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1369 - dev_priv->fb_location;
1371 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1372 ((dev_priv->front_offset
1373 + dev_priv->fb_location) >> 10));
1375 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1376 ((dev_priv->back_offset
1377 + dev_priv->fb_location) >> 10));
1379 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1380 ((dev_priv->depth_offset
1381 + dev_priv->fb_location) >> 10));
1383 dev_priv->gart_size = init->gart_size;
1385 /* New let's set the memory map ... */
1386 if (dev_priv->new_memmap) {
1389 DRM_INFO("Setting GART location based on new memory map\n");
1391 /* If using AGP, try to locate the AGP aperture at the same
1392 * location in the card and on the bus, though we have to
1396 if (dev_priv->flags & RADEON_IS_AGP) {
1397 base = dev->agp->base;
1398 /* Check if valid */
1399 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1400 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1401 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1407 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1409 base = dev_priv->fb_location + dev_priv->fb_size;
1410 if (base < dev_priv->fb_location ||
1411 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1412 base = dev_priv->fb_location
1413 - dev_priv->gart_size;
1415 dev_priv->gart_vm_start = base & 0xffc00000u;
1416 if (dev_priv->gart_vm_start != base)
1417 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1418 base, dev_priv->gart_vm_start);
1420 DRM_INFO("Setting GART location based on old memory map\n");
1421 dev_priv->gart_vm_start = dev_priv->fb_location +
1422 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1426 if (dev_priv->flags & RADEON_IS_AGP)
1427 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1429 + dev_priv->gart_vm_start);
1432 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1433 - (unsigned long)dev->sg->vaddr
1434 + dev_priv->gart_vm_start);
1436 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1437 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1438 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1439 dev_priv->gart_buffers_offset);
1441 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1442 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1443 + init->ring_size / sizeof(u32));
1444 dev_priv->ring.size = init->ring_size;
1445 dev_priv->ring.size_l2qw = order_base_2(init->ring_size / 8);
1447 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1448 dev_priv->ring.rptr_update_l2qw = order_base_2( /* init->rptr_update */ 4096 / 8);
1450 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1451 dev_priv->ring.fetch_size_l2ow = order_base_2( /* init->fetch_size */ 32 / 16);
1452 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1454 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1457 if (dev_priv->flags & RADEON_IS_AGP) {
1458 /* Turn off PCI GART */
1459 radeon_set_pcigart(dev_priv, 0);
1466 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1467 /* if we have an offset set from userspace */
1468 if (dev_priv->pcigart_offset_set) {
1469 dev_priv->gart_info.bus_addr =
1470 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1471 dev_priv->gart_info.mapping.offset =
1472 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1473 dev_priv->gart_info.mapping.size =
1474 dev_priv->gart_info.table_size;
1476 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1477 dev_priv->gart_info.addr =
1478 dev_priv->gart_info.mapping.handle;
1480 if (dev_priv->flags & RADEON_IS_PCIE)
1481 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1483 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1484 dev_priv->gart_info.gart_table_location =
1487 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1488 dev_priv->gart_info.addr,
1489 dev_priv->pcigart_offset);
1491 if (dev_priv->flags & RADEON_IS_IGPGART)
1492 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1494 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1495 dev_priv->gart_info.gart_table_location =
1497 dev_priv->gart_info.addr = NULL;
1498 dev_priv->gart_info.bus_addr = 0;
1499 if (dev_priv->flags & RADEON_IS_PCIE) {
1501 ("Cannot use PCI Express without GART in FB memory\n");
1502 radeon_do_cleanup_cp(dev);
1507 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1508 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1509 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1510 ret = r600_page_table_init(dev);
1512 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1513 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1516 DRM_ERROR("failed to init PCI GART!\n");
1517 radeon_do_cleanup_cp(dev);
1521 ret = radeon_setup_pcigart_surface(dev_priv);
1523 DRM_ERROR("failed to setup GART surface!\n");
1524 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1525 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1527 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1528 radeon_do_cleanup_cp(dev);
1532 /* Turn on PCI GART */
1533 radeon_set_pcigart(dev_priv, 1);
1536 if (!dev_priv->me_fw) {
1537 int err = radeon_cp_init_microcode(dev_priv);
1539 DRM_ERROR("Failed to load firmware!\n");
1540 radeon_do_cleanup_cp(dev);
1544 radeon_cp_load_microcode(dev_priv);
1545 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1547 dev_priv->last_buf = 0;
1549 radeon_do_engine_reset(dev);
1550 radeon_test_writeback(dev_priv);
1555 static int radeon_do_cleanup_cp(struct drm_device * dev)
1557 drm_radeon_private_t *dev_priv = dev->dev_private;
1560 /* Make sure interrupts are disabled here because the uninstall ioctl
1561 * may not have been called from userspace and after dev_private
1562 * is freed, it's too late.
1564 if (dev->irq_enabled)
1565 drm_irq_uninstall(dev);
1568 if (dev_priv->flags & RADEON_IS_AGP) {
1569 if (dev_priv->cp_ring != NULL) {
1570 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1571 dev_priv->cp_ring = NULL;
1573 if (dev_priv->ring_rptr != NULL) {
1574 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1575 dev_priv->ring_rptr = NULL;
1577 if (dev->agp_buffer_map != NULL) {
1578 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1579 dev->agp_buffer_map = NULL;
1585 if (dev_priv->gart_info.bus_addr) {
1586 /* Turn off PCI GART */
1587 radeon_set_pcigart(dev_priv, 0);
1588 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1589 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1591 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1592 DRM_ERROR("failed to cleanup PCI GART!\n");
1596 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1598 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1599 dev_priv->gart_info.addr = NULL;
1602 /* only clear to the start of flags */
1603 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1608 /* This code will reinit the Radeon CP hardware after a resume from disc.
1609 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1610 * here we make sure that all Radeon hardware initialisation is re-done without
1611 * affecting running applications.
1613 * Charl P. Botha <http://cpbotha.net>
1615 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1617 drm_radeon_private_t *dev_priv = dev->dev_private;
1620 DRM_ERROR("Called with no initialization\n");
1624 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1627 if (dev_priv->flags & RADEON_IS_AGP) {
1628 /* Turn off PCI GART */
1629 radeon_set_pcigart(dev_priv, 0);
1633 /* Turn on PCI GART */
1634 radeon_set_pcigart(dev_priv, 1);
1637 radeon_cp_load_microcode(dev_priv);
1638 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1640 dev_priv->have_z_offset = 0;
1641 radeon_do_engine_reset(dev);
1642 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1644 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1649 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1651 drm_radeon_private_t *dev_priv = dev->dev_private;
1652 drm_radeon_init_t *init = data;
1654 LOCK_TEST_WITH_RETURN(dev, file_priv);
1656 if (init->func == RADEON_INIT_R300_CP)
1657 r300_init_reg_flags(dev);
1659 switch (init->func) {
1660 case RADEON_INIT_CP:
1661 case RADEON_INIT_R200_CP:
1662 case RADEON_INIT_R300_CP:
1663 return radeon_do_init_cp(dev, init, file_priv);
1664 case RADEON_INIT_R600_CP:
1665 return r600_do_init_cp(dev, init, file_priv);
1667 case RADEON_CLEANUP_CP:
1668 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1669 return r600_do_cleanup_cp(dev);
1671 return radeon_do_cleanup_cp(dev);
1677 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1679 drm_radeon_private_t *dev_priv = dev->dev_private;
1682 LOCK_TEST_WITH_RETURN(dev, file_priv);
1684 if (dev_priv->cp_running) {
1685 DRM_DEBUG("while CP running\n");
1688 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1689 DRM_DEBUG("called with bogus CP mode (%d)\n",
1694 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1695 r600_do_cp_start(dev_priv);
1697 radeon_do_cp_start(dev_priv);
1702 /* Stop the CP. The engine must have been idled before calling this
1705 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1707 drm_radeon_private_t *dev_priv = dev->dev_private;
1708 drm_radeon_cp_stop_t *stop = data;
1712 LOCK_TEST_WITH_RETURN(dev, file_priv);
1714 if (!dev_priv->cp_running)
1717 /* Flush any pending CP commands. This ensures any outstanding
1718 * commands are exectuted by the engine before we turn it off.
1721 radeon_do_cp_flush(dev_priv);
1724 /* If we fail to make the engine go idle, we return an error
1725 * code so that the DRM ioctl wrapper can try again.
1728 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1729 ret = r600_do_cp_idle(dev_priv);
1731 ret = radeon_do_cp_idle(dev_priv);
1736 /* Finally, we can turn off the CP. If the engine isn't idle,
1737 * we will get some dropped triangles as they won't be fully
1738 * rendered before the CP is shut down.
1740 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1741 r600_do_cp_stop(dev_priv);
1743 radeon_do_cp_stop(dev_priv);
1745 /* Reset the engine */
1746 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1747 r600_do_engine_reset(dev);
1749 radeon_do_engine_reset(dev);
1754 void radeon_do_release(struct drm_device * dev)
1756 drm_radeon_private_t *dev_priv = dev->dev_private;
1760 if (dev_priv->cp_running) {
1762 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1763 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1764 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1768 tsleep(&ret, 0, "rdnrel", 1);
1772 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1773 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1777 tsleep(&ret, 0, "rdnrel", 1);
1781 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1782 r600_do_cp_stop(dev_priv);
1783 r600_do_engine_reset(dev);
1785 radeon_do_cp_stop(dev_priv);
1786 radeon_do_engine_reset(dev);
1790 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1791 /* Disable *all* interrupts */
1792 if (dev_priv->mmio) /* remove this after permanent addmaps */
1793 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1795 if (dev_priv->mmio) { /* remove all surfaces */
1796 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1797 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1798 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1800 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1806 /* Free memory heap structures */
1807 radeon_mem_takedown(&(dev_priv->gart_heap));
1808 radeon_mem_takedown(&(dev_priv->fb_heap));
1810 /* deallocate kernel resources */
1811 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1812 r600_do_cleanup_cp(dev);
1814 radeon_do_cleanup_cp(dev);
1815 release_firmware(dev_priv->me_fw);
1816 dev_priv->me_fw = NULL;
1817 release_firmware(dev_priv->pfp_fw);
1818 dev_priv->pfp_fw = NULL;
1822 /* Just reset the CP ring. Called as part of an X Server engine reset.
1824 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1826 drm_radeon_private_t *dev_priv = dev->dev_private;
1829 LOCK_TEST_WITH_RETURN(dev, file_priv);
1832 DRM_DEBUG("called before init done\n");
1836 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1837 r600_do_cp_reset(dev_priv);
1839 radeon_do_cp_reset(dev_priv);
1841 /* The CP is no longer running after an engine reset */
1842 dev_priv->cp_running = 0;
1847 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1849 drm_radeon_private_t *dev_priv = dev->dev_private;
1852 LOCK_TEST_WITH_RETURN(dev, file_priv);
1854 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1855 return r600_do_cp_idle(dev_priv);
1857 return radeon_do_cp_idle(dev_priv);
1860 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1862 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1864 drm_radeon_private_t *dev_priv = dev->dev_private;
1867 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1868 return r600_do_resume_cp(dev, file_priv);
1870 return radeon_do_resume_cp(dev, file_priv);
1873 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1875 drm_radeon_private_t *dev_priv = dev->dev_private;
1878 LOCK_TEST_WITH_RETURN(dev, file_priv);
1880 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1881 return r600_do_engine_reset(dev);
1883 return radeon_do_engine_reset(dev);
1886 /* ================================================================
1890 /* KW: Deprecated to say the least:
1892 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1897 /* ================================================================
1898 * Freelist management
1901 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1902 * bufs until freelist code is used. Note this hides a problem with
1903 * the scratch register * (used to keep track of last buffer
1904 * completed) being written to before * the last buffer has actually
1905 * completed rendering.
1907 * KW: It's also a good way to find free buffers quickly.
1909 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1910 * sleep. However, bugs in older versions of radeon_accel.c mean that
1911 * we essentially have to do this, else old clients will break.
1913 * However, it does leave open a potential deadlock where all the
1914 * buffers are held by other clients, which can't release them because
1915 * they can't get the lock.
1918 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1920 struct drm_device_dma *dma = dev->dma;
1921 drm_radeon_private_t *dev_priv = dev->dev_private;
1922 drm_radeon_buf_priv_t *buf_priv;
1923 struct drm_buf *buf;
1927 if (++dev_priv->last_buf >= dma->buf_count)
1928 dev_priv->last_buf = 0;
1930 start = dev_priv->last_buf;
1932 for (t = 0; t < dev_priv->usec_timeout; t++) {
1933 u32 done_age = GET_SCRATCH(dev_priv, 1);
1934 DRM_DEBUG("done_age = %d\n", done_age);
1935 for (i = 0; i < dma->buf_count; i++) {
1936 buf = dma->buflist[start];
1937 buf_priv = buf->dev_private;
1938 if (buf->file_priv == NULL || (buf->pending &&
1941 dev_priv->stats.requested_bufs++;
1945 if (++start >= dma->buf_count)
1951 dev_priv->stats.freelist_loops++;
1958 void radeon_freelist_reset(struct drm_device * dev)
1960 struct drm_device_dma *dma = dev->dma;
1961 drm_radeon_private_t *dev_priv = dev->dev_private;
1964 dev_priv->last_buf = 0;
1965 for (i = 0; i < dma->buf_count; i++) {
1966 struct drm_buf *buf = dma->buflist[i];
1967 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1972 /* ================================================================
1973 * CP command submission
1976 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1978 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1980 u32 last_head = GET_RING_HEAD(dev_priv);
1982 for (i = 0; i < dev_priv->usec_timeout; i++) {
1983 u32 head = GET_RING_HEAD(dev_priv);
1985 ring->space = (head - ring->tail) * sizeof(u32);
1986 if (ring->space <= 0)
1987 ring->space += ring->size;
1988 if (ring->space > n)
1991 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1993 if (head != last_head)
2000 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2001 #if RADEON_FIFO_DEBUG
2002 radeon_status(dev_priv);
2003 DRM_ERROR("failed!\n");
2008 static int radeon_cp_get_buffers(struct drm_device *dev,
2009 struct drm_file *file_priv,
2013 struct drm_buf *buf;
2015 for (i = d->granted_count; i < d->request_count; i++) {
2016 buf = radeon_freelist_get(dev);
2018 return -EBUSY; /* NOTE: broken client */
2020 buf->file_priv = file_priv;
2022 if (copy_to_user(&d->request_indices[i], &buf->idx,
2025 if (copy_to_user(&d->request_sizes[i], &buf->total,
2026 sizeof(buf->total)))
2034 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2036 struct drm_device_dma *dma = dev->dma;
2038 struct drm_dma *d = data;
2040 LOCK_TEST_WITH_RETURN(dev, file_priv);
2042 /* Please don't send us buffers.
2044 if (d->send_count != 0) {
2045 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2046 DRM_CURRENTPID, d->send_count);
2050 /* We'll send you buffers.
2052 if (d->request_count < 0 || d->request_count > dma->buf_count) {
2053 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2054 DRM_CURRENTPID, d->request_count, dma->buf_count);
2058 d->granted_count = 0;
2060 if (d->request_count) {
2061 ret = radeon_cp_get_buffers(dev, file_priv, d);
2067 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2069 drm_radeon_private_t *dev_priv;
2072 dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL);
2073 if (dev_priv == NULL)
2076 dev->dev_private = (void *)dev_priv;
2077 dev_priv->flags = flags;
2079 switch (flags & RADEON_FAMILY_MASK) {
2092 dev_priv->flags |= RADEON_HAS_HIERZ;
2095 /* all other chips have no hierarchical z buffer */
2099 pci_enable_busmaster(dev->pdev->dev);
2101 if (drm_device_is_agp(dev))
2102 dev_priv->flags |= RADEON_IS_AGP;
2103 else if (drm_device_is_pcie(dev))
2104 dev_priv->flags |= RADEON_IS_PCIE;
2106 dev_priv->flags |= RADEON_IS_PCI;
2108 ret = drm_legacy_addmap(dev, pci_resource_start(dev->pdev, 2),
2109 pci_resource_len(dev->pdev, 2), _DRM_REGISTERS,
2110 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2114 ret = drm_vblank_init(dev, 2);
2116 radeon_driver_unload(dev);
2120 DRM_DEBUG("%s card detected\n",
2121 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2125 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2127 struct drm_radeon_master_private *master_priv;
2128 unsigned long sareapage;
2131 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
2135 /* prebuild the SAREA */
2136 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2137 ret = drm_legacy_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2138 &master_priv->sarea);
2140 DRM_ERROR("SAREA setup failed\n");
2144 master_priv->sarea_priv = (drm_radeon_sarea_t *)((char *)master_priv->sarea->handle) +
2145 sizeof(struct drm_sarea);
2146 master_priv->sarea_priv->pfCurrentPage = 0;
2148 master->driver_priv = master_priv;
2152 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2154 struct drm_radeon_master_private *master_priv = master->driver_priv;
2159 if (master_priv->sarea_priv &&
2160 master_priv->sarea_priv->pfCurrentPage != 0)
2161 radeon_cp_dispatch_flip(dev, master);
2163 master_priv->sarea_priv = NULL;
2164 if (master_priv->sarea)
2166 drm_legacy_rmmap_locked(dev, master_priv->sarea);
2168 drm_legacy_rmmap(dev, master_priv->sarea);
2173 master->driver_priv = NULL;
2176 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2177 * have to find them.
2179 int radeon_driver_firstopen(struct drm_device *dev)
2182 drm_local_map_t *map;
2183 drm_radeon_private_t *dev_priv = dev->dev_private;
2185 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2187 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2188 ret = drm_legacy_addmap(dev, dev_priv->fb_aper_offset,
2189 pci_resource_len(dev->pdev, 0),
2190 _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING, &map);
2197 int radeon_driver_unload(struct drm_device *dev)
2199 drm_radeon_private_t *dev_priv = dev->dev_private;
2203 drm_legacy_rmmap(dev, dev_priv->mmio);
2207 dev->dev_private = NULL;
2211 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2217 /* check if the ring is padded out to 16-dword alignment */
2219 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2221 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2223 ring = dev_priv->ring.start;
2224 /* pad with some CP_PACKET2 */
2225 for (i = 0; i < num_p2; i++)
2226 ring[dev_priv->ring.tail + i] = CP_PACKET2();
2228 dev_priv->ring.tail += i;
2230 dev_priv->ring.space -= num_p2 * sizeof(u32);
2233 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2236 GET_RING_HEAD( dev_priv );
2238 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2239 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2240 /* read from PCI bus to ensure correct posting */
2241 RADEON_READ(R600_CP_RB_RPTR);
2243 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2244 /* read from PCI bus to ensure correct posting */
2245 RADEON_READ(RADEON_CP_RB_RPTR);