2 * Copyright (c) 1997, 1998, 1999, 2000
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_skreg.h,v 1.8.2.1 2000/04/27 14:48:07 wpaul Exp $
33 * $DragonFly: src/sys/dev/netif/sk/if_skreg.h,v 1.2 2003/06/17 04:28:57 dillon Exp $
37 * SysKonnect PCI vendor ID
39 #define SK_VENDORID 0x1148
42 * SK-NET gigabit ethernet device ID
44 #define SK_DEVICEID_GE 0x4300
47 * GEnesis registers. The GEnesis chip has a 256-byte I/O window
48 * but internally it has a 16K register space. This 16K space is
49 * divided into 128-byte blocks. The first 128 bytes of the I/O
50 * window represent the first block, which is permanently mapped
51 * at the start of the window. The other 127 blocks can be mapped
52 * to the second 128 bytes of the I/O window by setting the desired
53 * block value in the RAP register in block 0. Not all of the 127
54 * blocks are actually used. Most registers are 32 bits wide, but
55 * there are a few 16-bit and 8-bit ones as well.
59 /* Start of remappable register window. */
60 #define SK_WIN_BASE 0x0080
62 /* Size of a window */
63 #define SK_WIN_LEN 0x80
65 #define SK_WIN_MASK 0x3F80
66 #define SK_REG_MASK 0x7F
68 /* Compute the window of a given register (for the RAP register) */
69 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN)
71 /* Compute the relative offset of a register within the window */
72 #define SK_REG(reg) ((reg) & SK_REG_MASK)
78 * Compute offset of port-specific register. Since there are two
79 * ports, there are two of some GEnesis modules (e.g. two sets of
80 * DMA queues, two sets of FIFO control registers, etc...). Normally,
81 * the block for port 0 is at offset 0x0 and the block for port 1 is
82 * at offset 0x80 (i.e. the next page over). However for the transmit
83 * BMUs and RAMbuffers, there are two blocks for each port: one for
84 * the sync transmit queue and one for the async queue (which we don't
85 * use). However instead of ordering them like this:
86 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2
87 * SysKonnect has instead ordered them like this:
88 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2
89 * This means that when referencing the TX BMU and RAMbuffer registers,
90 * we have to double the block offset (0x80 * 2) in order to reach the
91 * second queue. This prevents us from using the same formula
92 * (sk_port * 0x80) to compute the offsets for all of the port-specific
93 * blocks: we need an extra offset for the BMU and RAMbuffer registers.
94 * The simplest thing is to provide an extra argument to these macros:
95 * the 'skip' parameter. The 'skip' value is the number of extra pages
96 * for skip when computing the port0/port1 offsets. For most registers,
97 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1.
99 #define SK_IF_READ_4(sc_if, skip, reg) \
100 sk_win_read_4(sc_if->sk_softc, reg + \
101 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
102 #define SK_IF_READ_2(sc_if, skip, reg) \
103 sk_win_read_2(sc_if->sk_softc, reg + \
104 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
105 #define SK_IF_READ_1(sc_if, skip, reg) \
106 sk_win_read_1(sc_if->sk_softc, reg + \
107 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
109 #define SK_IF_WRITE_4(sc_if, skip, reg, val) \
110 sk_win_write_4(sc_if->sk_softc, \
111 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
112 #define SK_IF_WRITE_2(sc_if, skip, reg, val) \
113 sk_win_write_2(sc_if->sk_softc, \
114 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
115 #define SK_IF_WRITE_1(sc_if, skip, reg, val) \
116 sk_win_write_1(sc_if->sk_softc, \
117 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
119 /* Block 0 registers, permanently mapped at iobase. */
120 #define SK_RAP 0x0000
121 #define SK_CSR 0x0004
122 #define SK_LED 0x0006
123 #define SK_ISR 0x0008 /* interrupt source */
124 #define SK_IMR 0x000C /* interrupt mask */
125 #define SK_IESR 0x0010 /* interrupt hardware error source */
126 #define SK_IEMR 0x0014 /* interrupt hardware error mask */
127 #define SK_ISSR 0x0018 /* special interrupt source */
128 #define SK_XM_IMR0 0x0020
129 #define SK_XM_ISR0 0x0028
130 #define SK_XM_PHYADDR0 0x0030
131 #define SK_XM_PHYDATA0 0x0034
132 #define SK_XM_IMR1 0x0040
133 #define SK_XM_ISR1 0x0048
134 #define SK_XM_PHYADDR1 0x0050
135 #define SK_XM_PHYDATA1 0x0054
136 #define SK_BMU_RX_CSR0 0x0060
137 #define SK_BMU_RX_CSR1 0x0064
138 #define SK_BMU_TXS_CSR0 0x0068
139 #define SK_BMU_TXA_CSR0 0x006C
140 #define SK_BMU_TXS_CSR1 0x0070
141 #define SK_BMU_TXA_CSR1 0x0074
143 /* SK_CSR register */
144 #define SK_CSR_SW_RESET 0x0001
145 #define SK_CSR_SW_UNRESET 0x0002
146 #define SK_CSR_MASTER_RESET 0x0004
147 #define SK_CSR_MASTER_UNRESET 0x0008
148 #define SK_CSR_MASTER_STOP 0x0010
149 #define SK_CSR_MASTER_DONE 0x0020
150 #define SK_CSR_SW_IRQ_CLEAR 0x0040
151 #define SK_CSR_SW_IRQ_SET 0x0080
152 #define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */
153 #define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */
155 /* SK_LED register */
156 #define SK_LED_GREEN_OFF 0x01
157 #define SK_LED_GREEN_ON 0x02
159 /* SK_ISR register */
160 #define SK_ISR_TX2_AS_CHECK 0x00000001
161 #define SK_ISR_TX2_AS_EOF 0x00000002
162 #define SK_ISR_TX2_AS_EOB 0x00000004
163 #define SK_ISR_TX2_S_CHECK 0x00000008
164 #define SK_ISR_TX2_S_EOF 0x00000010
165 #define SK_ISR_TX2_S_EOB 0x00000020
166 #define SK_ISR_TX1_AS_CHECK 0x00000040
167 #define SK_ISR_TX1_AS_EOF 0x00000080
168 #define SK_ISR_TX1_AS_EOB 0x00000100
169 #define SK_ISR_TX1_S_CHECK 0x00000200
170 #define SK_ISR_TX1_S_EOF 0x00000400
171 #define SK_ISR_TX1_S_EOB 0x00000800
172 #define SK_ISR_RX2_CHECK 0x00001000
173 #define SK_ISR_RX2_EOF 0x00002000
174 #define SK_ISR_RX2_EOB 0x00004000
175 #define SK_ISR_RX1_CHECK 0x00008000
176 #define SK_ISR_RX1_EOF 0x00010000
177 #define SK_ISR_RX1_EOB 0x00020000
178 #define SK_ISR_LINK2_OFLOW 0x00040000
179 #define SK_ISR_MAC2 0x00080000
180 #define SK_ISR_LINK1_OFLOW 0x00100000
181 #define SK_ISR_MAC1 0x00200000
182 #define SK_ISR_TIMER 0x00400000
183 #define SK_ISR_EXTERNAL_REG 0x00800000
184 #define SK_ISR_SW 0x01000000
185 #define SK_ISR_I2C_RDY 0x02000000
186 #define SK_ISR_TX2_TIMEO 0x04000000
187 #define SK_ISR_TX1_TIMEO 0x08000000
188 #define SK_ISR_RX2_TIMEO 0x10000000
189 #define SK_ISR_RX1_TIMEO 0x20000000
190 #define SK_ISR_RSVD 0x40000000
191 #define SK_ISR_HWERR 0x80000000
193 /* SK_IMR register */
194 #define SK_IMR_TX2_AS_CHECK 0x00000001
195 #define SK_IMR_TX2_AS_EOF 0x00000002
196 #define SK_IMR_TX2_AS_EOB 0x00000004
197 #define SK_IMR_TX2_S_CHECK 0x00000008
198 #define SK_IMR_TX2_S_EOF 0x00000010
199 #define SK_IMR_TX2_S_EOB 0x00000020
200 #define SK_IMR_TX1_AS_CHECK 0x00000040
201 #define SK_IMR_TX1_AS_EOF 0x00000080
202 #define SK_IMR_TX1_AS_EOB 0x00000100
203 #define SK_IMR_TX1_S_CHECK 0x00000200
204 #define SK_IMR_TX1_S_EOF 0x00000400
205 #define SK_IMR_TX1_S_EOB 0x00000800
206 #define SK_IMR_RX2_CHECK 0x00001000
207 #define SK_IMR_RX2_EOF 0x00002000
208 #define SK_IMR_RX2_EOB 0x00004000
209 #define SK_IMR_RX1_CHECK 0x00008000
210 #define SK_IMR_RX1_EOF 0x00010000
211 #define SK_IMR_RX1_EOB 0x00020000
212 #define SK_IMR_LINK2_OFLOW 0x00040000
213 #define SK_IMR_MAC2 0x00080000
214 #define SK_IMR_LINK1_OFLOW 0x00100000
215 #define SK_IMR_MAC1 0x00200000
216 #define SK_IMR_TIMER 0x00400000
217 #define SK_IMR_EXTERNAL_REG 0x00800000
218 #define SK_IMR_SW 0x01000000
219 #define SK_IMR_I2C_RDY 0x02000000
220 #define SK_IMR_TX2_TIMEO 0x04000000
221 #define SK_IMR_TX1_TIMEO 0x08000000
222 #define SK_IMR_RX2_TIMEO 0x10000000
223 #define SK_IMR_RX1_TIMEO 0x20000000
224 #define SK_IMR_RSVD 0x40000000
225 #define SK_IMR_HWERR 0x80000000
228 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1)
231 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2)
233 /* SK_IESR register */
234 #define SK_IESR_PAR_RX2 0x00000001
235 #define SK_IESR_PAR_RX1 0x00000002
236 #define SK_IESR_PAR_MAC2 0x00000004
237 #define SK_IESR_PAR_MAC1 0x00000008
238 #define SK_IESR_PAR_WR_RAM 0x00000010
239 #define SK_IESR_PAR_RD_RAM 0x00000020
240 #define SK_IESR_NO_TSTAMP_MAC2 0x00000040
241 #define SK_IESR_NO_TSTAMO_MAC1 0x00000080
242 #define SK_IESR_NO_STS_MAC2 0x00000100
243 #define SK_IESR_NO_STS_MAC1 0x00000200
244 #define SK_IESR_IRQ_STS 0x00000400
245 #define SK_IESR_MASTERERR 0x00000800
247 /* SK_IEMR register */
248 #define SK_IEMR_PAR_RX2 0x00000001
249 #define SK_IEMR_PAR_RX1 0x00000002
250 #define SK_IEMR_PAR_MAC2 0x00000004
251 #define SK_IEMR_PAR_MAC1 0x00000008
252 #define SK_IEMR_PAR_WR_RAM 0x00000010
253 #define SK_IEMR_PAR_RD_RAM 0x00000020
254 #define SK_IEMR_NO_TSTAMP_MAC2 0x00000040
255 #define SK_IEMR_NO_TSTAMO_MAC1 0x00000080
256 #define SK_IEMR_NO_STS_MAC2 0x00000100
257 #define SK_IEMR_NO_STS_MAC1 0x00000200
258 #define SK_IEMR_IRQ_STS 0x00000400
259 #define SK_IEMR_MASTERERR 0x00000800
262 #define SK_MAC0_0 0x0100
263 #define SK_MAC0_1 0x0104
264 #define SK_MAC1_0 0x0108
265 #define SK_MAC1_1 0x010C
266 #define SK_MAC2_0 0x0110
267 #define SK_MAC2_1 0x0114
268 #define SK_CONNTYPE 0x0118
269 #define SK_PMDTYPE 0x0119
270 #define SK_CONFIG 0x011A
271 #define SK_CHIPVER 0x011B
272 #define SK_EPROM0 0x011C
273 #define SK_EPROM1 0x011D
274 #define SK_EPROM2 0x011E
275 #define SK_EPROM3 0x011F
276 #define SK_EP_ADDR 0x0120
277 #define SK_EP_DATA 0x0124
278 #define SK_EP_LOADCTL 0x0128
279 #define SK_EP_LOADTST 0x0129
280 #define SK_TIMERINIT 0x0130
281 #define SK_TIMER 0x0134
282 #define SK_TIMERCTL 0x0138
283 #define SK_TIMERTST 0x0139
284 #define SK_IMTIMERINIT 0x0140
285 #define SK_IMTIMER 0x0144
286 #define SK_IMTIMERCTL 0x0148
287 #define SK_IMTIMERTST 0x0149
288 #define SK_IMMR 0x014C
289 #define SK_IHWEMR 0x0150
290 #define SK_TESTCTL1 0x0158
291 #define SK_TESTCTL2 0x0159
292 #define SK_GPIO 0x015C
293 #define SK_I2CHWCTL 0x0160
294 #define SK_I2CHWDATA 0x0164
295 #define SK_I2CHWIRQ 0x0168
296 #define SK_I2CSW 0x016C
297 #define SK_BLNKINIT 0x0170
298 #define SK_BLNKCOUNT 0x0174
299 #define SK_BLNKCTL 0x0178
300 #define SK_BLNKSTS 0x0179
301 #define SK_BLNKTST 0x017A
303 #define SK_IMCTL_STOP 0x02
304 #define SK_IMCTL_START 0x04
306 #define SK_IMTIMER_TICKS 54
307 #define SK_IM_USECS(x) ((x) * SK_IMTIMER_TICKS)
310 * The SK_EPROM0 register contains a byte that describes the
311 * amount of SRAM mounted on the NIC. The value also tells if
312 * the chips are 64K or 128K. This affects the RAMbuffer address
313 * offset that we need to use.
315 #define SK_RAMSIZE_512K_64 0x1
316 #define SK_RAMSIZE_1024K_128 0x2
317 #define SK_RAMSIZE_1024K_64 0x3
318 #define SK_RAMSIZE_2048K_128 0x4
320 #define SK_RBOFF_0 0x0
321 #define SK_RBOFF_80000 0x80000
324 * SK_EEPROM1 contains the PHY type, which may be XMAC for
325 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom
328 #define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */
329 #define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */
330 #define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */
331 #define SK_PHYTYPE_NAT 3 /* National DP83891 */
336 #define SK_PHYADDR_XMAC 0x0
337 #define SK_PHYADDR_BCOM 0x1
338 #define SK_PHYADDR_LONE 0x3
339 #define SK_PHYADDR_NAT 0x0
341 #define SK_CONFIG_SINGLEMAC 0x01
342 #define SK_CONFIG_DIS_DSL_CLK 0x02
344 #define SK_PMD_1000BASELX 0x4C
345 #define SK_PMD_1000BASESX 0x53
346 #define SK_PMD_1000BASECX 0x43
347 #define SK_PMD_1000BASETX 0x54
350 #define SK_GPIO_DAT0 0x00000001
351 #define SK_GPIO_DAT1 0x00000002
352 #define SK_GPIO_DAT2 0x00000004
353 #define SK_GPIO_DAT3 0x00000008
354 #define SK_GPIO_DAT4 0x00000010
355 #define SK_GPIO_DAT5 0x00000020
356 #define SK_GPIO_DAT6 0x00000040
357 #define SK_GPIO_DAT7 0x00000080
358 #define SK_GPIO_DAT8 0x00000100
359 #define SK_GPIO_DAT9 0x00000200
360 #define SK_GPIO_DIR0 0x00010000
361 #define SK_GPIO_DIR1 0x00020000
362 #define SK_GPIO_DIR2 0x00040000
363 #define SK_GPIO_DIR3 0x00080000
364 #define SK_GPIO_DIR4 0x00100000
365 #define SK_GPIO_DIR5 0x00200000
366 #define SK_GPIO_DIR6 0x00400000
367 #define SK_GPIO_DIR7 0x00800000
368 #define SK_GPIO_DIR8 0x01000000
369 #define SK_GPIO_DIR9 0x02000000
371 /* Block 3 Ram interface and MAC arbiter registers */
372 #define SK_RAMADDR 0x0180
373 #define SK_RAMDATA0 0x0184
374 #define SK_RAMDATA1 0x0188
375 #define SK_TO0 0x0190
376 #define SK_TO1 0x0191
377 #define SK_TO2 0x0192
378 #define SK_TO3 0x0193
379 #define SK_TO4 0x0194
380 #define SK_TO5 0x0195
381 #define SK_TO6 0x0196
382 #define SK_TO7 0x0197
383 #define SK_TO8 0x0198
384 #define SK_TO9 0x0199
385 #define SK_TO10 0x019A
386 #define SK_TO11 0x019B
387 #define SK_RITIMEO_TMR 0x019C
388 #define SK_RAMCTL 0x01A0
389 #define SK_RITIMER_TST 0x01A2
391 #define SK_RAMCTL_RESET 0x0001
392 #define SK_RAMCTL_UNRESET 0x0002
393 #define SK_RAMCTL_CLR_IRQ_WPAR 0x0100
394 #define SK_RAMCTL_CLR_IRQ_RPAR 0x0200
396 /* Mac arbiter registers */
397 #define SK_MINIT_RX1 0x01B0
398 #define SK_MINIT_RX2 0x01B1
399 #define SK_MINIT_TX1 0x01B2
400 #define SK_MINIT_TX2 0x01B3
401 #define SK_MTIMEO_RX1 0x01B4
402 #define SK_MTIMEO_RX2 0x01B5
403 #define SK_MTIMEO_TX1 0x01B6
404 #define SK_MTIEMO_TX2 0x01B7
405 #define SK_MACARB_CTL 0x01B8
406 #define SK_MTIMER_TST 0x01BA
407 #define SK_RCINIT_RX1 0x01C0
408 #define SK_RCINIT_RX2 0x01C1
409 #define SK_RCINIT_TX1 0x01C2
410 #define SK_RCINIT_TX2 0x01C3
411 #define SK_RCTIMEO_RX1 0x01C4
412 #define SK_RCTIMEO_RX2 0x01C5
413 #define SK_RCTIMEO_TX1 0x01C6
414 #define SK_RCTIMEO_TX2 0x01C7
415 #define SK_RECOVERY_CTL 0x01C8
416 #define SK_RCTIMER_TST 0x01CA
418 /* Packet arbiter registers */
419 #define SK_RXPA1_TINIT 0x01D0
420 #define SK_RXPA2_TINIT 0x01D4
421 #define SK_TXPA1_TINIT 0x01D8
422 #define SK_TXPA2_TINIT 0x01DC
423 #define SK_RXPA1_TIMEO 0x01E0
424 #define SK_RXPA2_TIMEO 0x01E4
425 #define SK_TXPA1_TIMEO 0x01E8
426 #define SK_TXPA2_TIMEO 0x01EC
427 #define SK_PKTARB_CTL 0x01F0
428 #define SK_PKTATB_TST 0x01F2
430 #define SK_PKTARB_TIMEOUT 0x2000
432 #define SK_PKTARBCTL_RESET 0x0001
433 #define SK_PKTARBCTL_UNRESET 0x0002
434 #define SK_PKTARBCTL_RXTO1_OFF 0x0004
435 #define SK_PKTARBCTL_RXTO1_ON 0x0008
436 #define SK_PKTARBCTL_RXTO2_OFF 0x0010
437 #define SK_PKTARBCTL_RXTO2_ON 0x0020
438 #define SK_PKTARBCTL_TXTO1_OFF 0x0040
439 #define SK_PKTARBCTL_TXTO1_ON 0x0080
440 #define SK_PKTARBCTL_TXTO2_OFF 0x0100
441 #define SK_PKTARBCTL_TXTO2_ON 0x0200
442 #define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400
443 #define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800
444 #define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000
445 #define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000
447 #define SK_MINIT_XMAC_B2 54
448 #define SK_MINIT_XMAC_C1 63
450 #define SK_MACARBCTL_RESET 0x0001
451 #define SK_MACARBCTL_UNRESET 0x0002
452 #define SK_MACARBCTL_FASTOE_OFF 0x0004
453 #define SK_MACARBCRL_FASTOE_ON 0x0008
455 #define SK_RCINIT_XMAC_B2 54
456 #define SK_RCINIT_XMAC_C1 0
458 #define SK_RECOVERYCTL_RX1_OFF 0x0001
459 #define SK_RECOVERYCTL_RX1_ON 0x0002
460 #define SK_RECOVERYCTL_RX2_OFF 0x0004
461 #define SK_RECOVERYCTL_RX2_ON 0x0008
462 #define SK_RECOVERYCTL_TX1_OFF 0x0010
463 #define SK_RECOVERYCTL_TX1_ON 0x0020
464 #define SK_RECOVERYCTL_TX2_OFF 0x0040
465 #define SK_RECOVERYCTL_TX2_ON 0x0080
467 #define SK_RECOVERY_XMAC_B2 \
468 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \
469 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON)
471 #define SK_RECOVERY_XMAC_C1 \
472 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \
473 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF)
475 /* Block 4 -- TX Arbiter MAC 1 */
476 #define SK_TXAR1_TIMERINIT 0x0200
477 #define SK_TXAR1_TIMERVAL 0x0204
478 #define SK_TXAR1_LIMITINIT 0x0208
479 #define SK_TXAR1_LIMITCNT 0x020C
480 #define SK_TXAR1_COUNTERCTL 0x0210
481 #define SK_TXAR1_COUNTERTST 0x0212
482 #define SK_TXAR1_COUNTERSTS 0x0212
484 /* Block 5 -- TX Arbiter MAC 2 */
485 #define SK_TXAR2_TIMERINIT 0x0280
486 #define SK_TXAR2_TIMERVAL 0x0284
487 #define SK_TXAR2_LIMITINIT 0x0288
488 #define SK_TXAR2_LIMITCNT 0x028C
489 #define SK_TXAR2_COUNTERCTL 0x0290
490 #define SK_TXAR2_COUNTERTST 0x0291
491 #define SK_TXAR2_COUNTERSTS 0x0292
493 #define SK_TXARCTL_OFF 0x01
494 #define SK_TXARCTL_ON 0x02
495 #define SK_TXARCTL_RATECTL_OFF 0x04
496 #define SK_TXARCTL_RATECTL_ON 0x08
497 #define SK_TXARCTL_ALLOC_OFF 0x10
498 #define SK_TXARCTL_ALLOC_ON 0x20
499 #define SK_TXARCTL_FSYNC_OFF 0x40
500 #define SK_TXARCTL_FSYNC_ON 0x80
502 /* Block 6 -- External registers */
503 #define SK_EXTREG_BASE 0x300
504 #define SK_EXTREG_END 0x37C
506 /* Block 7 -- PCI config registers */
507 #define SK_PCI_BASE 0x0380
508 #define SK_PCI_END 0x03FC
510 /* Compute offset of mirrored PCI register */
511 #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE)
513 /* Block 8 -- RX queue 1 */
514 #define SK_RXQ1_BUFCNT 0x0400
515 #define SK_RXQ1_BUFCTL 0x0402
516 #define SK_RXQ1_NEXTDESC 0x0404
517 #define SK_RXQ1_RXBUF_LO 0x0408
518 #define SK_RXQ1_RXBUF_HI 0x040C
519 #define SK_RXQ1_RXSTAT 0x0410
520 #define SK_RXQ1_TIMESTAMP 0x0414
521 #define SK_RXQ1_CSUM1 0x0418
522 #define SK_RXQ1_CSUM2 0x041A
523 #define SK_RXQ1_CSUM1_START 0x041C
524 #define SK_RXQ1_CSUM2_START 0x041E
525 #define SK_RXQ1_CURADDR_LO 0x0420
526 #define SK_RXQ1_CURADDR_HI 0x0424
527 #define SK_RXQ1_CURCNT_LO 0x0428
528 #define SK_RXQ1_CURCNT_HI 0x042C
529 #define SK_RXQ1_CURBYTES 0x0430
530 #define SK_RXQ1_BMU_CSR 0x0434
531 #define SK_RXQ1_WATERMARK 0x0438
532 #define SK_RXQ1_FLAG 0x043A
533 #define SK_RXQ1_TEST1 0x043C
534 #define SK_RXQ1_TEST2 0x0440
535 #define SK_RXQ1_TEST3 0x0444
537 /* Block 9 -- RX queue 2 */
538 #define SK_RXQ2_BUFCNT 0x0480
539 #define SK_RXQ2_BUFCTL 0x0482
540 #define SK_RXQ2_NEXTDESC 0x0484
541 #define SK_RXQ2_RXBUF_LO 0x0488
542 #define SK_RXQ2_RXBUF_HI 0x048C
543 #define SK_RXQ2_RXSTAT 0x0490
544 #define SK_RXQ2_TIMESTAMP 0x0494
545 #define SK_RXQ2_CSUM1 0x0498
546 #define SK_RXQ2_CSUM2 0x049A
547 #define SK_RXQ2_CSUM1_START 0x049C
548 #define SK_RXQ2_CSUM2_START 0x049E
549 #define SK_RXQ2_CURADDR_LO 0x04A0
550 #define SK_RXQ2_CURADDR_HI 0x04A4
551 #define SK_RXQ2_CURCNT_LO 0x04A8
552 #define SK_RXQ2_CURCNT_HI 0x04AC
553 #define SK_RXQ2_CURBYTES 0x04B0
554 #define SK_RXQ2_BMU_CSR 0x04B4
555 #define SK_RXQ2_WATERMARK 0x04B8
556 #define SK_RXQ2_FLAG 0x04BA
557 #define SK_RXQ2_TEST1 0x04BC
558 #define SK_RXQ2_TEST2 0x04C0
559 #define SK_RXQ2_TEST3 0x04C4
561 #define SK_RXBMU_CLR_IRQ_ERR 0x00000001
562 #define SK_RXBMU_CLR_IRQ_EOF 0x00000002
563 #define SK_RXBMU_CLR_IRQ_EOB 0x00000004
564 #define SK_RXBMU_CLR_IRQ_PAR 0x00000008
565 #define SK_RXBMU_RX_START 0x00000010
566 #define SK_RXBMU_RX_STOP 0x00000020
567 #define SK_RXBMU_POLL_OFF 0x00000040
568 #define SK_RXBMU_POLL_ON 0x00000080
569 #define SK_RXBMU_TRANSFER_SM_RESET 0x00000100
570 #define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200
571 #define SK_RXBMU_DESCWR_SM_RESET 0x00000400
572 #define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800
573 #define SK_RXBMU_DESCRD_SM_RESET 0x00001000
574 #define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000
575 #define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000
576 #define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000
577 #define SK_RXBMU_PFI_SM_RESET 0x00010000
578 #define SK_RXBMU_PFI_SM_UNRESET 0x00020000
579 #define SK_RXBMU_FIFO_RESET 0x00040000
580 #define SK_RXBMU_FIFO_UNRESET 0x00080000
581 #define SK_RXBMU_DESC_RESET 0x00100000
582 #define SK_RXBMU_DESC_UNRESET 0x00200000
583 #define SK_RXBMU_SUPERVISOR_IDLE 0x01000000
585 #define SK_RXBMU_ONLINE \
586 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \
587 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \
588 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \
589 SK_RXBMU_DESC_UNRESET)
591 #define SK_RXBMU_OFFLINE \
592 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \
593 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \
594 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \
597 /* Block 12 -- TX sync queue 1 */
598 #define SK_TXQS1_BUFCNT 0x0600
599 #define SK_TXQS1_BUFCTL 0x0602
600 #define SK_TXQS1_NEXTDESC 0x0604
601 #define SK_TXQS1_RXBUF_LO 0x0608
602 #define SK_TXQS1_RXBUF_HI 0x060C
603 #define SK_TXQS1_RXSTAT 0x0610
604 #define SK_TXQS1_CSUM_STARTVAL 0x0614
605 #define SK_TXQS1_CSUM_STARTPOS 0x0618
606 #define SK_TXQS1_CSUM_WRITEPOS 0x061A
607 #define SK_TXQS1_CURADDR_LO 0x0620
608 #define SK_TXQS1_CURADDR_HI 0x0624
609 #define SK_TXQS1_CURCNT_LO 0x0628
610 #define SK_TXQS1_CURCNT_HI 0x062C
611 #define SK_TXQS1_CURBYTES 0x0630
612 #define SK_TXQS1_BMU_CSR 0x0634
613 #define SK_TXQS1_WATERMARK 0x0638
614 #define SK_TXQS1_FLAG 0x063A
615 #define SK_TXQS1_TEST1 0x063C
616 #define SK_TXQS1_TEST2 0x0640
617 #define SK_TXQS1_TEST3 0x0644
619 /* Block 13 -- TX async queue 1 */
620 #define SK_TXQA1_BUFCNT 0x0680
621 #define SK_TXQA1_BUFCTL 0x0682
622 #define SK_TXQA1_NEXTDESC 0x0684
623 #define SK_TXQA1_RXBUF_LO 0x0688
624 #define SK_TXQA1_RXBUF_HI 0x068C
625 #define SK_TXQA1_RXSTAT 0x0690
626 #define SK_TXQA1_CSUM_STARTVAL 0x0694
627 #define SK_TXQA1_CSUM_STARTPOS 0x0698
628 #define SK_TXQA1_CSUM_WRITEPOS 0x069A
629 #define SK_TXQA1_CURADDR_LO 0x06A0
630 #define SK_TXQA1_CURADDR_HI 0x06A4
631 #define SK_TXQA1_CURCNT_LO 0x06A8
632 #define SK_TXQA1_CURCNT_HI 0x06AC
633 #define SK_TXQA1_CURBYTES 0x06B0
634 #define SK_TXQA1_BMU_CSR 0x06B4
635 #define SK_TXQA1_WATERMARK 0x06B8
636 #define SK_TXQA1_FLAG 0x06BA
637 #define SK_TXQA1_TEST1 0x06BC
638 #define SK_TXQA1_TEST2 0x06C0
639 #define SK_TXQA1_TEST3 0x06C4
641 /* Block 14 -- TX sync queue 2 */
642 #define SK_TXQS2_BUFCNT 0x0700
643 #define SK_TXQS2_BUFCTL 0x0702
644 #define SK_TXQS2_NEXTDESC 0x0704
645 #define SK_TXQS2_RXBUF_LO 0x0708
646 #define SK_TXQS2_RXBUF_HI 0x070C
647 #define SK_TXQS2_RXSTAT 0x0710
648 #define SK_TXQS2_CSUM_STARTVAL 0x0714
649 #define SK_TXQS2_CSUM_STARTPOS 0x0718
650 #define SK_TXQS2_CSUM_WRITEPOS 0x071A
651 #define SK_TXQS2_CURADDR_LO 0x0720
652 #define SK_TXQS2_CURADDR_HI 0x0724
653 #define SK_TXQS2_CURCNT_LO 0x0728
654 #define SK_TXQS2_CURCNT_HI 0x072C
655 #define SK_TXQS2_CURBYTES 0x0730
656 #define SK_TXQS2_BMU_CSR 0x0734
657 #define SK_TXQS2_WATERMARK 0x0738
658 #define SK_TXQS2_FLAG 0x073A
659 #define SK_TXQS2_TEST1 0x073C
660 #define SK_TXQS2_TEST2 0x0740
661 #define SK_TXQS2_TEST3 0x0744
663 /* Block 15 -- TX async queue 2 */
664 #define SK_TXQA2_BUFCNT 0x0780
665 #define SK_TXQA2_BUFCTL 0x0782
666 #define SK_TXQA2_NEXTDESC 0x0784
667 #define SK_TXQA2_RXBUF_LO 0x0788
668 #define SK_TXQA2_RXBUF_HI 0x078C
669 #define SK_TXQA2_RXSTAT 0x0790
670 #define SK_TXQA2_CSUM_STARTVAL 0x0794
671 #define SK_TXQA2_CSUM_STARTPOS 0x0798
672 #define SK_TXQA2_CSUM_WRITEPOS 0x079A
673 #define SK_TXQA2_CURADDR_LO 0x07A0
674 #define SK_TXQA2_CURADDR_HI 0x07A4
675 #define SK_TXQA2_CURCNT_LO 0x07A8
676 #define SK_TXQA2_CURCNT_HI 0x07AC
677 #define SK_TXQA2_CURBYTES 0x07B0
678 #define SK_TXQA2_BMU_CSR 0x07B4
679 #define SK_TXQA2_WATERMARK 0x07B8
680 #define SK_TXQA2_FLAG 0x07BA
681 #define SK_TXQA2_TEST1 0x07BC
682 #define SK_TXQA2_TEST2 0x07C0
683 #define SK_TXQA2_TEST3 0x07C4
685 #define SK_TXBMU_CLR_IRQ_ERR 0x00000001
686 #define SK_TXBMU_CLR_IRQ_EOF 0x00000002
687 #define SK_TXBMU_CLR_IRQ_EOB 0x00000004
688 #define SK_TXBMU_TX_START 0x00000010
689 #define SK_TXBMU_TX_STOP 0x00000020
690 #define SK_TXBMU_POLL_OFF 0x00000040
691 #define SK_TXBMU_POLL_ON 0x00000080
692 #define SK_TXBMU_TRANSFER_SM_RESET 0x00000100
693 #define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200
694 #define SK_TXBMU_DESCWR_SM_RESET 0x00000400
695 #define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800
696 #define SK_TXBMU_DESCRD_SM_RESET 0x00001000
697 #define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000
698 #define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000
699 #define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000
700 #define SK_TXBMU_PFI_SM_RESET 0x00010000
701 #define SK_TXBMU_PFI_SM_UNRESET 0x00020000
702 #define SK_TXBMU_FIFO_RESET 0x00040000
703 #define SK_TXBMU_FIFO_UNRESET 0x00080000
704 #define SK_TXBMU_DESC_RESET 0x00100000
705 #define SK_TXBMU_DESC_UNRESET 0x00200000
706 #define SK_TXBMU_SUPERVISOR_IDLE 0x01000000
708 #define SK_TXBMU_ONLINE \
709 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \
710 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \
711 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \
712 SK_TXBMU_DESC_UNRESET)
714 #define SK_TXBMU_OFFLINE \
715 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \
716 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \
717 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \
720 /* Block 16 -- Receive RAMbuffer 1 */
721 #define SK_RXRB1_START 0x0800
722 #define SK_RXRB1_END 0x0804
723 #define SK_RXRB1_WR_PTR 0x0808
724 #define SK_RXRB1_RD_PTR 0x080C
725 #define SK_RXRB1_UTHR_PAUSE 0x0810
726 #define SK_RXRB1_LTHR_PAUSE 0x0814
727 #define SK_RXRB1_UTHR_HIPRIO 0x0818
728 #define SK_RXRB1_UTHR_LOPRIO 0x081C
729 #define SK_RXRB1_PKTCNT 0x0820
730 #define SK_RXRB1_LVL 0x0824
731 #define SK_RXRB1_CTLTST 0x0828
733 /* Block 17 -- Receive RAMbuffer 2 */
734 #define SK_RXRB2_START 0x0880
735 #define SK_RXRB2_END 0x0884
736 #define SK_RXRB2_WR_PTR 0x0888
737 #define SK_RXRB2_RD_PTR 0x088C
738 #define SK_RXRB2_UTHR_PAUSE 0x0890
739 #define SK_RXRB2_LTHR_PAUSE 0x0894
740 #define SK_RXRB2_UTHR_HIPRIO 0x0898
741 #define SK_RXRB2_UTHR_LOPRIO 0x089C
742 #define SK_RXRB2_PKTCNT 0x08A0
743 #define SK_RXRB2_LVL 0x08A4
744 #define SK_RXRB2_CTLTST 0x08A8
746 /* Block 20 -- Sync. Transmit RAMbuffer 1 */
747 #define SK_TXRBS1_START 0x0A00
748 #define SK_TXRBS1_END 0x0A04
749 #define SK_TXRBS1_WR_PTR 0x0A08
750 #define SK_TXRBS1_RD_PTR 0x0A0C
751 #define SK_TXRBS1_PKTCNT 0x0A20
752 #define SK_TXRBS1_LVL 0x0A24
753 #define SK_TXRBS1_CTLTST 0x0A28
755 /* Block 21 -- Async. Transmit RAMbuffer 1 */
756 #define SK_TXRBA1_START 0x0A80
757 #define SK_TXRBA1_END 0x0A84
758 #define SK_TXRBA1_WR_PTR 0x0A88
759 #define SK_TXRBA1_RD_PTR 0x0A8C
760 #define SK_TXRBA1_PKTCNT 0x0AA0
761 #define SK_TXRBA1_LVL 0x0AA4
762 #define SK_TXRBA1_CTLTST 0x0AA8
764 /* Block 22 -- Sync. Transmit RAMbuffer 2 */
765 #define SK_TXRBS2_START 0x0B00
766 #define SK_TXRBS2_END 0x0B04
767 #define SK_TXRBS2_WR_PTR 0x0B08
768 #define SK_TXRBS2_RD_PTR 0x0B0C
769 #define SK_TXRBS2_PKTCNT 0x0B20
770 #define SK_TXRBS2_LVL 0x0B24
771 #define SK_TXRBS2_CTLTST 0x0B28
773 /* Block 23 -- Async. Transmit RAMbuffer 2 */
774 #define SK_TXRBA2_START 0x0B80
775 #define SK_TXRBA2_END 0x0B84
776 #define SK_TXRBA2_WR_PTR 0x0B88
777 #define SK_TXRBA2_RD_PTR 0x0B8C
778 #define SK_TXRBA2_PKTCNT 0x0BA0
779 #define SK_TXRBA2_LVL 0x0BA4
780 #define SK_TXRBA2_CTLTST 0x0BA8
782 #define SK_RBCTL_RESET 0x00000001
783 #define SK_RBCTL_UNRESET 0x00000002
784 #define SK_RBCTL_OFF 0x00000004
785 #define SK_RBCTL_ON 0x00000008
786 #define SK_RBCTL_STORENFWD_OFF 0x00000010
787 #define SK_RBCTL_STORENFWD_ON 0x00000020
789 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */
790 #define SK_RXF1_END 0x0C00
791 #define SK_RXF1_WPTR 0x0C04
792 #define SK_RXF1_RPTR 0x0C0C
793 #define SK_RXF1_PKTCNT 0x0C10
794 #define SK_RXF1_LVL 0x0C14
795 #define SK_RXF1_MACCTL 0x0C18
796 #define SK_RXF1_CTL 0x0C1C
797 #define SK_RXLED1_CNTINIT 0x0C20
798 #define SK_RXLED1_COUNTER 0x0C24
799 #define SK_RXLED1_CTL 0x0C28
800 #define SK_RXLED1_TST 0x0C29
801 #define SK_LINK_SYNC1_CINIT 0x0C30
802 #define SK_LINK_SYNC1_COUNTER 0x0C34
803 #define SK_LINK_SYNC1_CTL 0x0C38
804 #define SK_LINK_SYNC1_TST 0x0C39
805 #define SK_LINKLED1_CTL 0x0C3C
807 #define SK_FIFO_END 0x3F
809 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */
810 #define SK_RXF2_END 0x0C80
811 #define SK_RXF2_WPTR 0x0C84
812 #define SK_RXF2_RPTR 0x0C8C
813 #define SK_RXF2_PKTCNT 0x0C90
814 #define SK_RXF2_LVL 0x0C94
815 #define SK_RXF2_MACCTL 0x0C98
816 #define SK_RXF2_CTL 0x0C9C
817 #define SK_RXLED2_CNTINIT 0x0CA0
818 #define SK_RXLED2_COUNTER 0x0CA4
819 #define SK_RXLED2_CTL 0x0CA8
820 #define SK_RXLED2_TST 0x0CA9
821 #define SK_LINK_SYNC2_CINIT 0x0CB0
822 #define SK_LINK_SYNC2_COUNTER 0x0CB4
823 #define SK_LINK_SYNC2_CTL 0x0CB8
824 #define SK_LINK_SYNC2_TST 0x0CB9
825 #define SK_LINKLED2_CTL 0x0CBC
827 #define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001
828 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002
829 #define SK_RXMACCTL_TSTAMP_OFF 0x00000004
830 #define SK_RXMACCTL_RSTAMP_ON 0x00000008
831 #define SK_RXMACCTL_FLUSH_OFF 0x00000010
832 #define SK_RXMACCTL_FLUSH_ON 0x00000020
833 #define SK_RXMACCTL_PAUSE_OFF 0x00000040
834 #define SK_RXMACCTL_PAUSE_ON 0x00000080
835 #define SK_RXMACCTL_AFULL_OFF 0x00000100
836 #define SK_RXMACCTL_AFULL_ON 0x00000200
837 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400
838 #define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800
839 #define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000
840 #define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000
841 #define SK_RXMACCTL_STS_TIMEO 0x00FF0000
842 #define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000
844 #define SK_RXLEDCTL_ENABLE 0x0001
845 #define SK_RXLEDCTL_COUNTER_STOP 0x0002
846 #define SK_RXLEDCTL_COUNTER_START 0x0004
848 #define SK_LINKLED_OFF 0x0001
849 #define SK_LINKLED_ON 0x0002
850 #define SK_LINKLED_LINKSYNC_OFF 0x0004
851 #define SK_LINKLED_LINKSYNC_ON 0x0008
852 #define SK_LINKLED_BLINK_OFF 0x0010
853 #define SK_LINKLED_BLINK_ON 0x0020
855 /* Block 26 -- TX MAC FIFO 1 regisrers */
856 #define SK_TXF1_END 0x0D00
857 #define SK_TXF1_WPTR 0x0D04
858 #define SK_TXF1_RPTR 0x0D0C
859 #define SK_TXF1_PKTCNT 0x0D10
860 #define SK_TXF1_LVL 0x0D14
861 #define SK_TXF1_MACCTL 0x0D18
862 #define SK_TXF1_CTL 0x0D1C
863 #define SK_TXLED1_CNTINIT 0x0D20
864 #define SK_TXLED1_COUNTER 0x0D24
865 #define SK_TXLED1_CTL 0x0D28
866 #define SK_TXLED1_TST 0x0D29
868 /* Block 27 -- TX MAC FIFO 2 regisrers */
869 #define SK_TXF2_END 0x0D80
870 #define SK_TXF2_WPTR 0x0D84
871 #define SK_TXF2_RPTR 0x0D8C
872 #define SK_TXF2_PKTCNT 0x0D90
873 #define SK_TXF2_LVL 0x0D94
874 #define SK_TXF2_MACCTL 0x0D98
875 #define SK_TXF2_CTL 0x0D9C
876 #define SK_TXLED2_CNTINIT 0x0DA0
877 #define SK_TXLED2_COUNTER 0x0DA4
878 #define SK_TXLED2_CTL 0x0DA8
879 #define SK_TXLED2_TST 0x0DA9
881 #define SK_TXMACCTL_XMAC_RESET 0x00000001
882 #define SK_TXMACCTL_XMAC_UNRESET 0x00000002
883 #define SK_TXMACCTL_LOOP_OFF 0x00000004
884 #define SK_TXMACCTL_LOOP_ON 0x00000008
885 #define SK_TXMACCTL_FLUSH_OFF 0x00000010
886 #define SK_TXMACCTL_FLUSH_ON 0x00000020
887 #define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040
888 #define SK_TXMACCTL_WAITEMPTY_ON 0x00000080
889 #define SK_TXMACCTL_AFULL_OFF 0x00000100
890 #define SK_TXMACCTL_AFULL_ON 0x00000200
891 #define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400
892 #define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800
893 #define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000
894 #define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000
895 #define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000
896 #define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000
898 #define SK_TXLEDCTL_ENABLE 0x0001
899 #define SK_TXLEDCTL_COUNTER_STOP 0x0002
900 #define SK_TXLEDCTL_COUNTER_START 0x0004
902 #define SK_FIFO_RESET 0x00000001
903 #define SK_FIFO_UNRESET 0x00000002
904 #define SK_FIFO_OFF 0x00000004
905 #define SK_FIFO_ON 0x00000008
907 /* Block 0x40 to 0x4F -- XMAC 1 registers */
908 #define SK_XMAC1_BASE 0x2000
909 #define SK_XMAC1_END 0x23FF
911 /* Block 0x60 to 0x6F -- XMAC 2 registers */
912 #define SK_XMAC2_BASE 0x3000
913 #define SK_XMAC2_END 0x33FF
915 /* Compute relative offset of an XMAC register in the XMAC window(s). */
916 #define SK_XMAC_REG(reg, mac) (((reg) * 2) + SK_XMAC1_BASE + \
917 (mac * (SK_XMAC2_BASE - SK_XMAC1_BASE)))
919 #define SK_XM_READ_4(sc, reg) \
920 (sk_win_read_2(sc->sk_softc, \
921 SK_XMAC_REG(reg, sc->sk_port)) & 0xFFFF) | \
922 ((sk_win_read_2(sc->sk_softc, \
923 SK_XMAC_REG(reg + 2, sc->sk_port)) << 16) & 0xFFFF0000)
925 #define SK_XM_WRITE_4(sc, reg, val) \
926 sk_win_write_2(sc->sk_softc, \
927 SK_XMAC_REG(reg, sc->sk_port), ((val) & 0xFFFF)); \
928 sk_win_write_2(sc->sk_softc, \
929 SK_XMAC_REG(reg + 2, sc->sk_port), ((val) >> 16) & 0xFFFF);
931 #define SK_XM_READ_2(sc, reg) \
932 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(reg, sc->sk_port))
934 #define SK_XM_WRITE_2(sc, reg, val) \
935 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(reg, sc->sk_port), val)
937 #define SK_XM_SETBIT_4(sc, reg, x) \
938 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x))
940 #define SK_XM_CLRBIT_4(sc, reg, x) \
941 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x))
943 #define SK_XM_SETBIT_2(sc, reg, x) \
944 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x))
946 #define SK_XM_CLRBIT_2(sc, reg, x) \
947 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x))
951 * The default FIFO threshold on the XMAC II is 4 bytes. On
952 * dual port NICs, this often leads to transmit underruns, so we
953 * bump the threshold a little.
955 #define SK_XM_TX_FIFOTHRESH 512
957 #define SK_PCI_VENDOR_ID 0x0000
958 #define SK_PCI_DEVICE_ID 0x0002
959 #define SK_PCI_COMMAND 0x0004
960 #define SK_PCI_STATUS 0x0006
961 #define SK_PCI_REVID 0x0008
962 #define SK_PCI_CLASSCODE 0x0009
963 #define SK_PCI_CACHELEN 0x000C
964 #define SK_PCI_LATENCY_TIMER 0x000D
965 #define SK_PCI_HEADER_TYPE 0x000E
966 #define SK_PCI_LOMEM 0x0010
967 #define SK_PCI_LOIO 0x0014
968 #define SK_PCI_SUBVEN_ID 0x002C
969 #define SK_PCI_SYBSYS_ID 0x002E
970 #define SK_PCI_BIOSROM 0x0030
971 #define SK_PCI_INTLINE 0x003C
972 #define SK_PCI_INTPIN 0x003D
973 #define SK_PCI_MINGNT 0x003E
974 #define SK_PCI_MINLAT 0x003F
976 /* device specific PCI registers */
977 #define SK_PCI_OURREG1 0x0040
978 #define SK_PCI_OURREG2 0x0044
979 #define SK_PCI_CAPID 0x0048 /* 8 bits */
980 #define SK_PCI_NEXTPTR 0x0049 /* 8 bits */
981 #define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */
982 #define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */
983 #define SK_PCI_PME_EVENT 0x004F
984 #define SK_PCI_VPD_CAPID 0x0050
985 #define SK_PCI_VPD_NEXTPTR 0x0051
986 #define SK_PCI_VPD_ADDR 0x0052
987 #define SK_PCI_VPD_DATA 0x0054
989 #define SK_PSTATE_MASK 0x0003
990 #define SK_PSTATE_D0 0x0000
991 #define SK_PSTATE_D1 0x0001
992 #define SK_PSTATE_D2 0x0002
993 #define SK_PSTATE_D3 0x0003
994 #define SK_PME_EN 0x0010
995 #define SK_PME_STATUS 0x8000
998 * VPD flag bit. Set to 0 to initiate a read, will become 1 when
999 * read is complete. Set to 1 to initiate a write, will become 0
1000 * when write is finished.
1002 #define SK_VPD_FLAG 0x8000
1004 /* VPD structures */
1016 #define VPD_RES_ID 0x82 /* ID string */
1017 #define VPD_RES_READ 0x90 /* start of read only area */
1018 #define VPD_RES_WRITE 0x81 /* start of read/write area */
1019 #define VPD_RES_END 0x78 /* end tag */
1021 #define CSR_WRITE_4(sc, reg, val) \
1022 bus_space_write_4(sc->sk_btag, sc->sk_bhandle, reg, val)
1023 #define CSR_WRITE_2(sc, reg, val) \
1024 bus_space_write_2(sc->sk_btag, sc->sk_bhandle, reg, val)
1025 #define CSR_WRITE_1(sc, reg, val) \
1026 bus_space_write_1(sc->sk_btag, sc->sk_bhandle, reg, val)
1028 #define CSR_READ_4(sc, reg) \
1029 bus_space_read_4(sc->sk_btag, sc->sk_bhandle, reg)
1030 #define CSR_READ_2(sc, reg) \
1031 bus_space_read_2(sc->sk_btag, sc->sk_bhandle, reg)
1032 #define CSR_READ_1(sc, reg) \
1033 bus_space_read_1(sc->sk_btag, sc->sk_bhandle, reg)
1041 /* RX queue descriptor data structure */
1045 u_int32_t sk_data_lo;
1046 u_int32_t sk_data_hi;
1047 u_int32_t sk_xmac_rxstat;
1048 u_int32_t sk_timestamp;
1051 u_int16_t sk_csum2_start;
1052 u_int16_t sk_csum1_start;
1055 #define SK_OPCODE_DEFAULT 0x00550000
1056 #define SK_OPCODE_CSUM 0x00560000
1058 #define SK_RXCTL_LEN 0x0000FFFF
1059 #define SK_RXCTL_OPCODE 0x00FF0000
1060 #define SK_RXCTL_TSTAMP_VALID 0x01000000
1061 #define SK_RXCTL_STATUS_VALID 0x02000000
1062 #define SK_RXCTL_DEV0 0x04000000
1063 #define SK_RXCTL_EOF_INTR 0x08000000
1064 #define SK_RXCTL_EOB_INTR 0x10000000
1065 #define SK_RXCTL_LASTFRAG 0x20000000
1066 #define SK_RXCTL_FIRSTFRAG 0x40000000
1067 #define SK_RXCTL_OWN 0x80000000
1070 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \
1071 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN)
1076 u_int32_t sk_data_lo;
1077 u_int32_t sk_data_hi;
1078 u_int32_t sk_xmac_txstat;
1080 u_int16_t sk_csum_startval;
1081 u_int16_t sk_csum_startpos;
1082 u_int16_t sk_csum_writepos;
1086 #define SK_TXCTL_LEN 0x0000FFFF
1087 #define SK_TXCTL_OPCODE 0x00FF0000
1088 #define SK_TXCTL_SW 0x01000000
1089 #define SK_TXCTL_NOCRC 0x02000000
1090 #define SK_TXCTL_STORENFWD 0x04000000
1091 #define SK_TXCTL_EOF_INTR 0x08000000
1092 #define SK_TXCTL_EOB_INTR 0x10000000
1093 #define SK_TXCTL_LASTFRAG 0x20000000
1094 #define SK_TXCTL_FIRSTFRAG 0x40000000
1095 #define SK_TXCTL_OWN 0x80000000
1098 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN)
1100 #define SK_RXBYTES(x) (x) & 0x0000FFFF;
1101 #define SK_TXBYTES SK_RXBYTES
1103 #define SK_TX_RING_CNT 512
1104 #define SK_RX_RING_CNT 256
1107 * Jumbo buffer stuff. Note that we must allocate more jumbo
1108 * buffers than there are descriptors in the receive ring. This
1109 * is because we don't know how long it will take for a packet
1110 * to be released after we hand it off to the upper protocol
1111 * layers. To be safe, we allocate 1.5 times the number of
1112 * receive descriptors.
1114 #define SK_JUMBO_FRAMELEN 9018
1115 #define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
1116 #define SK_JSLOTS 384
1118 #define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN + sizeof(u_int64_t))
1119 #define SK_JLEN (SK_JRAWLEN + (sizeof(u_int64_t) - \
1120 (SK_JRAWLEN % sizeof(u_int64_t))))
1121 #define SK_MCLBYTES (SK_JLEN - sizeof(u_int64_t))
1122 #define SK_JPAGESZ PAGE_SIZE
1123 #define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ)
1124 #define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID)
1131 struct sk_jpool_entry {
1133 SLIST_ENTRY(sk_jpool_entry) jpool_entries;
1138 struct mbuf *sk_mbuf;
1139 struct sk_chain *sk_next;
1142 struct sk_chain_data {
1143 struct sk_chain sk_tx_chain[SK_TX_RING_CNT];
1144 struct sk_chain sk_rx_chain[SK_RX_RING_CNT];
1151 /* Stick the jumbo mem management stuff here too. */
1152 struct sk_jslot sk_jslots[SK_JSLOTS];
1157 struct sk_ring_data {
1158 struct sk_tx_desc sk_tx_ring[SK_TX_RING_CNT];
1159 struct sk_rx_desc sk_rx_ring[SK_RX_RING_CNT];
1162 struct sk_bcom_hack {
1167 #define SK_INC(x, y) (x) = (x + 1) % y
1172 /* Softc for the GEnesis controller. */
1174 bus_space_handle_t sk_bhandle; /* bus space handle */
1175 bus_space_tag_t sk_btag; /* bus space tag */
1176 void *sk_intrhand; /* irq handler handle */
1177 struct resource *sk_irq; /* IRQ resource handle */
1178 struct resource *sk_res; /* I/O or shared mem handle */
1179 u_int8_t sk_unit; /* controller number */
1181 char *sk_vpd_prodname;
1182 char *sk_vpd_readonly;
1183 u_int32_t sk_rboff; /* RAMbuffer offset */
1184 u_int32_t sk_ramsize; /* amount of RAM on NIC */
1185 u_int32_t sk_pmd; /* physical media type */
1186 u_int32_t sk_intrmask;
1187 struct sk_if_softc *sk_if[2];
1188 device_t sk_devs[2];
1191 /* Softc for each logical interface */
1192 struct sk_if_softc {
1193 struct arpcom arpcom; /* interface info */
1195 u_int8_t sk_unit; /* interface number */
1196 u_int8_t sk_port; /* port # on controller */
1197 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */
1198 u_int32_t sk_rx_ramstart;
1199 u_int32_t sk_rx_ramend;
1200 u_int32_t sk_tx_ramstart;
1201 u_int32_t sk_tx_ramend;
1207 struct callout_handle sk_tick_ch;
1208 struct sk_chain_data sk_cdata;
1209 struct sk_ring_data *sk_rdata;
1210 struct sk_softc *sk_softc; /* parent controller */
1211 int sk_tx_bmu; /* TX BMU register */
1213 SLIST_HEAD(__sk_jfreehead, sk_jpool_entry) sk_jfree_listhead;
1214 SLIST_HEAD(__sk_jinusehead, sk_jpool_entry) sk_jinuse_listhead;
1217 #define SK_MAXUNIT 256
1218 #define SK_TIMEOUT 1000
1219 #define ETHER_ALIGN 2
1223 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)