1 /* $FreeBSD: src/sys/pci/if_wxreg.h,v 1.3.2.6 2001/10/20 17:44:12 mjacob Exp $ */
2 /* $DragonFly: src/sys/dev/netif/wx/Attic/if_wxreg.h,v 1.2 2003/06/17 04:28:57 dillon Exp $ */
4 * Principal Author: Matthew Jacob
5 * Copyright (c) 1999, 2001 by Traakan Software
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Additional Copyright (c) 2001 by Parag Patel
31 * under same licence for MII PHY code.
34 #define WX_VENDOR_INTEL 0x8086
35 #define WX_PRODUCT_82452 0x1000
36 #define WX_PRODUCT_LIVENGOOD 0x1001
37 #define WX_PRODUCT_82452_SC 0x1003
38 #define WX_PRODUCT_82543 0x1004
40 #define MWI 0x10 /* Memory Write Invalidate */
41 #define WX_CACHELINE_SIZE 0x20
43 /* Join PCI ID and revision into one value */
44 #define WX_WISEMAN_0 0x10000000
45 #define WX_WISEMAN_2_0 0x10000002
46 #define WX_WISEMAN_2_1 0x10000003
47 #define WX_LIVENGOOD 0x10010000
48 #define WX_LIVENGOOD_CU 0x10040002
50 #define IS_WISEMAN(sc) ((sc)->wx_idnrev < WX_LIVENGOOD)
51 #define IS_LIVENGOOD(sc) ((sc)->wx_idnrev >= WX_LIVENGOOD)
52 #define IS_LIVENGOOD_CU(sc) ((sc)->wx_idnrev == WX_LIVENGOOD_CU)
55 * Information about this chipset gathered from a released Intel Linux driver,
56 * which was clearly a port of an NT driver.
60 * Various Descriptor Structures.
61 * These are all in little endian format (for now).
71 * The base address of a receive descriptor ring must be on a 4KB boundary,
72 * and they must be allocated in multiples of 8.
75 wxpa_t address; /* physical address of buffer */
83 #define RDSTAT_DD 0x1 /* descriptor done */
84 #define RDSTAT_EOP 0x2 /* end of packet */
85 #define RDSTAT_RSVD 0x74 /* reserved bits */
87 #define RDERR_CRC 0x1 /* CRC Error */
88 #define RDERR_SE 0x2 /* Symbol Error */
89 #define RDERR_SEQ 0x4 /* Sequence Error */
93 * The base address of a transmit descriptor ring must be on a 4KB boundary,
94 * and they must be allocated in multiples of 8.
99 u_int8_t cso; /* checksum offset */
100 u_int8_t cmd; /* cmd */
101 u_int8_t status; /* status */
102 u_int8_t css; /* checksum start */
106 #define TXCMD_EOP 0x1 /* last packet */
107 #define TXCMD_IFCS 0x2 /* insert FCS */
108 #define TXCMD_IC 0x4 /* insert checksum */
109 #define TXCMD_RS 0x8 /* report status */
110 #define TXCMD_RPS 0x10 /* report packet sent */
111 #define TXCMD_SM 0x20 /* symbol mode */
112 #define TXCMD_IDE 0x80 /* interrupt delay enable */
114 #define TXSTS_DD 0x1 /* descriptor done */
115 #define TXSTS_EC 0x2 /* excess collisions */
116 #define TXSTS_LC 0x4 /* late collision */
119 * This device can only be accessed via memory space.
123 * Register access via offsets.
125 * Our brilliant friends at Intel decided to move registers offsets
126 * around from chip version to chip version. It's amazing that some
127 * deity doesn't zap these suckers. Really.
130 #define WXREG_DCR 0x00000000
131 #define WXREG_DSR 0x00000008
132 #define WXREG_EECDR 0x00000010
133 #define WXREG_EXCT 0x00000018
134 #define WXREG_MDIC 0x00000020
135 #define WXREG_FCAL 0x00000028
136 #define WXREG_FCAH 0x0000002C
137 #define WXREG_FCT 0x00000030
138 #define WXREG_VET 0x00000038
139 #define WXREG_RAL_BASE 0x00000040
140 #define WXREG_RAL_LO(x) (WXREG_RAL_BASE + ((x) << 3))
141 #define WXREG_RAL_HI(x) (WXREG_RAL_LO(x) + 4)
142 #define WXREG_ICR 0x000000c0
143 #define WXREG_ICS 0x000000c8
144 #define WXREG_IMASK 0x000000d0
145 #define WXREG_IMCLR 0x000000d8
146 #define WXREG_RCTL 0x00000100
147 #define WXREG_RDTR0 0x00000108
148 #define WXREG_RDTR0_LIVENGOOD 0x00002820
149 #define WXREG_RDBA0_LO 0x00000110
150 #define WXREG_RDBA0_LO_LIVENGOOD 0x00002800
151 #define WXREG_RDBA0_HI 0x00000114
152 #define WXREG_RDBA0_HI_LIVENGOOD 0x00002804
153 #define WXREG_RDLEN0 0x00000118
154 #define WXREG_RDLEN0_LIVENGOOD 0x00002808
155 #define WXREG_RDH0 0x00000120
156 #define WXREG_RDH0_LIVENGOOD 0x00002810
157 #define WXREG_RDT0 0x00000128
158 #define WXREG_RDT0_LIVENGOOD 0x00002818
159 #define WXREG_RDTR1 0x00000130
160 #define WXREG_RDBA1_LO 0x00000138
161 #define WXREG_RDBA1_HI 0x0000013C
162 #define WXREG_RDLEN1 0x00000140
163 #define WXREG_RDH1 0x00000148
164 #define WXREG_RDT1 0x00000150
165 #define WXREG_FLOW_RCV_HI 0x00000160
166 #define WXREG_FLOW_RCV_HI_LIVENGOOD 0x00002168
167 #define WXREG_FLOW_RCV_LO 0x00000168
168 #define WXREG_FLOW_RCV_LO_LIVENGOOD 0x00002160
169 #define WXREG_FLOW_XTIMER 0x00000170
170 #define WXREG_XMIT_CFGW 0x00000178
171 #define WXREG_RECV_CFGW 0x00000180
172 #define WXREG_MTA 0x00000200
173 #define WXREG_TCTL 0x00000400
174 #define WXREG_TQSA_LO 0x00000408
175 #define WXREG_TQSA_HI 0x0000040C
176 #define WXREG_TIPG 0x00000410
177 #define WXREG_TQC 0x00000418
178 #define WXREG_TDBA_LO 0x00000420
179 #define WXREG_TDBA_LO_LIVENGOOD 0x00003800
180 #define WXREG_TDBA_HI 0x00000424
181 #define WXREG_TDBA_HI_LIVENGOOD 0x00003804
182 #define WXREG_TDLEN 0x00000428
183 #define WXREG_TDLEN_LIVENGOOD 0x00003808
184 #define WXREG_TDH 0x00000430
185 #define WXREG_TDH_LIVENGOOD 0x00003810
186 #define WXREG_TDT 0x00000438
187 #define WXREG_TDT_LIVENGOOD 0x00003818
188 #define WXREG_TIDV 0x00000440
189 #define WXREG_TIDV_LIVENGOOD 0x00003820
190 #define WXREG_VFTA 0x00000600
192 #define WX_RAL_TAB_SIZE 16
193 #define WX_RAL_AV 0x80000000
195 #define WX_MC_TAB_SIZE 128
196 #define WX_VLAN_TAB_SIZE 128
199 * Device Control Register Defines
201 #define WXDCR_FD 0x1 /* full duplex */
202 #define WXDCR_BEM 0x2 /* big endian mode */
203 #define WXDCR_FAIR 0x4 /* 1->Fairness, 0->Receive Priority */
204 #define WXDCR_LRST 0x8 /* Link Reset */
205 #define WXDCR_ASDE 0x20 /* ??? */
206 #define WXDCR_SLE 0x20 /* ??? */
207 #define WXDCR_SLU 0x40 /* Set Link Up */
208 #define WXDCR_ILOS 0x80 /* Invert Loss-of-Signal */
209 #define WXDCR_10BT 0x000 /* set 10BaseT */
210 #define WXDCR_100BT 0x100 /* LIVENGOOD: Set 100BaseT */
211 #define WXDCR_1000BT 0x200 /* LIVENGOOD: Set 1000BaseT */
212 #define WXDCR_SPEED_MASK 0x300
213 #define WXDCR_BEM32 0x400 /* LIVENGOOD: Set Big Endian 32 (?) */
214 #define WXDCR_FRCSPD 0x800 /* LIVENGOOD: Force Speed (?) */
215 #define WXDCR_FRCDPX 0x1000 /* LIVENGOOD: Force Full Duplex */
218 * General purpose I/O pins
220 * Pin 0 is for the LED.
222 * Pin 1 is to detect loss of signal (LOS)- if it is set, we've lost signal.
224 #define WXDCR_SWDPINS_SHIFT 18
225 #define WXDCR_SWDPINS_MASK 0xf
226 #define WXDCR_SWDPIN0 (1 << 18) /* 0x00040000 - PHY reset */
227 #define WXDCR_SWDPIN1 (1 << 19) /* 0x00080000 */
228 #define WXDCR_SWDPIN2 (1 << 20) /* 0x00100000 - PHY data */
229 #define WXDCR_SWDPIN3 (1 << 21) /* 0x00200000 - PHY clk */
230 #define WXDCR_SWDPIO_SHIFT 22
231 #define WXDCR_SWDPIO_MASK 0xf
232 #define WXDCR_SWDPIO0 (1 << 22) /* 0x00400000 - PHY rst dir */
233 #define WXDCR_SWDPIO1 (1 << 23) /* 0x00800000 */
234 #define WXDCR_SWDPIO2 (1 << 24) /* 0x01000000 - PHY data dir */
235 #define WXDCR_SWDPIO3 (1 << 25) /* 0x02000000 - PHY clk dir */
238 #define WXDCR_RST 0x04000000 /* Device Reset (self clearing) */
239 #define WXDCR_RFCE 0x08000000 /* Receive Flow Control Enable */
240 #define WXDCR_TFCE 0x10000000 /* Transmit Flow Control Enable */
241 #define WXDCR_RTE 0x20000000 /* Routing Tag Enable */
242 #define WXDCR_VME 0x40000000 /* VLAN Mode Enable */
245 * Device Status Register Defines
247 #define WXDSR_FD 0x1 /* full duplex */
248 #define WXDSR_LU 0x2 /* link up */
249 #define WXDSR_TXCLK 0x4 /* transmit clock running */
250 #define WXDSR_RBCLK 0x8 /* receive clock running */
251 #define WXDSR_TXOFF 0x10 /* transmit paused */
252 #define WXDSR_TBIMODE 0x20 /* LIVENGOOD: Fibre Mode */
253 #define WXDSR_100BT 0x40 /* LIVENGOOD: 100BaseT */
254 #define WXDSR_1000BT 0x80 /* LIVENGOOD: 1000BaseT */
255 #define WXDSR_ASDV 0x300 /* LIVENGOOD: ?? */
256 #define WXDSR_MTXCKOK 0x400 /* LIVENGOOD: ?? */
257 #define WXDSR_PCI66 0x800 /* LIVENGOOD: 66 MHz bus */
258 #define WXDSR_BUS64 0x1000 /* LIVENGOOD: In 64 bit slot */
261 * EEPROM Register Defines
263 #define WXEECD_SK 0x1 /* enable clock */
264 #define WXEECD_CS 0x2 /* chip select */
265 #define WXEECD_DI 0x4 /* data input */
266 #define WXEECD_DO 0x8 /* data output */
268 #define EEPROM_READ_OPCODE 0x6
271 * Constant Flow Control Frame MAC Address and Type values.
273 #define FC_FRM_CONST_LO 0x00C28001
274 #define FC_FRM_CONST_HI 0x0100
275 #define FC_TYP_CONST 0x8808
278 * Bits pertinent for the Receive Address register pairs. The low address
279 * is the low 32 bits of a 48 bit MAC address. The high address contains
280 * bits 32-47 of the 48 bit MAC address. The top bit in the high address
283 #define WXRAH_RDR1 0x40000000 /* second receive descriptor ring */
284 #define WXRAH_VALID 0x80000000
287 * Interrupt Cause Bits
289 #define WXISR_TXDW 0x1 /* transmit descriptor written back */
290 #define WXISR_TXQE 0x2 /* transmit queue empty */
291 #define WXISR_LSC 0x4 /* link status change */
292 #define WXISR_RXSEQ 0x8 /* receive sequence error */
293 #define WXISR_RXDMT0 0x10 /* receiver ring 0 getting empty */
294 #define WXISR_RXDMT1 0x20 /* receiver ring 1 getting empty */
295 #define WXISR_RXO 0x40 /* receiver overrun */
296 #define WXISR_RXT0 0x80 /* ring 0 receiver timer interrupt */
297 #define WXISR_RXT1 0x100 /* ring 1 receiver timer interrupt */
298 #define WXISR_PCIE 0x200 /* ?? Probably PCI interface error... */
299 #define WXISR_MDIAC 0x200
300 #define WXISR_RXCFG 0x400
301 #define WXISR_GPI_EN0 0x800
302 #define WXISR_GPI_EN1 0x1000 /* appears to be PHY intr line */
303 #define WXISR_GPI_EN2 0x2000
304 #define WXISR_GPI_EN3 0x4000
306 #define WXIENABLE_DEFAULT \
307 (WXISR_RXO | WXISR_RXT0 | WXISR_RXDMT0 | WXISR_RXSEQ | WXISR_TXDW |\
308 WXISR_LSC | WXISR_PCIE | WXISR_GPI_EN1)
310 #define WXDISABLE 0xffffffff
313 * Receive Control Register bits.
316 #define WXRCTL_RST 0x1 /* receiver reset */
317 #define WXRCTL_EN 0x2 /* receiver enable */
318 #define WXRCTL_SBP 0x4 /* store bad packets */
319 #define WXRCTL_UPE 0x8 /* unicast promiscuos mode */
320 #define WXRCTL_MPE 0x10 /* multicast promiscuous mode */
321 #define WXRCTL_LPE 0x20 /* large packet enable */
322 #define WXRCTL_BAM 0x8000 /* broadcast accept mode */
323 #define WXRCTL_BSEX 0x2000000 /* LIVENGOOD: Buffer Size Extension */
325 #define WXRCTL_2KRBUF (0 << 16) /* 2KB Receive Buffers */
326 #define WXRCTL_1KRBUF (1 << 16) /* 1KB Receive Buffers */
327 #define WXRCTL_512BRBUF (2 << 16) /* 512 Byte Receive Buffers */
328 #define WXRCTL_256BRBUF (3 << 16) /* 256 Byte Receive Buffers */
330 #define WXRCTL_4KRBUF (3 << 16) /* LIVENGOOD: 4KB Receive Buffers */
331 #define WXRCTL_8KRBUF (2 << 16) /* LIVENGOOD: 8KB Receive Buffers */
332 #define WXRCTL_16KRBUF (1 << 16) /* LIVENGOOD: 16KB Receive Buffers */
336 * Receive Delay Timer Register bits.
338 #define WXRDTR_FPD 0x80000000 /* flush partial descriptor */
341 * Transmit Configuration Word defines
343 #define WXTXCW_FD 0x00000020 /* Full Duplex */
344 #define WXTXCW_PMASK 0x00000180 /* pause mask */
345 #define WXTXCW_ANE 0x80000000 /* AutoNegotiate */
346 #define WXTXCW_DEFAULT 0x800001A0
349 * Transmit Control Register defines.
351 #define WXTCTL_RST 0x1 /* transmitter reset */
352 #define WXTCTL_EN 0x2 /* transmitter enable */
353 #define WXTCTL_PSP 0x8 /* pad short packets */
354 #define WXTCTL_CT(x) (((x) & 0xff) << 4) /* 4:11 - Collision Threshold */
355 #define WXTCTL_COLD(x) (((x) & 0x3ff) << 12) /* 12:21 - Collision Distance */
356 #define WXTCTL_SWXOFF (1 << 22) /* Software XOFF */
358 #define WX_COLLISION_THRESHOLD 15
359 #define WX_FDX_COLLISION_DX 64
360 #define WX_HDX_COLLISION_DX 512
363 * MDI control register bits - (best-guess)
365 #define WXMDIC_WRITE 0x04000000
366 #define WXMDIC_READ 0x08000000
367 #define WXMDIC_READY 0x10000000
368 #define WXMDIC_INTR 0x20000000
369 #define WXMDIC_ERR 0x40000000
370 #define WXMDIC_REGADDR_MASK 0x001F0000
371 #define WXMDIC_REGADDR_SHIFT 16
372 #define WXMDIC_PHYADDR_MASK 0x03E00000
373 #define WXMDIC_PHYADDR_SHIFT 21
374 #define WXMDIC_DATA_MASK 0x0000FFFF
377 * EXCT control register bits
379 #define WXEXCT_GPI_EN0 0x00000001
380 #define WXEXCT_GPI_EN1 0x00000002
381 #define WXEXCT_GPI_EN2 0x00000004
382 #define WXEXCT_GPI_EN3 0x00000008
383 #define WXEXCT_SWDPIN4 0x00000010
384 #define WXEXCT_SWDPIN5 0x00000020
385 #define WXEXCT_SWDPIN6 0x00000040
386 #define WXEXCT_SWDPIN7 0x00000080
387 #define WXEXCT_SWDPIO4 0x00000100
388 #define WXEXCT_SWDPIO5 0x00000200
389 #define WXEXCT_SWDPIO6 0x00000400
390 #define WXEXCT_SWDPIO7 0x00000800
391 #define WXEXCT_ASDCHK 0x00001000
392 #define WXEXCT_EE_RST 0x00002000
393 #define WXEXCT_IPS 0x00004000
394 #define WXEXCT_SPD_BYPS 0x00008000
397 * PHY access using GPIO pins
399 #define WXPHY_RESET_DIR WXDCR_SWDPIO0
400 #define WXPHY_RESET WXDCR_SWDPIN0
401 #define WXPHY_MDIO_DIR WXDCR_SWDPIO2
402 #define WXPHY_MDIO WXDCR_SWDPIN2
403 #define WXPHY_MDC_DIR WXDCR_SWDPIO3
404 #define WXPHY_MDC WXDCR_SWDPIN3
405 #define WXPHY_RESET_DIR4 WXEXCT_SWDPIO4
406 #define WXPHY_RESET4 WXEXCT_SWDPIN4
411 #define WXPHYC_PREAMBLE 0xFFFFFFFF
412 #define WXPHYC_PREAMBLE_LEN 32
413 #define WXPHYC_SOF 0x01
414 #define WXPHYC_READ 0x02
415 #define WXPHYC_WRITE 0x01
416 #define WXPHYC_TURNAROUND 0x02
419 * Receive Configuration Word defines
422 #define WXRXCW_CWMASK 0x0000ffff
423 #define WXRXCW_NC 0x04000000
424 #define WXRXCW_IV 0x08000000
425 #define WXRXCW_CC 0x10000000
426 #define WXRXCW_C 0x20000000
427 #define WXRXCW_SYNCH 0x40000000
428 #define WXRXCW_ANC 0x80000000
433 #define WX_EEPROM_MAC_OFF 0
436 * Offset for Initialization Control Word #1
438 #define WX_EEPROM_CTLR1_OFF 0xA
439 #define WX_EEPROM_CTLR1_FD (1 << 10)
440 #define WX_EEPROM_CTLR1_SWDPIO_SHIFT 5
441 #define WX_EEPROM_CTLR1_ILOS (1 << 4)
443 #define WX_EEPROM_CTLR2_OFF 0xF
444 #define WX_EEPROM_CTLR2_SWDPIO 0xF0
445 #define WX_EEPROM_EXT_SHIFT 4
448 #define WX_XTIMER_DFLT 0x100
449 #define WX_RCV_FLOW_HI_DFLT 0x8000
450 #define WX_RCV_FLOW_LO_DFLT 0x4000
452 #define WX_WISEMAN_TIPG_DFLT (10 | (2 << 10) | (10 << 20))
453 #define WX_LIVENGOOD_TIPG_DFLT (6 | (8 << 10) | (6 << 20))
454 #define WX_LIVENGOOD_CU_TIPG_DFLT (8 | (8 << 10) | (6 << 20))
456 #define WX_CRC_LENGTH 4
460 * Hardware cannot transmit less than 16 bytes. It also cannot
461 * successfully receive less than 60 bytes.
463 #define WX_MIN_XPKT_SIZE 16
464 #define WX_MIN_RPKT_SIZE 60
465 #define WX_MAX_PKT_SIZE 1514
466 #define WX_MAX_PKT_SIZE_JUMBO 9014