2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * from: @(#)comreg.h 7.2 (Berkeley) 5/9/91
34 * $FreeBSD: src/sys/isa/sioreg.h,v 1.15.2.3 2003/04/04 08:42:17 sobomax Exp $
35 * $DragonFly: src/sys/dev/serial/sio/sioreg.h,v 1.2 2003/06/17 04:28:40 dillon Exp $
38 /* Receiver clock frequency for "standard" pc serial ports. */
39 #define DEFAULT_RCLK 1843200
41 /* interrupt enable register */
42 #define IER_ERXRDY 0x1
43 #define IER_ETXRDY 0x2
47 /* interrupt identification register */
49 #define IIR_RXTOUT 0xc
53 #define IIR_NOPEND 0x1
55 #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
57 /* fifo control register */
58 #define FIFO_ENABLE 0x01
59 #define FIFO_RCV_RST 0x02
60 #define FIFO_XMT_RST 0x04
61 #define FIFO_DMA_MODE 0x08
62 #define FIFO_RX_LOW 0x00
63 #define FIFO_RX_MEDL 0x40
64 #define FIFO_RX_MEDH 0x80
65 #define FIFO_RX_HIGH 0xc0
67 /* character format control register (aka line control register) */
68 #define CFCR_DLAB 0x80
69 #define CFCR_SBREAK 0x40
70 #define CFCR_PZERO 0x30
71 #define CFCR_PONE 0x20
72 #define CFCR_PEVEN 0x10
73 #define CFCR_PODD 0x00
74 #define CFCR_PENAB 0x08
75 #define CFCR_STOPB 0x04
76 #define CFCR_8BITS 0x03
77 #define CFCR_7BITS 0x02
78 #define CFCR_6BITS 0x01
79 #define CFCR_5BITS 0x00
80 #define CFCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */
82 /* modem control register */
83 #define MCR_PRESCALE 0x80 /* only available on 16650 up */
84 #define MCR_LOOPBACK 0x10
85 #define MCR_IENABLE 0x08
90 /* line status register */
91 #define LSR_RCV_FIFO 0x80
93 #define LSR_TXRDY 0x20
98 #define LSR_RXRDY 0x01
99 #define LSR_RCV_MASK 0x1f
101 /* modem status register */
106 #define MSR_DDCD 0x08
107 #define MSR_TERI 0x04
108 #define MSR_DDSR 0x02
109 #define MSR_DCTS 0x01
111 /* enhanced feature register (only available on 16650 up) */
112 #define com_efr com_fifo
113 #define EFR_EFE 0x10 /* enhanced functions enable */
116 /* Hardware extension mode register for RSB-2000/3000. */
117 #define EMR_EXBUFF 0x04
118 #define EMR_CTSFLW 0x08
119 #define EMR_DSRFLW 0x10
120 #define EMR_RTSFLW 0x20
121 #define EMR_DTRFLW 0x40
122 #define EMR_EFMODE 0x80
125 /* speed to initialize to during chip tests */
126 #define SIO_TEST_SPEED 9600
128 /* default serial console speed if not set with sysctl or probed from boot */
130 #define CONSPEED 9600