2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/i386/i386/Attic/mp_machdep.c,v 1.2 2003/06/17 04:28:35 dillon Exp $
31 #include "opt_user_ldt.h"
34 #include <machine/smptests.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
43 #include <sys/sysctl.h>
44 #include <sys/malloc.h>
45 #include <sys/memrange.h>
47 #include <sys/dkstat.h>
49 #include <sys/cons.h> /* cngetc() */
52 #include <vm/vm_param.h>
54 #include <vm/vm_kern.h>
55 #include <vm/vm_extern.h>
58 #include <vm/vm_map.h>
65 #include <machine/smp.h>
66 #include <machine/apic.h>
67 #include <machine/atomic.h>
68 #include <machine/cpufunc.h>
69 #include <machine/mpapic.h>
70 #include <machine/psl.h>
71 #include <machine/segments.h>
72 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
73 #include <machine/tss.h>
74 #include <machine/specialreg.h>
75 #include <machine/globaldata.h>
78 #include <machine/md_var.h> /* setidt() */
79 #include <i386/isa/icu.h> /* IPIs */
80 #include <i386/isa/intr_machdep.h> /* IPIs */
83 #if defined(TEST_DEFAULT_CONFIG)
84 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
86 #define MPFPS_MPFB1 mpfps->mpfb1
87 #endif /* TEST_DEFAULT_CONFIG */
89 #define WARMBOOT_TARGET 0
90 #define WARMBOOT_OFF (KERNBASE + 0x0467)
91 #define WARMBOOT_SEG (KERNBASE + 0x0469)
94 #define BIOS_BASE (0xe8000)
95 #define BIOS_SIZE (0x18000)
97 #define BIOS_BASE (0xf0000)
98 #define BIOS_SIZE (0x10000)
100 #define BIOS_COUNT (BIOS_SIZE/4)
102 #define CMOS_REG (0x70)
103 #define CMOS_DATA (0x71)
104 #define BIOS_RESET (0x0f)
105 #define BIOS_WARM (0x0a)
107 #define PROCENTRY_FLAG_EN 0x01
108 #define PROCENTRY_FLAG_BP 0x02
109 #define IOAPICENTRY_FLAG_EN 0x01
112 /* MP Floating Pointer Structure */
113 typedef struct MPFPS {
126 /* MP Configuration Table Header */
127 typedef struct MPCTH {
129 u_short base_table_length;
133 u_char product_id[12];
134 void *oem_table_pointer;
135 u_short oem_table_size;
138 u_short extended_table_length;
139 u_char extended_table_checksum;
144 typedef struct PROCENTRY {
149 u_long cpu_signature;
150 u_long feature_flags;
155 typedef struct BUSENTRY {
161 typedef struct IOAPICENTRY {
167 } *io_apic_entry_ptr;
169 typedef struct INTENTRY {
179 /* descriptions of MP basetable entries */
180 typedef struct BASETABLE_ENTRY {
187 * this code MUST be enabled here and in mpboot.s.
188 * it follows the very early stages of AP boot by placing values in CMOS ram.
189 * it NORMALLY will never be needed and thus the primitive method for enabling.
194 #if defined(CHECK_POINTS) && !defined(PC98)
195 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
196 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
198 #define CHECK_INIT(D); \
199 CHECK_WRITE(0x34, (D)); \
200 CHECK_WRITE(0x35, (D)); \
201 CHECK_WRITE(0x36, (D)); \
202 CHECK_WRITE(0x37, (D)); \
203 CHECK_WRITE(0x38, (D)); \
204 CHECK_WRITE(0x39, (D));
206 #define CHECK_PRINT(S); \
207 printf("%s: %d, %d, %d, %d, %d, %d\n", \
216 #else /* CHECK_POINTS */
218 #define CHECK_INIT(D)
219 #define CHECK_PRINT(S)
221 #endif /* CHECK_POINTS */
224 * Values to send to the POST hardware.
226 #define MP_BOOTADDRESS_POST 0x10
227 #define MP_PROBE_POST 0x11
228 #define MPTABLE_PASS1_POST 0x12
230 #define MP_START_POST 0x13
231 #define MP_ENABLE_POST 0x14
232 #define MPTABLE_PASS2_POST 0x15
234 #define START_ALL_APS_POST 0x16
235 #define INSTALL_AP_TRAMP_POST 0x17
236 #define START_AP_POST 0x18
238 #define MP_ANNOUNCE_POST 0x19
241 static int need_hyperthreading_fixup;
242 static u_int logical_cpus;
245 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
246 int current_postcode;
248 /** XXX FIXME: what system files declare these??? */
249 extern struct region_descriptor r_gdt, r_idt;
251 int bsp_apic_ready = 0; /* flags useability of BSP apic */
252 int mp_ncpus; /* # of CPUs, including BSP */
253 int mp_naps; /* # of Applications processors */
254 int mp_nbusses; /* # of busses */
255 int mp_napics; /* # of IO APICs */
256 int boot_cpu_id; /* designated BSP */
257 vm_offset_t cpu_apic_address;
258 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
261 u_int32_t cpu_apic_versions[MAXCPU];
262 u_int32_t *io_apic_versions;
264 #ifdef APIC_INTR_DIAGNOSTIC
265 int apic_itrace_enter[32];
266 int apic_itrace_tryisrlock[32];
267 int apic_itrace_gotisrlock[32];
268 int apic_itrace_active[32];
269 int apic_itrace_masked[32];
270 int apic_itrace_noisrlock[32];
271 int apic_itrace_masked2[32];
272 int apic_itrace_unmask[32];
273 int apic_itrace_noforward[32];
274 int apic_itrace_leave[32];
275 int apic_itrace_enter2[32];
276 int apic_itrace_doreti[32];
277 int apic_itrace_splz[32];
278 int apic_itrace_eoi[32];
279 #ifdef APIC_INTR_DIAGNOSTIC_IRQ
280 unsigned short apic_itrace_debugbuffer[32768];
281 int apic_itrace_debugbuffer_idx;
282 struct simplelock apic_itrace_debuglock;
286 #ifdef APIC_INTR_REORDER
288 volatile int *location;
290 } apic_isrbit_location[32];
293 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
296 * APIC ID logical/physical mapping structures.
297 * We oversize these to simplify boot-time config.
299 int cpu_num_to_apic_id[NAPICID];
300 int io_num_to_apic_id[NAPICID];
301 int apic_id_to_logical[NAPICID];
304 /* Bitmap of all available CPUs */
307 /* AP uses this during bootstrap. Do not staticize. */
311 /* Hotwire a 0->4MB V==P mapping */
312 extern pt_entry_t *KPTphys;
314 /* SMP page table page */
315 extern pt_entry_t *SMPpt;
317 struct pcb stoppcbs[MAXCPU];
319 int smp_started; /* has the system started? */
322 * Local data and functions.
325 static int mp_capable;
326 static u_int boot_address;
327 static u_int base_memory;
329 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
330 static mpfps_t mpfps;
331 static int search_for_sig(u_int32_t target, int count);
332 static void mp_enable(u_int boot_addr);
335 static void mptable_hyperthread_fixup(u_int id_mask);
337 static void mptable_pass1(void);
338 static int mptable_pass2(void);
339 static void default_mp_table(int type);
340 static void fix_mp_table(void);
341 static void setup_apic_irq_mapping(void);
342 static void init_locks(void);
343 static int start_all_aps(u_int boot_addr);
344 static void install_ap_tramp(u_int boot_addr);
345 static int start_ap(int logicalCpu, u_int boot_addr);
346 static int apic_int_is_bus_type(int intr, int bus_type);
349 * Calculate usable address in base memory for AP trampoline code.
352 mp_bootaddress(u_int basemem)
354 POSTCODE(MP_BOOTADDRESS_POST);
356 base_memory = basemem * 1024; /* convert to bytes */
358 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
359 if ((base_memory - boot_address) < bootMP_size)
360 boot_address -= 4096; /* not enough, lower by 4k */
367 * Look for an Intel MP spec table (ie, SMP capable hardware).
376 POSTCODE(MP_PROBE_POST);
378 /* see if EBDA exists */
379 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
380 /* search first 1K of EBDA */
381 target = (u_int32_t) (segment << 4);
382 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
385 /* last 1K of base memory, effective 'top of base' passed in */
386 target = (u_int32_t) (base_memory - 0x400);
387 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
391 /* search the BIOS */
392 target = (u_int32_t) BIOS_BASE;
393 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
402 /* calculate needed resources */
406 /* flag fact that we are running multiple processors */
413 * Startup the SMP processors.
418 POSTCODE(MP_START_POST);
420 /* look for MP capable motherboard */
422 mp_enable(boot_address);
424 panic("MP hardware not found!");
429 * Print various information about the SMP system hardware and setup.
436 POSTCODE(MP_ANNOUNCE_POST);
438 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
439 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
440 printf(", version: 0x%08x", cpu_apic_versions[0]);
441 printf(", at 0x%08x\n", cpu_apic_address);
442 for (x = 1; x <= mp_naps; ++x) {
443 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
444 printf(", version: 0x%08x", cpu_apic_versions[x]);
445 printf(", at 0x%08x\n", cpu_apic_address);
449 for (x = 0; x < mp_napics; ++x) {
450 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
451 printf(", version: 0x%08x", io_apic_versions[x]);
452 printf(", at 0x%08x\n", io_apic_address[x]);
455 printf(" Warning: APIC I/O disabled\n");
460 * AP cpu's call this to sync up protected mode.
466 int x, myid = bootAP;
469 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid];
470 gdt_segs[GPROC0_SEL].ssd_base =
471 (int) &SMP_prvspace[myid].globaldata.gd_common_tss;
472 SMP_prvspace[myid].globaldata.gd_prvspace = &SMP_prvspace[myid];
474 for (x = 0; x < NGDT; x++) {
475 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
478 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
479 r_gdt.rd_base = (int) &gdt[myid * NGDT];
480 lgdt(&r_gdt); /* does magic intra-segment return */
486 currentldt = _default_ldt;
489 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
490 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
491 common_tss.tss_esp0 = 0; /* not used until after switch */
492 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
493 common_tss.tss_ioopt = (sizeof common_tss) << 16;
494 tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
495 common_tssd = *tss_gdt;
499 * Set to a known state:
500 * Set by mpboot.s: CR0_PG, CR0_PE
501 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
504 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
513 * Final configuration of the BSP's local APIC:
514 * - disable 'pic mode'.
515 * - disable 'virtual wire mode'.
519 bsp_apic_configure(void)
524 /* leave 'pic mode' if necessary */
526 outb(0x22, 0x70); /* select IMCR */
527 byte = inb(0x23); /* current contents */
528 byte |= 0x01; /* mask external INTR */
529 outb(0x23, byte); /* disconnect 8259s/NMI */
532 /* mask lint0 (the 8259 'virtual wire' connection) */
533 temp = lapic.lvt_lint0;
534 temp |= APIC_LVT_M; /* set the mask */
535 lapic.lvt_lint0 = temp;
537 /* setup lint1 to handle NMI */
538 temp = lapic.lvt_lint1;
539 temp &= ~APIC_LVT_M; /* clear the mask */
540 lapic.lvt_lint1 = temp;
543 apic_dump("bsp_apic_configure()");
548 /*******************************************************************
549 * local functions and data
553 * start the SMP system
556 mp_enable(u_int boot_addr)
564 POSTCODE(MP_ENABLE_POST);
566 /* turn on 4MB of V == P addressing so we can get to MP table */
567 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
570 /* examine the MP table for needed info, uses physical addresses */
576 /* can't process default configs till the CPU APIC is pmapped */
580 /* initialize all SMP locks */
583 /* post scan cleanup */
585 setup_apic_irq_mapping();
589 /* fill the LOGICAL io_apic_versions table */
590 for (apic = 0; apic < mp_napics; ++apic) {
591 ux = io_apic_read(apic, IOAPIC_VER);
592 io_apic_versions[apic] = ux;
593 io_apic_set_id(apic, IO_TO_ID(apic));
596 /* program each IO APIC in the system */
597 for (apic = 0; apic < mp_napics; ++apic)
598 if (io_apic_setup(apic) < 0)
599 panic("IO APIC setup failure");
601 /* install a 'Spurious INTerrupt' vector */
602 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
603 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
605 /* install an inter-CPU IPI for TLB invalidation */
606 setidt(XINVLTLB_OFFSET, Xinvltlb,
607 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
610 /* install an inter-CPU IPI for reading processor state */
611 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate,
612 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
615 /* install an inter-CPU IPI for all-CPU rendezvous */
616 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
617 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
619 /* install an inter-CPU IPI for forcing an additional software trap */
620 setidt(XCPUAST_OFFSET, Xcpuast,
621 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
623 /* install an inter-CPU IPI for interrupt forwarding */
624 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq,
625 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
627 /* install an inter-CPU IPI for CPU stop/restart */
628 setidt(XCPUSTOP_OFFSET, Xcpustop,
629 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
631 #if defined(TEST_TEST1)
632 /* install a "fake hardware INTerrupt" vector */
633 setidt(XTEST1_OFFSET, Xtest1,
634 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
635 #endif /** TEST_TEST1 */
639 /* start each Application Processor */
640 start_all_aps(boot_addr);
645 * look for the MP spec signature
648 /* string defined by the Intel MP Spec as identifying the MP table */
649 #define MP_SIG 0x5f504d5f /* _MP_ */
650 #define NEXT(X) ((X) += 4)
652 search_for_sig(u_int32_t target, int count)
655 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
657 for (x = 0; x < count; NEXT(x))
658 if (addr[x] == MP_SIG)
659 /* make array index a byte index */
660 return (target + (x * sizeof(u_int32_t)));
666 static basetable_entry basetable_entry_types[] =
668 {0, 20, "Processor"},
675 typedef struct BUSDATA {
677 enum busTypes bus_type;
680 typedef struct INTDATA {
690 typedef struct BUSTYPENAME {
695 static bus_type_name bus_type_table[] =
701 {UNKNOWN_BUSTYPE, "---"},
704 {UNKNOWN_BUSTYPE, "---"},
705 {UNKNOWN_BUSTYPE, "---"},
706 {UNKNOWN_BUSTYPE, "---"},
707 {UNKNOWN_BUSTYPE, "---"},
708 {UNKNOWN_BUSTYPE, "---"},
710 {UNKNOWN_BUSTYPE, "---"},
711 {UNKNOWN_BUSTYPE, "---"},
712 {UNKNOWN_BUSTYPE, "---"},
713 {UNKNOWN_BUSTYPE, "---"},
715 {UNKNOWN_BUSTYPE, "---"}
717 /* from MP spec v1.4, table 5-1 */
718 static int default_data[7][5] =
720 /* nbus, id0, type0, id1, type1 */
721 {1, 0, ISA, 255, 255},
722 {1, 0, EISA, 255, 255},
723 {1, 0, EISA, 255, 255},
724 {1, 0, MCA, 255, 255},
726 {2, 0, EISA, 1, PCI},
732 static bus_datum *bus_data;
734 /* the IO INT data, one entry per possible APIC INTerrupt */
735 static io_int *io_apic_ints;
739 static int processor_entry __P((proc_entry_ptr entry, int cpu));
740 static int bus_entry __P((bus_entry_ptr entry, int bus));
741 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic));
742 static int int_entry __P((int_entry_ptr entry, int intr));
743 static int lookup_bus_type __P((char *name));
747 * 1st pass on motherboard's Intel MP specification table.
753 * cpu_apic_address (common to all CPUs)
773 POSTCODE(MPTABLE_PASS1_POST);
775 /* clear various tables */
776 for (x = 0; x < NAPICID; ++x) {
777 io_apic_address[x] = ~0; /* IO APIC address table */
780 /* init everything to empty */
789 /* check for use of 'default' configuration */
790 if (MPFPS_MPFB1 != 0) {
791 /* use default addresses */
792 cpu_apic_address = DEFAULT_APIC_BASE;
793 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
795 /* fill in with defaults */
796 mp_naps = 2; /* includes BSP */
797 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
804 if ((cth = mpfps->pap) == 0)
805 panic("MP Configuration Table Header MISSING!");
807 cpu_apic_address = (vm_offset_t) cth->apic_address;
809 /* walk the table, recording info of interest */
810 totalSize = cth->base_table_length - sizeof(struct MPCTH);
811 position = (u_char *) cth + sizeof(struct MPCTH);
812 count = cth->entry_count;
815 switch (type = *(u_char *) position) {
816 case 0: /* processor_entry */
817 if (((proc_entry_ptr)position)->cpu_flags
818 & PROCENTRY_FLAG_EN) {
822 ((proc_entry_ptr)position)->apic_id;
826 case 1: /* bus_entry */
829 case 2: /* io_apic_entry */
830 if (((io_apic_entry_ptr)position)->apic_flags
831 & IOAPICENTRY_FLAG_EN)
832 io_apic_address[mp_napics++] =
833 (vm_offset_t)((io_apic_entry_ptr)
834 position)->apic_address;
836 case 3: /* int_entry */
839 case 4: /* int_entry */
842 panic("mpfps Base Table HOSED!");
846 totalSize -= basetable_entry_types[type].length;
847 (u_char*)position += basetable_entry_types[type].length;
851 /* qualify the numbers */
852 if (mp_naps > MAXCPU) {
853 printf("Warning: only using %d of %d available CPUs!\n",
859 /* See if we need to fixup HT logical CPUs. */
860 mptable_hyperthread_fixup(id_mask);
865 * This is also used as a counter while starting the APs.
869 --mp_naps; /* subtract the BSP */
874 * 2nd pass on motherboard's Intel MP specification table.
878 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
879 * CPU_TO_ID(N), logical CPU to APIC ID table
880 * IO_TO_ID(N), logical IO to APIC ID table
888 struct PROCENTRY proc;
896 int apic, bus, cpu, intr;
900 POSTCODE(MPTABLE_PASS2_POST);
903 /* Initialize fake proc entry for use with HT fixup. */
904 bzero(&proc, sizeof(proc));
906 proc.cpu_flags = PROCENTRY_FLAG_EN;
909 pgeflag = 0; /* XXX - Not used under SMP yet. */
911 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
913 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
915 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
917 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
920 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
922 for (i = 0; i < mp_napics; i++) {
923 for (j = 0; j < mp_napics; j++) {
924 /* same page frame as a previous IO apic? */
925 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
926 (io_apic_address[i] & PG_FRAME)) {
927 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
928 + (NPTEPG-2-j) * PAGE_SIZE
929 + (io_apic_address[i] & PAGE_MASK));
932 /* use this slot if available */
933 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
934 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
935 pgeflag | (io_apic_address[i] & PG_FRAME));
936 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
937 + (NPTEPG-2-j) * PAGE_SIZE
938 + (io_apic_address[i] & PAGE_MASK));
944 /* clear various tables */
945 for (x = 0; x < NAPICID; ++x) {
946 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
947 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
948 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
951 /* clear bus data table */
952 for (x = 0; x < mp_nbusses; ++x)
953 bus_data[x].bus_id = 0xff;
955 /* clear IO APIC INT table */
956 for (x = 0; x < (nintrs + 1); ++x) {
957 io_apic_ints[x].int_type = 0xff;
958 io_apic_ints[x].int_vector = 0xff;
961 /* setup the cpu/apic mapping arrays */
964 /* record whether PIC or virtual-wire mode */
965 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
967 /* check for use of 'default' configuration */
968 if (MPFPS_MPFB1 != 0)
969 return MPFPS_MPFB1; /* return default configuration type */
971 if ((cth = mpfps->pap) == 0)
972 panic("MP Configuration Table Header MISSING!");
974 /* walk the table, recording info of interest */
975 totalSize = cth->base_table_length - sizeof(struct MPCTH);
976 position = (u_char *) cth + sizeof(struct MPCTH);
977 count = cth->entry_count;
978 apic = bus = intr = 0;
979 cpu = 1; /* pre-count the BSP */
982 switch (type = *(u_char *) position) {
984 if (processor_entry(position, cpu))
988 if (need_hyperthreading_fixup) {
990 * Create fake mptable processor entries
991 * and feed them to processor_entry() to
992 * enumerate the logical CPUs.
994 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
995 for (i = 1; i < logical_cpus; i++) {
997 (void)processor_entry(&proc, cpu);
1004 if (bus_entry(position, bus))
1008 if (io_apic_entry(position, apic))
1012 if (int_entry(position, intr))
1016 /* int_entry(position); */
1019 panic("mpfps Base Table HOSED!");
1023 totalSize -= basetable_entry_types[type].length;
1024 (u_char *) position += basetable_entry_types[type].length;
1027 if (boot_cpu_id == -1)
1028 panic("NO BSP found!");
1030 /* report fact that its NOT a default configuration */
1036 * Check if we should perform a hyperthreading "fix-up" to
1037 * enumerate any logical CPU's that aren't already listed
1040 * XXX: We assume that all of the physical CPUs in the
1041 * system have the same number of logical CPUs.
1043 * XXX: We assume that APIC ID's are allocated such that
1044 * the APIC ID's for a physical processor are aligned
1045 * with the number of logical CPU's in the processor.
1048 mptable_hyperthread_fixup(u_int id_mask)
1052 /* Nothing to do if there is no HTT support. */
1053 if ((cpu_feature & CPUID_HTT) == 0)
1055 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1056 if (logical_cpus <= 1)
1060 * For each APIC ID of a CPU that is set in the mask,
1061 * scan the other candidate APIC ID's for this
1062 * physical processor. If any of those ID's are
1063 * already in the table, then kill the fixup.
1065 for (id = 0; id <= MAXCPU; id++) {
1066 if ((id_mask & 1 << id) == 0)
1068 /* First, make sure we are on a logical_cpus boundary. */
1069 if (id % logical_cpus != 0)
1071 for (i = id + 1; i < id + logical_cpus; i++)
1072 if ((id_mask & 1 << i) != 0)
1077 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1078 * mp_naps right now.
1080 need_hyperthreading_fixup = 1;
1081 mp_naps *= logical_cpus;
1086 assign_apic_irq(int apic, int intpin, int irq)
1090 if (int_to_apicintpin[irq].ioapic != -1)
1091 panic("assign_apic_irq: inconsistent table");
1093 int_to_apicintpin[irq].ioapic = apic;
1094 int_to_apicintpin[irq].int_pin = intpin;
1095 int_to_apicintpin[irq].apic_address = ioapic[apic];
1096 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1098 for (x = 0; x < nintrs; x++) {
1099 if ((io_apic_ints[x].int_type == 0 ||
1100 io_apic_ints[x].int_type == 3) &&
1101 io_apic_ints[x].int_vector == 0xff &&
1102 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1103 io_apic_ints[x].dst_apic_int == intpin)
1104 io_apic_ints[x].int_vector = irq;
1109 revoke_apic_irq(int irq)
1115 if (int_to_apicintpin[irq].ioapic == -1)
1116 panic("revoke_apic_irq: inconsistent table");
1118 oldapic = int_to_apicintpin[irq].ioapic;
1119 oldintpin = int_to_apicintpin[irq].int_pin;
1121 int_to_apicintpin[irq].ioapic = -1;
1122 int_to_apicintpin[irq].int_pin = 0;
1123 int_to_apicintpin[irq].apic_address = NULL;
1124 int_to_apicintpin[irq].redirindex = 0;
1126 for (x = 0; x < nintrs; x++) {
1127 if ((io_apic_ints[x].int_type == 0 ||
1128 io_apic_ints[x].int_type == 3) &&
1129 io_apic_ints[x].int_vector != 0xff &&
1130 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1131 io_apic_ints[x].dst_apic_int == oldintpin)
1132 io_apic_ints[x].int_vector = 0xff;
1138 allocate_apic_irq(int intr)
1144 if (io_apic_ints[intr].int_vector != 0xff)
1145 return; /* Interrupt handler already assigned */
1147 if (io_apic_ints[intr].int_type != 0 &&
1148 (io_apic_ints[intr].int_type != 3 ||
1149 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1150 io_apic_ints[intr].dst_apic_int == 0)))
1151 return; /* Not INT or ExtInt on != (0, 0) */
1154 while (irq < APIC_INTMAPSIZE &&
1155 int_to_apicintpin[irq].ioapic != -1)
1158 if (irq >= APIC_INTMAPSIZE)
1159 return; /* No free interrupt handlers */
1161 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1162 intpin = io_apic_ints[intr].dst_apic_int;
1164 assign_apic_irq(apic, intpin, irq);
1165 io_apic_setup_intpin(apic, intpin);
1170 swap_apic_id(int apic, int oldid, int newid)
1177 return; /* Nothing to do */
1179 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1180 apic, oldid, newid);
1182 /* Swap physical APIC IDs in interrupt entries */
1183 for (x = 0; x < nintrs; x++) {
1184 if (io_apic_ints[x].dst_apic_id == oldid)
1185 io_apic_ints[x].dst_apic_id = newid;
1186 else if (io_apic_ints[x].dst_apic_id == newid)
1187 io_apic_ints[x].dst_apic_id = oldid;
1190 /* Swap physical APIC IDs in IO_TO_ID mappings */
1191 for (oapic = 0; oapic < mp_napics; oapic++)
1192 if (IO_TO_ID(oapic) == newid)
1195 if (oapic < mp_napics) {
1196 printf("Changing APIC ID for IO APIC #%d from "
1197 "%d to %d in MP table\n",
1198 oapic, newid, oldid);
1199 IO_TO_ID(oapic) = oldid;
1201 IO_TO_ID(apic) = newid;
1206 fix_id_to_io_mapping(void)
1210 for (x = 0; x < NAPICID; x++)
1213 for (x = 0; x <= mp_naps; x++)
1214 if (CPU_TO_ID(x) < NAPICID)
1215 ID_TO_IO(CPU_TO_ID(x)) = x;
1217 for (x = 0; x < mp_napics; x++)
1218 if (IO_TO_ID(x) < NAPICID)
1219 ID_TO_IO(IO_TO_ID(x)) = x;
1224 first_free_apic_id(void)
1228 for (freeid = 0; freeid < NAPICID; freeid++) {
1229 for (x = 0; x <= mp_naps; x++)
1230 if (CPU_TO_ID(x) == freeid)
1234 for (x = 0; x < mp_napics; x++)
1235 if (IO_TO_ID(x) == freeid)
1246 io_apic_id_acceptable(int apic, int id)
1248 int cpu; /* Logical CPU number */
1249 int oapic; /* Logical IO APIC number for other IO APIC */
1252 return 0; /* Out of range */
1254 for (cpu = 0; cpu <= mp_naps; cpu++)
1255 if (CPU_TO_ID(cpu) == id)
1256 return 0; /* Conflict with CPU */
1258 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1259 if (IO_TO_ID(oapic) == id)
1260 return 0; /* Conflict with other APIC */
1262 return 1; /* ID is acceptable for IO APIC */
1267 * parse an Intel MP specification table
1274 int bus_0 = 0; /* Stop GCC warning */
1275 int bus_pci = 0; /* Stop GCC warning */
1277 int apic; /* IO APIC unit number */
1278 int freeid; /* Free physical APIC ID */
1279 int physid; /* Current physical IO APIC ID */
1282 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1283 * did it wrong. The MP spec says that when more than 1 PCI bus
1284 * exists the BIOS must begin with bus entries for the PCI bus and use
1285 * actual PCI bus numbering. This implies that when only 1 PCI bus
1286 * exists the BIOS can choose to ignore this ordering, and indeed many
1287 * MP motherboards do ignore it. This causes a problem when the PCI
1288 * sub-system makes requests of the MP sub-system based on PCI bus
1289 * numbers. So here we look for the situation and renumber the
1290 * busses and associated INTs in an effort to "make it right".
1293 /* find bus 0, PCI bus, count the number of PCI busses */
1294 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1295 if (bus_data[x].bus_id == 0) {
1298 if (bus_data[x].bus_type == PCI) {
1304 * bus_0 == slot of bus with ID of 0
1305 * bus_pci == slot of last PCI bus encountered
1308 /* check the 1 PCI bus case for sanity */
1309 /* if it is number 0 all is well */
1310 if (num_pci_bus == 1 &&
1311 bus_data[bus_pci].bus_id != 0) {
1313 /* mis-numbered, swap with whichever bus uses slot 0 */
1315 /* swap the bus entry types */
1316 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1317 bus_data[bus_0].bus_type = PCI;
1319 /* swap each relavant INTerrupt entry */
1320 id = bus_data[bus_pci].bus_id;
1321 for (x = 0; x < nintrs; ++x) {
1322 if (io_apic_ints[x].src_bus_id == id) {
1323 io_apic_ints[x].src_bus_id = 0;
1325 else if (io_apic_ints[x].src_bus_id == 0) {
1326 io_apic_ints[x].src_bus_id = id;
1331 /* Assign IO APIC IDs.
1333 * First try the existing ID. If a conflict is detected, try
1334 * the ID in the MP table. If a conflict is still detected, find
1337 * We cannot use the ID_TO_IO table before all conflicts has been
1338 * resolved and the table has been corrected.
1340 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1342 /* First try to use the value set by the BIOS */
1343 physid = io_apic_get_id(apic);
1344 if (io_apic_id_acceptable(apic, physid)) {
1345 if (IO_TO_ID(apic) != physid)
1346 swap_apic_id(apic, IO_TO_ID(apic), physid);
1350 /* Then check if the value in the MP table is acceptable */
1351 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1354 /* Last resort, find a free APIC ID and use it */
1355 freeid = first_free_apic_id();
1356 if (freeid >= NAPICID)
1357 panic("No free physical APIC IDs found");
1359 if (io_apic_id_acceptable(apic, freeid)) {
1360 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1363 panic("Free physical APIC ID not usable");
1365 fix_id_to_io_mapping();
1367 /* detect and fix broken Compaq MP table */
1368 if (apic_int_type(0, 0) == -1) {
1369 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1370 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1371 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1372 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1373 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1374 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1380 /* Assign low level interrupt handlers */
1382 setup_apic_irq_mapping(void)
1388 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1389 int_to_apicintpin[x].ioapic = -1;
1390 int_to_apicintpin[x].int_pin = 0;
1391 int_to_apicintpin[x].apic_address = NULL;
1392 int_to_apicintpin[x].redirindex = 0;
1395 /* First assign ISA/EISA interrupts */
1396 for (x = 0; x < nintrs; x++) {
1397 int_vector = io_apic_ints[x].src_bus_irq;
1398 if (int_vector < APIC_INTMAPSIZE &&
1399 io_apic_ints[x].int_vector == 0xff &&
1400 int_to_apicintpin[int_vector].ioapic == -1 &&
1401 (apic_int_is_bus_type(x, ISA) ||
1402 apic_int_is_bus_type(x, EISA)) &&
1403 io_apic_ints[x].int_type == 0) {
1404 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1405 io_apic_ints[x].dst_apic_int,
1410 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1411 for (x = 0; x < nintrs; x++) {
1412 if (io_apic_ints[x].dst_apic_int == 0 &&
1413 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1414 io_apic_ints[x].int_vector == 0xff &&
1415 int_to_apicintpin[0].ioapic == -1 &&
1416 io_apic_ints[x].int_type == 3) {
1417 assign_apic_irq(0, 0, 0);
1421 /* PCI interrupt assignment is deferred */
1426 processor_entry(proc_entry_ptr entry, int cpu)
1428 /* check for usability */
1429 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1432 if(entry->apic_id >= NAPICID)
1433 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1434 /* check for BSP flag */
1435 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1436 boot_cpu_id = entry->apic_id;
1437 CPU_TO_ID(0) = entry->apic_id;
1438 ID_TO_CPU(entry->apic_id) = 0;
1439 return 0; /* its already been counted */
1442 /* add another AP to list, if less than max number of CPUs */
1443 else if (cpu < MAXCPU) {
1444 CPU_TO_ID(cpu) = entry->apic_id;
1445 ID_TO_CPU(entry->apic_id) = cpu;
1454 bus_entry(bus_entry_ptr entry, int bus)
1459 /* encode the name into an index */
1460 for (x = 0; x < 6; ++x) {
1461 if ((c = entry->bus_type[x]) == ' ')
1467 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1468 panic("unknown bus type: '%s'", name);
1470 bus_data[bus].bus_id = entry->bus_id;
1471 bus_data[bus].bus_type = x;
1478 io_apic_entry(io_apic_entry_ptr entry, int apic)
1480 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1483 IO_TO_ID(apic) = entry->apic_id;
1484 if (entry->apic_id < NAPICID)
1485 ID_TO_IO(entry->apic_id) = apic;
1492 lookup_bus_type(char *name)
1496 for (x = 0; x < MAX_BUSTYPE; ++x)
1497 if (strcmp(bus_type_table[x].name, name) == 0)
1498 return bus_type_table[x].type;
1500 return UNKNOWN_BUSTYPE;
1505 int_entry(int_entry_ptr entry, int intr)
1509 io_apic_ints[intr].int_type = entry->int_type;
1510 io_apic_ints[intr].int_flags = entry->int_flags;
1511 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1512 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1513 if (entry->dst_apic_id == 255) {
1514 /* This signal goes to all IO APICS. Select an IO APIC
1515 with sufficient number of interrupt pins */
1516 for (apic = 0; apic < mp_napics; apic++)
1517 if (((io_apic_read(apic, IOAPIC_VER) &
1518 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1519 entry->dst_apic_int)
1521 if (apic < mp_napics)
1522 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1524 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1526 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1527 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1534 apic_int_is_bus_type(int intr, int bus_type)
1538 for (bus = 0; bus < mp_nbusses; ++bus)
1539 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1540 && ((int) bus_data[bus].bus_type == bus_type))
1548 * Given a traditional ISA INT mask, return an APIC mask.
1551 isa_apic_mask(u_int isa_mask)
1556 #if defined(SKIP_IRQ15_REDIRECT)
1557 if (isa_mask == (1 << 15)) {
1558 printf("skipping ISA IRQ15 redirect\n");
1561 #endif /* SKIP_IRQ15_REDIRECT */
1563 isa_irq = ffs(isa_mask); /* find its bit position */
1564 if (isa_irq == 0) /* doesn't exist */
1566 --isa_irq; /* make it zero based */
1568 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1572 return (1 << apic_pin); /* convert pin# to a mask */
1577 * Determine which APIC pin an ISA/EISA INT is attached to.
1579 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1580 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1581 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1582 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1584 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1586 isa_apic_irq(int isa_irq)
1590 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1591 if (INTTYPE(intr) == 0) { /* standard INT */
1592 if (SRCBUSIRQ(intr) == isa_irq) {
1593 if (apic_int_is_bus_type(intr, ISA) ||
1594 apic_int_is_bus_type(intr, EISA)) {
1595 if (INTIRQ(intr) == 0xff)
1596 return -1; /* unassigned */
1597 return INTIRQ(intr); /* found */
1602 return -1; /* NOT found */
1607 * Determine which APIC pin a PCI INT is attached to.
1609 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1610 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1611 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1613 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1617 --pciInt; /* zero based */
1619 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1620 if ((INTTYPE(intr) == 0) /* standard INT */
1621 && (SRCBUSID(intr) == pciBus)
1622 && (SRCBUSDEVICE(intr) == pciDevice)
1623 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1624 if (apic_int_is_bus_type(intr, PCI)) {
1625 if (INTIRQ(intr) == 0xff)
1626 allocate_apic_irq(intr);
1627 if (INTIRQ(intr) == 0xff)
1628 return -1; /* unassigned */
1629 return INTIRQ(intr); /* exact match */
1632 return -1; /* NOT found */
1636 next_apic_irq(int irq)
1643 for (intr = 0; intr < nintrs; intr++) {
1644 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1646 bus = SRCBUSID(intr);
1647 bustype = apic_bus_type(bus);
1648 if (bustype != ISA &&
1654 if (intr >= nintrs) {
1657 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1658 if (INTTYPE(ointr) != 0)
1660 if (bus != SRCBUSID(ointr))
1662 if (bustype == PCI) {
1663 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1665 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1668 if (bustype == ISA || bustype == EISA) {
1669 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1672 if (INTPIN(intr) == INTPIN(ointr))
1676 if (ointr >= nintrs) {
1679 return INTIRQ(ointr);
1693 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1696 * Exactly what this means is unclear at this point. It is a solution
1697 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1698 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1699 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1703 undirect_isa_irq(int rirq)
1707 printf("Freeing redirected ISA irq %d.\n", rirq);
1708 /** FIXME: tickle the MB redirector chip */
1712 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1719 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1722 undirect_pci_irq(int rirq)
1726 printf("Freeing redirected PCI irq %d.\n", rirq);
1728 /** FIXME: tickle the MB redirector chip */
1732 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1740 * given a bus ID, return:
1741 * the bus type if found
1745 apic_bus_type(int id)
1749 for (x = 0; x < mp_nbusses; ++x)
1750 if (bus_data[x].bus_id == id)
1751 return bus_data[x].bus_type;
1758 * given a LOGICAL APIC# and pin#, return:
1759 * the associated src bus ID if found
1763 apic_src_bus_id(int apic, int pin)
1767 /* search each of the possible INTerrupt sources */
1768 for (x = 0; x < nintrs; ++x)
1769 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1770 (pin == io_apic_ints[x].dst_apic_int))
1771 return (io_apic_ints[x].src_bus_id);
1773 return -1; /* NOT found */
1778 * given a LOGICAL APIC# and pin#, return:
1779 * the associated src bus IRQ if found
1783 apic_src_bus_irq(int apic, int pin)
1787 for (x = 0; x < nintrs; x++)
1788 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1789 (pin == io_apic_ints[x].dst_apic_int))
1790 return (io_apic_ints[x].src_bus_irq);
1792 return -1; /* NOT found */
1797 * given a LOGICAL APIC# and pin#, return:
1798 * the associated INTerrupt type if found
1802 apic_int_type(int apic, int pin)
1806 /* search each of the possible INTerrupt sources */
1807 for (x = 0; x < nintrs; ++x)
1808 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1809 (pin == io_apic_ints[x].dst_apic_int))
1810 return (io_apic_ints[x].int_type);
1812 return -1; /* NOT found */
1816 apic_irq(int apic, int pin)
1821 for (x = 0; x < nintrs; ++x)
1822 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1823 (pin == io_apic_ints[x].dst_apic_int)) {
1824 res = io_apic_ints[x].int_vector;
1827 if (apic != int_to_apicintpin[res].ioapic)
1828 panic("apic_irq: inconsistent table");
1829 if (pin != int_to_apicintpin[res].int_pin)
1830 panic("apic_irq inconsistent table (2)");
1838 * given a LOGICAL APIC# and pin#, return:
1839 * the associated trigger mode if found
1843 apic_trigger(int apic, int pin)
1847 /* search each of the possible INTerrupt sources */
1848 for (x = 0; x < nintrs; ++x)
1849 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1850 (pin == io_apic_ints[x].dst_apic_int))
1851 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1853 return -1; /* NOT found */
1858 * given a LOGICAL APIC# and pin#, return:
1859 * the associated 'active' level if found
1863 apic_polarity(int apic, int pin)
1867 /* search each of the possible INTerrupt sources */
1868 for (x = 0; x < nintrs; ++x)
1869 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1870 (pin == io_apic_ints[x].dst_apic_int))
1871 return (io_apic_ints[x].int_flags & 0x03);
1873 return -1; /* NOT found */
1878 * set data according to MP defaults
1879 * FIXME: probably not complete yet...
1882 default_mp_table(int type)
1885 #if defined(APIC_IO)
1888 #endif /* APIC_IO */
1891 printf(" MP default config type: %d\n", type);
1894 printf(" bus: ISA, APIC: 82489DX\n");
1897 printf(" bus: EISA, APIC: 82489DX\n");
1900 printf(" bus: EISA, APIC: 82489DX\n");
1903 printf(" bus: MCA, APIC: 82489DX\n");
1906 printf(" bus: ISA+PCI, APIC: Integrated\n");
1909 printf(" bus: EISA+PCI, APIC: Integrated\n");
1912 printf(" bus: MCA+PCI, APIC: Integrated\n");
1915 printf(" future type\n");
1921 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1922 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1925 CPU_TO_ID(0) = boot_cpu_id;
1926 ID_TO_CPU(boot_cpu_id) = 0;
1928 /* one and only AP */
1929 CPU_TO_ID(1) = ap_cpu_id;
1930 ID_TO_CPU(ap_cpu_id) = 1;
1932 #if defined(APIC_IO)
1933 /* one and only IO APIC */
1934 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1937 * sanity check, refer to MP spec section 3.6.6, last paragraph
1938 * necessary as some hardware isn't properly setting up the IO APIC
1940 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1941 if (io_apic_id != 2) {
1943 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1944 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1945 io_apic_set_id(0, 2);
1948 IO_TO_ID(0) = io_apic_id;
1949 ID_TO_IO(io_apic_id) = 0;
1950 #endif /* APIC_IO */
1952 /* fill out bus entries */
1961 bus_data[0].bus_id = default_data[type - 1][1];
1962 bus_data[0].bus_type = default_data[type - 1][2];
1963 bus_data[1].bus_id = default_data[type - 1][3];
1964 bus_data[1].bus_type = default_data[type - 1][4];
1967 /* case 4: case 7: MCA NOT supported */
1968 default: /* illegal/reserved */
1969 panic("BAD default MP config: %d", type);
1973 #if defined(APIC_IO)
1974 /* general cases from MP v1.4, table 5-2 */
1975 for (pin = 0; pin < 16; ++pin) {
1976 io_apic_ints[pin].int_type = 0;
1977 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1978 io_apic_ints[pin].src_bus_id = 0;
1979 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1980 io_apic_ints[pin].dst_apic_id = io_apic_id;
1981 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1984 /* special cases from MP v1.4, table 5-2 */
1986 io_apic_ints[2].int_type = 0xff; /* N/C */
1987 io_apic_ints[13].int_type = 0xff; /* N/C */
1988 #if !defined(APIC_MIXED_MODE)
1990 panic("sorry, can't support type 2 default yet");
1991 #endif /* APIC_MIXED_MODE */
1994 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1997 io_apic_ints[0].int_type = 0xff; /* N/C */
1999 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2000 #endif /* APIC_IO */
2005 * initialize all the SMP locks
2008 /* critical region around IO APIC, apic_imen */
2009 struct simplelock imen_lock;
2011 /* critical region around splxx(), cpl, cml, cil, ipending */
2012 struct simplelock cpl_lock;
2014 /* Make FAST_INTR() routines sequential */
2015 struct simplelock fast_intr_lock;
2017 /* critical region around INTR() routines */
2018 struct simplelock intr_lock;
2020 /* lock regions protected in UP kernel via cli/sti */
2021 struct simplelock mpintr_lock;
2023 /* lock region used by kernel profiling */
2024 struct simplelock mcount_lock;
2027 /* locks com (tty) data/hardware accesses: a FASTINTR() */
2028 struct simplelock com_lock;
2029 #endif /* USE_COMLOCK */
2031 #ifdef USE_CLOCKLOCK
2032 /* lock regions around the clock hardware */
2033 struct simplelock clock_lock;
2034 #endif /* USE_CLOCKLOCK */
2036 /* lock around the MP rendezvous */
2037 static struct simplelock smp_rv_lock;
2043 * Get the initial mp_lock with a count of 1 for the BSP.
2044 * This uses a LOGICAL cpu ID, ie BSP == 0.
2046 mp_lock = 0x00000001;
2049 /* ISR uses its own "giant lock" */
2050 isr_lock = FREE_LOCK;
2053 #if defined(APIC_INTR_DIAGNOSTIC) && defined(APIC_INTR_DIAGNOSTIC_IRQ)
2054 s_lock_init((struct simplelock*)&apic_itrace_debuglock);
2057 s_lock_init((struct simplelock*)&mpintr_lock);
2059 s_lock_init((struct simplelock*)&mcount_lock);
2061 s_lock_init((struct simplelock*)&fast_intr_lock);
2062 s_lock_init((struct simplelock*)&intr_lock);
2063 s_lock_init((struct simplelock*)&imen_lock);
2064 s_lock_init((struct simplelock*)&cpl_lock);
2065 s_lock_init(&smp_rv_lock);
2068 s_lock_init((struct simplelock*)&com_lock);
2069 #endif /* USE_COMLOCK */
2070 #ifdef USE_CLOCKLOCK
2071 s_lock_init((struct simplelock*)&clock_lock);
2072 #endif /* USE_CLOCKLOCK */
2076 /* Wait for all APs to be fully initialized */
2077 extern int wait_ap(unsigned int);
2080 * start each AP in our list
2083 start_all_aps(u_int boot_addr)
2086 u_char mpbiosreason;
2087 u_long mpbioswarmvec;
2088 struct globaldata *gd;
2092 POSTCODE(START_ALL_APS_POST);
2094 /* initialize BSP's local APIC */
2098 /* install the AP 1st level boot code */
2099 install_ap_tramp(boot_addr);
2102 /* save the current value of the warm-start vector */
2103 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2105 outb(CMOS_REG, BIOS_RESET);
2106 mpbiosreason = inb(CMOS_DATA);
2109 /* record BSP in CPU map */
2112 /* set up temporary P==V mapping for AP boot */
2113 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2114 kptbase = (uintptr_t)(void *)KPTphys;
2115 for (x = 0; x < NKPT; x++)
2116 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2117 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2121 for (x = 1; x <= mp_naps; ++x) {
2123 /* This is a bit verbose, it will go away soon. */
2125 /* first page of AP's private space */
2126 pg = x * i386_btop(sizeof(struct privatespace));
2128 /* allocate a new private data page */
2129 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
2131 /* wire it into the private page table page */
2132 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd));
2134 /* allocate and set up an idle stack data page */
2135 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
2136 for (i = 0; i < UPAGES; i++)
2137 SMPpt[pg + 5 + i] = (pt_entry_t)
2138 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
2140 SMPpt[pg + 1] = 0; /* *prv_CMAP1 */
2141 SMPpt[pg + 2] = 0; /* *prv_CMAP2 */
2142 SMPpt[pg + 3] = 0; /* *prv_CMAP3 */
2143 SMPpt[pg + 4] = 0; /* *prv_PMAP1 */
2145 /* prime data page for it to use */
2147 gd->gd_cpu_lockid = x << 24;
2148 gd->gd_prv_CMAP1 = &SMPpt[pg + 1];
2149 gd->gd_prv_CMAP2 = &SMPpt[pg + 2];
2150 gd->gd_prv_CMAP3 = &SMPpt[pg + 3];
2151 gd->gd_prv_PMAP1 = &SMPpt[pg + 4];
2152 gd->gd_prv_CADDR1 = SMP_prvspace[x].CPAGE1;
2153 gd->gd_prv_CADDR2 = SMP_prvspace[x].CPAGE2;
2154 gd->gd_prv_CADDR3 = SMP_prvspace[x].CPAGE3;
2155 gd->gd_prv_PADDR1 = (unsigned *)SMP_prvspace[x].PPAGE1;
2157 /* setup a vector to our boot code */
2158 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2159 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2161 outb(CMOS_REG, BIOS_RESET);
2162 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2165 bootSTK = &SMP_prvspace[x].idlestack[UPAGES*PAGE_SIZE];
2168 /* attempt to start the Application Processor */
2169 CHECK_INIT(99); /* setup checkpoints */
2170 if (!start_ap(x, boot_addr)) {
2171 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2172 CHECK_PRINT("trace"); /* show checkpoints */
2173 /* better panic as the AP may be running loose */
2174 printf("panic y/n? [y] ");
2175 if (cngetc() != 'n')
2178 CHECK_PRINT("trace"); /* show checkpoints */
2180 /* record its version info */
2181 cpu_apic_versions[x] = cpu_apic_versions[0];
2183 all_cpus |= (1 << x); /* record AP in CPU map */
2186 /* build our map of 'other' CPUs */
2187 other_cpus = all_cpus & ~(1 << cpuid);
2189 /* fill in our (BSP) APIC version */
2190 cpu_apic_versions[0] = lapic.version;
2192 /* restore the warmstart vector */
2193 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2195 outb(CMOS_REG, BIOS_RESET);
2196 outb(CMOS_DATA, mpbiosreason);
2200 * Set up the idle context for the BSP. Similar to above except
2201 * that some was done by locore, some by pmap.c and some is implicit
2202 * because the BSP is cpu#0 and the page is initially zero, and also
2203 * because we can refer to variables by name on the BSP..
2206 /* Allocate and setup BSP idle stack */
2207 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE);
2208 for (i = 0; i < UPAGES; i++)
2209 SMPpt[5 + i] = (pt_entry_t)
2210 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
2212 for (x = 0; x < NKPT; x++)
2216 /* number of APs actually started */
2217 return mp_ncpus - 1;
2222 * load the 1st level AP boot code into base memory.
2225 /* targets for relocation */
2226 extern void bigJump(void);
2227 extern void bootCodeSeg(void);
2228 extern void bootDataSeg(void);
2229 extern void MPentry(void);
2230 extern u_int MP_GDT;
2231 extern u_int mp_gdtbase;
2234 install_ap_tramp(u_int boot_addr)
2237 int size = *(int *) ((u_long) & bootMP_size);
2238 u_char *src = (u_char *) ((u_long) bootMP);
2239 u_char *dst = (u_char *) boot_addr + KERNBASE;
2240 u_int boot_base = (u_int) bootMP;
2245 POSTCODE(INSTALL_AP_TRAMP_POST);
2247 for (x = 0; x < size; ++x)
2251 * modify addresses in code we just moved to basemem. unfortunately we
2252 * need fairly detailed info about mpboot.s for this to work. changes
2253 * to mpboot.s might require changes here.
2256 /* boot code is located in KERNEL space */
2257 dst = (u_char *) boot_addr + KERNBASE;
2259 /* modify the lgdt arg */
2260 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2261 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2263 /* modify the ljmp target for MPentry() */
2264 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2265 *dst32 = ((u_int) MPentry - KERNBASE);
2267 /* modify the target for boot code segment */
2268 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2269 dst8 = (u_int8_t *) (dst16 + 1);
2270 *dst16 = (u_int) boot_addr & 0xffff;
2271 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2273 /* modify the target for boot data segment */
2274 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2275 dst8 = (u_int8_t *) (dst16 + 1);
2276 *dst16 = (u_int) boot_addr & 0xffff;
2277 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2282 * this function starts the AP (application processor) identified
2283 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2284 * to accomplish this. This is necessary because of the nuances
2285 * of the different hardware we might encounter. It ain't pretty,
2286 * but it seems to work.
2289 start_ap(int logical_cpu, u_int boot_addr)
2294 u_long icr_lo, icr_hi;
2296 POSTCODE(START_AP_POST);
2298 /* get the PHYSICAL APIC ID# */
2299 physical_cpu = CPU_TO_ID(logical_cpu);
2301 /* calculate the vector */
2302 vector = (boot_addr >> 12) & 0xff;
2304 /* used as a watchpoint to signal AP startup */
2308 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2309 * and running the target CPU. OR this INIT IPI might be latched (P5
2310 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2314 /* setup the address for the target AP */
2315 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2316 icr_hi |= (physical_cpu << 24);
2317 lapic.icr_hi = icr_hi;
2319 /* do an INIT IPI: assert RESET */
2320 icr_lo = lapic.icr_lo & 0xfff00000;
2321 lapic.icr_lo = icr_lo | 0x0000c500;
2323 /* wait for pending status end */
2324 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2327 /* do an INIT IPI: deassert RESET */
2328 lapic.icr_lo = icr_lo | 0x00008500;
2330 /* wait for pending status end */
2331 u_sleep(10000); /* wait ~10mS */
2332 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2336 * next we do a STARTUP IPI: the previous INIT IPI might still be
2337 * latched, (P5 bug) this 1st STARTUP would then terminate
2338 * immediately, and the previously started INIT IPI would continue. OR
2339 * the previous INIT IPI has already run. and this STARTUP IPI will
2340 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2344 /* do a STARTUP IPI */
2345 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2346 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2348 u_sleep(200); /* wait ~200uS */
2351 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2352 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2353 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2354 * recognized after hardware RESET or INIT IPI.
2357 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2358 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2360 u_sleep(200); /* wait ~200uS */
2362 /* wait for it to start */
2363 set_apic_timer(5000000);/* == 5 seconds */
2364 while (read_apic_timer())
2365 if (mp_ncpus > cpus)
2366 return 1; /* return SUCCESS */
2368 return 0; /* return FAILURE */
2373 * Flush the TLB on all other CPU's
2375 * XXX: Needs to handshake and wait for completion before proceding.
2380 #if defined(APIC_IO)
2381 if (smp_started && invltlb_ok)
2382 all_but_self_ipi(XINVLTLB_OFFSET);
2383 #endif /* APIC_IO */
2389 __asm __volatile("invlpg (%0)"::"r"(addr):"memory");
2391 /* send a message to the other CPUs */
2401 * This should be implemented as load_cr3(rcr3()) when load_cr3() is
2404 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory");
2406 /* send a message to the other CPUs */
2412 * When called the executing CPU will send an IPI to all other CPUs
2413 * requesting that they halt execution.
2415 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2417 * - Signals all CPUs in map to stop.
2418 * - Waits for each to stop.
2425 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2426 * from executing at same time.
2429 stop_cpus(u_int map)
2434 /* send the Xcpustop IPI to all CPUs in map */
2435 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2437 while ((stopped_cpus & map) != map)
2445 * Called by a CPU to restart stopped CPUs.
2447 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2449 * - Signals all CPUs in map to restart.
2450 * - Waits for each to restart.
2458 restart_cpus(u_int map)
2463 started_cpus = map; /* signal other cpus to restart */
2465 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2471 int smp_active = 0; /* are the APs allowed to run? */
2472 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, "");
2474 /* XXX maybe should be hw.ncpu */
2475 static int smp_cpus = 1; /* how many cpu's running */
2476 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, "");
2478 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
2479 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
2481 /* Warning: Do not staticize. Used from swtch.s */
2482 int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */
2483 SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW,
2484 &do_page_zero_idle, 0, "");
2486 /* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */
2487 int forward_irq_enabled = 1;
2488 SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW,
2489 &forward_irq_enabled, 0, "");
2491 /* Enable forwarding of a signal to a process running on a different CPU */
2492 static int forward_signal_enabled = 1;
2493 SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW,
2494 &forward_signal_enabled, 0, "");
2496 /* Enable forwarding of roundrobin to all other cpus */
2497 static int forward_roundrobin_enabled = 1;
2498 SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW,
2499 &forward_roundrobin_enabled, 0, "");
2502 * This is called once the rest of the system is up and running and we're
2503 * ready to let the AP's out of the pen.
2512 /* BSP may have changed PTD while we're waiting for the lock */
2517 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2521 /* Build our map of 'other' CPUs. */
2522 other_cpus = all_cpus & ~(1 << cpuid);
2524 printf("SMP: AP CPU #%d Launched!\n", cpuid);
2526 /* set up CPU registers and state */
2529 /* set up FPU state on the AP */
2530 npxinit(__INITIAL_NPXCW__);
2532 /* set up SSE registers */
2535 /* A quick check from sanity claus */
2536 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2537 if (cpuid != apic_id) {
2538 printf("SMP: cpuid = %d\n", cpuid);
2539 printf("SMP: apic_id = %d\n", apic_id);
2540 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2541 panic("cpuid mismatch! boom!!");
2544 /* Init local apic for irq's */
2547 /* Set memory range attributes for this CPU to match the BSP */
2548 mem_range_AP_init();
2551 * Activate smp_invltlb, although strictly speaking, this isn't
2552 * quite correct yet. We should have a bitfield for cpus willing
2553 * to accept TLB flush IPI's or something and sync them.
2555 if (smp_cpus == mp_ncpus) {
2557 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2558 smp_active = 1; /* historic */
2564 #define CHECKSTATE_USER 0
2565 #define CHECKSTATE_SYS 1
2566 #define CHECKSTATE_INTR 2
2568 /* Do not staticize. Used from apic_vector.s */
2569 struct proc* checkstate_curproc[MAXCPU];
2570 int checkstate_cpustate[MAXCPU];
2571 u_long checkstate_pc[MAXCPU];
2573 #define PC_TO_INDEX(pc, prof) \
2574 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \
2575 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1)
2578 addupc_intr_forwarded(struct proc *p, int id, int *astmap)
2584 pc = checkstate_pc[id];
2585 prof = &p->p_stats->p_prof;
2586 if (pc >= prof->pr_off &&
2587 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) {
2588 if ((p->p_flag & P_OWEUPC) == 0) {
2591 p->p_flag |= P_OWEUPC;
2593 *astmap |= (1 << id);
2598 forwarded_statclock(int id, int pscnt, int *astmap)
2600 struct pstats *pstats;
2607 register struct gmonparam *g;
2611 p = checkstate_curproc[id];
2612 cpustate = checkstate_cpustate[id];
2615 case CHECKSTATE_USER:
2616 if (p->p_flag & P_PROFIL)
2617 addupc_intr_forwarded(p, id, astmap);
2621 if (p->p_nice > NZERO)
2626 case CHECKSTATE_SYS:
2629 * Kernel statistics are just like addupc_intr, only easier.
2632 if (g->state == GMON_PROF_ON) {
2633 i = checkstate_pc[id] - g->lowpc;
2634 if (i < g->textsize) {
2635 i /= HISTFRACTION * sizeof(*g->kcount);
2650 case CHECKSTATE_INTR:
2654 * Kernel statistics are just like addupc_intr, only easier.
2657 if (g->state == GMON_PROF_ON) {
2658 i = checkstate_pc[id] - g->lowpc;
2659 if (i < g->textsize) {
2660 i /= HISTFRACTION * sizeof(*g->kcount);
2674 /* Update resource usage integrals and maximums. */
2675 if ((pstats = p->p_stats) != NULL &&
2676 (ru = &pstats->p_ru) != NULL &&
2677 (vm = p->p_vmspace) != NULL) {
2678 ru->ru_ixrss += pgtok(vm->vm_tsize);
2679 ru->ru_idrss += pgtok(vm->vm_dsize);
2680 ru->ru_isrss += pgtok(vm->vm_ssize);
2681 rss = pgtok(vmspace_resident_count(vm));
2682 if (ru->ru_maxrss < rss)
2683 ru->ru_maxrss = rss;
2689 forward_statclock(int pscnt)
2695 /* Kludge. We don't yet have separate locks for the interrupts
2696 * and the kernel. This means that we cannot let the other processors
2697 * handle complex interrupts while inhibiting them from entering
2698 * the kernel in a non-interrupt context.
2700 * What we can do, without changing the locking mechanisms yet,
2701 * is letting the other processors handle a very simple interrupt
2702 * (wich determines the processor states), and do the main
2706 if (!smp_started || !invltlb_ok || cold || panicstr)
2709 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */
2711 map = other_cpus & ~stopped_cpus ;
2712 checkstate_probed_cpus = 0;
2714 selected_apic_ipi(map,
2715 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2718 while (checkstate_probed_cpus != map) {
2722 #ifdef BETTER_CLOCK_DIAGNOSTIC
2723 printf("forward_statclock: checkstate %x\n",
2724 checkstate_probed_cpus);
2731 * Step 2: walk through other processors processes, update ticks and
2736 for (id = 0; id < mp_ncpus; id++) {
2739 if (((1 << id) & checkstate_probed_cpus) == 0)
2741 forwarded_statclock(id, pscnt, &map);
2744 checkstate_need_ast |= map;
2745 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2747 while ((checkstate_need_ast & map) != 0) {
2751 #ifdef BETTER_CLOCK_DIAGNOSTIC
2752 printf("forward_statclock: dropped ast 0x%x\n",
2753 checkstate_need_ast & map);
2762 forward_hardclock(int pscnt)
2767 struct pstats *pstats;
2770 /* Kludge. We don't yet have separate locks for the interrupts
2771 * and the kernel. This means that we cannot let the other processors
2772 * handle complex interrupts while inhibiting them from entering
2773 * the kernel in a non-interrupt context.
2775 * What we can do, without changing the locking mechanisms yet,
2776 * is letting the other processors handle a very simple interrupt
2777 * (wich determines the processor states), and do the main
2781 if (!smp_started || !invltlb_ok || cold || panicstr)
2784 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */
2786 map = other_cpus & ~stopped_cpus ;
2787 checkstate_probed_cpus = 0;
2789 selected_apic_ipi(map,
2790 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2793 while (checkstate_probed_cpus != map) {
2797 #ifdef BETTER_CLOCK_DIAGNOSTIC
2798 printf("forward_hardclock: checkstate %x\n",
2799 checkstate_probed_cpus);
2806 * Step 2: walk through other processors processes, update virtual
2807 * timer and profiling timer. If stathz == 0, also update ticks and
2812 for (id = 0; id < mp_ncpus; id++) {
2815 if (((1 << id) & checkstate_probed_cpus) == 0)
2817 p = checkstate_curproc[id];
2819 pstats = p->p_stats;
2820 if (checkstate_cpustate[id] == CHECKSTATE_USER &&
2821 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) &&
2822 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) {
2823 psignal(p, SIGVTALRM);
2826 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) &&
2827 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) {
2828 psignal(p, SIGPROF);
2833 forwarded_statclock( id, pscnt, &map);
2837 checkstate_need_ast |= map;
2838 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2840 while ((checkstate_need_ast & map) != 0) {
2844 #ifdef BETTER_CLOCK_DIAGNOSTIC
2845 printf("forward_hardclock: dropped ast 0x%x\n",
2846 checkstate_need_ast & map);
2854 #endif /* BETTER_CLOCK */
2857 forward_signal(struct proc *p)
2863 /* Kludge. We don't yet have separate locks for the interrupts
2864 * and the kernel. This means that we cannot let the other processors
2865 * handle complex interrupts while inhibiting them from entering
2866 * the kernel in a non-interrupt context.
2868 * What we can do, without changing the locking mechanisms yet,
2869 * is letting the other processors handle a very simple interrupt
2870 * (wich determines the processor states), and do the main
2874 if (!smp_started || !invltlb_ok || cold || panicstr)
2876 if (!forward_signal_enabled)
2879 if (p->p_stat != SRUN)
2885 checkstate_need_ast |= map;
2886 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2888 while ((checkstate_need_ast & map) != 0) {
2893 printf("forward_signal: dropped ast 0x%x\n",
2894 checkstate_need_ast & map);
2899 if (id == p->p_oncpu)
2905 forward_roundrobin(void)
2910 if (!smp_started || !invltlb_ok || cold || panicstr)
2912 if (!forward_roundrobin_enabled)
2914 resched_cpus |= other_cpus;
2915 map = other_cpus & ~stopped_cpus ;
2917 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2919 (void) all_but_self_ipi(XCPUAST_OFFSET);
2922 while ((checkstate_need_ast & map) != 0) {
2927 printf("forward_roundrobin: dropped ast 0x%x\n",
2928 checkstate_need_ast & map);
2936 #ifdef APIC_INTR_REORDER
2938 * Maintain mapping from softintr vector to isr bit in local apic.
2941 set_lapic_isrloc(int intr, int vector)
2943 if (intr < 0 || intr > 32)
2944 panic("set_apic_isrloc: bad intr argument: %d",intr);
2945 if (vector < ICU_OFFSET || vector > 255)
2946 panic("set_apic_isrloc: bad vector argument: %d",vector);
2947 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2948 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2953 * All-CPU rendezvous. CPUs are signalled, all execute the setup function
2954 * (if specified), rendezvous, execute the action function (if specified),
2955 * rendezvous again, execute the teardown function (if specified), and then
2958 * Note that the supplied external functions _must_ be reentrant and aware
2959 * that they are running in parallel and in an unknown lock context.
2961 static void (*smp_rv_setup_func)(void *arg);
2962 static void (*smp_rv_action_func)(void *arg);
2963 static void (*smp_rv_teardown_func)(void *arg);
2964 static void *smp_rv_func_arg;
2965 static volatile int smp_rv_waiters[2];
2968 smp_rendezvous_action(void)
2970 /* setup function */
2971 if (smp_rv_setup_func != NULL)
2972 smp_rv_setup_func(smp_rv_func_arg);
2973 /* spin on entry rendezvous */
2974 atomic_add_int(&smp_rv_waiters[0], 1);
2975 while (smp_rv_waiters[0] < mp_ncpus)
2977 /* action function */
2978 if (smp_rv_action_func != NULL)
2979 smp_rv_action_func(smp_rv_func_arg);
2980 /* spin on exit rendezvous */
2981 atomic_add_int(&smp_rv_waiters[1], 1);
2982 while (smp_rv_waiters[1] < mp_ncpus)
2984 /* teardown function */
2985 if (smp_rv_teardown_func != NULL)
2986 smp_rv_teardown_func(smp_rv_func_arg);
2990 smp_rendezvous(void (* setup_func)(void *),
2991 void (* action_func)(void *),
2992 void (* teardown_func)(void *),
2997 /* obtain rendezvous lock */
2998 s_lock(&smp_rv_lock); /* XXX sleep here? NOWAIT flag? */
3000 /* set static function pointers */
3001 smp_rv_setup_func = setup_func;
3002 smp_rv_action_func = action_func;
3003 smp_rv_teardown_func = teardown_func;
3004 smp_rv_func_arg = arg;
3005 smp_rv_waiters[0] = 0;
3006 smp_rv_waiters[1] = 0;
3008 /* disable interrupts on this CPU, save interrupt status */
3009 efl = read_eflags();
3010 write_eflags(efl & ~PSL_I);
3012 /* signal other processors, which will enter the IPI with interrupts off */
3013 all_but_self_ipi(XRENDEZVOUS_OFFSET);
3015 /* call executor function */
3016 smp_rendezvous_action();
3018 /* restore interrupt flag */
3022 s_unlock(&smp_rv_lock);