1 /*****************************************************************************/
4 * sc26198.h -- SC26198 UART hardware info.
6 * Copyright (c) 1995-1998 Greg Ungerer (gerg@stallion.oz.au).
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Greg Ungerer.
20 * 4. Neither the name of the author nor the names of any co-contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * $FreeBSD: src/sys/i386/isa/ic/sc26198.h,v 1.1.2.1 2001/08/30 12:29:55 murray Exp $
37 * $DragonFly: src/sys/i386/isa/ic/Attic/sc26198.h,v 1.2 2003/06/17 04:28:37 dillon Exp $
40 /*****************************************************************************/
43 /*****************************************************************************/
46 * Define the number of async ports per sc26198 uart device.
48 #define SC26198_PORTS 8
51 * Baud rate timing clocks. All derived from a master 14.7456 MHz clock.
53 #define SC26198_MASTERCLOCK 14745600L
54 #define SC26198_DCLK (SC26198_MASTERCLOCK)
55 #define SC26198_CCLK (SC26198_MASTERCLOCK / 2)
56 #define SC26198_BCLK (SC26198_MASTERCLOCK / 4)
59 * Define internal FIFO sizes for the 26198 ports.
61 #define SC26198_TXFIFOSIZE 16
62 #define SC26198_RXFIFOSIZE 16
64 /*****************************************************************************/
67 * Global register definitions. These registers are global to each 26198
68 * device, not specific ports on it.
94 * Per port channel registers. These are the register offsets within
95 * the port address space, so need to have the port address (0 to 7)
96 * inserted in bit positions 4:6.
122 * For any given port calculate the address to use to access a specified
123 * register. This is only used for unusual access...
125 #define SC26198_PORTREG(port,reg) ((((port) & 0x07) << 4) | (reg))
127 /*****************************************************************************/
130 * Global configuration control register bit definitions.
132 #define GCCR_NOACK 0x00
133 #define GCCR_IVRACK 0x02
134 #define GCCR_IVRCHANACK 0x04
135 #define GCCR_IVRTYPCHANACK 0x06
136 #define GCCR_ASYNCCYCLE 0x00
137 #define GCCR_SYNCCYCLE 0x40
139 /*****************************************************************************/
142 * Mode register 0 bit definitions.
144 #define MR0_ADDRNONE 0x00
145 #define MR0_AUTOWAKE 0x01
146 #define MR0_AUTODOZE 0x02
147 #define MR0_AUTOWAKEDOZE 0x03
148 #define MR0_SWFNONE 0x00
149 #define MR0_SWFTX 0x04
150 #define MR0_SWFRX 0x08
151 #define MR0_SWFRXTX 0x0c
152 #define MR0_TXMASK 0x30
153 #define MR0_TXEMPTY 0x00
154 #define MR0_TXHIGH 0x10
155 #define MR0_TXHALF 0x20
156 #define MR0_TXRDY 0x00
157 #define MR0_ADDRNT 0x00
158 #define MR0_ADDRT 0x40
159 #define MR0_SWFNT 0x00
160 #define MR0_SWFT 0x80
163 * Mode register 1 bit definitions.
169 #define MR1_PAREVEN 0x00
170 #define MR1_PARODD 0x04
171 #define MR1_PARENB 0x00
172 #define MR1_PARFORCE 0x08
173 #define MR1_PARNONE 0x10
174 #define MR1_PARSPECIAL 0x18
175 #define MR1_ERRCHAR 0x00
176 #define MR1_ERRBLOCK 0x20
177 #define MR1_ISRUNMASKED 0x00
178 #define MR1_ISRMASKED 0x40
179 #define MR1_AUTORTS 0x80
182 * Mode register 2 bit definitions.
184 #define MR2_STOP1 0x00
185 #define MR2_STOP15 0x01
186 #define MR2_STOP2 0x02
187 #define MR2_STOP916 0x03
188 #define MR2_RXFIFORDY 0x00
189 #define MR2_RXFIFOHALF 0x04
190 #define MR2_RXFIFOHIGH 0x08
191 #define MR2_RXFIFOFULL 0x0c
192 #define MR2_AUTOCTS 0x10
193 #define MR2_TXRTS 0x20
194 #define MR2_MODENORM 0x00
195 #define MR2_MODEAUTOECHO 0x40
196 #define MR2_MODELOOP 0x80
197 #define MR2_MODEREMECHO 0xc0
199 /*****************************************************************************/
202 * Baud Rate Generator (BRG) selector values.
212 #define BRG_1200 0x08
213 #define BRG_1800 0x09
214 #define BRG_2400 0x0a
215 #define BRG_3600 0x0b
216 #define BRG_4800 0x0c
217 #define BRG_7200 0x0d
218 #define BRG_9600 0x0e
219 #define BRG_14400 0x0f
220 #define BRG_19200 0x10
221 #define BRG_28200 0x11
222 #define BRG_38400 0x12
223 #define BRG_57600 0x13
224 #define BRG_115200 0x14
225 #define BRG_230400 0x15
226 #define BRG_GIN0 0x16
227 #define BRG_GIN1 0x17
230 #define BRG_RX2TX316 0x1b
231 #define BRG_RX2TX31 0x1c
233 /*****************************************************************************/
236 * Command register command definitions.
239 #define CR_ADDRNORMAL 0x0c
240 #define CR_RXRESET 0x14
241 #define CR_TXRESET 0x1c
242 #define CR_CLEARRXERR 0x24
243 #define CR_BREAKRESET 0x2c
244 #define CR_TXSTARTBREAK 0x34
245 #define CR_TXSTOPBREAK 0x3c
246 #define CR_RTSON 0x44
247 #define CR_RTSOFF 0x4c
248 #define CR_ADDRINIT 0x5c
249 #define CR_RXERRBLOCK 0x6c
250 #define CR_TXSENDXON 0x84
251 #define CR_TXSENDXOFF 0x8c
252 #define CR_GANGXONSET 0x94
253 #define CR_GANGXOFFSET 0x9c
254 #define CR_GANGXONINIT 0xa4
255 #define CR_GANGXOFFINIT 0xac
256 #define CR_HOSTXON 0xb4
257 #define CR_HOSTXOFF 0xbc
258 #define CR_CANCELXOFF 0xc4
259 #define CR_ADDRRESET 0xdc
260 #define CR_RESETALLPORTS 0xf4
261 #define CR_RESETALL 0xfc
263 #define CR_RXENABLE 0x01
264 #define CR_TXENABLE 0x02
266 /*****************************************************************************/
269 * Channel status register.
271 #define SR_RXRDY 0x01
272 #define SR_RXFULL 0x02
273 #define SR_TXRDY 0x04
274 #define SR_TXEMPTY 0x08
275 #define SR_RXOVERRUN 0x10
276 #define SR_RXPARITY 0x20
277 #define SR_RXFRAMING 0x40
278 #define SR_RXBREAK 0x80
280 #define SR_RXERRS (SR_RXPARITY | SR_RXFRAMING | SR_RXOVERRUN)
282 /*****************************************************************************/
285 * Interrupt status register and interrupt mask register bit definitions.
287 #define IR_TXRDY 0x01
288 #define IR_RXRDY 0x02
289 #define IR_RXBREAK 0x04
290 #define IR_XONXOFF 0x10
291 #define IR_ADDRRECOG 0x20
292 #define IR_RXWATCHDOG 0x40
293 #define IR_IOPORT 0x80
295 /*****************************************************************************/
298 * Interrupt vector register field definitions.
300 #define IVR_CHANMASK 0x07
301 #define IVR_TYPEMASK 0x18
302 #define IVR_CONSTMASK 0xc0
304 #define IVR_RXDATA 0x10
305 #define IVR_RXBADDATA 0x18
306 #define IVR_TXDATA 0x08
307 #define IVR_OTHER 0x00
309 /*****************************************************************************/
312 * BRG timer control register bit definitions.
314 #define BRGCTCR_DISABCLK0 0x00
315 #define BRGCTCR_ENABCLK0 0x08
316 #define BRGCTCR_DISABCLK1 0x00
317 #define BRGCTCR_ENABCLK1 0x80
319 #define BRGCTCR_0SCLK16 0x00
320 #define BRGCTCR_0SCLK32 0x01
321 #define BRGCTCR_0SCLK64 0x02
322 #define BRGCTCR_0SCLK128 0x03
323 #define BRGCTCR_0X1 0x04
324 #define BRGCTCR_0X12 0x05
325 #define BRGCTCR_0IO1A 0x06
326 #define BRGCTCR_0GIN0 0x07
328 #define BRGCTCR_1SCLK16 0x00
329 #define BRGCTCR_1SCLK32 0x10
330 #define BRGCTCR_1SCLK64 0x20
331 #define BRGCTCR_1SCLK128 0x30
332 #define BRGCTCR_1X1 0x40
333 #define BRGCTCR_1X12 0x50
334 #define BRGCTCR_1IO1B 0x60
335 #define BRGCTCR_1GIN1 0x70
337 /*****************************************************************************/
340 * Watch dog timer enable register.
342 #define WDTRCR_ENABALL 0xff
344 /*****************************************************************************/
347 * XON/XOFF interrupt status register.
349 #define XISR_TXCHARMASK 0x03
350 #define XISR_TXCHARNORMAL 0x00
351 #define XISR_TXWAIT 0x01
352 #define XISR_TXXOFFPEND 0x02
353 #define XISR_TXXONPEND 0x03
355 #define XISR_TXFLOWMASK 0x0c
356 #define XISR_TXNORMAL 0x00
357 #define XISR_TXSTOPPEND 0x04
358 #define XISR_TXSTARTED 0x08
359 #define XISR_TXSTOPPED 0x0c
361 #define XISR_RXFLOWMASK 0x30
362 #define XISR_RXFLOWNONE 0x00
363 #define XISR_RXXONSENT 0x10
364 #define XISR_RXXOFFSENT 0x20
366 #define XISR_RXXONGOT 0x40
367 #define XISR_RXXOFFGOT 0x80
369 /*****************************************************************************/
372 * Current interrupt register.
374 #define CIR_TYPEMASK 0xc0
375 #define CIR_TYPEOTHER 0x00
376 #define CIR_TYPETX 0x40
377 #define CIR_TYPERXGOOD 0x80
378 #define CIR_TYPERXBAD 0xc0
380 #define CIR_RXDATA 0x80
381 #define CIR_RXBADDATA 0x40
382 #define CIR_TXDATA 0x40
384 #define CIR_CHANMASK 0x07
385 #define CIR_CNTMASK 0x38
387 #define CIR_SUBTYPEMASK 0x38
388 #define CIR_SUBNONE 0x00
389 #define CIR_SUBCOS 0x08
390 #define CIR_SUBADDR 0x10
391 #define CIR_SUBXONXOFF 0x18
392 #define CIR_SUBBREAK 0x28
394 /*****************************************************************************/
397 * Global interrupting channel register.
399 #define GICR_CHANMASK 0x07
401 /*****************************************************************************/
404 * Global interrupting byte count register.
406 #define GICR_COUNTMASK 0x0f
408 /*****************************************************************************/
411 * Global interrupting type register.
413 #define GITR_RXMASK 0xc0
414 #define GITR_RXNONE 0x00
415 #define GITR_RXBADDATA 0x80
416 #define GITR_RXGOODDATA 0xc0
417 #define GITR_TXDATA 0x20
419 #define GITR_SUBTYPEMASK 0x07
420 #define GITR_SUBNONE 0x00
421 #define GITR_SUBCOS 0x01
422 #define GITR_SUBADDR 0x02
423 #define GITR_SUBXONXOFF 0x03
424 #define GITR_SUBBREAK 0x05
426 /*****************************************************************************/
429 * Input port change register.
435 #define IPR_CTSCHANGE 0x10
436 #define IPR_DTRCHANGE 0x20
437 #define IPR_RTSCHANGE 0x40
438 #define IPR_DCDCHANGE 0x80
440 #define IPR_CHANGEMASK 0xf0
442 /*****************************************************************************/
445 * IO port interrupt and output register.
447 #define IOPR_CTS 0x01
448 #define IOPR_DTR 0x02
449 #define IOPR_RTS 0x04
450 #define IOPR_DCD 0x08
451 #define IOPR_CTSCOS 0x10
452 #define IOPR_DTRCOS 0x20
453 #define IOPR_RTSCOS 0x40
454 #define IOPR_DCDCOS 0x80
456 /*****************************************************************************/
459 * IO port configuration register.
461 #define IOPCR_SETCTS 0x00
462 #define IOPCR_SETDTR 0x04
463 #define IOPCR_SETRTS 0x10
464 #define IOPCR_SETDCD 0x00
466 #define IOPCR_SETSIGS (IOPCR_SETRTS | IOPCR_SETRTS | IOPCR_SETDTR | IOPCR_SETDCD)
468 /*****************************************************************************/
471 * General purpose output select register.
473 #define GPORS_TXC1XA 0x08
474 #define GPORS_TXC16XA 0x09
475 #define GPORS_RXC16XA 0x0a
476 #define GPORS_TXC16XB 0x0b
477 #define GPORS_GPOR3 0x0c
478 #define GPORS_GPOR2 0x0d
479 #define GPORS_GPOR1 0x0e
480 #define GPORS_GPOR0 0x0f
482 /*****************************************************************************/
485 * General purpose output register.
492 /*****************************************************************************/
495 * General purpose output clock register.
497 #define GPORC_0NONE 0x00
498 #define GPORC_0GIN0 0x01
499 #define GPORC_0GIN1 0x02
500 #define GPORC_0IO3A 0x02
502 #define GPORC_1NONE 0x00
503 #define GPORC_1GIN0 0x04
504 #define GPORC_1GIN1 0x08
505 #define GPORC_1IO3C 0x0c
507 #define GPORC_2NONE 0x00
508 #define GPORC_2GIN0 0x10
509 #define GPORC_2GIN1 0x20
510 #define GPORC_2IO3E 0x20
512 #define GPORC_3NONE 0x00
513 #define GPORC_3GIN0 0x40
514 #define GPORC_3GIN1 0x80
515 #define GPORC_3IO3G 0xc0
517 /*****************************************************************************/
520 * General purpose output data register.
522 #define GPOD_0MASK 0x03
523 #define GPOD_0SET1 0x00
524 #define GPOD_0SET0 0x01
525 #define GPOD_0SETR0 0x02
526 #define GPOD_0SETIO3B 0x03
528 #define GPOD_1MASK 0x0c
529 #define GPOD_1SET1 0x00
530 #define GPOD_1SET0 0x04
531 #define GPOD_1SETR0 0x08
532 #define GPOD_1SETIO3D 0x0c
534 #define GPOD_2MASK 0x30
535 #define GPOD_2SET1 0x00
536 #define GPOD_2SET0 0x10
537 #define GPOD_2SETR0 0x20
538 #define GPOD_2SETIO3F 0x30
540 #define GPOD_3MASK 0xc0
541 #define GPOD_3SET1 0x00
542 #define GPOD_3SET0 0x40
543 #define GPOD_3SETR0 0x80
544 #define GPOD_3SETIO3H 0xc0
546 /*****************************************************************************/