2 * Copyright 1996 Massachusetts Institute of Technology
4 * Permission to use, copy, modify, and distribute this software and
5 * its documentation for any purpose and without fee is hereby
6 * granted, provided that both the above copyright notice and this
7 * permission notice appear in all copies, that both the above
8 * copyright notice and this permission notice appear in all
9 * supporting documentation, and that the name of M.I.T. not be used
10 * in advertising or publicity pertaining to distribution of the
11 * software without specific, written prior permission. M.I.T. makes
12 * no representations about the suitability of this software for any
13 * purpose. It is provided "as is" without express or implied
16 * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
17 * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
20 * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * $FreeBSD: src/sys/pci/ide_pci.c,v 1.42 2000/01/29 16:59:53 peter Exp $
30 * $DragonFly: src/sys/bus/pci/Attic/ide_pci.c,v 1.3 2003/08/07 21:16:47 dillon Exp $
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/kernel.h>
41 #include <dev/disk/wd/wdreg.h>
43 #include <pc98/pc98/pc98.h>
45 #include <bus/isa/i386/isa.h>
47 #include <bus/isa/i386/isa_device.h>
51 #include "ide_pcireg.h"
54 #define MIN(a,b) (((a)<(b))?(a):(b))
57 #define PROMISE_ULTRA33 0x4d33105a
58 #define CMD640B_PCI_ID 0x06401095
60 struct ide_pci_cookie; /* structs vendor_fns, ide_pci_cookie are recursive */
63 int (*vendor_dmainit) /* initialize DMA controller and drive */
64 (struct ide_pci_cookie *cookie,
66 int (*wdcmd)(int, void *),
69 void (*vendor_status) /* prints off DMA timing info */
70 (struct ide_pci_cookie *cookie);
74 * XXX the fact that this list keeps all kinds of info on PCI controllers
75 * is pretty grotty-- much of this should be replaced by a proper integration
76 * of PCI probes into the wd driver.
77 * XXX if we're going to support native-PCI controllers, we also need to
78 * keep the address of the IDE control block register, which is something wd.c
79 * needs to know, which is why this info is in the wrong place.
82 struct ide_pci_cookie {
83 LIST_ENTRY(ide_pci_cookie) le;
85 int ctlr; /* controller 0/1 on PCI IDE interface */
87 int iobase_bm; /* SFF-8038 control registers */
91 struct ide_pci_prd *prd;
95 struct ide_pci_softc {
96 LIST_HEAD(, ide_pci_cookie) cookies;
100 generic_dmainit(struct ide_pci_cookie *cookie,
102 int (*wdcmd)(int, void *),
106 generic_status(struct ide_pci_cookie *cookie);
109 sis_5591_dmainit(struct ide_pci_cookie *cookie,
111 int (*wdcmd)(int, void *),
115 sis_5591_status(struct ide_pci_cookie *cookie);
118 via_571_status(struct ide_pci_cookie *cookie);
121 via_571_dmainit(struct ide_pci_cookie *cookie,
123 int (*wdcmd)(int, void *),
127 acer_status(struct ide_pci_cookie *cookie);
130 acer_dmainit(struct ide_pci_cookie *cookie,
132 int (*wdcmd)(int, void *),
136 intel_piix_dump_drive(char *ctlr,
146 intel_piix_status(struct ide_pci_cookie *cookie);
148 intel_piix_dmainit(struct ide_pci_cookie *cookie,
150 int (*wdcmd)(int, void *),
153 static struct ide_pci_cookie *
154 mkcookie(int iobase_wd,
160 struct vendor_fns *vp,
165 static void ide_pci_attach(pcici_t tag, int unit);
166 static void *ide_pci_candma(int, int, int);
167 static int ide_pci_dmainit(void *,
169 int (*)(int, void *),
172 static int ide_pci_dmaverify(void *, char *, u_long, int);
173 static int ide_pci_dmasetup(void *, char *, u_long, int);
174 static void ide_pci_dmastart(void *);
175 static int ide_pci_dmadone(void *);
176 static int ide_pci_status(void *);
177 static int ide_pci_iobase(void *xcp);
178 static int ide_pci_altiobase(void *xcp);
180 static struct ide_pci_softc softc;
182 static int ide_pci_softc_cookies_initted = 0;
184 extern struct isa_driver wdcdriver;
187 * PRD_ALLOC_SIZE should be something that will not be allocated across a 64k
189 * PRD_MAX_SEGS is defined to be the maximum number of segments required for
190 * a transfer on an IDE drive, for an xfer that is linear in virtual memory.
191 * PRD_BUF_SIZE is the size of the buffer needed for a PRD table.
193 #define PRD_ALLOC_SIZE PAGE_SIZE
194 #define PRD_MAX_SEGS ((256 * 512 / PAGE_SIZE) + 1)
195 #define PRD_BUF_SIZE PRD_MAX_SEGS * 8
197 static void *prdbuf = 0;
198 static void *prdbuf_next = 0;
201 * Hardware specific IDE controller code. All vendor-specific code
202 * for handling IDE timing and other chipset peculiarities should be
209 * nnn_mode() return the highest valid mode, or -1 if the mode class is
214 pio_mode(struct wdparams *wp)
216 if ((wp->wdp_atavalid & 2) == 2) {
217 if ((wp->wdp_eidepiomodes & 2) == 2) return 4;
218 if ((wp->wdp_eidepiomodes & 1) == 1) return 3;
225 dma_mode(struct wdparams *wp)
227 /* XXX not quite sure how to verify validity on this field */
232 mwdma_mode(struct wdparams *wp)
235 * XXX technically, using wdp_atavalid to test for validity of
236 * this field is not quite correct
238 if ((wp->wdp_atavalid & 2) == 2) {
239 if ((wp->wdp_dmamword & 4) == 4) return 2;
240 if ((wp->wdp_dmamword & 2) == 2) return 1;
241 if ((wp->wdp_dmamword & 1) == 1) return 0;
247 udma_mode(struct wdparams *wp)
249 if ((wp->wdp_atavalid & 4) == 4) {
250 if ((wp->wdp_udmamode & 4) == 4) return 2;
251 if ((wp->wdp_udmamode & 2) == 2) return 1;
252 if ((wp->wdp_udmamode & 1) == 1) return 0;
258 /* Generic busmastering PCI-IDE */
261 generic_dmainit(struct ide_pci_cookie *cookie,
263 int(*wdcmd)(int, void *),
267 * punt on the whole timing issue by looking for either a
268 * drive programmed for both PIO4 and mDMA2 (which use similar
269 * timing) or a drive in an UltraDMA mode (hopefully all
270 * controllers have separate timing for UDMA). one hopes that if
271 * the drive's DMA mode has been configured by the BIOS, the
272 * controller's has also.
274 * XXX there are examples where this approach is now known to be
275 * broken, at least on systems based on Intel chipsets.
278 if ((pio_mode(wp) >= 4 && mwdma_mode(wp) >= 2) ||
279 (udma_mode(wp) >= 2)) {
280 printf("ide_pci: generic_dmainit %04x:%d: warning, IDE controller timing not set\n",
283 /* If we're here, then this controller is most likely not set
284 for UDMA, even if the drive may be. Make the drive wise
287 if(!wdcmd(WDDMA_MDMA2, wdinfo))
288 printf("generic_dmainit: could not set multiword DMA mode!\n");
292 printf("pio_mode: %d, mwdma_mode(wp): %d, udma_mode(wp): %d\n",
293 pio_mode(wp), mwdma_mode(wp), udma_mode(wp));
299 generic_status(struct ide_pci_cookie *cookie)
301 printf("generic_status: no PCI IDE timing info available\n");
304 static struct vendor_fns vs_generic =
310 /* VIA Technologies "82C571" PCI-IDE controller core */
313 via_571_status(struct ide_pci_cookie *cookie)
323 iobase_wd = cookie->iobase_wd;
326 iobase_bm = cookie->iobase_bm;
330 unitno = ctlr * 2 + unit;
332 for (i=0; i<5; i++) {
333 word40[i] = pci_conf_read(tag, i * 4 + 0x40);
337 printf("via_571_status: Primary IDE prefetch/postwrite %s/%s\n",
338 word40[0] & 0x8000 ? "enabled" : "disabled",
339 word40[0] & 0x4000 ? "enabled" : "disabled");
341 printf("via_571_status: Secondary IDE prefetch/postwrite %s/%s\n",
342 word40[0] & 0x2000 ? "enabled" : "disabled",
343 word40[0] & 0x1000 ? "enabled" : "disabled");
345 printf("via_571_status: busmaster status read retry %s\n",
346 (word40[1] & 0x08) ? "enabled" : "disabled");
349 printf("via_571_status: %s drive %d data setup=%d active=%d recovery=%d\n",
350 unitno < 2 ? "primary" : "secondary",
352 ((u_int)(word40[3] >> ((3 - unitno) * 2)) & 3) + 1,
353 ((u_int)(word40[2] >> (((3 - unitno) * 8) + 4)) & 0x0f) + 1,
354 ((u_int)(word40[2] >> ((3 - unitno) * 8)) & 0x0f) + 1);
357 printf("via_571_status: primary ctrl active=%d recovery=%d\n",
358 ((u_int)(word40[3] >> 28) & 0x0f) + 1,
359 ((u_int)(word40[2] >> 24) & 0x0f) + 1);
361 printf("via_571_status: secondary ctrl active=%d recovery=%d\n",
362 ((u_int)(word40[3] >> 20) & 0x0f) + 1,
363 ((u_int)(word40[2] >> 16) & 0x0f) + 1);
369 foo = word40[4] >> ((3 - unitno) * 8);
370 printf("via_571_status: %s drive %d udma method=%d enable=%d PIOmode=%d cycle=%d\n",
371 i < 2 ? "primary" : "secondary",
381 * XXX timing values set here are only good for 30/33MHz buses; should deal
382 * with slower ones too (BTW: you overclock-- you lose)
386 via_571_dmainit(struct ide_pci_cookie *cookie,
388 int(*wdcmd)(int, void *),
394 pci_revision = pci_conf_read(cookie->tag, PCI_CLASS_REG) &
397 unitno = cookie->ctlr * 2 + cookie->unit;
399 /* If it's a UDMA drive on a '590, set it up */
401 * XXX the revision number we check for is of dubious validity.
402 * it's extracted from the AMD 645 datasheet.
404 if (pci_revision >= 1 && udma_mode(wp) >= 2) {
405 unsigned int word50, mask, new;
406 word50 = pci_conf_read(cookie->tag, 0x50);
408 /* UDMA enable by SET FEATURES, DMA cycles, cycle time 2T */
409 mask = 0xe3000000 >> (unitno * 8);
410 new = 0x40000000 >> (unitno * 8);
415 pci_conf_write(cookie->tag, 0x50, word50);
418 * With the '590, drive configuration should come *after* the
419 * controller configuration, to make sure the controller sees
420 * the SET FEATURES command and does the right thing.
422 /* Set UDMA mode 2 on drive */
424 printf("via_571_dmainit: setting ultra DMA mode 2\n");
425 if (!wdcmd(WDDMA_UDMA2, wdinfo)) {
426 printf("via_571_dmainit: setting DMA mode failed\n");
431 via_571_status(cookie);
436 /* otherwise, try and program it for MW DMA mode 2 */
437 else if (mwdma_mode(wp) >= 2 && pio_mode(wp) >= 4) {
440 /* Set multiword DMA mode 2 on drive */
442 printf("via_571_dmainit: setting multiword DMA mode 2\n");
443 if (!wdcmd(WDDMA_MDMA2, wdinfo)) {
444 printf("via_571_dmainit: setting DMA mode failed\n");
448 /* Configure the controller appropriately for MWDMA mode 2 */
450 workword = pci_conf_read(cookie->tag, 0x40);
453 * enable prefetch/postwrite-- XXX may cause problems
456 workword |= 0xc000 >> (cookie->ctlr * 2);
458 /* FIFO configurations-- equal split, threshold 1/2 */
459 workword &= 0x90ffffff;
460 workword |= 0x2a000000;
462 pci_conf_write(cookie->tag, 0x40, workword);
464 workword = pci_conf_read(cookie->tag, 0x44);
466 /* enable status read retry */
469 /* enable FIFO flush on interrupt and end of sector */
470 workword &= 0xff0cffff;
471 workword |= 0x00f00000;
472 pci_conf_write(cookie->tag, 0x44, workword);
474 workword = pci_conf_read(cookie->tag, 0x48);
475 /* set Mode2 timing */
476 workword &= ~(0xff000000 >> (unitno * 8));
477 workword |= 0x31000000 >> (unitno * 8);
478 pci_conf_write(cookie->tag, 0x48, workword);
480 /* set sector size */
481 pci_conf_write(cookie->tag, cookie->ctlr ? 0x68 : 0x60, 0x200);
484 via_571_status(cookie);
493 static struct vendor_fns vs_via_571 =
499 /* Cyrix Cx5530 Courtesy of Whistle Communications */
502 * Verify that controller can handle a dma request for cp. Should
503 * not affect any hardware or driver state.
504 * Special version for 5530 that allows only transfers on 16 byte boundaries.(!)
505 * (Yes the Cyrix 5530 can only UDMA to cache-line boundaries.(bleh!))
506 * Luckily nearly all disk IO is to kernel bufers which are page alligned.
507 * They may fix this in some other version of the chip, but it's in the latest
508 * at this time (Jan 1999).
511 cyrix_5530_dmaverify(void *xcp, char *vaddr, u_long count, int dir)
516 * check for nonaligned or odd-length Stuff
518 badfu = ((unsigned int)vaddr & 0xf) || (count & 0xf);
521 printf("ide_pci: dmaverify odd vaddr or length, ");
522 printf("vaddr = %p length = %08lx\n", (void *)vaddr, count);
529 * XXX Unit number handling may be broken in the Cx5530 modules.
530 * It has only been checked with a single drive.
531 * 12MByte/Sec transfer rates were seen with Quantum Fireball drives
532 * with negligable CPU usage.
535 cyrix_5530_status(struct ide_pci_cookie *cookie)
546 iobase_wd = cookie->iobase_wd;
549 iobase_bm = cookie->iobase_bm;
553 unitno = ctlr * 2 + unit;
555 PIO_config = inl(iobase_bm + (unit * 0x10) + 0x20);
556 DMA_config = inl(iobase_bm + (unit * 0x10) + 0x24);
559 printf("cyrix_5530_status: %s:%u IDE PIO cfg: 0x%08lx\n",
560 (ctlr ? "Secondary" : "Primary"), unit, PIO_config);
561 printf("cyrix_5530_status: %s:%u IDE DMA cfg: 0x%08lx\n",
562 (ctlr ? "Secondary" : "Primary"), unit, DMA_config);
566 * XXX timing values set here are only good for 30/33MHz buses; should deal
567 * with slower ones too (BTW: you overclock-- you lose)
571 cyrix_5530_dmainit(struct ide_pci_cookie *cookie,
573 int(*wdcmd)(int, void *),
584 /*cookie->unit = 0; */ /* XXX */
586 pci_revision = pci_conf_read(cookie->tag, PCI_CLASS_REG) &
589 unitno = cookie->ctlr * 2 + unit;
590 iobase_bm = cookie->iobase_bm;
592 printf("Setting using 0x%x\n", iobase_bm);
593 if ((cookie->ctlr == 0) && (unit == 0)) /* XXX */
594 outb(iobase_bm + (unit * 0x10) + BMISTA_PORT, 0xe6);
595 /* If it's a UDMA drive on a '5530, set it up */
597 * depending on what the drive can do,
598 * set the correct modes,
600 printf("wd%d: mw=0x%x, pio=0x%x, pcirev=0x%lx, udma=0x%x\n",
602 mwdma_mode(wp), pio_mode(wp),
603 pci_revision, udma_mode(wp));
604 if (/* pci_revision >= 1 && */ udma_mode(wp) >= 0) {
605 switch(udma_mode(wp)) {
608 drivemode = WDDMA_UDMA0;
611 default: /* newer modes not supported */
615 * XXX The 5530 can do mode 2 but if you do use it, it will block all
616 * access to the PCI bus (and thus the ISA bus, PICs, PIT, etc. etc.) until the
617 * transfer is complete. Mode 2 swamps the 5530 so much it can't really cope
618 * with any other operations. Therefore, use mode 1 for drives that can
619 * do mode 2 (or more). (FALL THROUGH)
624 drivemode = WDDMA_UDMA2;
630 drivemode = WDDMA_UDMA1;
635 * With the Cx5530, drive configuration
636 * should come *after* the controller configuration,
637 * to make sure the controller sees
638 * the command and does the right thing.
640 /* Set UDMA mode on drive */
642 printf("cyrix_5530_dmainit: set UDMA mode %d\n", mode);
643 outl(iobase_bm+0x24 + (unit * 16), regval);
644 if (!wdcmd(drivemode, wdinfo)) {
645 printf("cyrix_5530_dmainit: setting DMA mode failed\n");
650 cyrix_5530_status(cookie);
655 /* otherwise, try and program it for MW DMA mode 2 */
656 else if (mwdma_mode(wp) >= 0 && pio_mode(wp) >= 4) {
658 switch(mwdma_mode(wp)) {
661 drivemode = WDDMA_MDMA0;
666 drivemode = WDDMA_MDMA1;
669 default: /* newer modes not supported */
672 drivemode = WDDMA_MDMA2;
677 /* Set multiword DMA mode 2 on drive */
679 printf("cyrix_5530_dmainit: multiword DMA mode %d\n",
681 if (!wdcmd(drivemode, wdinfo)) {
682 printf("cyrix_5530_dmainit: setting DMA mode failed\n");
686 /* Configure the controller appropriately for MWDMA mode */
688 outl(iobase_bm + 0x24 + (unit * 16), regval);
691 cyrix_5530_status(cookie);
697 * Always set the PIO mode values.
699 switch(pio_mode(wp)) {
702 drivemode = WDDMA_MDMA0;
707 drivemode = WDDMA_MDMA1;
712 drivemode = WDDMA_MDMA1;
717 drivemode = WDDMA_MDMA1;
720 default: /* newer modes not supported */
723 drivemode = WDDMA_MDMA2;
728 outl(iobase_bm + 0x20 + (unit * 16), regval);
729 printf("cyrix_5530_dmainit: setting PIO mode %d\n", mode);
734 static struct vendor_fns vs_cyrix_5530 =
742 promise_status(struct ide_pci_cookie *cookie)
746 u_int32_t port0_command, port0_altstatus;
747 u_int32_t port1_command, port1_altstatus;
750 u_int32_t lat_and_interrupt;
751 u_int32_t drivetiming;
755 port0_command = pci_conf_read(tag, 0x10);
756 port0_altstatus = pci_conf_read(tag, 0x14);
757 port1_command = pci_conf_read(tag, 0x18);
758 port1_altstatus = pci_conf_read(tag, 0x1c);
760 dma_block = pci_conf_read(tag, 0x20);
761 lat_and_interrupt = pci_conf_read(tag, 0x3c);
763 printf("promise_status: port0: 0x%lx, port0_alt: 0x%lx, port1: 0x%lx, port1_alt: 0x%lx\n",
764 (u_long)port0_command, (u_long)port0_altstatus, (u_long)port1_command,
765 (u_long)port1_altstatus);
767 "promise_status: dma control blk address: 0x%lx, int: %d, irq: %d\n",
768 (u_long)dma_block, (u_int)(lat_and_interrupt >> 8) & 0xff,
769 (u_int)lat_and_interrupt & 0xff);
772 drivetiming = pci_conf_read(tag, 0x60 + i * 4);
773 printf("drivebits%d-%d: %b\n", i, i+1, drivetiming,
774 "\020\05Prefetch\06Iordy\07Errdy\010Sync\025DmaW\026DmaR");
775 pa = drivetiming & 0xf;
776 pb = (drivetiming >> 8) & 0x1f;
777 mb = (drivetiming >> 13) & 0x7;
778 mc = (drivetiming >> 16) & 0xf;
779 printf("drivetiming%d: pa: 0x%x, pb: 0x%x, mb: 0x%x, mc: 0x%x\n",
782 drivetiming = pci_conf_read(tag, 0x60 + (i + 1) * 4);
783 pa = drivetiming & 0xf;
784 pb = (drivetiming >> 8) & 0x1f;
785 mb = (drivetiming >> 13) & 0x7;
786 mc = (drivetiming >> 16) & 0xf;
787 printf("drivetiming%d: pa: 0x%x, pb: 0x%x, mb: 0x%x, mc: 0x%x\n",
788 i + 1, pa, pb, mb, mc);
792 static struct vendor_fns vs_promise =
798 /* Intel PIIX, PIIX3, and PIIX4 IDE controller subfunctions */
800 intel_piix_dump_drive(char *ctlr,
818 printf("intel_piix_status: %s %s sample = %d, %s recovery = %d\n",
821 5 - ((sitre && drive) ?
822 ((word44 >> 2) & 3) :
823 ((word40 >> 12) & 3)),
825 4 - ((sitre && drive) ?
826 ((word44 >> 0) & 3) :
827 ((word40 >> 8) & 3)));
829 word40 >>= (drive * 4);
830 printf("intel_piix_status: %s %s fastDMAonly %s, pre/post %s,\n\
831 intel_piix_status: IORDY sampling %s,\n\
832 intel_piix_status: fast PIO %s%s\n",
834 (drive == 0) ? "master" : "slave",
835 (word40 & 8) ? "enabled" : "disabled",
836 (word40 & 4) ? "enabled" : "disabled",
837 (word40 & 2) ? "enabled" : "disabled",
838 (word40 & 1) ? "enabled" : "disabled",
839 ((word40 & 9) == 9) ? " (overridden by fastDMAonly)" : "" );
842 printf("intel_piix_status: UltraDMA %s, CT/RP = %d/%d\n",
843 word48 ? "enabled": "disabled",
849 intel_piix_status(struct ide_pci_cookie *cookie)
857 u_long word40, word44, word48;
860 iobase_wd = cookie->iobase_wd;
862 iobase_bm = cookie->iobase_bm;
867 word40 = pci_conf_read(tag, 0x40);
868 word44 = pci_conf_read(tag, 0x44);
869 word48 = pci_conf_read(tag, 0x48);
872 * XXX will not be right for the *next* generation of upward-compatible
873 * intel IDE controllers...
875 is_piix4 = pci_conf_read(tag, PCI_CLASS_REG) == 0x71118086;
877 sitre = word40 & 0x4000;
879 switch (ctlr * 2 + unit) {
881 intel_piix_dump_drive("primary",
891 intel_piix_dump_drive("primary",
901 intel_piix_dump_drive("secondary",
904 (word40 >> 16) & 0xffff,
905 (word44 >> 4) & 0x0f,
911 intel_piix_dump_drive("secondary",
914 (word40 >> 16) & 0xffff,
915 (word44 >> 4) & 0x0f,
921 printf("intel_piix_status: bad drive or controller number\n");
926 * XXX timing values set hereare only good for 30/33MHz buses; should deal
927 * with slower ones too (BTW: you overclock-- you lose)
931 intel_piix_dmainit(struct ide_pci_cookie *cookie,
933 int(*wdcmd)(int, void *),
937 /* If it's a UDMA drive and a PIIX4, set it up */
938 if (cookie->type == 0x71118086 && udma_mode(wp) >= 2) {
939 /* Set UDMA mode 2 on controller */
940 int unitno, mask, new;
943 printf("intel_piix_dmainit: setting ultra DMA mode 2\n");
945 if (!wdcmd(WDDMA_UDMA2, wdinfo)) {
946 printf("intel_piix_dmainit: setting DMA mode failed\n");
950 unitno = cookie->ctlr * 2 + cookie->unit;
952 mask = (1 << unitno) + (3 << (16 + unitno * 4));
953 new = (1 << unitno) + (2 << (16 + unitno * 4));
955 pci_conf_write(cookie->tag, 0x48,
956 (pci_conf_read(cookie->tag, 0x48) & ~mask) | new);
959 intel_piix_status(cookie);
963 * if it's an 82371FB, which can't do independent programming of
964 * drive timing, we punt; we're not going to fuss with trying to
965 * coordinate timing modes between drives. if this is you, get a
966 * new motherboard. or contribute patches :)
968 * we do now at least see if the modes set are OK to use. this should
969 * satisfy the majority of people, with mwdma mode2 drives.
971 else if (cookie->type == 0x12308086)
975 /* can drive do PIO 4 and MW DMA 2? */
976 if (!(mwdma_mode(wp) >= 2 && pio_mode(wp) >= 4))
979 word40 = pci_conf_read(cookie->tag, 0x40);
980 word40 >>= cookie->ctlr * 16;
982 /* Check for timing config usable for DMA on controller */
983 if (!((word40 & 0x3300) == 0x2300 &&
984 ((word40 >> (cookie->unit * 4)) & 1) == 1))
987 /* Set multiword DMA mode 2 on drive */
989 printf("intel_piix_dmainit: setting multiword DMA mode 2\n");
990 if (!wdcmd(WDDMA_MDMA2, wdinfo)) {
991 printf("intel_piix_dmainit: setting DMA mode failed\n");
997 /* otherwise, treat it as a PIIX3 and program it for MW DMA mode 2 */
998 else if (mwdma_mode(wp) >= 2 && pio_mode(wp) >= 4) {
999 u_long mask40, mask44, new40, new44;
1002 * If SITRE is not set, set it and copy the
1003 * appropriate bits into the secondary registers. Do
1004 * both controllers at once.
1006 if (((pci_conf_read(cookie->tag, 0x40) >> (16 * cookie->ctlr))
1008 unsigned int word40, word44;
1010 word40 = pci_conf_read(cookie->tag, 0x40);
1012 /* copy bits to secondary register */
1013 word44 = pci_conf_read(cookie->tag, 0x44);
1015 * I've got a Biostar motherboard with Award
1016 * BIOS that sets SITRE and secondary timing
1017 * on one controller but not the other.
1020 if ((word40 & 0x4000) == 0) {
1022 word44 |= ((word40 & 0x3000) >> 10) |
1023 ((word40 & 0x0300) >> 8);
1025 if ((word40 & 0x40000000) == 0) {
1027 word44 |= ((word40 & 0x30000000) >> 22) |
1028 ((word40 & 0x03000000) >> 20);
1031 word40 |= 0x40004000;
1033 pci_conf_write(cookie->tag, 0x40, word40);
1034 pci_conf_write(cookie->tag, 0x44, word44);
1037 /* Set multiword DMA mode 2 on drive */
1039 printf("intel_piix_dmainit: setting multiword DMA mode 2\n");
1041 if (!wdcmd(WDDMA_MDMA2, wdinfo)) {
1042 printf("intel_piix_dmainit: setting DMA mode failed\n");
1047 * backward compatible hardware leaves us with such
1048 * twisted masses of software (aka twiddle the
1049 * extremely weird register layout on a PIIX3, setting
1050 * PIO mode 4 and MWDMA mode 2)
1052 if (cookie->unit == 0) {
1071 pci_conf_write(cookie->tag, 0x40,
1072 (pci_conf_read(cookie->tag, 0x40) & ~mask40) | new40);
1073 pci_conf_write(cookie->tag, 0x44,
1074 (pci_conf_read(cookie->tag, 0x44) & ~mask44) | new44);
1077 intel_piix_status(cookie);
1083 static struct vendor_fns vs_intel_piix =
1091 acer_status(struct ide_pci_cookie *cookie) {
1092 /* XXX does not do anything right now */
1096 acer_dmainit(struct ide_pci_cookie *cookie,
1097 struct wdparams *wp,
1098 int(*wdcmd)(int, void *),
1101 /* Acer Aladdin DMA setup code. UDMA looks to be sinfully easy to set
1102 on this thing - just one register. */
1104 u_long word54 = pci_conf_read(cookie->tag, 0x54);
1106 /* Set the default Acer FIFO settings (0x55 = 13-word depth and
1107 slave operation mode 1) */
1111 /* Is this drive UDMA? Set it up if so... */
1112 if(udma_mode(wp) >= 2) {
1113 /* This is really easy to do. Just write 0xa (enable
1114 UDMA mode with 2T timing) into the word at the right
1116 word54 |= (0xA << (16 + (cookie->ctlr * 8) + (cookie->unit * 4)));
1118 /* Now set the drive for UDMA2. */
1119 if(!wdcmd(WDDMA_UDMA2, wdinfo)) {
1120 printf("acer_dmainit: could not set UDMA2 mode on wdc%d:%d!\n", cookie->ctlr, cookie->unit);
1124 /* Write the new config into the registers. I'm not
1125 sure if I'm doing this in the right order. */
1127 pci_conf_write(cookie->tag, 0x54, word54);
1129 } else if(mwdma_mode(wp) >= 2 && pio_mode(wp) >=4) {
1132 /* Otherwise, we're already set for regular DMA. */
1134 if(!wdcmd(WDDMA_MDMA2, wdinfo)) {
1135 printf("acer_dmainit: could not set MWDMA2 mode on wdc%d:%d!\n",
1136 cookie->ctlr, cookie->unit);
1145 static struct vendor_fns vs_acer =
1154 sis_5591_status(struct ide_pci_cookie *cookie)
1166 iobase_wd = cookie->iobase_wd;
1167 unit = cookie->unit;
1168 ctlr = cookie->ctlr;
1169 iobase_bm = cookie->iobase_bm;
1171 type = cookie->type;
1173 unitno = ctlr * 2 + unit;
1175 for (i=0; i<5; i++) {
1176 word40[i] = pci_conf_read(tag, i * 4 + 0x40);
1179 DRTC = word40[ctlr] >> (16 * unit);
1180 DATC = word40[ctlr] >> (8 + 16*unit);
1183 if ((word40[4] & 0x80000) == 0) {
1184 val = word40[2] & 0xf;
1189 printf ("SiS 5591 status: CRTC %d PCICLK, ", val);
1190 val = (word40[2] >> 8) & 0x7;
1195 printf ("CATC %d PCICLK, applies to all IDE devices\n", val);
1197 printf ("SiS 5591 status: CRTC and CATC timings are per device, taken from DRTC and DATC\n");
1199 printf ("SiS 5591 status: burst cycles %s, fast post write control %s\n",
1200 ((word40[2] >> 16) & 0x80) ? "enabled" : "disabled",
1201 ((word40[2] >> 16) & 0x20) ? "enabled" : "disabled");
1209 printf ("SiS 5591 status: %s drive %d DRTC %d PCICLK,",
1210 unitno < 2 ? "primary" : "secondary",
1218 printf (" DATC %d PCICLK\n", val);
1219 printf ("SiS 5591 status: %s drive %d Ultra DMA %s",
1220 unitno < 2 ? "primary" : "secondary",
1222 (DATC & 0x80) ? "disabled\n" : "enabled");
1223 if ((DATC & 0x80) == 0)
1224 printf (", %d PCICLK data out\n", ((DATC >> 5) & 0x3) + 1);
1225 printf ("SiS 5591 status: %s drive %d postwrite %s, prefetch %s prefetch count is %d\n",
1226 unitno < 2 ? "primary" : "secondary",
1228 ((word40[2] >> (28 + unitno)) & 1) ? "enabled" : "disabled",
1229 ((word40[2] >> (24 + unitno)) & 1) ? "enabled" : "disabled",
1230 (word40[3] >> (16 * ctlr)) & 0xffff);
1231 printf ("SiS 5591 status: %s drive %d has%s been configured for DMA\n",
1232 unitno < 2 ? "primary" : "secondary",
1234 (inb(iobase_bm + BMISTA_PORT) & ((unit == 0) ? BMISTA_DMA0CAP : BMISTA_DMA1CAP)) ?
1239 sis_5591_dmainit(struct ide_pci_cookie *cookie,
1240 struct wdparams *wp,
1241 int(*wdcmd)(int, void *),
1245 unsigned int workword, new, mask;
1251 unit = cookie->unit;
1252 ctlr = cookie->ctlr;
1253 iobase_bm = cookie->iobase_bm;
1256 unitno = ctlr * 2 + unit;
1258 if (udma_mode(wp) >= 2) {
1259 workword = pci_conf_read(tag, ctlr * 4 + 0x40);
1261 /* These settings are a little arbitrary. They're taken from my
1262 * system, where the BIOS has already set the values, but where
1263 * we don't detect that we're initialized because the
1264 * BMISTA_DMA?CAP values aren't set by the BIOS.
1265 * 0x8000 turns on UDMA
1266 * 0x2000 sets UDMA cycle time to 2 PCI clocks for data out
1267 * 0x0300 sets DATC to 3 PCI clocks
1268 * 0x0001 sets DRTC to 1 PCI clock
1281 pci_conf_write(tag, ctlr * 4 + 0x40, workword);
1283 outb(iobase_bm + BMISTA_PORT,
1284 (inb(iobase_bm + BMISTA_PORT) | ((unit == 0) ? BMISTA_DMA0CAP : BMISTA_DMA1CAP)));
1287 printf("SiS 5591 dmainit: %s drive %d setting ultra DMA mode 2\n",
1288 unitno < 2 ? "primary" : "secondary",
1290 r = wdcmd(WDDMA_UDMA2, wdinfo);
1292 printf("SiS 5591 dmainit: %s drive %d setting DMA mode failed\n",
1293 unitno < 2 ? "primary" : "secondary",
1299 sis_5591_status(cookie);
1305 /* otherwise, try and program it for MW DMA mode 2 */
1306 else if (mwdma_mode(wp) >= 2 && pio_mode(wp) >= 4) {
1307 workword = pci_conf_read(tag, ctlr * 4 + 0x40);
1309 /* These settings are a little arbitrary. They're taken from my
1310 * system, where the BIOS has already set the values, but where
1311 * we don't detect that we're initialized because the
1312 * BMISTA_DMA?CAP values aren't set by the BIOS.
1313 * 0x0300 sets DATC to 3 PCI clocks
1314 * 0x0001 sets DRTC to 1 PCI clock
1327 pci_conf_write(tag, ctlr * 4 + 0x40, workword);
1329 outb(iobase_bm + BMISTA_PORT,
1330 (inb(iobase_bm + BMISTA_PORT) | ((unit == 0) ? BMISTA_DMA0CAP : BMISTA_DMA1CAP)));
1332 /* Set multiword DMA mode 2 on drive */
1334 printf("SiS 5591 dmainit: %s drive %d setting multiword DMA mode 2\n",
1335 unitno < 2 ? "primary" : "secondary",
1337 r = wdcmd(WDDMA_MDMA2, wdinfo);
1339 printf("SiS 5591 dmainit: %s drive %d setting DMA mode failed\n",
1340 unitno < 2 ? "primary" : "secondary",
1346 sis_5591_status(cookie);
1354 static struct vendor_fns vs_sis_5591 =
1360 /* Generic SFF-8038i code-- all code below here, except for PCI probes,
1361 * more or less conforms to the SFF-8038i spec as extended for PCI.
1362 * There should be no code that goes beyond that feature set below.
1365 /* XXX mkcookie is overloaded with too many parameters */
1367 static struct ide_pci_cookie *
1368 mkcookie(int iobase_wd,
1374 struct vendor_fns *vp,
1377 struct ide_pci_cookie *cp;
1379 cp = malloc(sizeof *cp, M_DEVBUF, M_NOWAIT);
1382 cp->iobase_wd = iobase_wd;
1387 cp->iobase_bm = iobase_bm;
1388 cp->altiobase_wd = altiobase_wd;
1389 bcopy(vp, &cp->vs, sizeof(struct vendor_fns));
1392 prdbuf = malloc(PRD_ALLOC_SIZE, M_DEVBUF, M_NOWAIT);
1397 if (((int)prdbuf >> PAGE_SHIFT) ^
1398 (((int)prdbuf + PRD_ALLOC_SIZE - 1) >> PAGE_SHIFT)) {
1399 printf("ide_pci: prdbuf straddles page boundary, no DMA\n");
1401 FREE(prdbuf, M_DEVBUF);
1405 prdbuf_next = prdbuf;
1407 if (((char *)prdbuf_next + PRD_BUF_SIZE) >
1408 ((char *)prdbuf + PRD_ALLOC_SIZE)) {
1409 printf("ide_pci: mkcookie %04x:%d: no more space for PRDs, no DMA\n",
1415 cp->prd = prdbuf_next;
1416 (char *)prdbuf_next += PRD_BUF_SIZE;
1418 LIST_INSERT_HEAD(&softc.cookies, cp, le);
1423 ide_pci_probe(pcici_t tag, pcidi_t type)
1427 data = pci_conf_read(tag, PCI_CLASS_REG);
1429 if ((data & PCI_CLASS_MASK) == PCI_CLASS_MASS_STORAGE &&
1430 ((data & PCI_SUBCLASS_MASK) == 0x00010000 ||
1431 ((data & PCI_SUBCLASS_MASK) == 0x00040000))) {
1432 if (type == 0x71118086)
1433 return ("Intel PIIX4 Bus-master IDE controller");
1434 if (type == 0x70108086)
1435 return ("Intel PIIX3 Bus-master IDE controller");
1436 if (type == 0x12308086)
1437 return ("Intel PIIX Bus-master IDE controller");
1438 if (type == PROMISE_ULTRA33)
1439 return ("Promise Ultra/33 IDE controller");
1440 if (type == 0x05711106)
1441 return ("VIA 82C586x (Apollo) Bus-master IDE controller");
1442 if (type == 0x01021078)
1443 return ("Cyrix 5530 Bus-master IDE controller");
1444 if (type == 0x522910b9)
1445 return ("Acer Aladdin IV/V (M5229) Bus-master IDE controller");
1446 if (type == 0x55131039)
1447 return ("SiS 5591 Bus-master IDE Controller");
1448 if (type == CMD640B_PCI_ID)
1449 return "CMD 640B IDE controller";
1451 return ("PCI IDE controller (busmaster capable)");
1453 return ("PCI IDE controller (not busmaster capable)");
1459 ide_pci_attach(pcici_t tag, int unit)
1461 u_long class = 0, cmd;
1462 int bmista_1, bmista_2;
1463 int iobase_wd_1, iobase_wd_2, iobase_bm_1, iobase_bm_2;
1464 int altiobase_wd_1, altiobase_wd_2;
1465 struct vendor_fns *vp;
1467 struct ide_pci_cookie *cookie;
1472 /* set up vendor-specific stuff */
1473 type = pci_conf_read(tag, PCI_ID_REG);
1475 if (type == CMD640B_PCI_ID) {
1480 if (type != PROMISE_ULTRA33) {
1481 /* is it busmaster capable? bail if not */
1482 class = pci_conf_read(tag, PCI_CLASS_REG);
1483 if (!(class & 0x8000)) {
1487 /* is it enabled and is busmastering turned on? */
1488 cmd = pci_conf_read(tag, PCI_COMMAND_STATUS_REG);
1489 if ((cmd & 5) != 5) {
1498 /* Intel PIIX, PIIX3, PIIX4 */
1499 vp = &vs_intel_piix;
1503 /* VIA Apollo chipset family */
1507 case PROMISE_ULTRA33:
1508 /* Promise controllers */
1512 case 0x01021078: /* cyrix 5530 */
1513 printf("cyrix 5530\n");
1514 vp = &vs_cyrix_5530;
1516 case 0x522910B9: /* Acer Aladdin IV/V (M5229) */
1519 case 0x55131039: /* SiS 5591 */
1523 /* everybody else */
1528 if (type != PROMISE_ULTRA33) {
1529 if ((class & 0x100) == 0) {
1530 iobase_wd_1 = IO_WD1;
1531 altiobase_wd_1 = iobase_wd_1 + wd_altsts;
1533 iobase_wd_1 = pci_conf_read(tag, 0x10) & 0xfffc;
1534 altiobase_wd_1 = pci_conf_read(tag, 0x14) & 0xfffc;
1537 if ((class & 0x400) == 0) {
1538 iobase_wd_2 = IO_WD2;
1539 altiobase_wd_2 = iobase_wd_2 + wd_altsts;
1541 iobase_wd_2 = pci_conf_read(tag, 0x18) & 0xfffc;
1542 altiobase_wd_2 = pci_conf_read(tag, 0x1c) & 0xfffc;
1545 iobase_wd_1 = pci_conf_read(tag, 0x10) & 0xfffc;
1546 altiobase_wd_1 = pci_conf_read(tag, 0x14) & 0xfffc;
1547 iobase_wd_2 = pci_conf_read(tag, 0x18) & 0xfffc;
1548 altiobase_wd_2 = pci_conf_read(tag, 0x1c) & 0xfffc;
1551 iobase_bm_1 = pci_conf_read(tag, 0x20) & 0xfffc;
1552 if (iobase_bm_1 == 0) {
1553 printf("ide_pci: BIOS has not configured busmaster"
1554 "I/O address,\n ide_pci: giving up\n");
1557 iobase_bm_2 = iobase_bm_1 + SFF8038_CTLR_1;
1559 wddma[unit].wdd_candma = ide_pci_candma;
1560 wddma[unit].wdd_dmainit = ide_pci_dmainit;
1561 if (type == 0x01021078 /*CYRIX_5530*/)
1562 wddma[unit].wdd_dmaverify = cyrix_5530_dmaverify;
1564 wddma[unit].wdd_dmaverify = ide_pci_dmaverify;
1565 wddma[unit].wdd_dmaprep = ide_pci_dmasetup;
1566 wddma[unit].wdd_dmastart = ide_pci_dmastart;
1567 wddma[unit].wdd_dmadone = ide_pci_dmadone;
1568 wddma[unit].wdd_dmastatus = ide_pci_status;
1569 wddma[unit].wdd_iobase = ide_pci_iobase;
1570 wddma[unit].wdd_altiobase = ide_pci_altiobase;
1572 bmista_1 = inb(iobase_bm_1 + BMISTA_PORT);
1573 bmista_2 = inb(iobase_bm_2 + BMISTA_PORT);
1575 if (!ide_pci_softc_cookies_initted) {
1576 LIST_INIT(&softc.cookies);
1577 ide_pci_softc_cookies_initted = 1;
1580 if (iobase_wd_1 != 0) {
1581 cookie = mkcookie(iobase_wd_1,
1590 vp->vendor_status(cookie);
1591 cookie = mkcookie(iobase_wd_1,
1600 vp->vendor_status(cookie);
1602 bmista_1 = inb(iobase_bm_1 + BMISTA_PORT);
1603 bmista_2 = inb(iobase_bm_2 + BMISTA_PORT);
1604 printf("ide_pci: busmaster 0 status: %02x from port: %08x\n",
1605 bmista_1, iobase_bm_1+BMISTA_PORT);
1607 if (bmista_1 & BMISTA_DMA0CAP)
1608 printf("ide_pci: ide0:0 has been configured for DMA by BIOS\n");
1609 if (bmista_1 & BMISTA_DMA1CAP)
1610 printf("ide_pci: ide0:1 has been configured for DMA by BIOS\n");
1614 if (iobase_wd_2 != 0) {
1615 cookie = mkcookie(iobase_wd_2,
1624 vp->vendor_status(cookie);
1625 cookie = mkcookie(iobase_wd_2,
1634 vp->vendor_status(cookie);
1636 bmista_1 = inb(iobase_bm_1 + BMISTA_PORT);
1637 bmista_2 = inb(iobase_bm_2 + BMISTA_PORT);
1638 printf("ide_pci: busmaster 1 status: %02x from port: %08x\n",
1639 bmista_2, iobase_bm_2+BMISTA_PORT);
1641 if (bmista_2 & BMISTA_DMA0CAP)
1642 printf("ide_pci: ide1:0 has been configured for DMA by BIOS\n");
1643 if (bmista_2 & BMISTA_DMA1CAP)
1644 printf("ide_pci: ide1:1 has been configured for DMA by BIOS\n");
1649 static u_long ide_pci_count;
1651 static struct pci_device ide_pci_device = {
1659 COMPAT_PCI_DRIVER(ide_pci, ide_pci_device);
1662 * Return a cookie if we may be able to do DMA on the specified
1663 * (iobase_wd, ctlr, unit).
1666 ide_pci_candma(int iobase_wd, int ctlr, int unit)
1668 struct ide_pci_cookie *cp;
1670 cp = softc.cookies.lh_first;
1672 if (cp->ctlr == ctlr && cp->unit == unit &&
1673 ((iobase_wd == 0) || (cp->iobase_wd == iobase_wd)))
1675 cp = cp->le.le_next;
1682 * Initialize controller and drive for DMA operation, including timing modes.
1683 * Uses data passed from the wd driver and a callback function to initialize
1684 * timing modes on the drive.
1687 ide_pci_dmainit(void *cookie,
1688 struct wdparams *wp,
1689 int(*wdcmd)(int, void *),
1692 struct ide_pci_cookie *cp = cookie;
1694 * If the controller status indicates that DMA is configured already,
1695 * we flounce happily away
1697 if (inb(cp->iobase_bm + BMISTA_PORT) &
1698 ((cp->unit == 0) ? BMISTA_DMA0CAP : BMISTA_DMA1CAP))
1701 /* We take a stab at it with device-dependent code */
1702 return(cp->vs.vendor_dmainit(cp, wp, wdcmd, wdinfo));
1706 * Verify that controller can handle a dma request for cp. Should
1707 * not affect any hardware or driver state.
1710 ide_pci_dmaverify(void *xcp, char *vaddr, u_long count, int dir)
1715 * check for nonaligned or odd-length Stuff
1717 badfu = ((unsigned int)vaddr & 1) || (count & 1);
1720 printf("ide_pci: dmaverify odd vaddr or length, ");
1721 printf("vaddr = %p length = %08lx\n", (void *)vaddr, count);
1728 * Set up DMA for cp. It is the responsibility of the caller
1729 * to ensure that the controller is idle before this routine
1733 ide_pci_dmasetup(void *xcp, char *vaddr, u_long vcount, int dir)
1735 struct ide_pci_cookie *cp = xcp;
1736 struct ide_pci_prd *prd;
1739 u_long prd_base, prd_count;
1740 u_long nbase, ncount, nend;
1750 iobase_bm = cp->iobase_bm;
1753 printf("ide_pci: dmasetup 0-length transfer, ");
1754 printf("vaddr = %p length = %08lx\n", (void *)vaddr, count);
1758 /* Generate first PRD entry, which may be non-aligned. */
1760 firstpage = PAGE_SIZE - ((uintptr_t)vaddr & PAGE_MASK);
1762 prd_base = vtophys(vaddr);
1763 prd_count = MIN(count, firstpage);
1769 * Step through virtual pages.
1770 * Note that it is not worth trying to coalesce pages that are
1771 * next to each other physically, and some DMA engines (e.g.
1772 * Cyrix Cx5530) actually blow up if you do.
1775 nbase = vtophys(vaddr);
1776 ncount = MIN(count, PAGE_SIZE);
1777 nend = nbase + ncount;
1779 prd[i].prd_base = prd_base;
1780 prd[i].prd_count = (prd_count & 0xffff);
1782 if (i >= PRD_MAX_SEGS) {
1783 printf("wd82371: too many segments in PRD table\n");
1792 /* Write last PRD entry. */
1793 prd[i].prd_base = prd_base;
1794 prd[i].prd_count = (prd_count & 0xffff) | PRD_EOT_BIT;
1796 /* Set up PRD base register */
1797 outl(iobase_bm + BMIDTP_PORT, vtophys(prd));
1799 /* Set direction of transfer */
1800 outb(iobase_bm + BMICOM_PORT, (dir == B_READ) ? BMICOM_READ_WRITE : 0);
1802 /* Clear interrupt and error bits */
1803 outb(iobase_bm + BMISTA_PORT,
1804 (inb(iobase_bm + BMISTA_PORT)
1805 | (BMISTA_INTERRUPT | BMISTA_DMA_ERROR)));
1811 ide_pci_dmastart(void *xcp)
1813 struct ide_pci_cookie *cp = xcp;
1816 iobase_bm = cp->iobase_bm;
1818 outb(iobase_bm + BMICOM_PORT,
1819 inb(iobase_bm + BMICOM_PORT) | BMICOM_STOP_START);
1824 ide_pci_dmadone(void *xcp)
1826 struct ide_pci_cookie *cp = xcp;
1827 int iobase_bm, status;
1829 status = ide_pci_status(xcp);
1830 iobase_bm = cp->iobase_bm;
1832 outb(iobase_bm + BMICOM_PORT,
1833 inb(iobase_bm + BMICOM_PORT) & ~BMICOM_STOP_START);
1839 ide_pci_status(void *xcp)
1841 int iobase_bm, status, bmista;
1844 iobase_bm = ((struct ide_pci_cookie *)xcp)->iobase_bm;
1846 bmista = inb(iobase_bm + BMISTA_PORT);
1848 if (bmista & BMISTA_INTERRUPT)
1849 status |= WDDS_INTERRUPT;
1850 if (bmista & BMISTA_DMA_ERROR)
1851 status |= WDDS_ERROR;
1852 if (bmista & BMISTA_DMA_ACTIVE)
1853 status |= WDDS_ACTIVE;
1858 ide_pci_altiobase(void *xcp)
1860 struct ide_pci_cookie *cp = xcp;
1864 return cp->altiobase_wd;
1869 ide_pci_iobase(void *xcp)
1871 struct ide_pci_cookie *cp = xcp;
1875 return cp->iobase_wd;