1 /* $FreeBSD: src/sys/dev/ct/ct.c,v 1.4.2.1 2001/07/26 02:32:18 nyan Exp $ */
2 /* $DragonFly: src/sys/dev/disk/ct/Attic/ct.c,v 1.4 2003/08/07 21:16:52 dillon Exp $ */
3 /* $NecBSD: ct.c,v 1.13.12.5 2001/06/26 07:31:53 honda Exp $ */
7 #define CT_IO_CONTROL_FLAGS (CT_USE_CCSEQ | CT_FAST_INTR)
10 * [NetBSD for NEC PC-98 series]
11 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
12 * NetBSD/pc98 porting staff. All rights reserved.
14 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
15 * Naofumi HONDA. All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. The name of the author may not be used to endorse or promote products
26 * derived from this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
30 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
32 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
33 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #if defined(__FreeBSD__) && __FreeBSD_version > 500001
48 #endif /* __ FreeBSD__ */
50 #include <sys/queue.h>
51 #include <sys/malloc.h>
52 #include <sys/errno.h>
55 #include <sys/device.h>
57 #include <machine/bus.h>
58 #include <machine/intr.h>
60 #include <dev/scsipi/scsi_all.h>
61 #include <dev/scsipi/scsipi_all.h>
62 #include <dev/scsipi/scsiconf.h>
63 #include <dev/scsipi/scsi_disk.h>
65 #include <machine/dvcfg.h>
66 #include <machine/physio_proc.h>
68 #include <i386/Cbus/dev/scsi_low.h>
70 #include <dev/ic/wd33c93reg.h>
71 #include <i386/Cbus/dev/ct/ctvar.h>
72 #include <i386/Cbus/dev/ct/ct_machdep.h>
73 #endif /* __NetBSD__ */
76 #include <machine/clock.h>
77 #include <machine/bus.h>
78 #include <machine/dvcfg.h>
79 #include <machine/physio_proc.h>
81 #include <bus/cam/scsi/scsi_low.h>
83 #include <dev/ic/wd33c93reg.h>
85 #include "ct_machdep.h"
86 #endif /* __FreeBSD__ */
90 #define CT_RESET_DEFAULT 2000
91 #define CT_DELAY_MAX (2 * 1000 * 1000)
92 #define CT_DELAY_INTERVAL (1)
94 /***************************************************
96 ***************************************************/
101 /***************************************************
103 ***************************************************/
104 #define CT_USE_CCSEQ 0x0100
105 #define CT_FAST_INTR 0x0200
107 u_int ct_io_control = CT_IO_CONTROL_FLAGS;
109 /***************************************************
111 ***************************************************/
112 u_int8_t cthw_cmdlevel[256] = {
113 /* 0 1 2 3 4 5 6 7 8 9 A B C E D F */
114 /*0*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 ,
115 /*1*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
116 /*2*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 ,
117 /*3*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
118 /*4*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
119 /*5*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
120 /*6*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
121 /*7*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
122 /*8*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
123 /*9*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
124 /*A*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
125 /*B*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
126 /*C*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
127 /*D*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
128 /*E*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
129 /*F*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
133 /* default synch data table */
134 /* A 10 6.6 5.0 4.0 3.3 2.8 2.5 2.0 M/s */
135 /* X 100 150 200 250 300 350 400 500 ns */
136 static struct ct_synch_data ct_synch_data_FSCSI[] = {
137 {25, 0xa0}, {37, 0xb0}, {50, 0x20}, {62, 0xd0}, {75, 0x30},
138 {87, 0xf0}, {100, 0x40}, {125, 0x50}, {0, 0}
141 static struct ct_synch_data ct_synch_data_SCSI[] = {
142 {50, 0x20}, {75, 0x30}, {100, 0x40}, {125, 0x50}, {0, 0}
145 /***************************************************
147 ***************************************************/
148 extern struct cfdriver ct_cd;
150 /*****************************************************************
151 * Interface functions
152 *****************************************************************/
153 static int ct_xfer __P((struct ct_softc *, u_int8_t *, int, int, u_int *));
154 static void ct_io_xfer __P((struct ct_softc *));
155 static int ct_reselected __P((struct ct_softc *, u_int8_t));
156 static void ct_phase_error __P((struct ct_softc *, u_int8_t));
157 static int ct_start_selection __P((struct ct_softc *, struct slccb *));
158 static int ct_msg __P((struct ct_softc *, struct targ_info *, u_int));
159 static int ct_world_start __P((struct ct_softc *, int));
160 static __inline void cthw_phase_bypass __P((struct ct_softc *, u_int8_t));
161 static int cthw_chip_reset __P((struct ct_bus_access_handle *, int *, int, int));
162 static void cthw_bus_reset __P((struct ct_softc *));
163 static int ct_ccb_nexus_establish __P((struct ct_softc *));
164 static int ct_lun_nexus_establish __P((struct ct_softc *));
165 static int ct_target_nexus_establish __P((struct ct_softc *, int, int));
166 static void cthw_attention __P((struct ct_softc *));
167 static int ct_targ_init __P((struct ct_softc *, struct targ_info *, int));
168 static int ct_unbusy __P((struct ct_softc *));
169 static void ct_attention __P((struct ct_softc *));
170 static struct ct_synch_data *ct_make_synch_table __P((struct ct_softc *));
171 static int ct_catch_intr __P((struct ct_softc *));
173 struct scsi_low_funcs ct_funcs = {
174 SC_LOW_INIT_T ct_world_start,
175 SC_LOW_BUSRST_T cthw_bus_reset,
176 SC_LOW_TARG_INIT_T ct_targ_init,
177 SC_LOW_LUN_INIT_T NULL,
179 SC_LOW_SELECT_T ct_start_selection,
180 SC_LOW_NEXUS_T ct_lun_nexus_establish,
181 SC_LOW_NEXUS_T ct_ccb_nexus_establish,
183 SC_LOW_ATTEN_T cthw_attention,
186 SC_LOW_TIMEOUT_T NULL,
187 SC_LOW_POLL_T ctintr,
189 NULL, /* SC_LOW_POWER_T cthw_power, */
192 /**************************************************
194 **************************************************/
196 cthw_phase_bypass(ct, ph)
200 struct ct_bus_access_handle *chp = &ct->sc_ch;
202 ct_cr_write_1(chp, wd3s_cph, ph);
203 ct_cr_write_1(chp, wd3s_cmd, WD3S_SELECT_ATN_TFR);
212 * wd33c93 does not have bus reset function.
214 if (ct->ct_bus_reset != NULL)
215 ((*ct->ct_bus_reset) (ct));
219 cthw_chip_reset(chp, chiprevp, chipclk, hostid)
220 struct ct_bus_access_handle *chp;
224 #define CT_SELTIMEOUT_20MHz_REGV (0x80)
229 /* issue abort cmd */
230 ct_cr_write_1(chp, wd3s_cmd, WD3S_ABORT);
231 SCSI_LOW_DELAY(1000); /* 1ms wait */
232 (void) ct_stat_read_1(chp);
233 (void) ct_cr_read_1(chp, wd3s_stat);
235 /* setup chip registers */
237 seltout = CT_SELTIMEOUT_20MHz_REGV;
242 seltout = (seltout * chipclk) / 20;
248 seltout = (seltout * chipclk) / 20;
254 seltout = (seltout * chipclk) / 20;
259 panic("ct: illegal chip clk rate\n");
263 regv |= IDR_EHP | hostid | IDR_RAF | IDR_EAF;
264 ct_cr_write_1(chp, wd3s_oid, regv);
266 ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
267 for (wc = CT_RESET_DEFAULT; wc > 0; wc --)
269 aux = ct_stat_read_1(chp);
270 if (aux != 0xff && (aux & STR_INT))
272 regv = ct_cr_read_1(chp, wd3s_stat);
273 if (regv == BSR_RESET || regv == BSR_AFM_RESET)
276 ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
283 ct_cr_write_1(chp, wd3s_tout, seltout);
284 ct_cr_write_1(chp, wd3s_sid, SIDR_RESEL);
285 ct_cr_write_1(chp, wd3s_ctrl, CR_DEFAULT);
286 ct_cr_write_1(chp, wd3s_synch, 0);
287 if (chiprevp != NULL)
289 *chiprevp = CT_WD33C93;
290 if (regv == BSR_RESET)
293 *chiprevp = CT_WD33C93_A;
294 ct_cr_write_1(chp, wd3s_qtag, 0xaa);
295 if (ct_cr_read_1(chp, wd3s_qtag) != 0xaa)
297 ct_cr_write_1(chp, wd3s_qtag, 0x0);
300 ct_cr_write_1(chp, wd3s_qtag, 0x55);
301 if (ct_cr_read_1(chp, wd3s_qtag) != 0x55)
303 ct_cr_write_1(chp, wd3s_qtag, 0x0);
306 ct_cr_write_1(chp, wd3s_qtag, 0x0);
307 *chiprevp = CT_WD33C93_B;
311 (void) ct_stat_read_1(chp);
312 (void) ct_cr_read_1(chp, wd3s_stat);
316 static struct ct_synch_data *
317 ct_make_synch_table(ct)
320 struct ct_synch_data *sdtp, *sdp;
321 u_int base, i, period;
323 sdtp = sdp = &ct->sc_default_sdt[0];
325 if ((ct->sc_chipclk % 5) == 0)
326 base = 1000 / (5 * 2); /* 5 MHz type */
328 base = 1000 / (4 * 2); /* 4 MHz type */
330 if (ct->sc_chiprev >= CT_WD33C93_B)
333 for (i = 2; i < 8; i ++, sdp ++)
335 period = (base * i) / 2;
336 if (period >= 200) /* 5 MHz */
338 sdp->cs_period = period / 4;
339 sdp->cs_syncr = (i * 0x10) | 0x80;
343 for (i = 2; i < 8; i ++, sdp ++)
346 if (period > 500) /* 2 MHz */
348 sdp->cs_period = period / 4;
349 sdp->cs_syncr = (i * 0x10);
357 /**************************************************
359 **************************************************/
361 ctprobesubr(chp, dvcfg, hsid, chipclk, chiprevp)
362 struct ct_bus_access_handle *chp;
363 u_int dvcfg, chipclk;
369 if ((ct_stat_read_1(chp) & STR_BSY) != 0)
372 if (cthw_chip_reset(chp, chiprevp, chipclk, hsid) != 0)
384 printf("%s: scsibus ", name);
392 struct scsi_low_softc *slp = &ct->sc_sclow;
394 ct->sc_tmaxcnt = SCSI_LOW_MIN_TOUT * 1000 * 1000; /* default */
395 slp->sl_funcs = &ct_funcs;
396 slp->sl_flags |= HW_READ_PADDING;
397 (void) scsi_low_attach(slp, 0, CT_NTARGETS, CT_NLUNS,
398 sizeof(struct ct_targ_info), 0);
401 /**************************************************
402 * SCSI LOW interface functions
403 **************************************************/
408 struct ct_bus_access_handle *chp = &ct->sc_ch;
411 if ((ct_stat_read_1(chp) & (STR_BSY | STR_CIP)) != 0)
414 ct_cr_write_1(chp, wd3s_cmd, WD3S_ASSERT_ATN);
416 if ((ct_stat_read_1(chp) & STR_LCI) == 0)
426 struct scsi_low_softc *slp = &ct->sc_sclow;
428 if (slp->sl_atten == 0)
431 scsi_low_attention(slp);
433 else if (ct->sc_atten != 0)
441 ct_targ_init(ct, ti, action)
443 struct targ_info *ti;
446 struct ct_targ_info *cti = (void *) ti;
448 if (action == SCSI_LOW_INFO_ALLOC || action == SCSI_LOW_INFO_REVOKE)
450 if (ct->sc_sdp == NULL)
452 ct->sc_sdp = ct_make_synch_table(ct);
455 switch (ct->sc_chiprev)
458 ti->ti_maxsynch.offset = 5;
463 ti->ti_maxsynch.offset = 12;
468 ti->ti_maxsynch.offset = 12;
472 ti->ti_maxsynch.period = ct->sc_sdp[0].cs_period;
473 ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
474 cti->cti_syncreg = 0;
481 ct_world_start(ct, fdone)
485 struct scsi_low_softc *slp = &ct->sc_sclow;
486 struct ct_bus_access_handle *chp = &ct->sc_ch;
488 if (ct->sc_sdp == NULL)
490 ct->sc_sdp = ct_make_synch_table(ct);
493 if (slp->sl_cfgflags & CFG_NOPARITY)
494 ct->sc_creg = CR_DEFAULT;
496 ct->sc_creg = CR_DEFAULT_HP;
498 if (ct->sc_dma & CT_DMA_DMASTART)
499 (*ct->ct_dma_xfer_stop) (ct);
500 if (ct->sc_dma & CT_DMA_PIOSTART)
501 (*ct->ct_pio_xfer_stop) (ct);
505 cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
506 scsi_low_bus_reset(slp);
507 cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
509 SOFT_INTR_REQUIRED(slp);
514 ct_start_selection(ct, cb)
518 struct scsi_low_softc *slp = &ct->sc_sclow;
519 struct ct_bus_access_handle *chp = &ct->sc_ch;
521 struct targ_info *ti = slp->sl_Tnexus;
522 struct lun_info *li = slp->sl_Lnexus;
526 ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
530 if (scsi_low_is_disconnect_ok(cb) != 0)
532 if (ct->sc_chiprev >= CT_WD33C93_A)
534 else if (cthw_cmdlevel[slp->sl_scp.scp_cmd[0]] != 0)
539 scsi_low_is_msgout_continue(ti, SCSI_LOW_MSG_IDENTIFY) == 0)
541 cmd = WD3S_SELECT_ATN_TFR;
542 ct->sc_satgo = CT_SAT_GOING;
546 cmd = WD3S_SELECT_ATN;
550 if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) != 0)
551 return SCSI_LOW_START_FAIL;
553 if ((ct->sc_satgo & CT_SAT_GOING) != 0)
555 (void) scsi_low_msgout(slp, ti, SCSI_LOW_MSGOUT_INIT);
556 scsi_low_cmd(slp, ti);
557 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
558 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
562 /* anyway attention assert */
563 SCSI_LOW_ASSERT_ATN(slp);
566 ct_target_nexus_establish(ct, li->li_lun, slp->sl_scp.scp_direction);
569 if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) == 0)
572 * Reload a lun again here.
574 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
575 ct_cr_write_1(chp, wd3s_cmd, cmd);
576 if ((ct_stat_read_1(chp) & STR_LCI) == 0)
579 SCSI_LOW_SETUP_PHASE(ti, PH_SELSTART);
580 return SCSI_LOW_START_OK;
584 return SCSI_LOW_START_FAIL;
590 struct targ_info *ti;
593 struct ct_bus_access_handle *chp = &ct->sc_ch;
594 struct ct_targ_info *cti = (void *) ti;
595 struct ct_synch_data *csp = ct->sc_sdp;
596 u_int offset, period;
599 if ((msg & SCSI_LOW_MSG_WIDE) != 0)
601 if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8)
603 ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
609 if ((msg & SCSI_LOW_MSG_SYNCH) == 0)
612 offset = ti->ti_maxsynch.offset;
613 period = ti->ti_maxsynch.period;
614 for ( ; csp->cs_period != 0; csp ++)
616 if (period == csp->cs_period)
620 if (ti->ti_maxsynch.period != 0 && csp->cs_period == 0)
622 ti->ti_maxsynch.period = 0;
623 ti->ti_maxsynch.offset = 0;
624 cti->cti_syncreg = 0;
629 cti->cti_syncreg = ((offset & 0x0f) | csp->cs_syncr);
633 if (ct->ct_synch_setup != 0)
634 (*ct->ct_synch_setup) (ct, ti);
635 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
639 /*************************************************
641 *************************************************/
643 ct_xfer(ct, data, len, direction, statp)
649 struct ct_bus_access_handle *chp = &ct->sc_ch;
656 ct_cr_write_1(chp, wd3s_cmd, WD3S_SBT | WD3S_TFR_INFO);
660 cthw_set_count(chp, len);
661 ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO);
664 aux = ct_stat_read_1(chp);
665 if ((aux & STR_LCI) != 0)
667 cthw_set_count(chp, 0);
671 for (wc = 0; wc < ct->sc_tmaxcnt; wc ++)
673 /* check data ready */
674 if ((aux & (STR_BSY | STR_DBR)) == (STR_BSY | STR_DBR))
676 if (direction == SCSI_LOW_READ)
678 *data = ct_cr_read_1(chp, wd3s_data);
679 if ((aux & STR_PE) != 0)
680 *statp |= SCSI_LOW_DATA_PE;
684 ct_cr_write_1(chp, wd3s_data, *data);
696 /* check phase miss */
697 aux = ct_stat_read_1(chp);
698 if ((aux & STR_INT) != 0)
704 #define CT_PADDING_BUF_SIZE 32
710 struct scsi_low_softc *slp = &ct->sc_sclow;
711 struct ct_bus_access_handle *chp = &ct->sc_ch;
712 struct sc_p *sp = &slp->sl_scp;
715 u_int8_t pbuf[CT_PADDING_BUF_SIZE];
718 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg);
720 if (sp->scp_datalen <= 0)
722 slp->sl_error |= PDMAERR;
724 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
725 SCSI_LOW_BZERO(pbuf, CT_PADDING_BUF_SIZE);
726 ct_xfer(ct, pbuf, CT_PADDING_BUF_SIZE,
727 sp->scp_direction, &stat);
731 len = ct_xfer(ct, sp->scp_data, sp->scp_datalen,
732 sp->scp_direction, &stat);
733 sp->scp_data += (sp->scp_datalen - len);
734 sp->scp_datalen = len;
738 /**************************************************
740 **************************************************/
748 struct ct_err ct_cmderr[] = {
749 /*0*/ { "illegal cmd", FATALIO, SCSI_LOW_MSG_ABORT, 1},
750 /*1*/ { "unexpected bus free", FATALIO, 0, 1},
751 /*2*/ { NULL, SELTIMEOUTIO, 0, 1},
752 /*3*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
753 /*4*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
754 /*5*/ { "unknown" , FATALIO, SCSI_LOW_MSG_ABORT, 1},
755 /*6*/ { "miss reselection (target mode)", FATALIO, SCSI_LOW_MSG_ABORT, 0},
756 /*7*/ { "wrong status byte", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
760 ct_phase_error(ct, scsi_status)
762 u_int8_t scsi_status;
764 struct scsi_low_softc *slp = &ct->sc_sclow;
765 struct targ_info *ti = slp->sl_Tnexus;
769 if ((scsi_status & BSR_CM) == BSR_CMDERR &&
770 (scsi_status & BSR_PHVALID) == 0)
772 pep = &ct_cmderr[scsi_status & BSR_PM];
773 slp->sl_error |= pep->pe_err;
774 if ((pep->pe_err & PARITYERR) != 0)
776 if (ti->ti_phase == PH_MSGIN)
777 msg = SCSI_LOW_MSG_PARITY;
779 msg = SCSI_LOW_MSG_ERROR;
782 msg = pep->pe_errmsg;
785 scsi_low_assert_msg(slp, slp->sl_Tnexus, msg, 1);
787 if (pep->pe_msg != NULL)
789 printf("%s: phase error: %s",
790 slp->sl_xname, pep->pe_msg);
791 scsi_low_print(slp, slp->sl_Tnexus);
794 if (pep->pe_done != 0)
795 scsi_low_disconnected(slp, ti);
799 slp->sl_error |= FATALIO;
800 scsi_low_restart(slp, SCSI_LOW_RESTART_HARD, "phase error");
804 /**************************************************
805 * ### SCSI PHASE SEQUENCER ###
806 **************************************************/
808 ct_reselected(ct, scsi_status)
810 u_int8_t scsi_status;
812 struct scsi_low_softc *slp = &ct->sc_sclow;
813 struct ct_bus_access_handle *chp = &ct->sc_ch;
814 struct targ_info *ti;
819 ct->sc_satgo &= ~CT_SAT_GOING;
820 regv = ct_cr_read_1(chp, wd3s_sid);
821 if ((regv & SIDR_VALID) == 0)
824 sid = regv & SIDR_IDM;
825 if ((ti = scsi_low_reselected(slp, sid)) == NULL)
828 ct_target_nexus_establish(ct, 0, SCSI_LOW_READ);
829 if (scsi_status != BSR_AFM_RESEL)
832 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
833 regv = ct_cr_read_1(chp, wd3s_data);
834 if (scsi_low_msgin(slp, ti, (u_int) regv) == 0)
836 if (scsi_low_is_msgout_continue(ti, 0) != 0)
838 /* XXX: scsi_low_attetion */
839 scsi_low_attention(slp);
843 if (ct->sc_atten != 0)
848 ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
853 ct_target_nexus_establish(ct, lun, dir)
857 struct scsi_low_softc *slp = &ct->sc_sclow;
858 struct ct_bus_access_handle *chp = &ct->sc_ch;
859 struct targ_info *ti = slp->sl_Tnexus;
860 struct ct_targ_info *cti = (void *) ti;
862 if (dir == SCSI_LOW_WRITE)
863 ct_cr_write_1(chp, wd3s_did, ti->ti_id);
865 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
866 ct_cr_write_1(chp, wd3s_lun, lun);
867 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA);
868 ct_cr_write_1(chp, wd3s_cph, 0);
869 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
870 cthw_set_count(chp, 0);
875 ct_lun_nexus_establish(ct)
878 struct scsi_low_softc *slp = &ct->sc_sclow;
879 struct ct_bus_access_handle *chp = &ct->sc_ch;
880 struct lun_info *li = slp->sl_Lnexus;
882 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
887 ct_ccb_nexus_establish(ct)
890 struct scsi_low_softc *slp = &ct->sc_sclow;
891 struct ct_bus_access_handle *chp = &ct->sc_ch;
892 struct lun_info *li = slp->sl_Lnexus;
893 struct targ_info *ti = slp->sl_Tnexus;
894 struct ct_targ_info *cti = (void *) ti;
895 struct slccb *cb = slp->sl_Qnexus;
897 ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
899 if ((ct->sc_satgo & CT_SAT_GOING) != 0)
901 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
902 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
904 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
905 ct_cr_write_1(chp, wd3s_did, ti->ti_id);
907 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
908 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
909 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
917 struct scsi_low_softc *slp = &ct->sc_sclow;
918 struct ct_bus_access_handle *chp = &ct->sc_ch;
922 for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
924 regv = ct_stat_read_1(chp);
925 if ((regv & (STR_BSY | STR_CIP)) == 0)
927 if (regv == (u_int8_t) -1)
930 SCSI_LOW_DELAY(CT_DELAY_INTERVAL);
933 printf("%s: unbusy timeout\n", slp->sl_xname);
941 struct ct_bus_access_handle *chp = &ct->sc_ch;
945 for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
947 regv = ct_stat_read_1(chp);
948 if ((regv & (STR_INT | STR_BSY | STR_CIP)) == STR_INT)
951 SCSI_LOW_DELAY(CT_DELAY_INTERVAL);
960 struct ct_softc *ct = arg;
961 struct scsi_low_softc *slp = &ct->sc_sclow;
962 struct ct_bus_access_handle *chp = &ct->sc_ch;
963 struct targ_info *ti;
964 struct physio_proc *pp;
967 int len, satgo, error;
968 u_int8_t scsi_status, regv;
971 if (slp->sl_flags & HW_INACTIVE)
974 /**************************************************
975 * Get status & bus phase
976 **************************************************/
977 if ((ct_stat_read_1(chp) & STR_INT) == 0)
980 scsi_status = ct_cr_read_1(chp, wd3s_stat);
981 if (scsi_status == ((u_int8_t) -1))
984 /**************************************************
985 * Check reselection, or nexus
986 **************************************************/
987 if (scsi_status == BSR_RESEL || scsi_status == BSR_AFM_RESEL)
989 if (ct_reselected(ct, scsi_status) == EJUSTRETURN)
993 if ((ti = slp->sl_Tnexus) == NULL)
996 /**************************************************
998 **************************************************/
1002 scsi_low_print(slp, NULL);
1003 printf("%s: scsi_status 0x%x\n\n", slp->sl_xname,
1004 (u_int) scsi_status);
1007 SCSI_LOW_DEBUGGER("ct");
1010 #endif /* CT_DEBUG */
1012 /**************************************************
1013 * Internal scsi phase
1014 **************************************************/
1015 satgo = ct->sc_satgo;
1016 ct->sc_satgo &= ~CT_SAT_GOING;
1018 switch (ti->ti_phase)
1021 if ((satgo & CT_SAT_GOING) == 0)
1023 if (scsi_status != BSR_SELECTED)
1025 ct_phase_error(ct, scsi_status);
1028 scsi_low_arbit_win(slp);
1029 SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED);
1034 scsi_low_arbit_win(slp);
1035 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); /* XXX */
1040 if ((scsi_status & BSR_PHVALID) == 0 ||
1041 (scsi_status & BSR_PM) != BSR_MSGIN)
1043 scsi_low_restart(slp, SCSI_LOW_RESTART_HARD,
1044 "phase miss after reselect");
1050 if (slp->sl_flags & HW_PDMASTART)
1052 slp->sl_flags &= ~HW_PDMASTART;
1053 if (ct->sc_dma & CT_DMA_DMASTART)
1055 (*ct->ct_dma_xfer_stop) (ct);
1056 ct->sc_dma &= ~CT_DMA_DMASTART;
1058 else if (ct->sc_dma & CT_DMA_PIOSTART)
1060 (*ct->ct_pio_xfer_stop) (ct);
1061 ct->sc_dma &= ~CT_DMA_PIOSTART;
1065 scsi_low_data_finish(slp);
1071 /**************************************************
1073 **************************************************/
1074 if (scsi_status & BSR_PHVALID)
1076 /**************************************************
1077 * Normal SCSI phase.
1078 **************************************************/
1079 if ((scsi_status & BSR_CM) == BSR_CMDABT)
1081 ct_phase_error(ct, scsi_status);
1085 switch (scsi_status & BSR_PM)
1088 SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
1089 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_WRITE) != 0)
1093 goto common_data_phase;
1096 SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
1097 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_READ) != 0)
1103 if (slp->sl_scp.scp_datalen > 0)
1105 slp->sl_flags |= HW_PDMASTART;
1106 if ((ct->sc_xmode & CT_XMODE_PIO) != 0)
1108 pp = physio_proc_enter(bp);
1109 error = (*ct->ct_pio_xfer_start) (ct);
1110 physio_proc_leave(pp);
1113 ct->sc_dma |= CT_DMA_PIOSTART;
1118 if ((ct->sc_xmode & CT_XMODE_DMA) != 0)
1120 error = (*ct->ct_dma_xfer_start) (ct);
1123 ct->sc_dma |= CT_DMA_DMASTART;
1130 if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
1132 if (!(slp->sl_flags & HW_READ_PADDING))
1134 printf("%s: read padding required\n", slp->sl_xname);
1140 if (!(slp->sl_flags & HW_WRITE_PADDING))
1142 printf("%s: write padding required\n", slp->sl_xname);
1146 slp->sl_flags |= HW_PDMASTART;
1153 SCSI_LOW_SETUP_PHASE(ti, PH_CMD);
1154 if (scsi_low_cmd(slp, ti) != 0)
1159 if (ct_xfer(ct, slp->sl_scp.scp_cmd,
1160 slp->sl_scp.scp_cmdlen,
1161 SCSI_LOW_WRITE, &derror) != 0)
1163 printf("%s: scsi cmd xfer short\n",
1169 SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
1170 if ((ct_io_control & CT_USE_CCSEQ) != 0)
1172 if (scsi_low_is_msgout_continue(ti, 0) != 0 ||
1175 ct_xfer(ct, ®v, 1, SCSI_LOW_READ,
1177 scsi_low_statusin(slp, ti,
1182 ct->sc_satgo |= CT_SAT_GOING;
1183 cthw_set_count(chp, 0);
1184 cthw_phase_bypass(ct, 0x41);
1189 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror);
1190 scsi_low_statusin(slp, ti, regv | derror);
1196 printf("%s: illegal bus phase (0x%x)\n", slp->sl_xname,
1197 (u_int) scsi_status);
1198 scsi_low_print(slp, ti);
1202 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT);
1203 flags = SCSI_LOW_MSGOUT_UNIFY;
1204 if (ti->ti_ophase != ti->ti_phase)
1205 flags |= SCSI_LOW_MSGOUT_INIT;
1206 len = scsi_low_msgout(slp, ti, flags);
1208 if (len > 1 && slp->sl_atten == 0)
1213 if (ct_xfer(ct, ti->ti_msgoutstr, len,
1214 SCSI_LOW_WRITE, &derror) != 0)
1216 printf("%s: scsi msgout xfer short\n",
1219 SCSI_LOW_DEASSERT_ATN(slp);
1223 case BSR_MSGIN:/* msg in */
1224 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1226 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror);
1227 if (scsi_low_msgin(slp, ti, regv | derror) == 0)
1229 if (scsi_low_is_msgout_continue(ti, 0) != 0)
1231 /* XXX: scsi_low_attetion */
1232 scsi_low_attention(slp);
1236 if ((ct_io_control & CT_FAST_INTR) != 0)
1238 if (ct_catch_intr(ct) == 0)
1246 /**************************************************
1247 * Special SCSI phase
1248 **************************************************/
1249 switch (scsi_status)
1251 case BSR_SATSDP: /* SAT with save data pointer */
1252 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1253 ct->sc_satgo |= CT_SAT_GOING;
1254 scsi_low_msgin(slp, ti, MSG_SAVESP);
1255 cthw_phase_bypass(ct, 0x41);
1258 case BSR_SATFIN: /* SAT COMPLETE */
1260 * emulate statusin => msgin
1262 SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
1263 scsi_low_statusin(slp, ti, ct_cr_read_1(chp, wd3s_lun));
1265 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1266 scsi_low_msgin(slp, ti, MSG_COMP);
1268 scsi_low_disconnected(slp, ti);
1271 case BSR_ACKREQ: /* negate ACK */
1272 if (ct->sc_atten != 0)
1277 ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
1278 if ((ct_io_control & CT_FAST_INTR) != 0)
1281 * Should clear a pending interrupt and
1282 * sync with a next interrupt!
1288 case BSR_DISC: /* disconnect */
1289 if (slp->sl_msgphase == MSGPH_NULL &&
1290 (satgo & CT_SAT_GOING) != 0)
1293 * emulate disconnect msg
1295 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1296 scsi_low_msgin(slp, ti, MSG_DISCON);
1298 scsi_low_disconnected(slp, ti);
1306 ct_phase_error(ct, scsi_status);