2 * Copyright (c) 2002 Myson Technology Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions, and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. The name of the author may not be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/
28 * $FreeBSD: src/sys/dev/my/if_my.c,v 1.2.2.4 2002/04/17 02:05:27 julian Exp $
29 * $DragonFly: src/sys/dev/netif/my/if_my.c,v 1.4 2003/08/07 21:17:04 dillon Exp $
31 * Myson fast ethernet PCI NIC driver
33 * $Id: if_my.c,v 1.40 2001/11/30 03:55:00 <yen_cw@myson.com.tw> wpaul Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
43 #include <sys/types.h>
45 #include <sys/module.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_media.h>
53 #include <net/if_dl.h>
56 #include <vm/vm.h> /* for vtophys */
57 #include <vm/pmap.h> /* for vtophys */
58 #include <machine/clock.h> /* for DELAY */
59 #include <machine/bus_memio.h>
60 #include <machine/bus_pio.h>
61 #include <machine/bus.h>
62 #include <machine/resource.h>
66 #include <bus/pci/pcireg.h>
67 #include <bus/pci/pcivar.h>
69 #include "../mii_layer/mii.h"
70 #include "../mii_layer/miivar.h"
72 #include "miibus_if.h"
75 * #define MY_USEIOSPACE
78 static int MY_USEIOSPACE = 1;
81 #define MY_RES SYS_RES_IOPORT
82 #define MY_RID MY_PCI_LOIO
84 #define MY_RES SYS_RES_MEMORY
85 #define MY_RID MY_PCI_LOMEM
92 * Various supported device vendors/types and their names.
94 struct my_type *my_info_tmp;
95 static struct my_type my_devs[] = {
96 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
97 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
98 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
103 * Various supported PHY vendors/types and their names. Note that this driver
104 * will work with pretty much any MII-compliant PHY, so failure to positively
105 * identify the chip is not a fatal error.
107 static struct my_type my_phys[] = {
108 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
109 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
110 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
111 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
112 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
113 {0, 0, "<MII-compliant physical interface>"}
116 static int my_probe(device_t);
117 static int my_attach(device_t);
118 static int my_detach(device_t);
119 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
120 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
121 static void my_rxeof(struct my_softc *);
122 static void my_txeof(struct my_softc *);
123 static void my_txeoc(struct my_softc *);
124 static void my_intr(void *);
125 static void my_start(struct ifnet *);
126 static int my_ioctl(struct ifnet *, u_long, caddr_t);
127 static void my_init(void *);
128 static void my_stop(struct my_softc *);
129 static void my_watchdog(struct ifnet *);
130 static void my_shutdown(device_t);
131 static int my_ifmedia_upd(struct ifnet *);
132 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
133 static u_int16_t my_phy_readreg(struct my_softc *, int);
134 static void my_phy_writereg(struct my_softc *, int, int);
135 static void my_autoneg_xmit(struct my_softc *);
136 static void my_autoneg_mii(struct my_softc *, int, int);
137 static void my_setmode_mii(struct my_softc *, int);
138 static void my_getmode_mii(struct my_softc *);
139 static void my_setcfg(struct my_softc *, int);
140 static u_int8_t my_calchash(caddr_t);
141 static void my_setmulti(struct my_softc *);
142 static void my_reset(struct my_softc *);
143 static int my_list_rx_init(struct my_softc *);
144 static int my_list_tx_init(struct my_softc *);
145 static long my_send_cmd_to_phy(struct my_softc *, int, int);
147 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
148 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
150 static device_method_t my_methods[] = {
151 /* Device interface */
152 DEVMETHOD(device_probe, my_probe),
153 DEVMETHOD(device_attach, my_attach),
154 DEVMETHOD(device_detach, my_detach),
155 DEVMETHOD(device_shutdown, my_shutdown),
160 static driver_t my_driver = {
163 sizeof(struct my_softc)
166 static devclass_t my_devclass;
168 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0);
171 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
179 /* enable MII output */
180 miir = CSR_READ_4(sc, MY_MANAGEMENT);
183 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
185 /* send 32 1's preamble */
186 for (i = 0; i < 32; i++) {
187 /* low MDC; MDO is already high (miir) */
188 miir &= ~MY_MASK_MIIR_MII_MDC;
189 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
192 miir |= MY_MASK_MIIR_MII_MDC;
193 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
196 /* calculate ST+OP+PHYAD+REGAD+TA */
197 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
202 /* low MDC, prepare MDO */
203 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
205 miir |= MY_MASK_MIIR_MII_MDO;
207 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
209 miir |= MY_MASK_MIIR_MII_MDC;
210 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
215 if (mask == 0x2 && opcode == MY_OP_READ)
216 miir &= ~MY_MASK_MIIR_MII_WRITE;
225 my_phy_readreg(struct my_softc * sc, int reg)
232 if (sc->my_info->my_did == MTD803ID)
233 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
235 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
242 miir &= ~MY_MASK_MIIR_MII_MDC;
243 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
246 miir = CSR_READ_4(sc, MY_MANAGEMENT);
247 if (miir & MY_MASK_MIIR_MII_MDI)
250 /* high MDC, and wait */
251 miir |= MY_MASK_MIIR_MII_MDC;
252 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
260 miir &= ~MY_MASK_MIIR_MII_MDC;
261 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
265 return (u_int16_t) data;
270 my_phy_writereg(struct my_softc * sc, int reg, int data)
277 if (sc->my_info->my_did == MTD803ID)
278 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
280 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
285 /* low MDC, prepare MDO */
286 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
288 miir |= MY_MASK_MIIR_MII_MDO;
289 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
293 miir |= MY_MASK_MIIR_MII_MDC;
294 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
302 miir &= ~MY_MASK_MIIR_MII_MDC;
303 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
310 my_calchash(caddr_t addr)
312 u_int32_t crc, carry;
316 /* Compute CRC for the address value. */
317 crc = 0xFFFFFFFF; /* initial value */
319 for (i = 0; i < 6; i++) {
321 for (j = 0; j < 8; j++) {
322 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
326 crc = (crc ^ 0x04c11db6) | carry;
331 * return the filter bit position Note: I arrived at the following
332 * nonsense through experimentation. It's not the usual way to
333 * generate the bit position but it's the only thing I could come up
336 return (~(crc >> 26) & 0x0000003F);
341 * Program the 64-bit multicast hash filter.
344 my_setmulti(struct my_softc * sc)
348 u_int32_t hashes[2] = {0, 0};
349 struct ifmultiaddr *ifma;
355 ifp = &sc->arpcom.ac_if;
357 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
359 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
361 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
362 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
363 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
369 /* first, zot all the existing hash bits */
370 CSR_WRITE_4(sc, MY_MAR0, 0);
371 CSR_WRITE_4(sc, MY_MAR1, 0);
373 /* now program new ones */
374 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
375 if (ifma->ifma_addr->sa_family != AF_LINK)
377 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr));
379 hashes[0] |= (1 << h);
381 hashes[1] |= (1 << (h - 32));
389 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
390 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
391 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
397 * Initiate an autonegotiation session.
400 my_autoneg_xmit(struct my_softc * sc)
402 u_int16_t phy_sts = 0;
406 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
408 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
410 phy_sts = my_phy_readreg(sc, PHY_BMCR);
411 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
412 my_phy_writereg(sc, PHY_BMCR, phy_sts);
420 * Invoke autonegotiation on a PHY.
423 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
425 u_int16_t phy_sts = 0, media, advert, ability;
426 u_int16_t ability2 = 0;
433 ifp = &sc->arpcom.ac_if;
435 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
437 #ifndef FORCE_AUTONEG_TFOUR
439 * First, see if autoneg is supported. If not, there's no point in
442 phy_sts = my_phy_readreg(sc, PHY_BMSR);
443 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
445 printf("my%d: autonegotiation not supported\n",
447 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
453 case MY_FLAG_FORCEDELAY:
455 * XXX Never use this option anywhere but in the probe
456 * routine: making the kernel stop dead in its tracks for
457 * three whole seconds after we've gone multi-user is really
463 case MY_FLAG_SCHEDDELAY:
465 * Wait for the transmitter to go idle before starting an
466 * autoneg session, otherwise my_start() may clobber our
467 * timeout, and we don't want to allow transmission during an
468 * autoneg session since that can screw it up.
470 if (sc->my_cdata.my_tx_head != NULL) {
471 sc->my_want_auto = 1;
478 sc->my_want_auto = 0;
481 case MY_FLAG_DELAYTIMEO:
486 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag);
491 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
493 printf("my%d: autoneg complete, ", sc->my_unit);
494 phy_sts = my_phy_readreg(sc, PHY_BMSR);
497 printf("my%d: autoneg not complete, ", sc->my_unit);
500 media = my_phy_readreg(sc, PHY_BMCR);
502 /* Link is good. Report modes and set duplex mode. */
503 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
505 printf("my%d: link status good. ", sc->my_unit);
506 advert = my_phy_readreg(sc, PHY_ANAR);
507 ability = my_phy_readreg(sc, PHY_LPAR);
508 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
509 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
510 ability2 = my_phy_readreg(sc, PHY_1000SR);
511 if (ability2 & PHY_1000SR_1000BTXFULL) {
515 * this version did not support 1000M,
517 * IFM_ETHER|IFM_1000_TX|IFM_FDX;
520 IFM_ETHER | IFM_100_TX | IFM_FDX;
521 media &= ~PHY_BMCR_SPEEDSEL;
522 media |= PHY_BMCR_1000;
523 media |= PHY_BMCR_DUPLEX;
524 printf("(full-duplex, 1000Mbps)\n");
525 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
529 * this version did not support 1000M,
530 * ifm->ifm_media = IFM_ETHER|IFM_1000_TX;
532 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
533 media &= ~PHY_BMCR_SPEEDSEL;
534 media &= ~PHY_BMCR_DUPLEX;
535 media |= PHY_BMCR_1000;
536 printf("(half-duplex, 1000Mbps)\n");
539 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
540 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
541 media |= PHY_BMCR_SPEEDSEL;
542 media &= ~PHY_BMCR_DUPLEX;
543 printf("(100baseT4)\n");
544 } else if (advert & PHY_ANAR_100BTXFULL &&
545 ability & PHY_ANAR_100BTXFULL) {
546 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
547 media |= PHY_BMCR_SPEEDSEL;
548 media |= PHY_BMCR_DUPLEX;
549 printf("(full-duplex, 100Mbps)\n");
550 } else if (advert & PHY_ANAR_100BTXHALF &&
551 ability & PHY_ANAR_100BTXHALF) {
552 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
553 media |= PHY_BMCR_SPEEDSEL;
554 media &= ~PHY_BMCR_DUPLEX;
555 printf("(half-duplex, 100Mbps)\n");
556 } else if (advert & PHY_ANAR_10BTFULL &&
557 ability & PHY_ANAR_10BTFULL) {
558 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
559 media &= ~PHY_BMCR_SPEEDSEL;
560 media |= PHY_BMCR_DUPLEX;
561 printf("(full-duplex, 10Mbps)\n");
563 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
564 media &= ~PHY_BMCR_SPEEDSEL;
565 media &= ~PHY_BMCR_DUPLEX;
566 printf("(half-duplex, 10Mbps)\n");
568 media &= ~PHY_BMCR_AUTONEGENBL;
570 /* Set ASIC's duplex mode to match the PHY. */
571 my_phy_writereg(sc, PHY_BMCR, media);
572 my_setcfg(sc, media);
575 printf("my%d: no carrier\n", sc->my_unit);
579 if (sc->my_tx_pend) {
589 * To get PHY ability.
592 my_getmode_mii(struct my_softc * sc)
598 ifp = &sc->arpcom.ac_if;
599 bmsr = my_phy_readreg(sc, PHY_BMSR);
601 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr);
604 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
606 if (bmsr & PHY_BMSR_10BTHALF) {
608 printf("my%d: 10Mbps half-duplex mode supported\n",
610 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
612 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
614 if (bmsr & PHY_BMSR_10BTFULL) {
616 printf("my%d: 10Mbps full-duplex mode supported\n",
619 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
621 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
623 if (bmsr & PHY_BMSR_100BTXHALF) {
625 printf("my%d: 100Mbps half-duplex mode supported\n",
627 ifp->if_baudrate = 100000000;
628 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
629 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
631 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
633 if (bmsr & PHY_BMSR_100BTXFULL) {
635 printf("my%d: 100Mbps full-duplex mode supported\n",
637 ifp->if_baudrate = 100000000;
638 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
640 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
642 /* Some also support 100BaseT4. */
643 if (bmsr & PHY_BMSR_100BT4) {
645 printf("my%d: 100baseT4 mode supported\n", sc->my_unit);
646 ifp->if_baudrate = 100000000;
647 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
648 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
649 #ifdef FORCE_AUTONEG_TFOUR
651 printf("my%d: forcing on autoneg support for BT4\n",
653 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
654 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
657 #if 0 /* this version did not support 1000M, */
658 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
660 printf("my%d: 1000Mbps half-duplex mode supported\n",
663 ifp->if_baudrate = 1000000000;
664 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX, 0, NULL);
665 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX | IFM_HDX,
668 printf("my%d: 1000Mbps full-duplex mode supported\n",
670 ifp->if_baudrate = 1000000000;
671 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX | IFM_FDX,
673 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_TX | IFM_FDX;
676 if (bmsr & PHY_BMSR_CANAUTONEG) {
678 printf("my%d: autoneg supported\n", sc->my_unit);
679 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
680 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
687 * Set speed and duplex mode.
690 my_setmode_mii(struct my_softc * sc, int media)
696 ifp = &sc->arpcom.ac_if;
698 * If an autoneg session is in progress, stop it.
700 if (sc->my_autoneg) {
701 printf("my%d: canceling autoneg session\n", sc->my_unit);
702 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0;
703 bmcr = my_phy_readreg(sc, PHY_BMCR);
704 bmcr &= ~PHY_BMCR_AUTONEGENBL;
705 my_phy_writereg(sc, PHY_BMCR, bmcr);
707 printf("my%d: selecting MII, ", sc->my_unit);
708 bmcr = my_phy_readreg(sc, PHY_BMCR);
709 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
710 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
712 #if 0 /* this version did not support 1000M, */
713 if (IFM_SUBTYPE(media) == IFM_1000_TX) {
714 printf("1000Mbps/T4, half-duplex\n");
715 bmcr &= ~PHY_BMCR_SPEEDSEL;
716 bmcr &= ~PHY_BMCR_DUPLEX;
717 bmcr |= PHY_BMCR_1000;
720 if (IFM_SUBTYPE(media) == IFM_100_T4) {
721 printf("100Mbps/T4, half-duplex\n");
722 bmcr |= PHY_BMCR_SPEEDSEL;
723 bmcr &= ~PHY_BMCR_DUPLEX;
725 if (IFM_SUBTYPE(media) == IFM_100_TX) {
727 bmcr |= PHY_BMCR_SPEEDSEL;
729 if (IFM_SUBTYPE(media) == IFM_10_T) {
731 bmcr &= ~PHY_BMCR_SPEEDSEL;
733 if ((media & IFM_GMASK) == IFM_FDX) {
734 printf("full duplex\n");
735 bmcr |= PHY_BMCR_DUPLEX;
737 printf("half duplex\n");
738 bmcr &= ~PHY_BMCR_DUPLEX;
740 my_phy_writereg(sc, PHY_BMCR, bmcr);
747 * The Myson manual states that in order to fiddle with the 'full-duplex' and
748 * '100Mbps' bits in the netconfig register, we first have to put the
749 * transmit and/or receive logic in the idle state.
752 my_setcfg(struct my_softc * sc, int bmcr)
757 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
759 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
760 for (i = 0; i < MY_TIMEOUT; i++) {
762 if (!(CSR_READ_4(sc, MY_TCRRCR) &
763 (MY_TXRUN | MY_RXRUN)))
767 printf("my%d: failed to force tx and rx to idle \n",
770 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
771 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
772 if (bmcr & PHY_BMCR_1000)
773 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
774 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
775 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
776 if (bmcr & PHY_BMCR_DUPLEX)
777 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
779 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
781 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
787 my_reset(struct my_softc * sc)
792 MY_SETBIT(sc, MY_BCR, MY_SWR);
793 for (i = 0; i < MY_TIMEOUT; i++) {
795 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
799 printf("m0x%d: reset never completed!\n", sc->my_unit);
801 /* Wait a little while for the chip to get its brains in order. */
808 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
809 * list and return a device name if we find a match.
812 my_probe(device_t dev)
817 while (t->my_name != NULL) {
818 if ((pci_get_vendor(dev) == t->my_vid) &&
819 (pci_get_device(dev) == t->my_did)) {
820 device_set_desc(dev, t->my_name);
830 * Attach the interface. Allocate softc structures, do ifmedia setup and
831 * ethernet/BPF attach.
834 my_attach(device_t dev)
837 u_char eaddr[ETHER_ADDR_LEN];
838 u_int32_t command, iobase;
841 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
845 u_int16_t phy_vid, phy_did, phy_sts = 0;
846 int rid, unit, error = 0;
849 sc = device_get_softc(dev);
850 unit = device_get_unit(dev);
852 printf("my%d: no memory for softc struct!\n", unit);
857 bzero(sc, sizeof(struct my_softc));
858 /*mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);*/
862 * Map control/status registers.
865 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
866 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
867 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4);
868 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
870 command = pci_read_config(dev, PCIR_COMMAND, 4);
871 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
872 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4);
873 command = pci_read_config(dev, PCIR_COMMAND, 4);
875 if (my_info_tmp->my_did == MTD800ID) {
876 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
881 if (!(command & PCIM_CMD_PORTEN)) {
882 printf("my%d: failed to enable I/O ports!\n", unit);
888 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) {
889 printf("my%d: couldn't map ports\n", unit);
894 sc->my_btag = I386_BUS_SPACE_IO;
897 if (!(command & PCIM_CMD_MEMEN)) {
898 printf("my%d: failed to enable memory mapping!\n",
904 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) {
905 printf ("my%d: couldn't map memory\n", unit);
909 sc->my_btag = I386_BUS_SPACE_MEM;
910 sc->my_bhandle = vbase;
915 sc->my_res = bus_alloc_resource(dev, MY_RES, &rid,
916 0, ~0, 1, RF_ACTIVE);
918 if (sc->my_res == NULL) {
919 printf("my%d: couldn't map ports/memory\n", unit);
923 sc->my_btag = rman_get_bustag(sc->my_res);
924 sc->my_bhandle = rman_get_bushandle(sc->my_res);
927 sc->my_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
928 RF_SHAREABLE | RF_ACTIVE);
930 if (sc->my_irq == NULL) {
931 printf("my%d: couldn't map interrupt\n", unit);
932 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
936 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET,
937 my_intr, sc, &sc->my_intrhand);
940 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
941 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
942 printf("my%d: couldn't set up irq\n", unit);
945 callout_handle_init(&sc->my_stat_ch);
947 sc->my_info = my_info_tmp;
949 /* Reset the adapter. */
953 * Get station address
955 for (i = 0; i < ETHER_ADDR_LEN; ++i)
956 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
959 * A Myson chip was detected. Inform the world.
961 printf("my%d: Ethernet address: %6D\n", unit, eaddr, ":");
964 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
966 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
968 if (sc->my_ldata_ptr == NULL) {
970 printf("my%d: no memory for list buffers!\n", unit);
974 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
975 round = (unsigned int)sc->my_ldata_ptr & 0xF;
976 roundptr = sc->my_ldata_ptr;
977 for (i = 0; i < 8; i++) {
984 sc->my_ldata = (struct my_list_data *) roundptr;
985 bzero(sc->my_ldata, sizeof(struct my_list_data));
987 ifp = &sc->arpcom.ac_if;
991 ifp->if_mtu = ETHERMTU;
992 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
993 ifp->if_ioctl = my_ioctl;
994 ifp->if_output = ether_output;
995 ifp->if_start = my_start;
996 ifp->if_watchdog = my_watchdog;
997 ifp->if_init = my_init;
998 ifp->if_baudrate = 10000000;
999 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1001 if (sc->my_info->my_did == MTD803ID)
1002 sc->my_pinfo = my_phys;
1005 printf("my%d: probing for a PHY\n", sc->my_unit);
1006 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
1008 printf("my%d: checking address: %d\n",
1010 sc->my_phy_addr = i;
1011 phy_sts = my_phy_readreg(sc, PHY_BMSR);
1012 if ((phy_sts != 0) && (phy_sts != 0xffff))
1018 phy_vid = my_phy_readreg(sc, PHY_VENID);
1019 phy_did = my_phy_readreg(sc, PHY_DEVID);
1021 printf("my%d: found PHY at address %d, ",
1022 sc->my_unit, sc->my_phy_addr);
1023 printf("vendor id: %x device id: %x\n",
1028 if (phy_vid == p->my_vid) {
1034 if (sc->my_pinfo == NULL)
1035 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
1037 printf("my%d: PHY type: %s\n",
1038 sc->my_unit, sc->my_pinfo->my_name);
1040 printf("my%d: MII without any phy!\n", sc->my_unit);
1046 /* Do ifmedia setup. */
1047 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
1049 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
1050 media = sc->ifmedia.ifm_media;
1052 ifmedia_set(&sc->ifmedia, media);
1054 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1057 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC);
1058 shutdownhook_establish(my_shutdown, sc);
1066 /*mtx_destroy(&sc->my_mtx);*/
1072 my_detach(device_t dev)
1074 struct my_softc *sc;
1079 sc = device_get_softc(dev);
1081 ifp = &sc->arpcom.ac_if;
1082 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1086 bus_generic_detach(dev);
1087 device_delete_child(dev, sc->rl_miibus);
1090 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
1091 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1092 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1094 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF);
1099 /*mtx_destroy(&sc->my_mtx);*/
1105 * Initialize the transmit descriptors.
1108 my_list_tx_init(struct my_softc * sc)
1110 struct my_chain_data *cd;
1111 struct my_list_data *ld;
1117 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1118 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1119 if (i == (MY_TX_LIST_CNT - 1))
1120 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1122 cd->my_tx_chain[i].my_nextdesc =
1123 &cd->my_tx_chain[i + 1];
1125 cd->my_tx_free = &cd->my_tx_chain[0];
1126 cd->my_tx_tail = cd->my_tx_head = NULL;
1132 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1133 * arrange the descriptors in a closed ring, so that the last descriptor
1134 * points back to the first.
1137 my_list_rx_init(struct my_softc * sc)
1139 struct my_chain_data *cd;
1140 struct my_list_data *ld;
1146 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1147 cd->my_rx_chain[i].my_ptr =
1148 (struct my_desc *) & ld->my_rx_list[i];
1149 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS)
1151 if (i == (MY_RX_LIST_CNT - 1)) {
1152 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1153 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1155 cd->my_rx_chain[i].my_nextdesc =
1156 &cd->my_rx_chain[i + 1];
1157 ld->my_rx_list[i].my_next =
1158 vtophys(&ld->my_rx_list[i + 1]);
1161 cd->my_rx_head = &cd->my_rx_chain[0];
1167 * Initialize an RX descriptor and attach an MBUF cluster.
1170 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1172 struct mbuf *m_new = NULL;
1175 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1176 if (m_new == NULL) {
1177 printf("my%d: no memory for rx list -- packet dropped!\n",
1181 MCLGET(m_new, M_DONTWAIT);
1182 if (!(m_new->m_flags & M_EXT)) {
1183 printf("my%d: no memory for rx list -- packet dropped!\n",
1189 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1190 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1191 c->my_ptr->my_status = MY_OWNByNIC;
1197 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1201 my_rxeof(struct my_softc * sc)
1203 struct ether_header *eh;
1206 struct my_chain_onefrag *cur_rx;
1211 ifp = &sc->arpcom.ac_if;
1212 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1214 cur_rx = sc->my_cdata.my_rx_head;
1215 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1217 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1219 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1222 /* No errors; receive the packet. */
1223 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1224 total_len -= ETHER_CRC_LEN;
1226 if (total_len < MINCLSIZE) {
1227 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1228 total_len, 0, ifp, NULL);
1229 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1235 m = cur_rx->my_mbuf;
1237 * Try to conjure up a new mbuf cluster. If that
1238 * fails, it means we have an out of memory condition
1239 * and should leave the buffer in place and continue.
1240 * This will result in a lost packet, but there's
1241 * little else we can do in this situation.
1243 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1245 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1248 m->m_pkthdr.rcvif = ifp;
1249 m->m_pkthdr.len = m->m_len = total_len;
1252 eh = mtod(m, struct ether_header *);
1255 * Handle BPF listeners. Let the BPF user see the packet, but
1256 * don't pass it up to the ether_input() layer unless it's a
1257 * broadcast packet, multicast packet, matches our ethernet
1258 * address or the interface is in promiscuous mode.
1262 if (ifp->if_flags & IFF_PROMISC &&
1263 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1265 (eh->ether_dhost[0] & 1) == 0)) {
1271 /* Remove header from mbuf and pass it on. */
1272 m_adj(m, sizeof(struct ether_header));
1273 ether_input(ifp, eh, m);
1281 * A frame was downloaded to the chip. It's safe for us to clean up the list
1285 my_txeof(struct my_softc * sc)
1287 struct my_chain *cur_tx;
1291 ifp = &sc->arpcom.ac_if;
1292 /* Clear the timeout timer. */
1294 if (sc->my_cdata.my_tx_head == NULL)
1297 * Go through our tx list and free mbufs for those frames that have
1300 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1303 cur_tx = sc->my_cdata.my_tx_head;
1304 txstat = MY_TXSTATUS(cur_tx);
1305 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1307 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1308 if (txstat & MY_TXERR) {
1310 if (txstat & MY_EC) /* excessive collision */
1311 ifp->if_collisions++;
1312 if (txstat & MY_LC) /* late collision */
1313 ifp->if_collisions++;
1315 ifp->if_collisions += (txstat & MY_NCRMASK) >>
1319 m_freem(cur_tx->my_mbuf);
1320 cur_tx->my_mbuf = NULL;
1321 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1322 sc->my_cdata.my_tx_head = NULL;
1323 sc->my_cdata.my_tx_tail = NULL;
1326 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1328 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1329 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask);
1336 * TX 'end of channel' interrupt handler.
1339 my_txeoc(struct my_softc * sc)
1344 ifp = &sc->arpcom.ac_if;
1346 if (sc->my_cdata.my_tx_head == NULL) {
1347 ifp->if_flags &= ~IFF_OACTIVE;
1348 sc->my_cdata.my_tx_tail = NULL;
1349 if (sc->my_want_auto)
1350 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1352 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1353 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1355 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1365 struct my_softc *sc;
1371 ifp = &sc->arpcom.ac_if;
1372 if (!(ifp->if_flags & IFF_UP)) {
1376 /* Disable interrupts. */
1377 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1380 status = CSR_READ_4(sc, MY_ISR);
1383 CSR_WRITE_4(sc, MY_ISR, status);
1387 if (status & MY_RI) /* receive interrupt */
1390 if ((status & MY_RBU) || (status & MY_RxErr)) {
1391 /* rx buffer unavailable or rx error */
1399 if (status & MY_TI) /* tx interrupt */
1401 if (status & MY_ETI) /* tx early interrupt */
1403 if (status & MY_TBU) /* tx buffer unavailable */
1406 #if 0 /* 90/1/18 delete */
1407 if (status & MY_FBE) {
1415 /* Re-enable interrupts. */
1416 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1417 if (ifp->if_snd.ifq_head != NULL)
1424 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1425 * pointers to the fragment pointers.
1428 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1430 struct my_desc *f = NULL;
1432 struct mbuf *m, *m_new = NULL;
1435 /* calculate the total tx pkt length */
1437 for (m = m_head; m != NULL; m = m->m_next)
1438 total_len += m->m_len;
1440 * Start packing the mbufs in this chain into the fragment pointers.
1441 * Stop when we run out of fragments or hit the end of the mbuf
1445 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1446 if (m_new == NULL) {
1447 printf("my%d: no memory for tx list", sc->my_unit);
1450 if (m_head->m_pkthdr.len > MHLEN) {
1451 MCLGET(m_new, M_DONTWAIT);
1452 if (!(m_new->m_flags & M_EXT)) {
1454 printf("my%d: no memory for tx list", sc->my_unit);
1458 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1459 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1462 f = &c->my_ptr->my_frag[0];
1464 f->my_data = vtophys(mtod(m_new, caddr_t));
1465 total_len = m_new->m_len;
1466 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1467 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1468 f->my_ctl |= total_len; /* buffer size */
1469 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1470 if (sc->my_info->my_did == MTD891ID)
1471 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1472 c->my_mbuf = m_head;
1474 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1480 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1481 * to the mbuf data regions directly in the transmit lists. We also save a
1482 * copy of the pointers since the transmit list fragment pointers are
1483 * physical addresses.
1486 my_start(struct ifnet * ifp)
1488 struct my_softc *sc;
1489 struct mbuf *m_head = NULL;
1490 struct my_chain *cur_tx = NULL, *start_tx;
1494 if (sc->my_autoneg) {
1500 * Check for an available queue slot. If there are none, punt.
1502 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1503 ifp->if_flags |= IFF_OACTIVE;
1507 start_tx = sc->my_cdata.my_tx_free;
1508 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1509 IF_DEQUEUE(&ifp->if_snd, m_head);
1513 /* Pick a descriptor off the free list. */
1514 cur_tx = sc->my_cdata.my_tx_free;
1515 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1517 /* Pack the data into the descriptor. */
1518 my_encap(sc, cur_tx, m_head);
1520 if (cur_tx != start_tx)
1521 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1524 * If there's a BPF listener, bounce a copy of this frame to
1528 bpf_mtap(ifp, cur_tx->my_mbuf);
1532 * If there are no packets queued, bail.
1534 if (cur_tx == NULL) {
1539 * Place the request for the upload interrupt in the last descriptor
1540 * in the chain. This way, if we're chaining several packets at once,
1541 * we'll only get an interupt once for the whole chain rather than
1542 * once for each packet.
1544 MY_TXCTL(cur_tx) |= MY_TXIC;
1545 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1546 sc->my_cdata.my_tx_tail = cur_tx;
1547 if (sc->my_cdata.my_tx_head == NULL)
1548 sc->my_cdata.my_tx_head = start_tx;
1549 MY_TXOWN(start_tx) = MY_OWNByNIC;
1550 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1553 * Set a timeout in case the chip goes out to lunch.
1563 struct my_softc *sc = xsc;
1564 struct ifnet *ifp = &sc->arpcom.ac_if;
1566 u_int16_t phy_bmcr = 0;
1569 if (sc->my_autoneg) {
1574 if (sc->my_pinfo != NULL)
1575 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1577 * Cancel pending I/O and free all RX/TX buffers.
1583 * Set cache alignment and burst length.
1585 #if 0 /* 89/9/1 modify, */
1586 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1587 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1589 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1590 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1592 * 89/12/29 add, for mtd891,
1594 if (sc->my_info->my_did == MTD891ID) {
1595 MY_SETBIT(sc, MY_BCR, MY_PROG);
1596 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1598 my_setcfg(sc, phy_bmcr);
1599 /* Init circular RX list. */
1600 if (my_list_rx_init(sc) == ENOBUFS) {
1601 printf("my%d: init failed: no memory for rx buffers\n",
1608 /* Init TX descriptors. */
1609 my_list_tx_init(sc);
1611 /* If we want promiscuous mode, set the allframes bit. */
1612 if (ifp->if_flags & IFF_PROMISC)
1613 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1615 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1618 * Set capture broadcast bit to capture broadcast frames.
1620 if (ifp->if_flags & IFF_BROADCAST)
1621 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1623 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1626 * Program the multicast filter, if necessary.
1631 * Load the address of the RX list.
1633 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1634 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1637 * Enable interrupts.
1639 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1640 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1642 /* Enable receiver and transmitter. */
1643 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1644 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1645 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1646 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1648 /* Restore state of BMCR */
1649 if (sc->my_pinfo != NULL)
1650 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1651 ifp->if_flags |= IFF_RUNNING;
1652 ifp->if_flags &= ~IFF_OACTIVE;
1659 * Set media options.
1663 my_ifmedia_upd(struct ifnet * ifp)
1665 struct my_softc *sc;
1666 struct ifmedia *ifm;
1671 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1675 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1676 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1678 my_setmode_mii(sc, ifm->ifm_media);
1684 * Report current media status.
1688 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1690 struct my_softc *sc;
1691 u_int16_t advert = 0, ability = 0;
1695 ifmr->ifm_active = IFM_ETHER;
1696 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1697 #if 0 /* this version did not support 1000M, */
1698 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1699 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1701 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1702 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1704 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1705 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1706 ifmr->ifm_active |= IFM_FDX;
1708 ifmr->ifm_active |= IFM_HDX;
1713 ability = my_phy_readreg(sc, PHY_LPAR);
1714 advert = my_phy_readreg(sc, PHY_ANAR);
1716 #if 0 /* this version did not support 1000M, */
1717 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1718 ability2 = my_phy_readreg(sc, PHY_1000SR);
1719 if (ability2 & PHY_1000SR_1000BTXFULL) {
1722 ifmr->ifm_active = IFM_ETHER|IFM_1000_TX|IFM_FDX;
1723 } else if (ability & PHY_1000SR_1000BTXHALF) {
1726 ifmr->ifm_active = IFM_ETHER|IFM_1000_TX|IFM_HDX;
1730 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1731 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1732 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1733 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1734 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1735 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1736 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1737 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1738 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1739 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1745 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
1747 struct my_softc *sc = ifp->if_softc;
1748 struct ifreq *ifr = (struct ifreq *) data;
1757 error = ether_ioctl(ifp, command, data);
1760 if (ifp->if_flags & IFF_UP)
1762 else if (ifp->if_flags & IFF_RUNNING)
1773 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1785 my_watchdog(struct ifnet * ifp)
1787 struct my_softc *sc;
1791 if (sc->my_autoneg) {
1792 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
1797 printf("my%d: watchdog timeout\n", sc->my_unit);
1798 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1799 printf("my%d: no carrier - transceiver cable problem?\n",
1804 if (ifp->if_snd.ifq_head != NULL)
1812 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1815 my_stop(struct my_softc * sc)
1821 ifp = &sc->arpcom.ac_if;
1824 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1825 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1826 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1827 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1830 * Free data in the RX lists.
1832 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1833 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1834 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1835 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1838 bzero((char *)&sc->my_ldata->my_rx_list,
1839 sizeof(sc->my_ldata->my_rx_list));
1841 * Free the TX list buffers.
1843 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1844 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1845 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1846 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1849 bzero((char *)&sc->my_ldata->my_tx_list,
1850 sizeof(sc->my_ldata->my_tx_list));
1851 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1857 * Stop all chip I/O so that the kernel's probe routines don't get confused
1858 * by errant DMAs when rebooting.
1861 my_shutdown(device_t dev)
1863 struct my_softc *sc;
1865 sc = device_get_softc(dev);