2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.4 2003/08/07 21:17:05 dillon Exp $
35 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
39 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
40 * available from http://www.sis.com.tw.
42 * This driver also supports the NatSemi DP83815. Datasheets are
43 * available from http://www.national.com.
45 * Written by Bill Paul <wpaul@ee.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
51 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
52 * simple TX and RX descriptors of 3 longwords in size. The receiver
53 * has a single perfect filter entry for the station address and a
54 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
55 * transceiver while the 7016 requires an external transceiver chip.
56 * Both chips offer the standard bit-bang MII interface as well as
57 * an enchanced PHY interface which simplifies accessing MII registers.
59 * The only downside to this chipset is that RX descriptors must be
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/sockio.h>
67 #include <sys/malloc.h>
68 #include <sys/kernel.h>
69 #include <sys/socket.h>
70 #include <sys/sysctl.h>
73 #include <net/if_arp.h>
74 #include <net/ethernet.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/vlan/if_vlan_var.h>
82 #include <vm/vm.h> /* for vtophys */
83 #include <vm/pmap.h> /* for vtophys */
84 #include <machine/clock.h> /* for DELAY */
85 #include <machine/bus_pio.h>
86 #include <machine/bus_memio.h>
87 #include <machine/bus.h>
88 #include <machine/resource.h>
92 #include "../mii_layer/mii.h"
93 #include "../mii_layer/miivar.h"
95 #include <bus/pci/pcireg.h>
96 #include <bus/pci/pcivar.h>
98 #define SIS_USEIOSPACE
100 #include "if_sisreg.h"
102 /* "controller miibus0" required. See GENERIC if you get errors here. */
103 #include "miibus_if.h"
106 * Various supported device vendors/types and their names.
108 static struct sis_type sis_devs[] = {
109 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
110 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
111 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" },
115 static int sis_probe __P((device_t));
116 static int sis_attach __P((device_t));
117 static int sis_detach __P((device_t));
119 static int sis_newbuf __P((struct sis_softc *,
122 static int sis_encap __P((struct sis_softc *,
123 struct mbuf *, u_int32_t *));
124 static void sis_rxeof __P((struct sis_softc *));
125 static void sis_rxeoc __P((struct sis_softc *));
126 static void sis_txeof __P((struct sis_softc *));
127 static void sis_intr __P((void *));
128 static void sis_tick __P((void *));
129 static void sis_start __P((struct ifnet *));
130 static int sis_ioctl __P((struct ifnet *, u_long, caddr_t));
131 static void sis_init __P((void *));
132 static void sis_stop __P((struct sis_softc *));
133 static void sis_watchdog __P((struct ifnet *));
134 static void sis_shutdown __P((device_t));
135 static int sis_ifmedia_upd __P((struct ifnet *));
136 static void sis_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
138 static u_int16_t sis_reverse __P((u_int16_t));
139 static void sis_delay __P((struct sis_softc *));
140 static void sis_eeprom_idle __P((struct sis_softc *));
141 static void sis_eeprom_putbyte __P((struct sis_softc *, int));
142 static void sis_eeprom_getword __P((struct sis_softc *, int, u_int16_t *));
143 static void sis_read_eeprom __P((struct sis_softc *, caddr_t, int,
146 static void sis_read_cmos __P((struct sis_softc *, device_t, caddr_t,
148 static void sis_read_mac __P((struct sis_softc *, device_t, caddr_t));
149 static device_t sis_find_bridge __P((device_t));
152 static void sis_mii_sync __P((struct sis_softc *));
153 static void sis_mii_send __P((struct sis_softc *, u_int32_t, int));
154 static int sis_mii_readreg __P((struct sis_softc *, struct sis_mii_frame *));
155 static int sis_mii_writereg __P((struct sis_softc *, struct sis_mii_frame *));
156 static int sis_miibus_readreg __P((device_t, int, int));
157 static int sis_miibus_writereg __P((device_t, int, int, int));
158 static void sis_miibus_statchg __P((device_t));
160 static void sis_setmulti_sis __P((struct sis_softc *));
161 static void sis_setmulti_ns __P((struct sis_softc *));
162 static u_int32_t sis_crc __P((struct sis_softc *, caddr_t));
163 static void sis_reset __P((struct sis_softc *));
164 static int sis_list_rx_init __P((struct sis_softc *));
165 static int sis_list_tx_init __P((struct sis_softc *));
167 #ifdef SIS_USEIOSPACE
168 #define SIS_RES SYS_RES_IOPORT
169 #define SIS_RID SIS_PCI_LOIO
171 #define SIS_RES SYS_RES_MEMORY
172 #define SIS_RID SIS_PCI_LOMEM
175 static device_method_t sis_methods[] = {
176 /* Device interface */
177 DEVMETHOD(device_probe, sis_probe),
178 DEVMETHOD(device_attach, sis_attach),
179 DEVMETHOD(device_detach, sis_detach),
180 DEVMETHOD(device_shutdown, sis_shutdown),
183 DEVMETHOD(bus_print_child, bus_generic_print_child),
184 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
187 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
188 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
189 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
194 static driver_t sis_driver = {
197 sizeof(struct sis_softc)
200 static devclass_t sis_devclass;
202 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0);
203 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
205 #define SIS_SETBIT(sc, reg, x) \
206 CSR_WRITE_4(sc, reg, \
207 CSR_READ_4(sc, reg) | (x))
209 #define SIS_CLRBIT(sc, reg, x) \
210 CSR_WRITE_4(sc, reg, \
211 CSR_READ_4(sc, reg) & ~(x))
214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
217 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
220 * Routine to reverse the bits in a word. Stolen almost
221 * verbatim from /usr/games/fortune.
223 static u_int16_t sis_reverse(n)
226 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
227 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
228 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
229 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
234 static void sis_delay(sc)
235 struct sis_softc *sc;
239 for (idx = (300 / 33) + 1; idx > 0; idx--)
240 CSR_READ_4(sc, SIS_CSR);
245 static void sis_eeprom_idle(sc)
246 struct sis_softc *sc;
250 SIO_SET(SIS_EECTL_CSEL);
252 SIO_SET(SIS_EECTL_CLK);
255 for (i = 0; i < 25; i++) {
256 SIO_CLR(SIS_EECTL_CLK);
258 SIO_SET(SIS_EECTL_CLK);
262 SIO_CLR(SIS_EECTL_CLK);
264 SIO_CLR(SIS_EECTL_CSEL);
266 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
272 * Send a read command and address to the EEPROM, check for ACK.
274 static void sis_eeprom_putbyte(sc, addr)
275 struct sis_softc *sc;
280 d = addr | SIS_EECMD_READ;
283 * Feed in each bit and stobe the clock.
285 for (i = 0x400; i; i >>= 1) {
287 SIO_SET(SIS_EECTL_DIN);
289 SIO_CLR(SIS_EECTL_DIN);
292 SIO_SET(SIS_EECTL_CLK);
294 SIO_CLR(SIS_EECTL_CLK);
302 * Read a word of data stored in the EEPROM at address 'addr.'
304 static void sis_eeprom_getword(sc, addr, dest)
305 struct sis_softc *sc;
312 /* Force EEPROM to idle state. */
315 /* Enter EEPROM access mode. */
317 SIO_CLR(SIS_EECTL_CLK);
319 SIO_SET(SIS_EECTL_CSEL);
323 * Send address of word we want to read.
325 sis_eeprom_putbyte(sc, addr);
328 * Start reading bits from EEPROM.
330 for (i = 0x8000; i; i >>= 1) {
331 SIO_SET(SIS_EECTL_CLK);
333 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
336 SIO_CLR(SIS_EECTL_CLK);
340 /* Turn off EEPROM access mode. */
349 * Read a sequence of words from the EEPROM.
351 static void sis_read_eeprom(sc, dest, off, cnt, swap)
352 struct sis_softc *sc;
359 u_int16_t word = 0, *ptr;
361 for (i = 0; i < cnt; i++) {
362 sis_eeprom_getword(sc, off + i, &word);
363 ptr = (u_int16_t *)(dest + (i * 2));
374 static device_t sis_find_bridge(dev)
377 devclass_t pci_devclass;
378 device_t *pci_devices;
380 device_t *pci_children;
381 int pci_childcount = 0;
382 device_t *busp, *childp;
383 device_t child = NULL;
386 if ((pci_devclass = devclass_find("pci")) == NULL)
389 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
391 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
393 device_get_children(*busp, &pci_children, &pci_childcount);
394 for (j = 0, childp = pci_children;
395 j < pci_childcount; j++, childp++) {
396 if (pci_get_vendor(*childp) == SIS_VENDORID &&
397 pci_get_device(*childp) == 0x0008) {
405 free(pci_devices, M_TEMP);
406 free(pci_children, M_TEMP);
410 static void sis_read_cmos(sc, dev, dest, off, cnt)
411 struct sis_softc *sc;
420 bus_space_tag_t btag;
422 bridge = sis_find_bridge(dev);
425 reg = pci_read_config(bridge, 0x48, 1);
426 pci_write_config(bridge, 0x48, reg|0x40, 1);
429 btag = I386_BUS_SPACE_IO;
431 for (i = 0; i < cnt; i++) {
432 bus_space_write_1(btag, 0x0, 0x70, i + off);
433 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
436 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
440 static void sis_read_mac(sc, dev, dest)
441 struct sis_softc *sc;
445 u_int32_t filtsave, csrsave;
447 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
448 csrsave = CSR_READ_4(sc, SIS_CSR);
450 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
451 CSR_WRITE_4(sc, SIS_CSR, 0);
453 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
455 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
456 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
457 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
458 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
459 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
460 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
462 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
463 CSR_WRITE_4(sc, SIS_CSR, csrsave);
469 * Sync the PHYs by setting data bit and strobing the clock 32 times.
471 static void sis_mii_sync(sc)
472 struct sis_softc *sc;
476 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
478 for (i = 0; i < 32; i++) {
479 SIO_SET(SIS_MII_CLK);
481 SIO_CLR(SIS_MII_CLK);
489 * Clock a series of bits through the MII.
491 static void sis_mii_send(sc, bits, cnt)
492 struct sis_softc *sc;
498 SIO_CLR(SIS_MII_CLK);
500 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
502 SIO_SET(SIS_MII_DATA);
504 SIO_CLR(SIS_MII_DATA);
507 SIO_CLR(SIS_MII_CLK);
509 SIO_SET(SIS_MII_CLK);
514 * Read an PHY register through the MII.
516 static int sis_mii_readreg(sc, frame)
517 struct sis_softc *sc;
518 struct sis_mii_frame *frame;
526 * Set up frame for RX.
528 frame->mii_stdelim = SIS_MII_STARTDELIM;
529 frame->mii_opcode = SIS_MII_READOP;
530 frame->mii_turnaround = 0;
536 SIO_SET(SIS_MII_DIR);
541 * Send command/address info.
543 sis_mii_send(sc, frame->mii_stdelim, 2);
544 sis_mii_send(sc, frame->mii_opcode, 2);
545 sis_mii_send(sc, frame->mii_phyaddr, 5);
546 sis_mii_send(sc, frame->mii_regaddr, 5);
549 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
551 SIO_SET(SIS_MII_CLK);
555 SIO_CLR(SIS_MII_DIR);
558 SIO_CLR(SIS_MII_CLK);
560 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
561 SIO_SET(SIS_MII_CLK);
565 * Now try reading data bits. If the ack failed, we still
566 * need to clock through 16 cycles to keep the PHY(s) in sync.
569 for(i = 0; i < 16; i++) {
570 SIO_CLR(SIS_MII_CLK);
572 SIO_SET(SIS_MII_CLK);
578 for (i = 0x8000; i; i >>= 1) {
579 SIO_CLR(SIS_MII_CLK);
582 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
583 frame->mii_data |= i;
586 SIO_SET(SIS_MII_CLK);
592 SIO_CLR(SIS_MII_CLK);
594 SIO_SET(SIS_MII_CLK);
605 * Write to a PHY register through the MII.
607 static int sis_mii_writereg(sc, frame)
608 struct sis_softc *sc;
609 struct sis_mii_frame *frame;
616 * Set up frame for TX.
619 frame->mii_stdelim = SIS_MII_STARTDELIM;
620 frame->mii_opcode = SIS_MII_WRITEOP;
621 frame->mii_turnaround = SIS_MII_TURNAROUND;
624 * Turn on data output.
626 SIO_SET(SIS_MII_DIR);
630 sis_mii_send(sc, frame->mii_stdelim, 2);
631 sis_mii_send(sc, frame->mii_opcode, 2);
632 sis_mii_send(sc, frame->mii_phyaddr, 5);
633 sis_mii_send(sc, frame->mii_regaddr, 5);
634 sis_mii_send(sc, frame->mii_turnaround, 2);
635 sis_mii_send(sc, frame->mii_data, 16);
638 SIO_SET(SIS_MII_CLK);
640 SIO_CLR(SIS_MII_CLK);
646 SIO_CLR(SIS_MII_DIR);
653 static int sis_miibus_readreg(dev, phy, reg)
657 struct sis_softc *sc;
659 struct sis_mii_frame frame;
661 sc = device_get_softc(dev);
663 if (sc->sis_type == SIS_TYPE_83815) {
667 * The NatSemi chip can take a while after
668 * a reset to come ready, during which the BMSR
669 * returns a value of 0. This is *never* supposed
670 * to happen: some of the BMSR bits are meant to
671 * be hardwired in the on position, and this can
672 * confuse the miibus code a bit during the probe
673 * and attach phase. So we make an effort to check
674 * for this condition and wait for it to clear.
676 if (!CSR_READ_4(sc, NS_BMSR))
678 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
681 * Chipsets < SIS_635 seem not to be able to read/write
682 * through mdio. Use the enhanced PHY access register
685 if (sc->sis_type == SIS_TYPE_900 &&
686 sc->sis_rev < SIS_REV_635) {
691 CSR_WRITE_4(sc, SIS_PHYCTL,
692 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
693 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
695 for (i = 0; i < SIS_TIMEOUT; i++) {
696 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
700 if (i == SIS_TIMEOUT) {
701 printf("sis%d: PHY failed to come ready\n",
706 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
713 bzero((char *)&frame, sizeof(frame));
714 frame.mii_phyaddr = phy;
715 frame.mii_regaddr = reg;
716 sis_mii_readreg(sc, &frame);
717 return(frame.mii_data);
721 static int sis_miibus_writereg(dev, phy, reg, data)
725 struct sis_softc *sc;
727 struct sis_mii_frame frame;
729 sc = device_get_softc(dev);
731 if (sc->sis_type == SIS_TYPE_83815) {
734 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
738 if (sc->sis_type == SIS_TYPE_900 &&
739 sc->sis_rev < SIS_REV_635) {
743 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
744 (reg << 6) | SIS_PHYOP_WRITE);
745 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
747 for (i = 0; i < SIS_TIMEOUT; i++) {
748 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
752 if (i == SIS_TIMEOUT)
753 printf("sis%d: PHY failed to come ready\n",
756 bzero((char *)&frame, sizeof(frame));
758 frame.mii_phyaddr = phy;
759 frame.mii_regaddr = reg;
760 frame.mii_data = data;
761 sis_mii_writereg(sc, &frame);
766 static void sis_miibus_statchg(dev)
769 struct sis_softc *sc;
771 sc = device_get_softc(dev);
777 static u_int32_t sis_crc(sc, addr)
778 struct sis_softc *sc;
781 u_int32_t crc, carry;
785 /* Compute CRC for the address value. */
786 crc = 0xFFFFFFFF; /* initial value */
788 for (i = 0; i < 6; i++) {
790 for (j = 0; j < 8; j++) {
791 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
795 crc = (crc ^ 0x04c11db6) | carry;
800 * return the filter bit position
802 * The NatSemi chip has a 512-bit filter, which is
803 * different than the SiS, so we special-case it.
805 if (sc->sis_type == SIS_TYPE_83815)
807 else if (sc->sis_rev >= SIS_REV_635 ||
808 sc->sis_rev == SIS_REV_900B)
814 static void sis_setmulti_ns(sc)
815 struct sis_softc *sc;
818 struct ifmultiaddr *ifma;
819 u_int32_t h = 0, i, filtsave;
822 ifp = &sc->arpcom.ac_if;
824 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
825 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
826 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
831 * We have to explicitly enable the multicast hash table
832 * on the NatSemi chip if we want to use it, which we do.
834 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
835 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
837 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
839 /* first, zot all the existing hash bits */
840 for (i = 0; i < 32; i++) {
841 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
842 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
845 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
846 ifma = ifma->ifma_link.le_next) {
847 if (ifma->ifma_addr->sa_family != AF_LINK)
849 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
852 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
855 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
858 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
863 static void sis_setmulti_sis(sc)
864 struct sis_softc *sc;
867 struct ifmultiaddr *ifma;
868 u_int32_t h, i, n, ctl;
869 u_int16_t hashes[16];
871 ifp = &sc->arpcom.ac_if;
873 /* hash table size */
874 if (sc->sis_rev >= SIS_REV_635 ||
875 sc->sis_rev == SIS_REV_900B)
880 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
882 if (ifp->if_flags & IFF_BROADCAST)
883 ctl |= SIS_RXFILTCTL_BROAD;
885 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
886 ctl |= SIS_RXFILTCTL_ALLMULTI;
887 if (ifp->if_flags & IFF_PROMISC)
888 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
889 for (i = 0; i < n; i++)
892 for (i = 0; i < n; i++)
895 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
896 if (ifma->ifma_addr->sa_family != AF_LINK)
899 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
900 hashes[h >> 4] |= 1 << (h & 0xf);
904 ctl |= SIS_RXFILTCTL_ALLMULTI;
905 for (i = 0; i < n; i++)
910 for (i = 0; i < n; i++) {
911 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
912 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
915 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
918 static void sis_reset(sc)
919 struct sis_softc *sc;
923 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
925 for (i = 0; i < SIS_TIMEOUT; i++) {
926 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
930 if (i == SIS_TIMEOUT)
931 printf("sis%d: reset never completed\n", sc->sis_unit);
933 /* Wait a little while for the chip to get its brains in order. */
937 * If this is a NetSemi chip, make sure to clear
940 if (sc->sis_type == SIS_TYPE_83815) {
941 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
942 CSR_WRITE_4(sc, NS_CLKRUN, 0);
949 * Probe for an SiS chip. Check the PCI vendor and device
950 * IDs against our list and return a device name if we find a match.
952 static int sis_probe(dev)
959 while(t->sis_name != NULL) {
960 if ((pci_get_vendor(dev) == t->sis_vid) &&
961 (pci_get_device(dev) == t->sis_did)) {
962 device_set_desc(dev, t->sis_name);
972 * Attach the interface. Allocate softc structures, do ifmedia
973 * setup and ethernet/BPF attach.
975 static int sis_attach(dev)
979 u_char eaddr[ETHER_ADDR_LEN];
981 struct sis_softc *sc;
983 int unit, error, rid, waittime;
987 error = waittime = 0;
988 sc = device_get_softc(dev);
989 unit = device_get_unit(dev);
990 bzero(sc, sizeof(struct sis_softc));
992 if (pci_get_device(dev) == SIS_DEVICEID_900)
993 sc->sis_type = SIS_TYPE_900;
994 if (pci_get_device(dev) == SIS_DEVICEID_7016)
995 sc->sis_type = SIS_TYPE_7016;
996 if (pci_get_vendor(dev) == NS_VENDORID)
997 sc->sis_type = SIS_TYPE_83815;
999 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
1002 * Handle power management nonsense.
1005 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF;
1006 if (command == 0x01) {
1008 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4);
1009 if (command & SIS_PSTATE_MASK) {
1010 u_int32_t iobase, membase, irq;
1012 /* Save important PCI config data. */
1013 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
1014 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
1015 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
1017 /* Reset the power state. */
1018 printf("sis%d: chip is in D%d power mode "
1019 "-- setting to D0\n", unit, command & SIS_PSTATE_MASK);
1020 command &= 0xFFFFFFFC;
1021 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4);
1023 /* Restore PCI config data. */
1024 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
1025 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
1026 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
1031 * Map control/status registers.
1033 command = pci_read_config(dev, PCIR_COMMAND, 4);
1034 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1035 pci_write_config(dev, PCIR_COMMAND, command, 4);
1036 command = pci_read_config(dev, PCIR_COMMAND, 4);
1038 #ifdef SIS_USEIOSPACE
1039 if (!(command & PCIM_CMD_PORTEN)) {
1040 printf("sis%d: failed to enable I/O ports!\n", unit);
1045 if (!(command & PCIM_CMD_MEMEN)) {
1046 printf("sis%d: failed to enable memory mapping!\n", unit);
1053 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid,
1054 0, ~0, 1, RF_ACTIVE);
1056 if (sc->sis_res == NULL) {
1057 printf("sis%d: couldn't map ports/memory\n", unit);
1062 sc->sis_btag = rman_get_bustag(sc->sis_res);
1063 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1065 /* Allocate interrupt */
1067 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1068 RF_SHAREABLE | RF_ACTIVE);
1070 if (sc->sis_irq == NULL) {
1071 printf("sis%d: couldn't map interrupt\n", unit);
1072 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1077 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET,
1078 sis_intr, sc, &sc->sis_intrhand);
1081 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1082 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1083 printf("sis%d: couldn't set up irq\n", unit);
1087 /* Reset the adapter. */
1090 if (sc->sis_type == SIS_TYPE_900 &&
1091 (sc->sis_rev == SIS_REV_635 ||
1092 sc->sis_rev == SIS_REV_900B)) {
1093 SIO_SET(SIS_CFG_RND_CNT);
1094 SIO_SET(SIS_CFG_PERR_DETECT);
1098 * Get station address from the EEPROM.
1100 switch (pci_get_vendor(dev)) {
1103 * Reading the MAC address out of the EEPROM on
1104 * the NatSemi chip takes a bit more work than
1105 * you'd expect. The address spans 4 16-bit words,
1106 * with the first word containing only a single bit.
1107 * You have to shift everything over one bit to
1108 * get it aligned properly. Also, the bits are
1109 * stored backwards (the LSB is really the MSB,
1110 * and so on) so you have to reverse them in order
1111 * to get the MAC address into the form we want.
1112 * Why? Who the hell knows.
1117 sis_read_eeprom(sc, (caddr_t)&tmp,
1118 NS_EE_NODEADDR, 4, 0);
1120 /* Shift everything over one bit. */
1121 tmp[3] = tmp[3] >> 1;
1122 tmp[3] |= tmp[2] << 15;
1123 tmp[2] = tmp[2] >> 1;
1124 tmp[2] |= tmp[1] << 15;
1125 tmp[1] = tmp[1] >> 1;
1126 tmp[1] |= tmp[0] << 15;
1128 /* Now reverse all the bits. */
1129 tmp[3] = sis_reverse(tmp[3]);
1130 tmp[2] = sis_reverse(tmp[2]);
1131 tmp[1] = sis_reverse(tmp[1]);
1133 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1140 * If this is a SiS 630E chipset with an embedded
1141 * SiS 900 controller, we have to read the MAC address
1142 * from the APC CMOS RAM. Our method for doing this
1143 * is very ugly since we have to reach out and grab
1144 * ahold of hardware for which we cannot properly
1145 * allocate resources. This code is only compiled on
1146 * the i386 architecture since the SiS 630E chipset
1147 * is for x86 motherboards only. Note that there are
1148 * a lot of magic numbers in this hack. These are
1149 * taken from SiS's Linux driver. I'd like to replace
1150 * them with proper symbolic definitions, but that
1151 * requires some datasheets that I don't have access
1154 if (sc->sis_rev == SIS_REV_630S ||
1155 sc->sis_rev == SIS_REV_630E ||
1156 sc->sis_rev == SIS_REV_630EA1)
1157 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1159 else if (sc->sis_rev == SIS_REV_635 ||
1160 sc->sis_rev == SIS_REV_630ET)
1161 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1162 else if (sc->sis_rev == SIS_REV_96x) {
1164 * Allow to read EEPROM from LAN. It is shared
1165 * between a 1394 controller and the NIC and each
1166 * time we access it, we need to set SIS_EECMD_REQ.
1168 SIO_SET(SIS_EECMD_REQ);
1169 for (waittime = 0; waittime < SIS_TIMEOUT;
1171 /* Force EEPROM to idle state. */
1172 sis_eeprom_idle(sc);
1173 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1174 sis_read_eeprom(sc, (caddr_t)&eaddr,
1175 SIS_EE_NODEADDR, 3, 0);
1181 * Set SIS_EECTL_CLK to high, so a other master
1182 * can operate on the i2c bus.
1184 SIO_SET(SIS_EECTL_CLK);
1185 /* Refuse EEPROM access by LAN */
1186 SIO_SET(SIS_EECMD_DONE);
1189 sis_read_eeprom(sc, (caddr_t)&eaddr,
1190 SIS_EE_NODEADDR, 3, 0);
1195 * A SiS chip was detected. Inform the world.
1197 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":");
1199 sc->sis_unit = unit;
1200 callout_handle_init(&sc->sis_stat_ch);
1201 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1203 sc->sis_ldata = contigmalloc(sizeof(struct sis_list_data), M_DEVBUF,
1204 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1206 if (sc->sis_ldata == NULL) {
1207 printf("sis%d: no memory for list buffers!\n", unit);
1208 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1209 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1210 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1214 bzero(sc->sis_ldata, sizeof(struct sis_list_data));
1216 ifp = &sc->arpcom.ac_if;
1218 ifp->if_unit = unit;
1219 ifp->if_name = "sis";
1220 ifp->if_mtu = ETHERMTU;
1221 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1222 ifp->if_ioctl = sis_ioctl;
1223 ifp->if_output = ether_output;
1224 ifp->if_start = sis_start;
1225 ifp->if_watchdog = sis_watchdog;
1226 ifp->if_init = sis_init;
1227 ifp->if_baudrate = 10000000;
1228 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1;
1233 if (mii_phy_probe(dev, &sc->sis_miibus,
1234 sis_ifmedia_upd, sis_ifmedia_sts)) {
1235 printf("sis%d: MII without any PHY!\n", sc->sis_unit);
1236 contigfree(sc->sis_ldata, sizeof(struct sis_list_data),
1238 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1239 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1240 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1246 * Call MI attach routine.
1248 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1251 * Tell the upper layer(s) we support long frames.
1253 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1255 callout_handle_init(&sc->sis_stat_ch);
1262 static int sis_detach(dev)
1265 struct sis_softc *sc;
1271 sc = device_get_softc(dev);
1272 ifp = &sc->arpcom.ac_if;
1276 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1278 bus_generic_detach(dev);
1279 device_delete_child(dev, sc->sis_miibus);
1281 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1282 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1283 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1285 contigfree(sc->sis_ldata, sizeof(struct sis_list_data), M_DEVBUF);
1293 * Initialize the transmit descriptors.
1295 static int sis_list_tx_init(sc)
1296 struct sis_softc *sc;
1298 struct sis_list_data *ld;
1299 struct sis_ring_data *cd;
1302 cd = &sc->sis_cdata;
1305 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1306 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1307 ld->sis_tx_list[i].sis_nextdesc =
1308 &ld->sis_tx_list[nexti];
1309 ld->sis_tx_list[i].sis_next =
1310 vtophys(&ld->sis_tx_list[nexti]);
1311 ld->sis_tx_list[i].sis_mbuf = NULL;
1312 ld->sis_tx_list[i].sis_ptr = 0;
1313 ld->sis_tx_list[i].sis_ctl = 0;
1316 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1323 * Initialize the RX descriptors and allocate mbufs for them. Note that
1324 * we arrange the descriptors in a closed ring, so that the last descriptor
1325 * points back to the first.
1327 static int sis_list_rx_init(sc)
1328 struct sis_softc *sc;
1330 struct sis_list_data *ld;
1331 struct sis_ring_data *cd;
1335 cd = &sc->sis_cdata;
1337 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1338 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS)
1340 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1341 ld->sis_rx_list[i].sis_nextdesc =
1342 &ld->sis_rx_list[nexti];
1343 ld->sis_rx_list[i].sis_next =
1344 vtophys(&ld->sis_rx_list[nexti]);
1347 cd->sis_rx_prod = 0;
1353 * Initialize an RX descriptor and attach an MBUF cluster.
1355 static int sis_newbuf(sc, c, m)
1356 struct sis_softc *sc;
1362 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1366 m->m_data = m->m_ext.ext_buf;
1370 c->sis_ptr = vtophys(mtod(m, caddr_t));
1371 c->sis_ctl = SIS_RXLEN;
1377 * A frame has been uploaded: pass the resulting mbuf chain up to
1378 * the higher level protocols.
1380 static void sis_rxeof(sc)
1381 struct sis_softc *sc;
1385 struct sis_desc *cur_rx;
1386 int i, total_len = 0;
1389 ifp = &sc->arpcom.ac_if;
1390 i = sc->sis_cdata.sis_rx_prod;
1392 while(SIS_OWNDESC(&sc->sis_ldata->sis_rx_list[i])) {
1394 #ifdef DEVICE_POLLING
1395 if (ifp->if_ipending & IFF_POLLING) {
1396 if (sc->rxcycles <= 0)
1400 #endif /* DEVICE_POLLING */
1401 cur_rx = &sc->sis_ldata->sis_rx_list[i];
1402 rxstat = cur_rx->sis_rxstat;
1403 m = cur_rx->sis_mbuf;
1404 cur_rx->sis_mbuf = NULL;
1405 total_len = SIS_RXBYTES(cur_rx);
1406 SIS_INC(i, SIS_RX_LIST_CNT);
1409 * If an error occurs, update stats, clear the
1410 * status word and leave the mbuf cluster in place:
1411 * it should simply get re-used next time this descriptor
1412 * comes up in the ring.
1414 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1416 if (rxstat & SIS_RXSTAT_COLL)
1417 ifp->if_collisions++;
1418 sis_newbuf(sc, cur_rx, m);
1422 /* No errors; receive the packet. */
1425 * On the x86 we do not have alignment problems, so try to
1426 * allocate a new buffer for the receive ring, and pass up
1427 * the one where the packet is already, saving the expensive
1428 * copy done in m_devget().
1429 * If we are on an architecture with alignment problems, or
1430 * if the allocation fails, then use m_devget and leave the
1431 * existing buffer in the receive ring.
1433 if (sis_newbuf(sc, cur_rx, NULL) == 0)
1434 m->m_pkthdr.len = m->m_len = total_len;
1439 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1440 total_len + ETHER_ALIGN, 0, ifp, NULL);
1441 sis_newbuf(sc, cur_rx, m);
1446 m_adj(m0, ETHER_ALIGN);
1451 ether_input(ifp, NULL, m);
1454 sc->sis_cdata.sis_rx_prod = i;
1460 struct sis_softc *sc;
1468 * A frame was downloaded to the chip. It's safe for us to clean up
1472 static void sis_txeof(sc)
1473 struct sis_softc *sc;
1475 struct sis_desc *cur_tx = NULL;
1479 ifp = &sc->arpcom.ac_if;
1482 * Go through our tx list and free mbufs for those
1483 * frames that have been transmitted.
1485 idx = sc->sis_cdata.sis_tx_cons;
1486 while (idx != sc->sis_cdata.sis_tx_prod) {
1487 cur_tx = &sc->sis_ldata->sis_tx_list[idx];
1489 if (SIS_OWNDESC(cur_tx))
1492 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) {
1493 sc->sis_cdata.sis_tx_cnt--;
1494 SIS_INC(idx, SIS_TX_LIST_CNT);
1498 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1500 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1501 ifp->if_collisions++;
1502 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1503 ifp->if_collisions++;
1506 ifp->if_collisions +=
1507 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1510 if (cur_tx->sis_mbuf != NULL) {
1511 m_freem(cur_tx->sis_mbuf);
1512 cur_tx->sis_mbuf = NULL;
1515 sc->sis_cdata.sis_tx_cnt--;
1516 SIS_INC(idx, SIS_TX_LIST_CNT);
1520 if (idx != sc->sis_cdata.sis_tx_cons) {
1521 sc->sis_cdata.sis_tx_cons = idx;
1522 ifp->if_flags &= ~IFF_OACTIVE;
1524 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5;
1528 static void sis_tick(xsc)
1531 struct sis_softc *sc;
1532 struct mii_data *mii;
1539 ifp = &sc->arpcom.ac_if;
1541 mii = device_get_softc(sc->sis_miibus);
1544 if (!sc->sis_link) {
1546 if (mii->mii_media_status & IFM_ACTIVE &&
1547 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1549 if (ifp->if_snd.ifq_head != NULL)
1553 sc->sis_stat_ch = timeout(sis_tick, sc, hz);
1560 #ifdef DEVICE_POLLING
1561 static poll_handler_t sis_poll;
1564 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1566 struct sis_softc *sc = ifp->if_softc;
1568 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1569 CSR_WRITE_4(sc, SIS_IER, 1);
1574 * On the sis, reading the status register also clears it.
1575 * So before returning to intr mode we must make sure that all
1576 * possible pending sources of interrupts have been served.
1577 * In practice this means run to completion the *eof routines,
1578 * and then call the interrupt routine
1580 sc->rxcycles = count;
1583 if (ifp->if_snd.ifq_head != NULL)
1586 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1589 /* Reading the ISR register clears all interrupts. */
1590 status = CSR_READ_4(sc, SIS_ISR);
1592 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1595 if (status & (SIS_ISR_RX_IDLE))
1596 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1598 if (status & SIS_ISR_SYSERR) {
1604 #endif /* DEVICE_POLLING */
1606 static void sis_intr(arg)
1609 struct sis_softc *sc;
1614 ifp = &sc->arpcom.ac_if;
1616 #ifdef DEVICE_POLLING
1617 if (ifp->if_ipending & IFF_POLLING)
1619 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */
1620 CSR_WRITE_4(sc, SIS_IER, 0);
1621 sis_poll(ifp, 0, 1);
1624 #endif /* DEVICE_POLLING */
1626 /* Supress unwanted interrupts */
1627 if (!(ifp->if_flags & IFF_UP)) {
1632 /* Disable interrupts. */
1633 CSR_WRITE_4(sc, SIS_IER, 0);
1636 /* Reading the ISR register clears all interrupts. */
1637 status = CSR_READ_4(sc, SIS_ISR);
1639 if ((status & SIS_INTRS) == 0)
1643 (SIS_ISR_TX_DESC_OK|SIS_ISR_TX_ERR|
1644 SIS_ISR_TX_OK|SIS_ISR_TX_IDLE) )
1647 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE))
1650 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1653 if (status & (SIS_ISR_RX_IDLE))
1654 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1656 if (status & SIS_ISR_SYSERR) {
1662 /* Re-enable interrupts. */
1663 CSR_WRITE_4(sc, SIS_IER, 1);
1665 if (ifp->if_snd.ifq_head != NULL)
1672 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1673 * pointers to the fragment pointers.
1675 static int sis_encap(sc, m_head, txidx)
1676 struct sis_softc *sc;
1677 struct mbuf *m_head;
1680 struct sis_desc *f = NULL;
1682 int frag, cur, cnt = 0;
1685 * Start packing the mbufs in this chain into
1686 * the fragment pointers. Stop when we run out
1687 * of fragments or hit the end of the mbuf chain.
1690 cur = frag = *txidx;
1692 for (m = m_head; m != NULL; m = m->m_next) {
1693 if (m->m_len != 0) {
1694 if ((SIS_TX_LIST_CNT -
1695 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2)
1697 f = &sc->sis_ldata->sis_tx_list[frag];
1698 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
1699 f->sis_ptr = vtophys(mtod(m, vm_offset_t));
1701 f->sis_ctl |= SIS_CMDSTS_OWN;
1703 SIS_INC(frag, SIS_TX_LIST_CNT);
1711 sc->sis_ldata->sis_tx_list[cur].sis_mbuf = m_head;
1712 sc->sis_ldata->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1713 sc->sis_ldata->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1714 sc->sis_cdata.sis_tx_cnt += cnt;
1721 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1722 * to the mbuf data regions directly in the transmit lists. We also save a
1723 * copy of the pointers since the transmit list fragment pointers are
1724 * physical addresses.
1727 static void sis_start(ifp)
1730 struct sis_softc *sc;
1731 struct mbuf *m_head = NULL;
1739 idx = sc->sis_cdata.sis_tx_prod;
1741 if (ifp->if_flags & IFF_OACTIVE)
1744 while(sc->sis_ldata->sis_tx_list[idx].sis_mbuf == NULL) {
1745 IF_DEQUEUE(&ifp->if_snd, m_head);
1749 if (sis_encap(sc, m_head, &idx)) {
1750 IF_PREPEND(&ifp->if_snd, m_head);
1751 ifp->if_flags |= IFF_OACTIVE;
1756 * If there's a BPF listener, bounce a copy of this frame
1760 bpf_mtap(ifp, m_head);
1765 sc->sis_cdata.sis_tx_prod = idx;
1766 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1769 * Set a timeout in case the chip goes out to lunch.
1776 static void sis_init(xsc)
1779 struct sis_softc *sc = xsc;
1780 struct ifnet *ifp = &sc->arpcom.ac_if;
1781 struct mii_data *mii;
1787 * Cancel pending I/O and free all RX/TX buffers.
1791 mii = device_get_softc(sc->sis_miibus);
1793 /* Set MAC address */
1794 if (sc->sis_type == SIS_TYPE_83815) {
1795 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1796 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1797 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
1798 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1799 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1800 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
1801 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1802 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1803 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
1805 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1806 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1807 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
1808 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1809 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1810 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
1811 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1812 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1813 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
1816 /* Init circular RX list. */
1817 if (sis_list_rx_init(sc) == ENOBUFS) {
1818 printf("sis%d: initialization failed: no "
1819 "memory for rx buffers\n", sc->sis_unit);
1826 * Init tx descriptors.
1828 sis_list_tx_init(sc);
1831 * For the NatSemi chip, we have to explicitly enable the
1832 * reception of ARP frames, as well as turn on the 'perfect
1833 * match' filter where we store the station address, otherwise
1834 * we won't receive unicasts meant for this host.
1836 if (sc->sis_type == SIS_TYPE_83815) {
1837 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1838 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1841 /* If we want promiscuous mode, set the allframes bit. */
1842 if (ifp->if_flags & IFF_PROMISC) {
1843 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1845 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1849 * Set the capture broadcast bit to capture broadcast frames.
1851 if (ifp->if_flags & IFF_BROADCAST) {
1852 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1854 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1858 * Load the multicast filter.
1860 if (sc->sis_type == SIS_TYPE_83815)
1861 sis_setmulti_ns(sc);
1863 sis_setmulti_sis(sc);
1865 /* Turn the receive filter on */
1866 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1869 * Load the address of the RX and TX lists.
1871 CSR_WRITE_4(sc, SIS_RX_LISTPTR,
1872 vtophys(&sc->sis_ldata->sis_rx_list[0]));
1873 CSR_WRITE_4(sc, SIS_TX_LISTPTR,
1874 vtophys(&sc->sis_ldata->sis_tx_list[0]));
1876 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1877 * the PCI bus. When this bit is set, the Max DMA Burst Size
1878 * for TX/RX DMA should be no larger than 16 double words.
1880 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
1881 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
1883 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
1886 /* Accept Long Packets for VLAN support */
1887 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1889 /* Set TX configuration */
1890 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
1891 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1893 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1896 /* Set full/half duplex mode. */
1897 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1898 SIS_SETBIT(sc, SIS_TX_CFG,
1899 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1900 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1902 SIS_CLRBIT(sc, SIS_TX_CFG,
1903 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1904 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1908 * Enable interrupts.
1910 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
1911 #ifdef DEVICE_POLLING
1913 * ... only enable interrupts if we are not polling, make sure
1914 * they are off otherwise.
1916 if (ifp->if_ipending & IFF_POLLING)
1917 CSR_WRITE_4(sc, SIS_IER, 0);
1919 #endif /* DEVICE_POLLING */
1920 CSR_WRITE_4(sc, SIS_IER, 1);
1922 /* Enable receiver and transmitter. */
1923 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
1924 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1931 * Page 75 of the DP83815 manual recommends the
1932 * following register settings "for optimum
1933 * performance." Note however that at least three
1934 * of the registers are listed as "reserved" in
1935 * the register map, so who knows what they do.
1937 if (sc->sis_type == SIS_TYPE_83815) {
1938 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
1939 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
1940 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
1941 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
1942 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
1945 ifp->if_flags |= IFF_RUNNING;
1946 ifp->if_flags &= ~IFF_OACTIVE;
1950 sc->sis_stat_ch = timeout(sis_tick, sc, hz);
1956 * Set media options.
1958 static int sis_ifmedia_upd(ifp)
1961 struct sis_softc *sc;
1962 struct mii_data *mii;
1966 mii = device_get_softc(sc->sis_miibus);
1968 if (mii->mii_instance) {
1969 struct mii_softc *miisc;
1970 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1971 miisc = LIST_NEXT(miisc, mii_list))
1972 mii_phy_reset(miisc);
1980 * Report current media status.
1982 static void sis_ifmedia_sts(ifp, ifmr)
1984 struct ifmediareq *ifmr;
1986 struct sis_softc *sc;
1987 struct mii_data *mii;
1991 mii = device_get_softc(sc->sis_miibus);
1993 ifmr->ifm_active = mii->mii_media_active;
1994 ifmr->ifm_status = mii->mii_media_status;
1999 static int sis_ioctl(ifp, command, data)
2004 struct sis_softc *sc = ifp->if_softc;
2005 struct ifreq *ifr = (struct ifreq *) data;
2006 struct mii_data *mii;
2015 error = ether_ioctl(ifp, command, data);
2018 if (ifp->if_flags & IFF_UP) {
2021 if (ifp->if_flags & IFF_RUNNING)
2028 if (sc->sis_type == SIS_TYPE_83815)
2029 sis_setmulti_ns(sc);
2031 sis_setmulti_sis(sc);
2036 mii = device_get_softc(sc->sis_miibus);
2037 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2049 static void sis_watchdog(ifp)
2052 struct sis_softc *sc;
2057 printf("sis%d: watchdog timeout\n", sc->sis_unit);
2063 if (ifp->if_snd.ifq_head != NULL)
2070 * Stop the adapter and free any mbufs allocated to the
2073 static void sis_stop(sc)
2074 struct sis_softc *sc;
2079 ifp = &sc->arpcom.ac_if;
2082 untimeout(sis_tick, sc, sc->sis_stat_ch);
2084 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2085 #ifdef DEVICE_POLLING
2086 ether_poll_deregister(ifp);
2088 CSR_WRITE_4(sc, SIS_IER, 0);
2089 CSR_WRITE_4(sc, SIS_IMR, 0);
2090 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2092 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2093 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2098 * Free data in the RX lists.
2100 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2101 if (sc->sis_ldata->sis_rx_list[i].sis_mbuf != NULL) {
2102 m_freem(sc->sis_ldata->sis_rx_list[i].sis_mbuf);
2103 sc->sis_ldata->sis_rx_list[i].sis_mbuf = NULL;
2106 bzero((char *)&sc->sis_ldata->sis_rx_list,
2107 sizeof(sc->sis_ldata->sis_rx_list));
2110 * Free the TX list buffers.
2112 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2113 if (sc->sis_ldata->sis_tx_list[i].sis_mbuf != NULL) {
2114 m_freem(sc->sis_ldata->sis_tx_list[i].sis_mbuf);
2115 sc->sis_ldata->sis_tx_list[i].sis_mbuf = NULL;
2119 bzero((char *)&sc->sis_ldata->sis_tx_list,
2120 sizeof(sc->sis_ldata->sis_tx_list));
2126 * Stop all chip I/O so that the kernel's probe routines don't
2127 * get confused by errant DMAs when rebooting.
2129 static void sis_shutdown(dev)
2132 struct sis_softc *sc;
2134 sc = device_get_softc(dev);