2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $
33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.23 2005/05/31 12:31:21 joerg Exp $
37 * Winbond fast ethernet PCI NIC driver
39 * Supports various cheap network adapters based on the Winbond W89C840F
40 * fast ethernet controller chip. This includes adapters manufactured by
41 * Winbond itself and some made by Linksys.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The Winbond W89C840F chip is a bus master; in some ways it resembles
50 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
51 * one major difference which is that while the registers do many of
52 * the same things as a tulip adapter, the offsets are different: where
53 * tulip registers are typically spaced 8 bytes apart, the Winbond
54 * registers are spaced 4 bytes apart. The receiver filter is also
55 * programmed differently.
57 * Like the tulip, the Winbond chip uses small descriptors containing
58 * a status word, a control word and 32-bit areas that can either be used
59 * to point to two external data blocks, or to point to a single block
60 * and another descriptor in a linked list. Descriptors can be grouped
61 * together in blocks to form fixed length rings or can be chained
62 * together in linked lists. A single packet may be spread out over
63 * several descriptors if necessary.
65 * For the receive ring, this driver uses a linked list of descriptors,
66 * each pointing to a single mbuf cluster buffer, which us large enough
67 * to hold an entire packet. The link list is looped back to created a
70 * For transmission, the driver creates a linked list of 'super descriptors'
71 * which each contain several individual descriptors linked toghether.
72 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
73 * abuse as fragment pointers. This allows us to use a buffer managment
74 * scheme very similar to that used in the ThunderLAN and Etherlink XL
77 * Autonegotiation is performed using the external PHY via the MII bus.
78 * The sample boards I have all use a Davicom PHY.
80 * Note: the author of the Linux driver for the Winbond chip alludes
81 * to some sort of flaw in the chip's design that seems to mandate some
82 * drastic workaround which signigicantly impairs transmit performance.
83 * I have no idea what he's on about: transmit performance with all
84 * three of my test boards seems fine.
89 #include <sys/param.h>
90 #include <sys/systm.h>
91 #include <sys/sockio.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/socket.h>
96 #include <sys/queue.h>
99 #include <net/ifq_var.h>
100 #include <net/if_arp.h>
101 #include <net/ethernet.h>
102 #include <net/if_dl.h>
103 #include <net/if_media.h>
107 #include <vm/vm.h> /* for vtophys */
108 #include <vm/pmap.h> /* for vtophys */
109 #include <machine/bus.h>
110 #include <machine/resource.h>
112 #include <sys/rman.h>
114 #include <bus/pci/pcireg.h>
115 #include <bus/pci/pcivar.h>
117 #include <dev/netif/mii_layer/mii.h>
118 #include <dev/netif/mii_layer/miivar.h>
120 /* "controller miibus0" required. See GENERIC if you get errors here. */
121 #include "miibus_if.h"
123 #define WB_USEIOSPACE
125 #include "if_wbreg.h"
128 * Various supported device vendors/types and their names.
130 static struct wb_type wb_devs[] = {
131 { WB_VENDORID, WB_DEVICEID_840F,
132 "Winbond W89C840F 10/100BaseTX" },
133 { CP_VENDORID, CP_DEVICEID_RL100,
134 "Compex RL100-ATX 10/100baseTX" },
138 static int wb_probe(device_t);
139 static int wb_attach(device_t);
140 static int wb_detach(device_t);
142 static void wb_bfree(void *);
143 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
145 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *);
147 static void wb_rxeof(struct wb_softc *);
148 static void wb_rxeoc(struct wb_softc *);
149 static void wb_txeof(struct wb_softc *);
150 static void wb_txeoc(struct wb_softc *);
151 static void wb_intr(void *);
152 static void wb_tick(void *);
153 static void wb_start(struct ifnet *);
154 static int wb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
155 static void wb_init(void *);
156 static void wb_stop(struct wb_softc *);
157 static void wb_watchdog(struct ifnet *);
158 static void wb_shutdown(device_t);
159 static int wb_ifmedia_upd(struct ifnet *);
160 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
162 static void wb_eeprom_putbyte(struct wb_softc *, int);
163 static void wb_eeprom_getword(struct wb_softc *, int, uint16_t *);
164 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int);
165 static void wb_mii_sync(struct wb_softc *);
166 static void wb_mii_send(struct wb_softc *, uint32_t, int);
167 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *);
168 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *);
170 static void wb_setcfg(struct wb_softc *, uint32_t);
171 static void wb_setmulti(struct wb_softc *);
172 static void wb_reset(struct wb_softc *);
173 static void wb_fixmedia(struct wb_softc *);
174 static int wb_list_rx_init(struct wb_softc *);
175 static int wb_list_tx_init(struct wb_softc *);
177 static int wb_miibus_readreg(device_t, int, int);
178 static int wb_miibus_writereg(device_t, int, int, int);
179 static void wb_miibus_statchg(device_t);
182 #define WB_RES SYS_RES_IOPORT
183 #define WB_RID WB_PCI_LOIO
185 #define WB_RES SYS_RES_MEMORY
186 #define WB_RID WB_PCI_LOMEM
189 static device_method_t wb_methods[] = {
190 /* Device interface */
191 DEVMETHOD(device_probe, wb_probe),
192 DEVMETHOD(device_attach, wb_attach),
193 DEVMETHOD(device_detach, wb_detach),
194 DEVMETHOD(device_shutdown, wb_shutdown),
196 /* bus interface, for miibus */
197 DEVMETHOD(bus_print_child, bus_generic_print_child),
198 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
201 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
202 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
203 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
207 static DEFINE_CLASS_0(wb, wb_driver, wb_methods, sizeof(struct wb_softc));
208 static devclass_t wb_devclass;
210 DECLARE_DUMMY_MODULE(if_wb);
211 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0);
212 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
214 #define WB_SETBIT(sc, reg, x) \
215 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
217 #define WB_CLRBIT(sc, reg, x) \
218 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
221 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) | (x))
224 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) & ~(x))
227 * Send a read command and address to the EEPROM, check for ACK.
230 wb_eeprom_putbyte(struct wb_softc *sc, int addr)
234 d = addr | WB_EECMD_READ;
237 * Feed in each bit and stobe the clock.
239 for (i = 0x400; i; i >>= 1) {
241 SIO_SET(WB_SIO_EE_DATAIN);
243 SIO_CLR(WB_SIO_EE_DATAIN);
245 SIO_SET(WB_SIO_EE_CLK);
247 SIO_CLR(WB_SIO_EE_CLK);
253 * Read a word of data stored in the EEPROM at address 'addr.'
256 wb_eeprom_getword(struct wb_softc *sc, int addr, uint16_t *dest)
261 /* Enter EEPROM access mode. */
262 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
265 * Send address of word we want to read.
267 wb_eeprom_putbyte(sc, addr);
269 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
272 * Start reading bits from EEPROM.
274 for (i = 0x8000; i; i >>= 1) {
275 SIO_SET(WB_SIO_EE_CLK);
277 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
279 SIO_CLR(WB_SIO_EE_CLK);
283 /* Turn off EEPROM access mode. */
284 CSR_WRITE_4(sc, WB_SIO, 0);
290 * Read a sequence of words from the EEPROM.
293 wb_read_eeprom(struct wb_softc *sc, caddr_t dest, int off, int cnt)
296 uint16_t word = 0, *ptr;
298 for (i = 0; i < cnt; i++) {
299 wb_eeprom_getword(sc, off + i, &word);
300 ptr = (uint16_t *)(dest + (i * 2));
306 * Sync the PHYs by setting data bit and strobing the clock 32 times.
309 wb_mii_sync(struct wb_softc *sc)
313 SIO_SET(WB_SIO_MII_DIR | WB_SIO_MII_DATAIN);
315 for (i = 0; i < 32; i++) {
316 SIO_SET(WB_SIO_MII_CLK);
318 SIO_CLR(WB_SIO_MII_CLK);
324 * Clock a series of bits through the MII.
327 wb_mii_send(struct wb_softc *sc, uint32_t bits, int cnt)
331 SIO_CLR(WB_SIO_MII_CLK);
333 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
335 SIO_SET(WB_SIO_MII_DATAIN);
337 SIO_CLR(WB_SIO_MII_DATAIN);
339 SIO_CLR(WB_SIO_MII_CLK);
341 SIO_SET(WB_SIO_MII_CLK);
346 * Read an PHY register through the MII.
349 wb_mii_readreg(struct wb_softc *sc, struct wb_mii_frame *frame)
356 * Set up frame for RX.
358 frame->mii_stdelim = WB_MII_STARTDELIM;
359 frame->mii_opcode = WB_MII_READOP;
360 frame->mii_turnaround = 0;
363 CSR_WRITE_4(sc, WB_SIO, 0);
368 SIO_SET(WB_SIO_MII_DIR);
373 * Send command/address info.
375 wb_mii_send(sc, frame->mii_stdelim, 2);
376 wb_mii_send(sc, frame->mii_opcode, 2);
377 wb_mii_send(sc, frame->mii_phyaddr, 5);
378 wb_mii_send(sc, frame->mii_regaddr, 5);
381 SIO_CLR((WB_SIO_MII_CLK | WB_SIO_MII_DATAIN));
383 SIO_SET(WB_SIO_MII_CLK);
387 SIO_CLR(WB_SIO_MII_DIR);
389 SIO_CLR(WB_SIO_MII_CLK);
391 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
392 SIO_SET(WB_SIO_MII_CLK);
394 SIO_CLR(WB_SIO_MII_CLK);
396 SIO_SET(WB_SIO_MII_CLK);
400 * Now try reading data bits. If the ack failed, we still
401 * need to clock through 16 cycles to keep the PHY(s) in sync.
404 for(i = 0; i < 16; i++) {
405 SIO_CLR(WB_SIO_MII_CLK);
407 SIO_SET(WB_SIO_MII_CLK);
413 for (i = 0x8000; i; i >>= 1) {
414 SIO_CLR(WB_SIO_MII_CLK);
417 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
418 frame->mii_data |= i;
421 SIO_SET(WB_SIO_MII_CLK);
427 SIO_CLR(WB_SIO_MII_CLK);
429 SIO_SET(WB_SIO_MII_CLK);
440 * Write to a PHY register through the MII.
443 wb_mii_writereg(struct wb_softc *sc, struct wb_mii_frame *frame)
449 * Set up frame for TX.
452 frame->mii_stdelim = WB_MII_STARTDELIM;
453 frame->mii_opcode = WB_MII_WRITEOP;
454 frame->mii_turnaround = WB_MII_TURNAROUND;
457 * Turn on data output.
459 SIO_SET(WB_SIO_MII_DIR);
463 wb_mii_send(sc, frame->mii_stdelim, 2);
464 wb_mii_send(sc, frame->mii_opcode, 2);
465 wb_mii_send(sc, frame->mii_phyaddr, 5);
466 wb_mii_send(sc, frame->mii_regaddr, 5);
467 wb_mii_send(sc, frame->mii_turnaround, 2);
468 wb_mii_send(sc, frame->mii_data, 16);
471 SIO_SET(WB_SIO_MII_CLK);
473 SIO_CLR(WB_SIO_MII_CLK);
479 SIO_CLR(WB_SIO_MII_DIR);
487 wb_miibus_readreg(device_t dev, int phy, int reg)
489 struct wb_softc *sc = device_get_softc(dev);
490 struct wb_mii_frame frame;
492 bzero(&frame, sizeof(frame));
494 frame.mii_phyaddr = phy;
495 frame.mii_regaddr = reg;
496 wb_mii_readreg(sc, &frame);
498 return(frame.mii_data);
502 wb_miibus_writereg(device_t dev, int phy, int reg, int data)
504 struct wb_softc *sc = device_get_softc(dev);
505 struct wb_mii_frame frame;
507 bzero(&frame, sizeof(frame));
509 frame.mii_phyaddr = phy;
510 frame.mii_regaddr = reg;
511 frame.mii_data = data;
513 wb_mii_writereg(sc, &frame);
519 wb_miibus_statchg(device_t dev)
521 struct wb_softc *sc = device_get_softc(dev);
522 struct mii_data *mii;
524 mii = device_get_softc(sc->wb_miibus);
525 wb_setcfg(sc, mii->mii_media_active);
529 * Program the 64-bit multicast hash filter.
532 wb_setmulti(struct wb_softc *sc)
534 struct ifnet *ifp = &sc->arpcom.ac_if;
536 uint32_t hashes[2] = { 0, 0 };
537 struct ifmultiaddr *ifma;
540 rxfilt = CSR_READ_4(sc, WB_NETCFG);
542 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
543 rxfilt |= WB_NETCFG_RX_MULTI;
544 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
545 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
546 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
550 /* first, zot all the existing hash bits */
551 CSR_WRITE_4(sc, WB_MAR0, 0);
552 CSR_WRITE_4(sc, WB_MAR1, 0);
554 /* now program new ones */
555 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
556 if (ifma->ifma_addr->sa_family != AF_LINK)
558 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
559 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
561 hashes[0] |= (1 << h);
563 hashes[1] |= (1 << (h - 32));
568 rxfilt |= WB_NETCFG_RX_MULTI;
570 rxfilt &= ~WB_NETCFG_RX_MULTI;
572 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
573 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
574 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
578 * The Winbond manual states that in order to fiddle with the
579 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
580 * first have to put the transmit and/or receive logic in the idle state.
583 wb_setcfg(struct wb_softc *sc, uint32_t media)
587 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)) {
589 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON));
591 for (i = 0; i < WB_TIMEOUT; i++) {
593 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
594 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
599 printf("wb%d: failed to force tx and "
600 "rx to idle state\n", sc->wb_unit);
603 if (IFM_SUBTYPE(media) == IFM_10_T)
604 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
606 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
608 if ((media & IFM_GMASK) == IFM_FDX)
609 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
611 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
614 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON | WB_NETCFG_RX_ON);
618 wb_reset(struct wb_softc *sc)
621 struct mii_data *mii;
623 CSR_WRITE_4(sc, WB_NETCFG, 0);
624 CSR_WRITE_4(sc, WB_BUSCTL, 0);
625 CSR_WRITE_4(sc, WB_TXADDR, 0);
626 CSR_WRITE_4(sc, WB_RXADDR, 0);
628 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
629 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
631 for (i = 0; i < WB_TIMEOUT; i++) {
633 if ((CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET) == 0)
637 printf("wb%d: reset never completed!\n", sc->wb_unit);
639 /* Wait a little while for the chip to get its brains in order. */
642 if (sc->wb_miibus == NULL)
645 mii = device_get_softc(sc->wb_miibus);
649 if (mii->mii_instance) {
650 struct mii_softc *miisc;
651 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
652 mii_phy_reset(miisc);
657 wb_fixmedia(struct wb_softc *sc)
659 struct mii_data *mii;
662 if (sc->wb_miibus == NULL)
665 mii = device_get_softc(sc->wb_miibus);
668 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
669 media = mii->mii_media_active & ~IFM_10_T;
671 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
672 media = mii->mii_media_active & ~IFM_100_TX;
677 ifmedia_set(&mii->mii_media, media);
681 * Probe for a Winbond chip. Check the PCI vendor and device
682 * IDs against our list and return a device name if we find a match.
684 static int wb_probe(device_t dev)
687 uint16_t vendor, product;
689 vendor = pci_get_vendor(dev);
690 product = pci_get_device(dev);
692 for (t = wb_devs; t->wb_name != NULL; t++) {
693 if (vendor == t->wb_vid && product == t->wb_did) {
694 device_set_desc(dev, t->wb_name);
703 * Attach the interface. Allocate softc structures, do ifmedia
704 * setup and ethernet/BPF attach.
707 wb_attach(device_t dev)
709 u_char eaddr[ETHER_ADDR_LEN];
713 int error = 0, rid, s, unit;
717 sc = device_get_softc(dev);
718 unit = device_get_unit(dev);
719 callout_init(&sc->wb_stat_timer);
722 * Handle power management nonsense.
725 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF;
726 if (command == 0x01) {
728 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4);
729 if (command & WB_PSTATE_MASK) {
730 uint32_t iobase, membase, irq;
732 /* Save important PCI config data. */
733 iobase = pci_read_config(dev, WB_PCI_LOIO, 4);
734 membase = pci_read_config(dev, WB_PCI_LOMEM, 4);
735 irq = pci_read_config(dev, WB_PCI_INTLINE, 4);
737 /* Reset the power state. */
738 printf("wb%d: chip is in D%d power mode "
739 "-- setting to D0\n", unit, command & WB_PSTATE_MASK);
740 command &= 0xFFFFFFFC;
741 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4);
743 /* Restore PCI config data. */
744 pci_write_config(dev, WB_PCI_LOIO, iobase, 4);
745 pci_write_config(dev, WB_PCI_LOMEM, membase, 4);
746 pci_write_config(dev, WB_PCI_INTLINE, irq, 4);
751 * Map control/status registers.
753 command = pci_read_config(dev, PCIR_COMMAND, 4);
754 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
755 pci_write_config(dev, PCIR_COMMAND, command, 4);
756 command = pci_read_config(dev, PCIR_COMMAND, 4);
759 if ((command & PCIM_CMD_PORTEN) == 0) {
760 printf("wb%d: failed to enable I/O ports!\n", unit);
765 if ((command & PCIM_CMD_MEMEN) == 0) {
766 printf("wb%d: failed to enable memory mapping!\n", unit);
773 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE);
775 if (sc->wb_res == NULL) {
776 printf("wb%d: couldn't map ports/memory\n", unit);
781 sc->wb_btag = rman_get_bustag(sc->wb_res);
782 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
784 /* Allocate interrupt */
786 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
787 RF_SHAREABLE | RF_ACTIVE);
789 if (sc->wb_irq == NULL) {
790 printf("wb%d: couldn't map interrupt\n", unit);
791 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
796 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET,
797 wb_intr, sc, &sc->wb_intrhand, NULL);
800 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
801 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
802 printf("wb%d: couldn't set up irq\n", unit);
806 /* Save the cache line size. */
807 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
809 /* Reset the adapter. */
813 * Get station address from the EEPROM.
815 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3);
819 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
820 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
822 if (sc->wb_ldata == NULL) {
823 printf("wb%d: no memory for list buffers!\n", unit);
824 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
825 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
826 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
831 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
833 ifp = &sc->arpcom.ac_if;
835 if_initname(ifp, "wb", unit);
836 ifp->if_mtu = ETHERMTU;
837 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
838 ifp->if_ioctl = wb_ioctl;
839 ifp->if_start = wb_start;
840 ifp->if_watchdog = wb_watchdog;
841 ifp->if_init = wb_init;
842 ifp->if_baudrate = 10000000;
843 ifq_set_maxlen(&ifp->if_snd, WB_TX_LIST_CNT - 1);
844 ifq_set_ready(&ifp->if_snd);
849 if (mii_phy_probe(dev, &sc->wb_miibus,
850 wb_ifmedia_upd, wb_ifmedia_sts)) {
851 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8,
853 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
854 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
855 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
861 * Call MI attach routine.
863 ether_ifattach(ifp, eaddr);
867 device_delete_child(dev, sc->wb_miibus);
874 wb_detach(device_t dev)
876 struct wb_softc *sc = device_get_softc(dev);
877 struct ifnet *ifp = &sc->arpcom.ac_if;
885 /* Delete any miibus and phy devices attached to this interface */
886 bus_generic_detach(dev);
887 device_delete_child(dev, sc->wb_miibus);
889 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
890 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
891 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
893 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8,
902 * Initialize the transmit descriptors.
905 wb_list_tx_init(struct wb_softc *sc)
907 struct wb_chain_data *cd;
908 struct wb_list_data *ld;
914 for (i = 0; i < WB_TX_LIST_CNT; i++) {
915 nexti = (i == WB_TX_LIST_CNT - 1) ? 0 : i + 1;
916 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
917 cd->wb_tx_chain[i].wb_nextdesc = &cd->wb_tx_chain[nexti];
920 cd->wb_tx_free = &cd->wb_tx_chain[0];
921 cd->wb_tx_tail = cd->wb_tx_head = NULL;
927 * Initialize the RX descriptors and allocate mbufs for them. Note that
928 * we arrange the descriptors in a closed ring, so that the last descriptor
929 * points back to the first.
932 wb_list_rx_init(struct wb_softc *sc)
934 struct wb_chain_data *cd;
935 struct wb_list_data *ld;
941 for (i = 0; i < WB_RX_LIST_CNT; i++) {
942 cd->wb_rx_chain[i].wb_ptr = &ld->wb_rx_list[i];
943 cd->wb_rx_chain[i].wb_buf = &ld->wb_rxbufs[i];
944 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
946 nexti = (WB_RX_LIST_CNT - 1) ? 0 : i + 1;
947 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[nexti];
948 ld->wb_rx_list[i].wb_next = vtophys(&ld->wb_rx_list[nexti]);
951 cd->wb_rx_head = &cd->wb_rx_chain[0];
962 * Initialize an RX descriptor and attach an MBUF cluster.
965 wb_newbuf(struct wb_softc *sc, struct wb_chain_onefrag *c, struct mbuf *m)
967 struct mbuf *m_new = NULL;
970 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
974 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf;
975 m_new->m_flags |= M_EXT | M_EXT_OLD;
976 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
977 m_new->m_len = WB_BUFBYTES;
978 m_new->m_ext.ext_nfree.new = wb_bfree;
979 m_new->m_ext.ext_nref.new = wb_bfree;
982 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
983 m_new->m_data = m_new->m_ext.ext_buf;
986 m_adj(m_new, sizeof(uint64_t));
989 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
990 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
991 c->wb_ptr->wb_status = WB_RXSTAT;
997 * A frame has been uploaded: pass the resulting mbuf chain up to
998 * the higher level protocols.
1001 wb_rxeof(struct wb_softc *sc)
1003 struct ifnet *ifp = &sc->arpcom.ac_if;
1004 struct mbuf *m, *m0;
1005 struct wb_chain_onefrag *cur_rx;
1010 rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status;
1011 if ((rxstat & WB_RXSTAT_OWN) == 0)
1014 cur_rx = sc->wb_cdata.wb_rx_head;
1015 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
1017 m = cur_rx->wb_mbuf;
1019 if ((rxstat & WB_RXSTAT_MIIERR) ||
1020 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
1021 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
1022 (rxstat & WB_RXSTAT_LASTFRAG) == 0||
1023 (rxstat & WB_RXSTAT_RXCMP) == 0) {
1025 wb_newbuf(sc, cur_rx, m);
1026 printf("wb%x: receiver babbling: possible chip "
1027 "bug, forcing reset\n", sc->wb_unit);
1034 if (rxstat & WB_RXSTAT_RXERR) {
1036 wb_newbuf(sc, cur_rx, m);
1040 /* No errors; receive the packet. */
1041 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1044 * XXX The Winbond chip includes the CRC with every
1045 * received frame, and there's no way to turn this
1046 * behavior off (at least, I can't find anything in
1047 * the manual that explains how to do it) so we have
1048 * to trim off the CRC manually.
1050 total_len -= ETHER_CRC_LEN;
1052 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1053 total_len + ETHER_ALIGN, 0, ifp, NULL);
1054 wb_newbuf(sc, cur_rx, m);
1059 m_adj(m0, ETHER_ALIGN);
1063 (*ifp->if_input)(ifp, m);
1068 wb_rxeoc(struct wb_softc *sc)
1072 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1073 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1074 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1075 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1076 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1080 * A frame was downloaded to the chip. It's safe for us to clean up
1084 wb_txeof(struct wb_softc *sc)
1086 struct ifnet *ifp = &sc->arpcom.ac_if;
1087 struct wb_chain *cur_tx;
1089 /* Clear the timeout timer. */
1092 if (sc->wb_cdata.wb_tx_head == NULL)
1096 * Go through our tx list and free mbufs for those
1097 * frames that have been transmitted.
1099 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1102 cur_tx = sc->wb_cdata.wb_tx_head;
1103 txstat = WB_TXSTATUS(cur_tx);
1105 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1108 if (txstat & WB_TXSTAT_TXERR) {
1110 if (txstat & WB_TXSTAT_ABORT)
1111 ifp->if_collisions++;
1112 if (txstat & WB_TXSTAT_LATECOLL)
1113 ifp->if_collisions++;
1116 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1119 m_freem(cur_tx->wb_mbuf);
1120 cur_tx->wb_mbuf = NULL;
1122 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1123 sc->wb_cdata.wb_tx_head = NULL;
1124 sc->wb_cdata.wb_tx_tail = NULL;
1128 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1133 * TX 'end of channel' interrupt handler.
1136 wb_txeoc(struct wb_softc *sc)
1138 struct ifnet *ifp = &sc->arpcom.ac_if;
1142 if (sc->wb_cdata.wb_tx_head == NULL) {
1143 ifp->if_flags &= ~IFF_OACTIVE;
1144 sc->wb_cdata.wb_tx_tail = NULL;
1145 } else if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1146 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1148 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1155 struct wb_softc *sc = arg;
1156 struct ifnet *ifp = &sc->arpcom.ac_if;
1159 if ((ifp->if_flags & IFF_UP) == 0)
1162 /* Disable interrupts. */
1163 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1166 status = CSR_READ_4(sc, WB_ISR);
1168 CSR_WRITE_4(sc, WB_ISR, status);
1170 if ((status & WB_INTRS) == 0)
1173 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1176 if (status & WB_ISR_RX_ERR)
1182 if (status & WB_ISR_RX_OK)
1185 if (status & WB_ISR_RX_IDLE)
1188 if (status & WB_ISR_TX_OK)
1191 if (status & WB_ISR_TX_NOBUF)
1194 if (status & WB_ISR_TX_IDLE) {
1196 if (sc->wb_cdata.wb_tx_head != NULL) {
1197 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1198 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1202 if (status & WB_ISR_TX_UNDERRUN) {
1205 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1206 /* Jack up TX threshold */
1207 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1208 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1209 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1210 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1213 if (status & WB_ISR_BUS_ERR) {
1219 /* Re-enable interrupts. */
1220 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1222 if (!ifq_is_empty(&ifp->if_snd))
1229 struct wb_softc *sc = xsc;
1230 struct mii_data *mii = device_get_softc(sc->wb_miibus);
1237 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc);
1243 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1244 * pointers to the fragment pointers.
1247 wb_encap(struct wb_softc *sc, struct wb_chain *c, struct mbuf *m_head)
1249 struct wb_desc *f = NULL;
1251 int frag, total_len;
1254 * Start packing the mbufs in this chain into
1255 * the fragment pointers. Stop when we run out
1256 * of fragments or hit the end of the mbuf chain.
1260 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1261 if (m->m_len != 0) {
1262 if (frag == WB_MAXFRAGS)
1264 total_len += m->m_len;
1265 f = &c->wb_ptr->wb_frag[frag];
1266 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1268 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1271 f->wb_status = WB_TXSTAT_OWN;
1273 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1274 f->wb_data = vtophys(mtod(m, vm_offset_t));
1280 * Handle special case: we used up all 16 fragments,
1281 * but we have more mbufs left in the chain. Copy the
1282 * data into an mbuf cluster. Note that we don't
1283 * bother clearing the values in the other fragment
1284 * pointers/counters; it wouldn't gain us anything,
1285 * and would waste cycles.
1288 struct mbuf *m_new = NULL;
1290 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1293 if (m_head->m_pkthdr.len > MHLEN) {
1294 MCLGET(m_new, MB_DONTWAIT);
1295 if ((m_new->m_flags & M_EXT) == 0) {
1300 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1301 mtod(m_new, caddr_t));
1302 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1305 f = &c->wb_ptr->wb_frag[0];
1307 f->wb_data = vtophys(mtod(m_new, caddr_t));
1308 f->wb_ctl = total_len = m_new->m_len;
1309 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1313 if (total_len < WB_MIN_FRAMELEN) {
1314 f = &c->wb_ptr->wb_frag[frag];
1315 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1316 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1317 f->wb_ctl |= WB_TXCTL_TLINK;
1318 f->wb_status = WB_TXSTAT_OWN;
1322 c->wb_mbuf = m_head;
1323 c->wb_lastdesc = frag - 1;
1324 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1325 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1331 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1332 * to the mbuf data regions directly in the transmit lists. We also save a
1333 * copy of the pointers since the transmit list fragment pointers are
1334 * physical addresses.
1337 wb_start(struct ifnet *ifp)
1339 struct wb_softc *sc = ifp->if_softc;
1340 struct mbuf *m_head = NULL;
1341 struct wb_chain *cur_tx = NULL, *start_tx;
1344 * Check for an available queue slot. If there are none,
1347 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1348 ifp->if_flags |= IFF_OACTIVE;
1352 start_tx = sc->wb_cdata.wb_tx_free;
1354 while (sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1355 m_head = ifq_dequeue(&ifp->if_snd);
1359 /* Pick a descriptor off the free list. */
1360 cur_tx = sc->wb_cdata.wb_tx_free;
1361 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1363 /* Pack the data into the descriptor. */
1364 wb_encap(sc, cur_tx, m_head);
1366 if (cur_tx != start_tx)
1367 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1369 BPF_MTAP(ifp, cur_tx->wb_mbuf);
1373 * If there are no packets queued, bail.
1379 * Place the request for the upload interrupt
1380 * in the last descriptor in the chain. This way, if
1381 * we're chaining several packets at once, we'll only
1382 * get an interupt once for the whole chain rather than
1383 * once for each packet.
1385 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1386 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1387 sc->wb_cdata.wb_tx_tail = cur_tx;
1389 if (sc->wb_cdata.wb_tx_head == NULL) {
1390 sc->wb_cdata.wb_tx_head = start_tx;
1391 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1392 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1395 * We need to distinguish between the case where
1396 * the own bit is clear because the chip cleared it
1397 * and where the own bit is clear because we haven't
1398 * set it yet. The magic value WB_UNSET is just some
1399 * ramdomly chosen number which doesn't have the own
1400 * bit set. When we actually transmit the frame, the
1401 * status word will have _only_ the own bit set, so
1402 * the txeoc handler will be able to tell if it needs
1403 * to initiate another transmission to flush out pending
1406 WB_TXOWN(start_tx) = WB_UNSENT;
1410 * Set a timeout in case the chip goes out to lunch.
1418 struct wb_softc *sc = xsc;
1419 struct ifnet *ifp = &sc->arpcom.ac_if;
1421 struct mii_data *mii;
1425 mii = device_get_softc(sc->wb_miibus);
1428 * Cancel pending I/O and free all RX/TX buffers.
1433 sc->wb_txthresh = WB_TXTHRESH_INIT;
1436 * Set cache alignment and burst length.
1439 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1440 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1441 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1444 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE | WB_BUSCTL_ARBITRATION);
1445 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1446 switch(sc->wb_cachesize) {
1448 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1451 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1454 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1458 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1462 /* This doesn't tend to work too well at 100Mbps. */
1463 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1465 /* Init our MAC address */
1466 for (i = 0; i < ETHER_ADDR_LEN; i++)
1467 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
1469 /* Init circular RX list. */
1470 if (wb_list_rx_init(sc) == ENOBUFS) {
1471 printf("wb%d: initialization failed: no "
1472 "memory for rx buffers\n", sc->wb_unit);
1478 /* Init TX descriptors. */
1479 wb_list_tx_init(sc);
1481 /* If we want promiscuous mode, set the allframes bit. */
1482 if (ifp->if_flags & IFF_PROMISC)
1483 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1485 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1488 * Set capture broadcast bit to capture broadcast frames.
1490 if (ifp->if_flags & IFF_BROADCAST)
1491 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1493 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1496 * Program the multicast filter, if necessary.
1501 * Load the address of the RX list.
1503 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1504 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1507 * Enable interrupts.
1509 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1510 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1512 /* Enable receiver and transmitter. */
1513 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1514 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1516 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1517 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1518 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1522 ifp->if_flags |= IFF_RUNNING;
1523 ifp->if_flags &= ~IFF_OACTIVE;
1527 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc);
1531 * Set media options.
1534 wb_ifmedia_upd(struct ifnet *ifp)
1536 struct wb_softc *sc = ifp->if_softc;
1538 if (ifp->if_flags & IFF_UP)
1545 * Report current media status.
1548 wb_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1550 struct wb_softc *sc = ifp->if_softc;
1551 struct mii_data *mii = device_get_softc(sc->wb_miibus);
1554 ifmr->ifm_active = mii->mii_media_active;
1555 ifmr->ifm_status = mii->mii_media_status;
1559 wb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1561 struct wb_softc *sc = ifp->if_softc;
1562 struct mii_data *mii;
1563 struct ifreq *ifr = (struct ifreq *) data;
1570 if (ifp->if_flags & IFF_UP)
1572 else if (ifp->if_flags & IFF_RUNNING)
1583 mii = device_get_softc(sc->wb_miibus);
1584 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1587 error = ether_ioctl(ifp, command, data);
1597 wb_watchdog(struct ifnet *ifp)
1599 struct wb_softc *sc = ifp->if_softc;
1602 printf("wb%d: watchdog timeout\n", sc->wb_unit);
1604 if ((wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) == 0)
1605 printf("wb%d: no carrier - transceiver cable problem?\n",
1612 if (!ifq_is_empty(&ifp->if_snd))
1617 * Stop the adapter and free any mbufs allocated to the
1621 wb_stop(struct wb_softc *sc)
1623 struct ifnet *ifp = &sc->arpcom.ac_if;
1628 callout_stop(&sc->wb_stat_timer);
1630 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON | WB_NETCFG_TX_ON));
1631 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1632 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1633 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1636 * Free data in the RX lists.
1638 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1639 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1640 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1641 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1644 bzero(&sc->wb_ldata->wb_rx_list, sizeof(sc->wb_ldata->wb_rx_list));
1647 * Free the TX list buffers.
1649 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1650 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1651 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1652 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1656 bzero(&sc->wb_ldata->wb_tx_list, sizeof(sc->wb_ldata->wb_tx_list));
1658 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1662 * Stop all chip I/O so that the kernel's probe routines don't
1663 * get confused by errant DMAs when rebooting.
1666 wb_shutdown(device_t dev)
1668 struct wb_softc *sc = device_get_softc(dev);