1 /******************************************************************************
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7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
36 * 82540EM Gigabit Ethernet Controller
37 * 82540EP Gigabit Ethernet Controller
38 * 82545EM Gigabit Ethernet Controller (Copper)
39 * 82545EM Gigabit Ethernet Controller (Fiber)
40 * 82545GM Gigabit Ethernet Controller
41 * 82546EB Gigabit Ethernet Controller (Copper)
42 * 82546EB Gigabit Ethernet Controller (Fiber)
43 * 82546GB Gigabit Ethernet Controller
46 #include "e1000_api.h"
48 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw);
49 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw);
50 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw);
51 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
52 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
53 static s32 e1000_init_hw_82540(struct e1000_hw *hw);
54 static s32 e1000_reset_hw_82540(struct e1000_hw *hw);
55 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw);
56 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw);
57 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw);
58 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
59 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
62 * e1000_init_phy_params_82540 - Init PHY func ptrs.
63 * @hw: pointer to the HW structure
65 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
67 struct e1000_phy_info *phy = &hw->phy;
68 s32 ret_val = E1000_SUCCESS;
71 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
72 phy->reset_delay_us = 10000;
73 phy->type = e1000_phy_m88;
75 /* Function Pointers */
76 phy->ops.check_polarity = e1000_check_polarity_m88;
77 phy->ops.commit = e1000_phy_sw_reset_generic;
78 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
79 phy->ops.get_cable_length = e1000_get_cable_length_m88;
80 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
81 phy->ops.read_reg = e1000_read_phy_reg_m88;
82 phy->ops.reset = e1000_phy_hw_reset_generic;
83 phy->ops.write_reg = e1000_write_phy_reg_m88;
84 phy->ops.get_info = e1000_get_phy_info_m88;
85 phy->ops.power_up = e1000_power_up_phy_copper;
86 phy->ops.power_down = e1000_power_down_phy_copper_82540;
88 ret_val = e1000_get_phy_id(hw);
93 switch (hw->mac.type) {
96 case e1000_82545_rev_3:
98 case e1000_82546_rev_3:
99 if (phy->id == M88E1011_I_PHY_ID)
103 ret_val = -E1000_ERR_PHY;
113 * e1000_init_nvm_params_82540 - Init NVM func ptrs.
114 * @hw: pointer to the HW structure
116 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
118 struct e1000_nvm_info *nvm = &hw->nvm;
119 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
121 DEBUGFUNC("e1000_init_nvm_params_82540");
123 nvm->type = e1000_nvm_eeprom_microwire;
124 nvm->delay_usec = 50;
125 nvm->opcode_bits = 3;
126 switch (nvm->override) {
127 case e1000_nvm_override_microwire_large:
128 nvm->address_bits = 8;
129 nvm->word_size = 256;
131 case e1000_nvm_override_microwire_small:
132 nvm->address_bits = 6;
136 nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;
137 nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;
141 /* Function Pointers */
142 nvm->ops.acquire = e1000_acquire_nvm_generic;
143 nvm->ops.read = e1000_read_nvm_microwire;
144 nvm->ops.release = e1000_release_nvm_generic;
145 nvm->ops.update = e1000_update_nvm_checksum_generic;
146 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
147 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
148 nvm->ops.write = e1000_write_nvm_microwire;
150 return E1000_SUCCESS;
154 * e1000_init_mac_params_82540 - Init MAC func ptrs.
155 * @hw: pointer to the HW structure
157 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
159 struct e1000_mac_info *mac = &hw->mac;
160 s32 ret_val = E1000_SUCCESS;
162 DEBUGFUNC("e1000_init_mac_params_82540");
165 switch (hw->device_id) {
166 case E1000_DEV_ID_82545EM_FIBER:
167 case E1000_DEV_ID_82545GM_FIBER:
168 case E1000_DEV_ID_82546EB_FIBER:
169 case E1000_DEV_ID_82546GB_FIBER:
170 hw->phy.media_type = e1000_media_type_fiber;
172 case E1000_DEV_ID_82545GM_SERDES:
173 case E1000_DEV_ID_82546GB_SERDES:
174 hw->phy.media_type = e1000_media_type_internal_serdes;
177 hw->phy.media_type = e1000_media_type_copper;
181 /* Set mta register count */
182 mac->mta_reg_count = 128;
183 /* Set rar entry count */
184 mac->rar_entry_count = E1000_RAR_ENTRIES;
186 /* Function pointers */
188 /* bus type/speed/width */
189 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
191 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
193 mac->ops.reset_hw = e1000_reset_hw_82540;
194 /* hw initialization */
195 mac->ops.init_hw = e1000_init_hw_82540;
197 mac->ops.setup_link = e1000_setup_link_generic;
198 /* physical interface setup */
199 mac->ops.setup_physical_interface =
200 (hw->phy.media_type == e1000_media_type_copper)
201 ? e1000_setup_copper_link_82540
202 : e1000_setup_fiber_serdes_link_82540;
204 switch (hw->phy.media_type) {
205 case e1000_media_type_copper:
206 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
208 case e1000_media_type_fiber:
209 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
211 case e1000_media_type_internal_serdes:
212 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
215 ret_val = -E1000_ERR_CONFIG;
220 mac->ops.get_link_up_info =
221 (hw->phy.media_type == e1000_media_type_copper)
222 ? e1000_get_speed_and_duplex_copper_generic
223 : e1000_get_speed_and_duplex_fiber_serdes_generic;
224 /* multicast address update */
225 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
227 mac->ops.write_vfta = e1000_write_vfta_generic;
229 mac->ops.clear_vfta = e1000_clear_vfta_generic;
231 mac->ops.mta_set = e1000_mta_set_generic;
233 mac->ops.setup_led = e1000_setup_led_generic;
235 mac->ops.cleanup_led = e1000_cleanup_led_generic;
236 /* turn on/off LED */
237 mac->ops.led_on = e1000_led_on_generic;
238 mac->ops.led_off = e1000_led_off_generic;
239 /* clear hardware counters */
240 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
247 * e1000_init_function_pointers_82540 - Init func ptrs.
248 * @hw: pointer to the HW structure
250 * Called to initialize all function pointers and parameters.
252 void e1000_init_function_pointers_82540(struct e1000_hw *hw)
254 DEBUGFUNC("e1000_init_function_pointers_82540");
256 hw->mac.ops.init_params = e1000_init_mac_params_82540;
257 hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
258 hw->phy.ops.init_params = e1000_init_phy_params_82540;
262 * e1000_reset_hw_82540 - Reset hardware
263 * @hw: pointer to the HW structure
265 * This resets the hardware into a known state.
267 static s32 e1000_reset_hw_82540(struct e1000_hw *hw)
270 s32 ret_val = E1000_SUCCESS;
272 DEBUGFUNC("e1000_reset_hw_82540");
274 DEBUGOUT("Masking off all interrupts\n");
275 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
277 E1000_WRITE_REG(hw, E1000_RCTL, 0);
278 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
279 E1000_WRITE_FLUSH(hw);
282 * Delay to allow any outstanding PCI transactions to complete
283 * before resetting the device.
287 ctrl = E1000_READ_REG(hw, E1000_CTRL);
289 DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
290 switch (hw->mac.type) {
291 case e1000_82545_rev_3:
292 case e1000_82546_rev_3:
293 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
297 * These controllers can't ack the 64-bit write when
298 * issuing the reset, so we use IO-mapping as a
299 * workaround to issue the reset.
301 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
305 /* Wait for EEPROM reload */
308 /* Disable HW ARPs on ASF enabled adapters */
309 manc = E1000_READ_REG(hw, E1000_MANC);
310 manc &= ~E1000_MANC_ARP_EN;
311 E1000_WRITE_REG(hw, E1000_MANC, manc);
313 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
314 icr = E1000_READ_REG(hw, E1000_ICR);
320 * e1000_init_hw_82540 - Initialize hardware
321 * @hw: pointer to the HW structure
323 * This inits the hardware readying it for operation.
325 static s32 e1000_init_hw_82540(struct e1000_hw *hw)
327 struct e1000_mac_info *mac = &hw->mac;
328 u32 txdctl, ctrl_ext;
329 s32 ret_val = E1000_SUCCESS;
332 DEBUGFUNC("e1000_init_hw_82540");
334 /* Initialize identification LED */
335 ret_val = e1000_id_led_init_generic(hw);
337 DEBUGOUT("Error initializing identification LED\n");
338 /* This is not fatal and we should not stop init due to this */
341 /* Disabling VLAN filtering */
342 DEBUGOUT("Initializing the IEEE VLAN\n");
343 if (mac->type < e1000_82545_rev_3)
344 E1000_WRITE_REG(hw, E1000_VET, 0);
346 mac->ops.clear_vfta(hw);
348 /* Setup the receive address. */
349 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
351 /* Zero out the Multicast HASH table */
352 DEBUGOUT("Zeroing the MTA\n");
353 for (i = 0; i < mac->mta_reg_count; i++) {
354 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
356 * Avoid back to back register writes by adding the register
357 * read (flush). This is to protect against some strange
358 * bridge configurations that may issue Memory Write Block
359 * (MWB) to our register space. The *_rev_3 hardware at
360 * least doesn't respond correctly to every other dword in an
361 * MWB to our register space.
363 E1000_WRITE_FLUSH(hw);
366 if (mac->type < e1000_82545_rev_3)
367 e1000_pcix_mmrbc_workaround_generic(hw);
369 /* Setup link and flow control */
370 ret_val = mac->ops.setup_link(hw);
372 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
373 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
374 E1000_TXDCTL_FULL_TX_DESC_WB;
375 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
378 * Clear all of the statistics registers (clear on read). It is
379 * important that we do this after we have tried to establish link
380 * because the symbol error count will increment wildly if there
383 e1000_clear_hw_cntrs_82540(hw);
385 if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
386 (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
387 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
389 * Relaxed ordering must be disabled to avoid a parity
390 * error crash in a PCI slot.
392 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
393 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
400 * e1000_setup_copper_link_82540 - Configure copper link settings
401 * @hw: pointer to the HW structure
403 * Calls the appropriate function to configure the link for auto-neg or forced
404 * speed and duplex. Then we check for link, once link is established calls
405 * to configure collision distance and flow control are called. If link is
406 * not established, we return -E1000_ERR_PHY (-2).
408 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
411 s32 ret_val = E1000_SUCCESS;
414 DEBUGFUNC("e1000_setup_copper_link_82540");
416 ctrl = E1000_READ_REG(hw, E1000_CTRL);
417 ctrl |= E1000_CTRL_SLU;
418 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
419 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
421 ret_val = e1000_set_phy_mode_82540(hw);
425 if (hw->mac.type == e1000_82545_rev_3 ||
426 hw->mac.type == e1000_82546_rev_3) {
427 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &data);
431 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, data);
436 ret_val = e1000_copper_link_setup_m88(hw);
440 ret_val = e1000_setup_copper_link_generic(hw);
447 * e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
448 * @hw: pointer to the HW structure
450 * Set the output amplitude to the value in the EEPROM and adjust the VCO
451 * speed to improve Bit Error Rate (BER) performance. Configures collision
452 * distance and flow control for fiber and serdes links. Upon successful
453 * setup, poll for link.
455 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
457 struct e1000_mac_info *mac = &hw->mac;
458 s32 ret_val = E1000_SUCCESS;
460 DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
463 case e1000_82545_rev_3:
464 case e1000_82546_rev_3:
465 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
467 * If we're on serdes media, adjust the output
468 * amplitude to value set in the EEPROM.
470 ret_val = e1000_adjust_serdes_amplitude_82540(hw);
474 /* Adjust VCO speed to improve BER performance */
475 ret_val = e1000_set_vco_speed_82540(hw);
482 ret_val = e1000_setup_fiber_serdes_link_generic(hw);
489 * e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
490 * @hw: pointer to the HW structure
492 * Adjust the SERDES output amplitude based on the EEPROM settings.
494 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
496 s32 ret_val = E1000_SUCCESS;
499 DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
501 ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
505 if (nvm_data != NVM_RESERVED_WORD) {
506 /* Adjust serdes output amplitude only. */
507 nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
508 ret_val = hw->phy.ops.write_reg(hw,
509 M88E1000_PHY_EXT_CTRL,
520 * e1000_set_vco_speed_82540 - Set VCO speed for better performance
521 * @hw: pointer to the HW structure
523 * Set the VCO speed to improve Bit Error Rate (BER) performance.
525 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
527 s32 ret_val = E1000_SUCCESS;
528 u16 default_page = 0;
531 DEBUGFUNC("e1000_set_vco_speed_82540");
533 /* Set PHY register 30, page 5, bit 8 to 0 */
535 ret_val = hw->phy.ops.read_reg(hw,
536 M88E1000_PHY_PAGE_SELECT,
541 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
545 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
549 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
550 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
554 /* Set PHY register 30, page 4, bit 11 to 1 */
556 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
560 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
564 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
565 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
569 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
577 * e1000_set_phy_mode_82540 - Set PHY to class A mode
578 * @hw: pointer to the HW structure
580 * Sets the PHY to class A mode and assumes the following operations will
581 * follow to enable the new class mode:
582 * 1. Do a PHY soft reset.
583 * 2. Restart auto-negotiation or force link.
585 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
587 struct e1000_phy_info *phy = &hw->phy;
588 s32 ret_val = E1000_SUCCESS;
591 DEBUGFUNC("e1000_set_phy_mode_82540");
593 if (hw->mac.type != e1000_82545_rev_3)
596 ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
598 ret_val = -E1000_ERR_PHY;
602 if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
603 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
606 ret_val = -E1000_ERR_PHY;
609 ret_val = hw->phy.ops.write_reg(hw,
610 M88E1000_PHY_GEN_CONTROL,
613 ret_val = -E1000_ERR_PHY;
617 phy->reset_disable = FALSE;
625 * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
626 * @hw: pointer to the HW structure
628 * In the case of a PHY power down to save power, or to turn off link during a
629 * driver unload, or wake on lan is not enabled, remove the link.
631 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
633 /* If the management interface is not enabled, then power down */
634 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
635 e1000_power_down_phy_copper(hw);
641 * e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
642 * @hw: pointer to the HW structure
644 * Clears the hardware counters by reading the counter registers.
646 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
648 DEBUGFUNC("e1000_clear_hw_cntrs_82540");
650 e1000_clear_hw_cntrs_base_generic(hw);
652 E1000_READ_REG(hw, E1000_PRC64);
653 E1000_READ_REG(hw, E1000_PRC127);
654 E1000_READ_REG(hw, E1000_PRC255);
655 E1000_READ_REG(hw, E1000_PRC511);
656 E1000_READ_REG(hw, E1000_PRC1023);
657 E1000_READ_REG(hw, E1000_PRC1522);
658 E1000_READ_REG(hw, E1000_PTC64);
659 E1000_READ_REG(hw, E1000_PTC127);
660 E1000_READ_REG(hw, E1000_PTC255);
661 E1000_READ_REG(hw, E1000_PTC511);
662 E1000_READ_REG(hw, E1000_PTC1023);
663 E1000_READ_REG(hw, E1000_PTC1522);
665 E1000_READ_REG(hw, E1000_ALGNERRC);
666 E1000_READ_REG(hw, E1000_RXERRC);
667 E1000_READ_REG(hw, E1000_TNCRS);
668 E1000_READ_REG(hw, E1000_CEXTERR);
669 E1000_READ_REG(hw, E1000_TSCTC);
670 E1000_READ_REG(hw, E1000_TSCTFC);
672 E1000_READ_REG(hw, E1000_MGTPRC);
673 E1000_READ_REG(hw, E1000_MGTPDC);
674 E1000_READ_REG(hw, E1000_MGTPTC);