2 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 #define DPRINTF(x) if_printf x
41 #define DPRINTF(x) ((void)0)
44 #define ACX_FRAME_HDRLEN sizeof(struct ieee80211_frame)
45 #define ACX_MEMBLOCK_SIZE 256
47 #define ACX_TX_DESC_CNT 16
48 #define ACX_RX_DESC_CNT 16
50 #define ACX_TX_RING_SIZE \
51 (2 * ACX_TX_DESC_CNT * sizeof(struct acx_host_desc))
52 #define ACX_RX_RING_SIZE \
53 (ACX_RX_DESC_CNT * sizeof(struct acx_host_desc))
55 #define CSR_READ_1(sc, reg) \
56 bus_space_read_1((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, \
57 (sc)->chip_ioreg[(reg)])
58 #define CSR_READ_2(sc, reg) \
59 bus_space_read_2((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, \
60 (sc)->chip_ioreg[(reg)])
61 #define CSR_READ_4(sc, reg) \
62 bus_space_read_4((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, \
63 (sc)->chip_ioreg[(reg)])
65 #define CSR_WRITE_2(sc, reg, val) \
66 bus_space_write_2((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, \
67 (sc)->chip_ioreg[(reg)], val)
68 #define CSR_WRITE_4(sc, reg, val) \
69 bus_space_write_4((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, \
70 (sc)->chip_ioreg[(reg)], val)
72 #define CSR_SETB_2(sc, reg, b) \
73 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (b))
74 #define CSR_CLRB_2(sc, reg, b) \
75 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & (~(b)))
77 #define DESC_READ_1(sc, off) \
78 bus_space_read_1((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off))
79 #define DESC_READ_2(sc, off) \
80 bus_space_read_2((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off))
81 #define DESC_READ_4(sc, off) \
82 bus_space_read_4((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off))
84 #define DESC_WRITE_1(sc, off, val) \
85 bus_space_write_1((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off), (val))
86 #define DESC_WRITE_2(sc, off, val) \
87 bus_space_write_2((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off), (val))
88 #define DESC_WRITE_4(sc, off, val) \
89 bus_space_write_4((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off), (val))
90 #define DESC_WRITE_REGION_1(sc, off, d, dlen) \
91 bus_space_write_region_1((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, \
92 (off), (const uint8_t *)(d), (dlen))
94 #define FW_TXDESC_SETFIELD(sc, mb, field, val, sz) \
95 DESC_WRITE_##sz((sc), (mb)->tb_fwdesc_ofs + \
96 __offsetof(struct acx_fw_txdesc, field), (val))
98 #define FW_TXDESC_GETFIELD(sc, mb, field, sz) \
99 DESC_READ_##sz((sc), (mb)->tb_fwdesc_ofs + \
100 __offsetof(struct acx_fw_txdesc, field))
102 #define FW_TXDESC_SETFIELD_1(sc, mb, field, val) \
103 FW_TXDESC_SETFIELD(sc, mb, field, val, 1)
104 #define FW_TXDESC_SETFIELD_2(sc, mb, field, val) \
105 FW_TXDESC_SETFIELD(sc, mb, field, htole16(val), 2)
106 #define FW_TXDESC_SETFIELD_4(sc, mb, field, val) \
107 FW_TXDESC_SETFIELD(sc, mb, field, htole32(val), 4)
109 #define FW_TXDESC_GETFIELD_1(sc, mb, field) \
110 FW_TXDESC_GETFIELD(sc, mb, field, 1)
111 #define FW_TXDESC_GETFIELD_2(sc, mb, field) \
112 le16toh(FW_TXDESC_GETFIELD(sc, mb, field, 2))
113 #define FW_TXDESC_GETFIELD_4(sc, mb, field) \
114 le32toh(FW_TXDESC_GETFIELD(sc, mb, field, 4))
117 * Firmware TX descriptor
118 * Fields are little endian
120 struct acx_fw_txdesc {
121 uint32_t f_tx_next_desc; /* next acx_fw_txdesc phyaddr */
122 uint32_t f_tx_host_desc; /* acx_host_desc phyaddr */
123 uint32_t f_tx_acx_ptr;
126 uint16_t f_tx_reserved;
128 uint32_t f_tx_dev_spec[4];
130 uint8_t f_tx_ctrl; /* see DESC_CTRL_ */
132 uint8_t f_tx_error; /* see DESC_ERR_ */
133 uint8_t f_tx_data_nretry; /* non-RTS retries */
134 uint8_t f_tx_rts_nretry; /* RTS retries */
137 /* XXX should be moved to chip specific file */
140 uint8_t rate100; /* acx100 tx rate */
144 uint16_t rate111; /* acx111 tx rate */
147 #define f_tx_rate100 u.r1.rate100
148 #define f_tx_queue_ctrl u.r1.queue_ctrl
149 #define f_tx_rate111 u.r2.rate111
150 uint32_t f_tx_queue_info;
154 * Firmware RX descriptor
155 * Fields are little endian
157 struct acx_fw_rxdesc {
158 uint32_t f_rx_next_desc; /* next acx_fw_rxdesc phyaddr */
159 uint32_t f_rx_host_desc; /* acx_host_desc phyaddr */
160 uint32_t f_rx_acx_ptr;
163 uint16_t f_rx_wep_len;
164 uint32_t f_rx_wep_ofs;
166 uint8_t f_rx_dev_spec[16];
168 uint8_t f_rx_ctrl; /* see DESC_CTRL_ */
171 uint8_t f_rx_snr; /* signal noise ratio */
173 uint8_t f_rx_queue_ctrl;
174 uint16_t f_rx_unknown0;
175 uint32_t f_rx_unknown1;
179 * Host TX/RX descriptor
180 * Fields are little endian
182 struct acx_host_desc {
183 uint32_t h_data_paddr; /* data phyaddr */
186 uint16_t h_ctrl; /* see DESC_CTRL_ */
187 uint16_t h_data_len; /* data length */
188 uint32_t h_next_desc; /* next acx_host_desc phyaddr */
190 uint32_t h_status; /* see DESC_STATUS_ */
193 #define DESC_STATUS_FULL 0x80000000
195 #define DESC_CTRL_SHORT_PREAMBLE 0x01
196 #define DESC_CTRL_FIRST_FRAG 0x02
197 #define DESC_CTRL_AUTODMA 0x04
198 #define DESC_CTRL_RECLAIM 0x08
199 #define DESC_CTRL_HOSTDONE 0x20 /* host finished buf proc */
200 #define DESC_CTRL_ACXDONE 0x40 /* chip finished buf proc */
201 #define DESC_CTRL_HOSTOWN 0x80 /* host controls desc */
203 #define DESC_ERR_OTHER_FRAG 0x01
204 #define DESC_ERR_ABORT 0x02
205 #define DESC_ERR_PARAM 0x04
206 #define DESC_ERR_NO_WEPKEY 0x08
207 #define DESC_ERR_MSDU_TIMEOUT 0x10
208 #define DESC_ERR_EXCESSIVE_RETRY 0x20
209 #define DESC_ERR_BUF_OVERFLOW 0x40
210 #define DESC_ERR_DMA 0x80
213 * Extra header in receiving buffer
214 * Fields are little endian
216 struct acx_rxbuf_hdr {
217 uint16_t rbh_len; /* ACX_RXBUG_LEN_MASK part is len */
218 uint8_t rbh_memblk_cnt;
220 uint8_t rbh_bbp_stat; /* see ACX_RXBUF_STAT_ */
222 uint8_t rbh_level; /* signal level */
223 uint8_t rbh_snr; /* signal noise ratio */
224 uint32_t rbh_time; /* recv timestamp */
227 * XXX may have 4~8 byte here which
228 * depends on firmware version
232 #define ACX_RXBUF_LEN_MASK 0xfff
234 #define ACX_RXBUF_STAT_OFDM 0x04
235 #define ACX_RXBUF_STAT_ANT1 0x10
236 #define ACX_RXBUF_STAT_SHPRE 0x80
238 struct acx_ring_data {
239 struct acx_host_desc *rx_ring;
240 bus_dma_tag_t rx_ring_dma_tag;
241 bus_dmamap_t rx_ring_dmamap;
242 uint32_t rx_ring_paddr;
244 struct acx_host_desc *tx_ring;
245 bus_dma_tag_t tx_ring_dma_tag;
246 bus_dmamap_t tx_ring_dmamap;
247 uint32_t tx_ring_paddr;
251 struct mbuf *tb_mbuf;
252 bus_dmamap_t tb_mbuf_dmamap;
254 struct acx_host_desc *tb_desc1;
255 struct acx_host_desc *tb_desc2;
257 uint32_t tb_fwdesc_ofs;
262 struct ieee80211_node *tb_node;
264 int tb_rateidx[IEEE80211_RATEIDX_MAX];
268 struct mbuf *rb_mbuf;
269 bus_dmamap_t rb_mbuf_dmamap;
271 struct acx_host_desc *rb_desc;
274 struct acx_buf_data {
275 struct acx_rxbuf rx_buf[ACX_RX_DESC_CNT];
276 struct acx_txbuf tx_buf[ACX_TX_DESC_CNT];
277 bus_dma_tag_t mbuf_dma_tag;
278 bus_dmamap_t mbuf_tmp_dmamap;
287 struct acx_firmware_hdr {
292 struct acx_firmware {
293 struct fw_image *base_fw_image;
294 const uint8_t *base_fw;
297 struct fw_image *radio_fw_image;
298 const uint8_t *radio_fw;
301 int combined_radio_fw;
306 uint8_t eaddr[IEEE80211_ADDR_LEN];
309 uint8_t cca_mode; /* acx100 */
310 uint8_t ed_thresh; /* acx100 */
314 uint64_t err_oth_frag; /* XXX error in other frag?? */
315 uint64_t err_abort; /* tx abortion */
316 uint64_t err_param; /* tx desc contains invalid param */
317 uint64_t err_no_wepkey; /* no WEP key exists */
318 uint64_t err_msdu_timeout; /* MSDU timed out */
319 uint64_t err_ex_retry; /* excessive tx retry */
320 uint64_t err_buf_oflow; /* buffer overflow */
321 uint64_t err_dma; /* DMA error */
322 uint64_t err_unkn; /* XXX unknown error */
325 #define ACX_RX_RADIOTAP_PRESENT \
326 ((1 << IEEE80211_RADIOTAP_TSFT) | \
327 (1 << IEEE80211_RADIOTAP_FLAGS) | \
328 (1 << IEEE80211_RADIOTAP_RATE) | \
329 (1 << IEEE80211_RADIOTAP_CHANNEL) | \
330 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)| \
331 (1 << IEEE80211_RADIOTAP_ANTENNA))
333 struct acx_rx_radiotap_header {
334 struct ieee80211_radiotap_header wr_ihdr;
338 uint16_t wr_chan_freq;
339 uint16_t wr_chan_flags;
340 uint8_t wr_antsignal;
344 #define ACX_TX_RADIOTAP_PRESENT \
345 ((1 << IEEE80211_RADIOTAP_FLAGS) | \
346 (1 << IEEE80211_RADIOTAP_RATE) | \
347 (1 << IEEE80211_RADIOTAP_CHANNEL))
349 struct acx_tx_radiotap_header {
350 struct ieee80211_radiotap_header wt_ihdr;
353 uint16_t wt_chan_freq;
354 uint16_t wt_chan_flags;
359 * sc_xxx are filled in by common code
360 * chip_xxx are filled in by chip specific code
362 struct ieee80211com sc_ic;
367 struct bpf_if *sc_drvbpf;
369 struct acx_tx_radiotap_header u_tx_th;
370 uint8_t u_pad[IEEE80211_RADIOTAP_HDRLEN];
374 struct acx_rx_radiotap_header u_rx_th;
375 uint8_t u_pad[IEEE80211_RADIOTAP_HDRLEN];
378 #define sc_tx_th sc_u_tx_th.u_tx_th
379 #define sc_rx_th sc_u_rx_th.u_rx_th
381 struct callout sc_scan_timer;
382 uint32_t sc_flags; /* see ACX_FLAG_ */
385 struct acx_firmware sc_firmware;
386 uint32_t sc_firmware_ver;
387 uint32_t sc_hardware_id;
392 struct resource *sc_mem1_res;
393 bus_space_tag_t sc_mem1_bt;
394 bus_space_handle_t sc_mem1_bh;
400 struct resource *sc_mem2_res;
401 bus_space_tag_t sc_mem2_bt;
402 bus_space_handle_t sc_mem2_bh;
405 struct resource *sc_irq_res;
409 uint32_t sc_cmd; /* cmd reg (MMIO 2) */
410 uint32_t sc_cmd_param; /* cmd param reg (MMIO 2) */
411 uint32_t sc_info; /* unused */
412 uint32_t sc_info_param; /* unused */
414 const uint16_t *chip_ioreg; /* reg map (MMIO 1) */
418 * chip_intr_enable is not necessarily same as
421 uint16_t chip_intr_enable;
422 uint16_t chip_intr_disable;
425 uint16_t chip_gpio_pled; /* power led */
426 uint16_t chip_chan_flags; /* see IEEE80211_CHAN_ */
427 uint16_t chip_txdesc1_len;
428 int chip_rxbuf_exhdr; /* based on fw ver */
429 uint32_t chip_ee_eaddr_ofs;
430 enum ieee80211_phymode chip_phymode; /* see IEEE80211_MODE_ */
431 uint8_t chip_fw_txdesc_ctrl;
434 uint8_t sc_eeprom_ver; /* unused */
435 uint8_t sc_form_factor; /* unused */
436 uint8_t sc_radio_type; /* see ACX_RADIO_TYPE_ */
438 struct acx_ring_data sc_ring_data;
439 struct acx_buf_data sc_buf_data;
441 struct acx_stats sc_stats; /* statistics */
446 struct ieee80211_onoe_param sc_onoe_param;
447 struct ieee80211_amrr_param sc_amrr_param;
448 int sc_long_retry_limit;
449 int chip_short_retry_limit;
450 int chip_rate_fallback;
453 * Per interface sysctl variables
455 int sc_msdu_lifetime;
456 int sc_scan_dwell; /* unit: millisecond */
457 int sc_calib_intvl; /* unit: minute */
460 (struct ieee80211com *,
461 enum ieee80211_state, int);
463 int (*chip_init) /* non-NULL */
464 (struct acx_softc *);
466 int (*chip_set_wepkey)
468 struct ieee80211_key *, int);
470 int (*chip_read_config)
471 (struct acx_softc *, struct acx_config *);
473 int (*chip_write_config)
474 (struct acx_softc *, struct acx_config *);
476 uint8_t (*chip_set_fw_txdesc_rate) /* non-NULL */
477 (struct acx_softc *, struct acx_txbuf *,
478 struct ieee80211_node *, int);
480 void (*chip_tx_complete) /* non-NULL */
481 (struct acx_softc *, struct acx_txbuf *,
484 void (*chip_set_bss_join_param) /* non-NULL */
485 (struct acx_softc *, void *, int);
487 void (*chip_proc_wep_rxbuf)
488 (struct acx_softc *, struct mbuf *, int *);
490 struct callout sc_calibrate_timer;
491 int (*chip_calibrate)
492 (struct acx_softc *);
495 #define ACX_FLAG_FW_LOADED 0x1
496 #define ACX_FLAG_PROMISC 0x2
498 #define ACX_RADIO_TYPE_MAXIM 0x0d
499 #define ACX_RADIO_TYPE_RFMD 0x11
500 #define ACX_RADIO_TYPE_RALINK 0x15
501 #define ACX_RADIO_TYPE_RADIA 0x16
502 #define ACX_RADIO_TYPE_UNKN17 0x17
503 #define ACX_RADIO_TYPE_UNKN19 0x19
505 #define ACX_BASE_FW_PATH "acx/%s/wlangen.bin"
506 #define ACX_RADIO_FW_PATH "acx/%s/radio%02x.bin"
507 #define ACX_BASE_RADIO_FW_PATH "acx/%s/FwRad%02x.bin"
509 extern const struct ieee80211_rateset acx_rates_11b;
510 extern const struct ieee80211_rateset acx_rates_11b_pbcc;
511 extern const struct ieee80211_rateset acx_rates_11g;
512 extern const struct ieee80211_rateset acx_rates_11g_pbcc;
513 extern int acx_enable_pbcc;
515 void acx100_set_param(device_t);
516 void acx111_set_param(device_t);
518 int acx_init_tmplt_ordered(struct acx_softc *);
519 void acx_write_phyreg(struct acx_softc *, uint32_t, uint8_t);
521 #endif /* !_IF_ACXVAR_H */