2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written consent.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
30 * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
34 * The following controllers are supported by this driver:
42 * The following controllers are not supported by this driver:
48 * BCM5709S A0, A1, B0, B1, B2, C0
52 #include "opt_polling.h"
54 #include <sys/param.h>
56 #include <sys/endian.h>
57 #include <sys/kernel.h>
58 #include <sys/interrupt.h>
60 #include <sys/malloc.h>
61 #include <sys/queue.h>
63 #include <sys/random.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
72 #include <net/ethernet.h>
74 #include <net/if_arp.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/ifq_var.h>
79 #include <net/vlan/if_vlan_var.h>
80 #include <net/vlan/if_vlan_ether.h>
82 #include <dev/netif/mii_layer/mii.h>
83 #include <dev/netif/mii_layer/miivar.h>
84 #include <dev/netif/mii_layer/brgphyreg.h>
86 #include <bus/pci/pcireg.h>
87 #include <bus/pci/pcivar.h>
89 #include "miibus_if.h"
91 #include <dev/netif/bce/if_bcereg.h>
92 #include <dev/netif/bce/if_bcefw.h>
94 /****************************************************************************/
95 /* BCE Debug Options */
96 /****************************************************************************/
99 static uint32_t bce_debug = BCE_WARN;
103 * 1 = 1 in 2,147,483,648
104 * 256 = 1 in 8,388,608
105 * 2048 = 1 in 1,048,576
106 * 65536 = 1 in 32,768
107 * 1048576 = 1 in 2,048
110 * 1073741824 = 1 in 2
112 * bce_debug_l2fhdr_status_check:
113 * How often the l2_fhdr frame error check will fail.
115 * bce_debug_unexpected_attention:
116 * How often the unexpected attention check will fail.
118 * bce_debug_mbuf_allocation_failure:
119 * How often to simulate an mbuf allocation failure.
121 * bce_debug_dma_map_addr_failure:
122 * How often to simulate a DMA mapping failure.
124 * bce_debug_bootcode_running_failure:
125 * How often to simulate a bootcode failure.
127 static int bce_debug_l2fhdr_status_check = 0;
128 static int bce_debug_unexpected_attention = 0;
129 static int bce_debug_mbuf_allocation_failure = 0;
130 static int bce_debug_dma_map_addr_failure = 0;
131 static int bce_debug_bootcode_running_failure = 0;
133 #endif /* BCE_DEBUG */
136 /****************************************************************************/
137 /* PCI Device ID Table */
139 /* Used by bce_probe() to identify the devices supported by this driver. */
140 /****************************************************************************/
141 #define BCE_DEVDESC_MAX 64
143 static struct bce_type bce_devs[] = {
144 /* BCM5706C Controllers and OEM boards. */
145 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
146 "HP NC370T Multifunction Gigabit Server Adapter" },
147 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
148 "HP NC370i Multifunction Gigabit Server Adapter" },
149 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070,
150 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
151 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709,
152 "HP NC371i Multifunction Gigabit Server Adapter" },
153 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
154 "Broadcom NetXtreme II BCM5706 1000Base-T" },
156 /* BCM5706S controllers and OEM boards. */
157 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
158 "HP NC370F Multifunction Gigabit Server Adapter" },
159 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
160 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
162 /* BCM5708C controllers and OEM boards. */
163 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037,
164 "HP NC373T PCIe Multifunction Gig Server Adapter" },
165 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038,
166 "HP NC373i Multifunction Gigabit Server Adapter" },
167 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045,
168 "HP NC374m PCIe Multifunction Adapter" },
169 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
170 "Broadcom NetXtreme II BCM5708 1000Base-T" },
172 /* BCM5708S controllers and OEM boards. */
173 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706,
174 "HP NC373m Multifunction Gigabit Server Adapter" },
175 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b,
176 "HP NC373i Multifunction Gigabit Server Adapter" },
177 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d,
178 "HP NC373F PCIe Multifunc Giga Server Adapter" },
179 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
180 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
182 /* BCM5709C controllers and OEM boards. */
183 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055,
184 "HP NC382i DP Multifunction Gigabit Server Adapter" },
185 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059,
186 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
187 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
188 "Broadcom NetXtreme II BCM5709 1000Base-T" },
190 /* BCM5709S controllers and OEM boards. */
191 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d,
192 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
193 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056,
194 "HP NC382i DP Multifunction Gigabit Server Adapter" },
195 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
196 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
198 /* BCM5716 controllers and OEM boards. */
199 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
200 "Broadcom NetXtreme II BCM5716 1000Base-T" },
206 /****************************************************************************/
207 /* Supported Flash NVRAM device data. */
208 /****************************************************************************/
209 static const struct flash_spec flash_table[] =
211 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
212 #define NONBUFFERED_FLAGS (BCE_NV_WREN)
215 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
216 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
217 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
219 /* Expansion entry 0001 */
220 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
221 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
222 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
224 /* Saifun SA25F010 (non-buffered flash) */
225 /* strap, cfg1, & write1 need updates */
226 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
227 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
228 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
229 "Non-buffered flash (128kB)"},
230 /* Saifun SA25F020 (non-buffered flash) */
231 /* strap, cfg1, & write1 need updates */
232 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
233 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
234 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
235 "Non-buffered flash (256kB)"},
236 /* Expansion entry 0100 */
237 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
238 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
239 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
241 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
242 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
243 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
244 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
245 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
246 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
247 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
248 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
249 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
250 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
251 /* Saifun SA25F005 (non-buffered flash) */
252 /* strap, cfg1, & write1 need updates */
253 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
254 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
255 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
256 "Non-buffered flash (64kB)"},
258 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
259 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
260 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
262 /* Expansion entry 1001 */
263 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
264 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
265 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
267 /* Expansion entry 1010 */
268 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
269 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
270 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
272 /* ATMEL AT45DB011B (buffered flash) */
273 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
274 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
275 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
276 "Buffered flash (128kB)"},
277 /* Expansion entry 1100 */
278 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
279 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
280 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
282 /* Expansion entry 1101 */
283 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
284 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
285 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
287 /* Ateml Expansion entry 1110 */
288 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
289 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
290 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
291 "Entry 1110 (Atmel)"},
292 /* ATMEL AT45DB021B (buffered flash) */
293 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
294 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
295 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
296 "Buffered flash (256kB)"},
300 * The BCM5709 controllers transparently handle the
301 * differences between Atmel 264 byte pages and all
302 * flash devices which use 256 byte pages, so no
303 * logical-to-physical mapping is required in the
306 static struct flash_spec flash_5709 = {
307 .flags = BCE_NV_BUFFERED,
308 .page_bits = BCM5709_FLASH_PAGE_BITS,
309 .page_size = BCM5709_FLASH_PAGE_SIZE,
310 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
311 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
312 .name = "5709/5716 buffered flash (256kB)",
316 /****************************************************************************/
317 /* DragonFly device entry points. */
318 /****************************************************************************/
319 static int bce_probe(device_t);
320 static int bce_attach(device_t);
321 static int bce_detach(device_t);
322 static void bce_shutdown(device_t);
324 /****************************************************************************/
325 /* BCE Debug Data Structure Dump Routines */
326 /****************************************************************************/
328 static void bce_dump_mbuf(struct bce_softc *, struct mbuf *);
329 static void bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
330 static void bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
331 static void bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
332 static void bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
333 static void bce_dump_l2fhdr(struct bce_softc *, int,
334 struct l2_fhdr *) __unused;
335 static void bce_dump_tx_chain(struct bce_softc *, int, int);
336 static void bce_dump_rx_chain(struct bce_softc *, int, int);
337 static void bce_dump_status_block(struct bce_softc *);
338 static void bce_dump_driver_state(struct bce_softc *);
339 static void bce_dump_stats_block(struct bce_softc *) __unused;
340 static void bce_dump_hw_state(struct bce_softc *);
341 static void bce_dump_txp_state(struct bce_softc *);
342 static void bce_dump_rxp_state(struct bce_softc *) __unused;
343 static void bce_dump_tpat_state(struct bce_softc *) __unused;
344 static void bce_freeze_controller(struct bce_softc *) __unused;
345 static void bce_unfreeze_controller(struct bce_softc *) __unused;
346 static void bce_breakpoint(struct bce_softc *);
347 #endif /* BCE_DEBUG */
350 /****************************************************************************/
351 /* BCE Register/Memory Access Routines */
352 /****************************************************************************/
353 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
354 static void bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
355 static void bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
356 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
357 static void bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
358 static int bce_miibus_read_reg(device_t, int, int);
359 static int bce_miibus_write_reg(device_t, int, int, int);
360 static void bce_miibus_statchg(device_t);
363 /****************************************************************************/
364 /* BCE NVRAM Access Routines */
365 /****************************************************************************/
366 static int bce_acquire_nvram_lock(struct bce_softc *);
367 static int bce_release_nvram_lock(struct bce_softc *);
368 static void bce_enable_nvram_access(struct bce_softc *);
369 static void bce_disable_nvram_access(struct bce_softc *);
370 static int bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
372 static int bce_init_nvram(struct bce_softc *);
373 static int bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
374 static int bce_nvram_test(struct bce_softc *);
376 /****************************************************************************/
377 /* BCE DMA Allocate/Free Routines */
378 /****************************************************************************/
379 static int bce_dma_alloc(struct bce_softc *);
380 static void bce_dma_free(struct bce_softc *);
381 static void bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
383 /****************************************************************************/
384 /* BCE Firmware Synchronization and Load */
385 /****************************************************************************/
386 static int bce_fw_sync(struct bce_softc *, uint32_t);
387 static void bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
389 static void bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
391 static void bce_start_cpu(struct bce_softc *, struct cpu_reg *);
392 static void bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
393 static void bce_start_rxp_cpu(struct bce_softc *);
394 static void bce_init_rxp_cpu(struct bce_softc *);
395 static void bce_init_txp_cpu(struct bce_softc *);
396 static void bce_init_tpat_cpu(struct bce_softc *);
397 static void bce_init_cp_cpu(struct bce_softc *);
398 static void bce_init_com_cpu(struct bce_softc *);
399 static void bce_init_cpus(struct bce_softc *);
401 static void bce_stop(struct bce_softc *);
402 static int bce_reset(struct bce_softc *, uint32_t);
403 static int bce_chipinit(struct bce_softc *);
404 static int bce_blockinit(struct bce_softc *);
405 static int bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
407 static void bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
408 static void bce_probe_pci_caps(struct bce_softc *);
409 static void bce_print_adapter_info(struct bce_softc *);
410 static void bce_get_media(struct bce_softc *);
412 static void bce_init_tx_context(struct bce_softc *);
413 static int bce_init_tx_chain(struct bce_softc *);
414 static void bce_init_rx_context(struct bce_softc *);
415 static int bce_init_rx_chain(struct bce_softc *);
416 static void bce_free_rx_chain(struct bce_softc *);
417 static void bce_free_tx_chain(struct bce_softc *);
419 static int bce_encap(struct bce_softc *, struct mbuf **);
420 static void bce_start(struct ifnet *);
421 static int bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
422 static void bce_watchdog(struct ifnet *);
423 static int bce_ifmedia_upd(struct ifnet *);
424 static void bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
425 static void bce_init(void *);
426 static void bce_mgmt_init(struct bce_softc *);
428 static int bce_init_ctx(struct bce_softc *);
429 static void bce_get_mac_addr(struct bce_softc *);
430 static void bce_set_mac_addr(struct bce_softc *);
431 static void bce_phy_intr(struct bce_softc *);
432 static void bce_rx_intr(struct bce_softc *, int, uint16_t);
433 static void bce_tx_intr(struct bce_softc *, uint16_t);
434 static void bce_disable_intr(struct bce_softc *);
435 static void bce_enable_intr(struct bce_softc *);
436 static void bce_reenable_intr(struct bce_softc *);
438 #ifdef DEVICE_POLLING
439 static void bce_poll(struct ifnet *, enum poll_cmd, int);
441 static void bce_intr(struct bce_softc *);
442 static void bce_intr_legacy(void *);
443 static void bce_intr_msi(void *);
444 static void bce_intr_msi_oneshot(void *);
445 static void bce_set_rx_mode(struct bce_softc *);
446 static void bce_stats_update(struct bce_softc *);
447 static void bce_tick(void *);
448 static void bce_tick_serialized(struct bce_softc *);
449 static void bce_pulse(void *);
450 static void bce_pulse_check_msi(struct bce_softc *);
451 static void bce_add_sysctls(struct bce_softc *);
453 static void bce_coal_change(struct bce_softc *);
454 static int bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
455 static int bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
456 static int bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
457 static int bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
458 static int bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
459 static int bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
460 static int bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
461 static int bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
462 static int bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
463 uint32_t *, uint32_t);
467 * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023. Linux's bnx2
468 * takes 1023 as the TX ticks limit. However, using 1023 will
469 * cause 5708(B2) to generate extra interrupts (~2000/s) even when
470 * there is _no_ network activity on the NIC.
472 static uint32_t bce_tx_bds_int = 255; /* bcm: 20 */
473 static uint32_t bce_tx_bds = 255; /* bcm: 20 */
474 static uint32_t bce_tx_ticks_int = 1022; /* bcm: 80 */
475 static uint32_t bce_tx_ticks = 1022; /* bcm: 80 */
476 static uint32_t bce_rx_bds_int = 128; /* bcm: 6 */
477 static uint32_t bce_rx_bds = 128; /* bcm: 6 */
478 static uint32_t bce_rx_ticks_int = 150; /* bcm: 18 */
479 static uint32_t bce_rx_ticks = 150; /* bcm: 18 */
481 static int bce_msi_enable = 1;
483 static int bce_rx_pages = RX_PAGES_DEFAULT;
484 static int bce_tx_pages = TX_PAGES_DEFAULT;
486 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
487 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
488 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
489 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
490 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
491 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
492 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
493 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
494 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
495 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
496 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
498 /****************************************************************************/
499 /* DragonFly device dispatch table. */
500 /****************************************************************************/
501 static device_method_t bce_methods[] = {
502 /* Device interface */
503 DEVMETHOD(device_probe, bce_probe),
504 DEVMETHOD(device_attach, bce_attach),
505 DEVMETHOD(device_detach, bce_detach),
506 DEVMETHOD(device_shutdown, bce_shutdown),
509 DEVMETHOD(bus_print_child, bus_generic_print_child),
510 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
513 DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
514 DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
515 DEVMETHOD(miibus_statchg, bce_miibus_statchg),
520 static driver_t bce_driver = {
523 sizeof(struct bce_softc)
526 static devclass_t bce_devclass;
529 DECLARE_DUMMY_MODULE(if_bce);
530 MODULE_DEPEND(bce, miibus, 1, 1, 1);
531 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
532 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
535 /****************************************************************************/
536 /* Device probe function. */
538 /* Compares the device to the driver's list of supported devices and */
539 /* reports back to the OS whether this is the right driver for the device. */
542 /* BUS_PROBE_DEFAULT on success, positive value on failure. */
543 /****************************************************************************/
545 bce_probe(device_t dev)
548 uint16_t vid, did, svid, sdid;
550 /* Get the data for the device to be probed. */
551 vid = pci_get_vendor(dev);
552 did = pci_get_device(dev);
553 svid = pci_get_subvendor(dev);
554 sdid = pci_get_subdevice(dev);
556 /* Look through the list of known devices for a match. */
557 for (t = bce_devs; t->bce_name != NULL; ++t) {
558 if (vid == t->bce_vid && did == t->bce_did &&
559 (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
560 (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
561 uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
564 descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
566 /* Print out the device identity. */
567 ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
569 ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
571 device_set_desc_copy(dev, descbuf);
572 kfree(descbuf, M_TEMP);
580 /****************************************************************************/
581 /* PCI Capabilities Probe Function. */
583 /* Walks the PCI capabiites list for the device to find what features are */
588 /****************************************************************************/
590 bce_print_adapter_info(struct bce_softc *sc)
592 device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
594 kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
595 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
598 if (sc->bce_flags & BCE_PCIE_FLAG) {
599 kprintf("Bus (PCIe x%d, ", sc->link_width);
600 switch (sc->link_speed) {
602 kprintf("2.5Gbps); ");
608 kprintf("Unknown link speed); ");
612 kprintf("Bus (PCI%s, %s, %dMHz); ",
613 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
614 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
618 /* Firmware version and device features. */
619 kprintf("B/C (%s)", sc->bce_bc_ver);
621 if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
622 (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
624 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
625 kprintf("MFW[%s]", sc->bce_mfw_ver);
626 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
634 /****************************************************************************/
635 /* PCI Capabilities Probe Function. */
637 /* Walks the PCI capabiites list for the device to find what features are */
642 /****************************************************************************/
644 bce_probe_pci_caps(struct bce_softc *sc)
646 device_t dev = sc->bce_dev;
649 if (pci_is_pcix(dev))
650 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
652 ptr = pci_get_pciecap_ptr(dev);
654 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
656 sc->link_speed = link_status & 0xf;
657 sc->link_width = (link_status >> 4) & 0x3f;
658 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
659 sc->bce_flags |= BCE_PCIE_FLAG;
664 /****************************************************************************/
665 /* Device attach function. */
667 /* Allocates device resources, performs secondary chip identification, */
668 /* resets and initializes the hardware, and initializes driver instance */
672 /* 0 on success, positive value on failure. */
673 /****************************************************************************/
675 bce_attach(device_t dev)
677 struct bce_softc *sc = device_get_softc(dev);
678 struct ifnet *ifp = &sc->arpcom.ac_if;
681 void (*irq_handle)(void *);
684 struct mii_probe_args mii_args;
685 uintptr_t mii_priv = 0;
688 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
690 pci_enable_busmaster(dev);
692 bce_probe_pci_caps(sc);
694 /* Allocate PCI memory resources. */
696 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
697 RF_ACTIVE | PCI_RF_DENSE);
698 if (sc->bce_res_mem == NULL) {
699 device_printf(dev, "PCI memory allocation failed\n");
702 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
703 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
705 /* Allocate PCI IRQ resources. */
706 sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
707 &sc->bce_irq_rid, &irq_flags);
709 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
710 &sc->bce_irq_rid, irq_flags);
711 if (sc->bce_res_irq == NULL) {
712 device_printf(dev, "PCI map interrupt failed\n");
718 * Configure byte swap and enable indirect register access.
719 * Rely on CPU to do target byte swapping on big endian systems.
720 * Access to registers outside of PCI configurtion space are not
721 * valid until this is done.
723 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
724 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
725 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
727 /* Save ASIC revsion info. */
728 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
730 /* Weed out any non-production controller revisions. */
731 switch (BCE_CHIP_ID(sc)) {
732 case BCE_CHIP_ID_5706_A0:
733 case BCE_CHIP_ID_5706_A1:
734 case BCE_CHIP_ID_5708_A0:
735 case BCE_CHIP_ID_5708_B0:
736 case BCE_CHIP_ID_5709_A0:
737 case BCE_CHIP_ID_5709_B0:
738 case BCE_CHIP_ID_5709_B1:
740 /* 5709C B2 seems to work fine */
741 case BCE_CHIP_ID_5709_B2:
743 device_printf(dev, "Unsupported chip id 0x%08x!\n",
749 mii_priv |= BRGPHY_FLAG_WIRESPEED;
750 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
751 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax ||
752 BCE_CHIP_REV(sc) == BCE_CHIP_REV_Bx)
753 mii_priv |= BRGPHY_FLAG_NO_EARLYDAC;
755 mii_priv |= BRGPHY_FLAG_BER_BUG;
758 if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
759 irq_handle = bce_intr_legacy;
760 } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
761 irq_handle = bce_intr_msi;
762 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
763 irq_handle = bce_intr_msi_oneshot;
764 sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
767 panic("%s: unsupported intr type %d",
768 device_get_nameunit(dev), sc->bce_irq_type);
772 * Find the base address for shared memory access.
773 * Newer versions of bootcode use a signature and offset
774 * while older versions use a fixed address.
776 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
777 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
778 BCE_SHM_HDR_SIGNATURE_SIG) {
779 /* Multi-port devices use different offsets in shared memory. */
780 sc->bce_shmem_base = REG_RD_IND(sc,
781 BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
783 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
785 DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
787 /* Fetch the bootcode revision. */
788 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
789 for (i = 0, j = 0; i < 3; i++) {
793 num = (uint8_t)(val >> (24 - (i * 8)));
794 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
795 if (num >= k || !skip0 || k == 1) {
796 sc->bce_bc_ver[j++] = (num / k) + '0';
801 sc->bce_bc_ver[j++] = '.';
804 /* Check if any management firwmare is running. */
805 val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
806 if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
807 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
809 /* Allow time for firmware to enter the running state. */
810 for (i = 0; i < 30; i++) {
811 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
812 if (val & BCE_CONDITION_MFW_RUN_MASK)
818 /* Check the current bootcode state. */
819 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
820 BCE_CONDITION_MFW_RUN_MASK;
821 if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
822 val != BCE_CONDITION_MFW_RUN_NONE) {
823 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
825 for (i = 0, j = 0; j < 3; j++) {
826 val = bce_reg_rd_ind(sc, addr + j * 4);
828 memcpy(&sc->bce_mfw_ver[i], &val, 4);
833 /* Get PCI bus information (speed and type). */
834 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
835 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
838 sc->bce_flags |= BCE_PCIX_FLAG;
840 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
841 BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
843 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
844 sc->bus_speed_mhz = 133;
847 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
848 sc->bus_speed_mhz = 100;
851 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
852 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
853 sc->bus_speed_mhz = 66;
856 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
857 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
858 sc->bus_speed_mhz = 50;
861 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
862 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
863 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
864 sc->bus_speed_mhz = 33;
868 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
869 sc->bus_speed_mhz = 66;
871 sc->bus_speed_mhz = 33;
874 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
875 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
877 /* Reset the controller. */
878 rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
882 /* Initialize the controller. */
883 rc = bce_chipinit(sc);
885 device_printf(dev, "Controller initialization failed!\n");
889 /* Perform NVRAM test. */
890 rc = bce_nvram_test(sc);
892 device_printf(dev, "NVRAM test failed!\n");
896 /* Fetch the permanent Ethernet MAC address. */
897 bce_get_mac_addr(sc);
900 * Trip points control how many BDs
901 * should be ready before generating an
902 * interrupt while ticks control how long
903 * a BD can sit in the chain before
904 * generating an interrupt. Set the default
905 * values for the RX and TX rings.
909 /* Force more frequent interrupts. */
910 sc->bce_tx_quick_cons_trip_int = 1;
911 sc->bce_tx_quick_cons_trip = 1;
912 sc->bce_tx_ticks_int = 0;
913 sc->bce_tx_ticks = 0;
915 sc->bce_rx_quick_cons_trip_int = 1;
916 sc->bce_rx_quick_cons_trip = 1;
917 sc->bce_rx_ticks_int = 0;
918 sc->bce_rx_ticks = 0;
920 sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
921 sc->bce_tx_quick_cons_trip = bce_tx_bds;
922 sc->bce_tx_ticks_int = bce_tx_ticks_int;
923 sc->bce_tx_ticks = bce_tx_ticks;
925 sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
926 sc->bce_rx_quick_cons_trip = bce_rx_bds;
927 sc->bce_rx_ticks_int = bce_rx_ticks_int;
928 sc->bce_rx_ticks = bce_rx_ticks;
931 /* Update statistics once every second. */
932 sc->bce_stats_ticks = 1000000 & 0xffff00;
934 /* Find the media type for the adapter. */
937 /* Allocate DMA memory resources. */
938 rc = bce_dma_alloc(sc);
940 device_printf(dev, "DMA resource allocation failed!\n");
944 /* Initialize the ifnet interface. */
946 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
947 ifp->if_ioctl = bce_ioctl;
948 ifp->if_start = bce_start;
949 ifp->if_init = bce_init;
950 ifp->if_watchdog = bce_watchdog;
951 #ifdef DEVICE_POLLING
952 ifp->if_poll = bce_poll;
954 ifp->if_mtu = ETHERMTU;
955 ifp->if_hwassist = BCE_IF_HWASSIST;
956 ifp->if_capabilities = BCE_IF_CAPABILITIES;
957 ifp->if_capenable = ifp->if_capabilities;
958 ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD(sc));
959 ifq_set_ready(&ifp->if_snd);
961 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
962 ifp->if_baudrate = IF_Gbps(2.5);
964 ifp->if_baudrate = IF_Gbps(1);
966 /* Assume a standard 1500 byte MTU size for mbuf allocations. */
967 sc->mbuf_alloc_size = MCLBYTES;
972 mii_probe_args_init(&mii_args, bce_ifmedia_upd, bce_ifmedia_sts);
973 mii_args.mii_probemask = 1 << sc->bce_phy_addr;
974 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
975 mii_args.mii_priv = mii_priv;
977 rc = mii_probe(dev, &sc->bce_miibus, &mii_args);
979 device_printf(dev, "PHY probe failed!\n");
983 /* Attach to the Ethernet interface list. */
984 ether_ifattach(ifp, sc->eaddr, NULL);
986 callout_init_mp(&sc->bce_tick_callout);
987 callout_init_mp(&sc->bce_pulse_callout);
989 /* Hookup IRQ last. */
990 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
991 &sc->bce_intrhand, ifp->if_serializer);
993 device_printf(dev, "Failed to setup IRQ!\n");
998 ifp->if_cpuid = rman_get_cpuid(sc->bce_res_irq);
999 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1001 /* Print some important debugging info. */
1002 DBRUN(BCE_INFO, bce_dump_driver_state(sc));
1004 /* Add the supported sysctls to the kernel. */
1005 bce_add_sysctls(sc);
1008 * The chip reset earlier notified the bootcode that
1009 * a driver is present. We now need to start our pulse
1010 * routine so that the bootcode is reminded that we're
1015 /* Get the firmware running so IPMI still works */
1019 bce_print_adapter_info(sc);
1028 /****************************************************************************/
1029 /* Device detach function. */
1031 /* Stops the controller, resets the controller, and releases resources. */
1034 /* 0 on success, positive value on failure. */
1035 /****************************************************************************/
1037 bce_detach(device_t dev)
1039 struct bce_softc *sc = device_get_softc(dev);
1041 if (device_is_attached(dev)) {
1042 struct ifnet *ifp = &sc->arpcom.ac_if;
1045 /* Stop and reset the controller. */
1046 lwkt_serialize_enter(ifp->if_serializer);
1047 callout_stop(&sc->bce_pulse_callout);
1049 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1050 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1052 msg = BCE_DRV_MSG_CODE_UNLOAD;
1054 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1055 lwkt_serialize_exit(ifp->if_serializer);
1057 ether_ifdetach(ifp);
1060 /* If we have a child device on the MII bus remove it too. */
1062 device_delete_child(dev, sc->bce_miibus);
1063 bus_generic_detach(dev);
1065 if (sc->bce_res_irq != NULL) {
1066 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1070 if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1071 pci_release_msi(dev);
1073 if (sc->bce_res_mem != NULL) {
1074 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1080 if (sc->bce_sysctl_tree != NULL)
1081 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1087 /****************************************************************************/
1088 /* Device shutdown function. */
1090 /* Stops and resets the controller. */
1094 /****************************************************************************/
1096 bce_shutdown(device_t dev)
1098 struct bce_softc *sc = device_get_softc(dev);
1099 struct ifnet *ifp = &sc->arpcom.ac_if;
1102 lwkt_serialize_enter(ifp->if_serializer);
1104 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1105 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1107 msg = BCE_DRV_MSG_CODE_UNLOAD;
1109 lwkt_serialize_exit(ifp->if_serializer);
1113 /****************************************************************************/
1114 /* Indirect register read. */
1116 /* Reads NetXtreme II registers using an index/data register pair in PCI */
1117 /* configuration space. Using this mechanism avoids issues with posted */
1118 /* reads but is much slower than memory-mapped I/O. */
1121 /* The value of the register. */
1122 /****************************************************************************/
1124 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1126 device_t dev = sc->bce_dev;
1128 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1132 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1133 DBPRINT(sc, BCE_EXCESSIVE,
1134 "%s(); offset = 0x%08X, val = 0x%08X\n",
1135 __func__, offset, val);
1139 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1144 /****************************************************************************/
1145 /* Indirect register write. */
1147 /* Writes NetXtreme II registers using an index/data register pair in PCI */
1148 /* configuration space. Using this mechanism avoids issues with posted */
1149 /* writes but is muchh slower than memory-mapped I/O. */
1153 /****************************************************************************/
1155 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1157 device_t dev = sc->bce_dev;
1159 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1160 __func__, offset, val);
1162 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1163 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1167 /****************************************************************************/
1168 /* Shared memory write. */
1170 /* Writes NetXtreme II shared memory region. */
1174 /****************************************************************************/
1176 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1178 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1182 /****************************************************************************/
1183 /* Shared memory read. */
1185 /* Reads NetXtreme II shared memory region. */
1188 /* The 32 bit value read. */
1189 /****************************************************************************/
1191 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1193 return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1197 /****************************************************************************/
1198 /* Context memory write. */
1200 /* The NetXtreme II controller uses context memory to track connection */
1201 /* information for L2 and higher network protocols. */
1205 /****************************************************************************/
1207 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1210 uint32_t idx, offset = ctx_offset + cid_addr;
1211 uint32_t val, retry_cnt = 5;
1213 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1214 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1215 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1216 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1218 for (idx = 0; idx < retry_cnt; idx++) {
1219 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1220 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1225 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1226 device_printf(sc->bce_dev,
1227 "Unable to write CTX memory: "
1228 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1229 cid_addr, ctx_offset);
1232 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1233 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1238 /****************************************************************************/
1239 /* PHY register read. */
1241 /* Implements register reads on the MII bus. */
1244 /* The value of the register. */
1245 /****************************************************************************/
1247 bce_miibus_read_reg(device_t dev, int phy, int reg)
1249 struct bce_softc *sc = device_get_softc(dev);
1253 /* Make sure we are accessing the correct PHY address. */
1254 KASSERT(phy == sc->bce_phy_addr,
1255 ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1257 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1258 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1259 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1261 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1262 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1267 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1268 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1269 BCE_EMAC_MDIO_COMM_START_BUSY;
1270 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1272 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1275 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1276 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1279 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1280 val &= BCE_EMAC_MDIO_COMM_DATA;
1285 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1286 if_printf(&sc->arpcom.ac_if,
1287 "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1291 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1294 DBPRINT(sc, BCE_EXCESSIVE,
1295 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1296 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1298 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1299 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1300 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1302 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1303 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1307 return (val & 0xffff);
1311 /****************************************************************************/
1312 /* PHY register write. */
1314 /* Implements register writes on the MII bus. */
1317 /* The value of the register. */
1318 /****************************************************************************/
1320 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1322 struct bce_softc *sc = device_get_softc(dev);
1326 /* Make sure we are accessing the correct PHY address. */
1327 KASSERT(phy == sc->bce_phy_addr,
1328 ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1330 DBPRINT(sc, BCE_EXCESSIVE,
1331 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1332 __func__, phy, (uint16_t)(reg & 0xffff),
1333 (uint16_t)(val & 0xffff));
1335 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1336 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1337 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1339 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1340 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1345 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1346 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1347 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1348 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1350 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1353 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1354 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1360 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1361 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1363 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1364 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1365 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1367 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1368 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1376 /****************************************************************************/
1377 /* MII bus status change. */
1379 /* Called by the MII bus driver when the PHY establishes link to set the */
1380 /* MAC interface registers. */
1384 /****************************************************************************/
1386 bce_miibus_statchg(device_t dev)
1388 struct bce_softc *sc = device_get_softc(dev);
1389 struct mii_data *mii = device_get_softc(sc->bce_miibus);
1391 DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1392 mii->mii_media_active);
1395 /* Decode the interface media flags. */
1396 if_printf(&sc->arpcom.ac_if, "Media: ( ");
1397 switch(IFM_TYPE(mii->mii_media_active)) {
1399 kprintf("Ethernet )");
1402 kprintf("Unknown )");
1406 kprintf(" Media Options: ( ");
1407 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1409 kprintf("Autoselect )");
1412 kprintf("Manual )");
1418 kprintf("10Base-T )");
1421 kprintf("100Base-TX )");
1424 kprintf("1000Base-SX )");
1427 kprintf("1000Base-T )");
1434 kprintf(" Global Options: (");
1435 if (mii->mii_media_active & IFM_FDX)
1436 kprintf(" FullDuplex");
1437 if (mii->mii_media_active & IFM_HDX)
1438 kprintf(" HalfDuplex");
1439 if (mii->mii_media_active & IFM_LOOP)
1440 kprintf(" Loopback");
1441 if (mii->mii_media_active & IFM_FLAG0)
1443 if (mii->mii_media_active & IFM_FLAG1)
1445 if (mii->mii_media_active & IFM_FLAG2)
1450 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1453 * Set MII or GMII interface based on the speed negotiated
1456 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1457 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1458 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1459 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1461 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1462 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1466 * Set half or full duplex based on the duplicity negotiated
1469 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1470 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1471 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1473 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1474 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1479 /****************************************************************************/
1480 /* Acquire NVRAM lock. */
1482 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
1483 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1484 /* for use by the driver. */
1487 /* 0 on success, positive value on failure. */
1488 /****************************************************************************/
1490 bce_acquire_nvram_lock(struct bce_softc *sc)
1495 DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1497 /* Request access to the flash interface. */
1498 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1499 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1500 val = REG_RD(sc, BCE_NVM_SW_ARB);
1501 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1507 if (j >= NVRAM_TIMEOUT_COUNT) {
1508 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1515 /****************************************************************************/
1516 /* Release NVRAM lock. */
1518 /* When the caller is finished accessing NVRAM the lock must be released. */
1519 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1520 /* for use by the driver. */
1523 /* 0 on success, positive value on failure. */
1524 /****************************************************************************/
1526 bce_release_nvram_lock(struct bce_softc *sc)
1531 DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1534 * Relinquish nvram interface.
1536 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1538 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1539 val = REG_RD(sc, BCE_NVM_SW_ARB);
1540 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1546 if (j >= NVRAM_TIMEOUT_COUNT) {
1547 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1554 /****************************************************************************/
1555 /* Enable NVRAM access. */
1557 /* Before accessing NVRAM for read or write operations the caller must */
1558 /* enabled NVRAM access. */
1562 /****************************************************************************/
1564 bce_enable_nvram_access(struct bce_softc *sc)
1568 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1570 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1571 /* Enable both bits, even on read. */
1572 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1573 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1577 /****************************************************************************/
1578 /* Disable NVRAM access. */
1580 /* When the caller is finished accessing NVRAM access must be disabled. */
1584 /****************************************************************************/
1586 bce_disable_nvram_access(struct bce_softc *sc)
1590 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1592 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1594 /* Disable both bits, even after read. */
1595 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1596 val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1600 /****************************************************************************/
1601 /* Read a dword (32 bits) from NVRAM. */
1603 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */
1604 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */
1607 /* 0 on success and the 32 bit value read, positive value on failure. */
1608 /****************************************************************************/
1610 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1616 /* Build the command word. */
1617 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1619 /* Calculate the offset for buffered flash. */
1620 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1621 offset = ((offset / sc->bce_flash_info->page_size) <<
1622 sc->bce_flash_info->page_bits) +
1623 (offset % sc->bce_flash_info->page_size);
1627 * Clear the DONE bit separately, set the address to read,
1628 * and issue the read.
1630 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1631 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1632 REG_WR(sc, BCE_NVM_COMMAND, cmd);
1634 /* Wait for completion. */
1635 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1640 val = REG_RD(sc, BCE_NVM_COMMAND);
1641 if (val & BCE_NVM_COMMAND_DONE) {
1642 val = REG_RD(sc, BCE_NVM_READ);
1645 memcpy(ret_val, &val, 4);
1650 /* Check for errors. */
1651 if (i >= NVRAM_TIMEOUT_COUNT) {
1652 if_printf(&sc->arpcom.ac_if,
1653 "Timeout error reading NVRAM at offset 0x%08X!\n",
1661 /****************************************************************************/
1662 /* Initialize NVRAM access. */
1664 /* Identify the NVRAM device in use and prepare the NVRAM interface to */
1665 /* access that device. */
1668 /* 0 on success, positive value on failure. */
1669 /****************************************************************************/
1671 bce_init_nvram(struct bce_softc *sc)
1674 int j, entry_count, rc = 0;
1675 const struct flash_spec *flash;
1677 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1679 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1680 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1681 sc->bce_flash_info = &flash_5709;
1682 goto bce_init_nvram_get_flash_size;
1685 /* Determine the selected interface. */
1686 val = REG_RD(sc, BCE_NVM_CFG1);
1688 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1691 * Flash reconfiguration is required to support additional
1692 * NVRAM devices not directly supported in hardware.
1693 * Check if the flash interface was reconfigured
1697 if (val & 0x40000000) {
1698 /* Flash interface reconfigured by bootcode. */
1700 DBPRINT(sc, BCE_INFO_LOAD,
1701 "%s(): Flash WAS reconfigured.\n", __func__);
1703 for (j = 0, flash = flash_table; j < entry_count;
1705 if ((val & FLASH_BACKUP_STRAP_MASK) ==
1706 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1707 sc->bce_flash_info = flash;
1712 /* Flash interface not yet reconfigured. */
1715 DBPRINT(sc, BCE_INFO_LOAD,
1716 "%s(): Flash was NOT reconfigured.\n", __func__);
1718 if (val & (1 << 23))
1719 mask = FLASH_BACKUP_STRAP_MASK;
1721 mask = FLASH_STRAP_MASK;
1723 /* Look for the matching NVRAM device configuration data. */
1724 for (j = 0, flash = flash_table; j < entry_count;
1726 /* Check if the device matches any of the known devices. */
1727 if ((val & mask) == (flash->strapping & mask)) {
1728 /* Found a device match. */
1729 sc->bce_flash_info = flash;
1731 /* Request access to the flash interface. */
1732 rc = bce_acquire_nvram_lock(sc);
1736 /* Reconfigure the flash interface. */
1737 bce_enable_nvram_access(sc);
1738 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1739 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1740 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1741 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1742 bce_disable_nvram_access(sc);
1743 bce_release_nvram_lock(sc);
1749 /* Check if a matching device was found. */
1750 if (j == entry_count) {
1751 sc->bce_flash_info = NULL;
1752 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1756 bce_init_nvram_get_flash_size:
1757 /* Write the flash config data to the shared memory interface. */
1758 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1759 BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1761 sc->bce_flash_size = val;
1763 sc->bce_flash_size = sc->bce_flash_info->total_size;
1765 DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1766 __func__, sc->bce_flash_info->total_size);
1768 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1774 /****************************************************************************/
1775 /* Read an arbitrary range of data from NVRAM. */
1777 /* Prepares the NVRAM interface for access and reads the requested data */
1778 /* into the supplied buffer. */
1781 /* 0 on success and the data read, positive value on failure. */
1782 /****************************************************************************/
1784 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1787 uint32_t cmd_flags, offset32, len32, extra;
1793 /* Request access to the flash interface. */
1794 rc = bce_acquire_nvram_lock(sc);
1798 /* Enable access to flash interface */
1799 bce_enable_nvram_access(sc);
1807 /* XXX should we release nvram lock if read_dword() fails? */
1813 pre_len = 4 - (offset & 3);
1815 if (pre_len >= len32) {
1817 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1819 cmd_flags = BCE_NVM_COMMAND_FIRST;
1822 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1826 memcpy(ret_buf, buf + (offset & 3), pre_len);
1834 extra = 4 - (len32 & 3);
1835 len32 = (len32 + 4) & ~3;
1842 cmd_flags = BCE_NVM_COMMAND_LAST;
1844 cmd_flags = BCE_NVM_COMMAND_FIRST |
1845 BCE_NVM_COMMAND_LAST;
1847 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1849 memcpy(ret_buf, buf, 4 - extra);
1850 } else if (len32 > 0) {
1853 /* Read the first word. */
1857 cmd_flags = BCE_NVM_COMMAND_FIRST;
1859 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1861 /* Advance to the next dword. */
1866 while (len32 > 4 && rc == 0) {
1867 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1869 /* Advance to the next dword. */
1876 goto bce_nvram_read_locked_exit;
1878 cmd_flags = BCE_NVM_COMMAND_LAST;
1879 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1881 memcpy(ret_buf, buf, 4 - extra);
1884 bce_nvram_read_locked_exit:
1885 /* Disable access to flash interface and release the lock. */
1886 bce_disable_nvram_access(sc);
1887 bce_release_nvram_lock(sc);
1893 /****************************************************************************/
1894 /* Verifies that NVRAM is accessible and contains valid data. */
1896 /* Reads the configuration data from NVRAM and verifies that the CRC is */
1900 /* 0 on success, positive value on failure. */
1901 /****************************************************************************/
1903 bce_nvram_test(struct bce_softc *sc)
1905 uint32_t buf[BCE_NVRAM_SIZE / 4];
1906 uint32_t magic, csum;
1907 uint8_t *data = (uint8_t *)buf;
1911 * Check that the device NVRAM is valid by reading
1912 * the magic value at offset 0.
1914 rc = bce_nvram_read(sc, 0, data, 4);
1918 magic = be32toh(buf[0]);
1919 if (magic != BCE_NVRAM_MAGIC) {
1920 if_printf(&sc->arpcom.ac_if,
1921 "Invalid NVRAM magic value! Expected: 0x%08X, "
1922 "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1927 * Verify that the device NVRAM includes valid
1928 * configuration data.
1930 rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1934 csum = ether_crc32_le(data, 0x100);
1935 if (csum != BCE_CRC32_RESIDUAL) {
1936 if_printf(&sc->arpcom.ac_if,
1937 "Invalid Manufacturing Information NVRAM CRC! "
1938 "Expected: 0x%08X, Found: 0x%08X\n",
1939 BCE_CRC32_RESIDUAL, csum);
1943 csum = ether_crc32_le(data + 0x100, 0x100);
1944 if (csum != BCE_CRC32_RESIDUAL) {
1945 if_printf(&sc->arpcom.ac_if,
1946 "Invalid Feature Configuration Information "
1947 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1948 BCE_CRC32_RESIDUAL, csum);
1955 /****************************************************************************/
1956 /* Identifies the current media type of the controller and sets the PHY */
1961 /****************************************************************************/
1963 bce_get_media(struct bce_softc *sc)
1967 sc->bce_phy_addr = 1;
1969 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1970 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1971 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1972 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1976 * The BCM5709S is software configurable
1977 * for Copper or SerDes operation.
1979 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1981 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1982 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1986 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1987 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1990 (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1993 if (pci_get_function(sc->bce_dev) == 0) {
1998 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2006 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2010 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
2011 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2014 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
2015 sc->bce_flags |= BCE_NO_WOL_FLAG;
2016 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2017 sc->bce_phy_addr = 2;
2018 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2019 if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2020 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2022 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2023 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2024 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2029 /****************************************************************************/
2030 /* Free any DMA memory owned by the driver. */
2032 /* Scans through each data structre that requires DMA memory and frees */
2033 /* the memory if allocated. */
2037 /****************************************************************************/
2039 bce_dma_free(struct bce_softc *sc)
2043 /* Destroy the status block. */
2044 if (sc->status_tag != NULL) {
2045 if (sc->status_block != NULL) {
2046 bus_dmamap_unload(sc->status_tag, sc->status_map);
2047 bus_dmamem_free(sc->status_tag, sc->status_block,
2050 bus_dma_tag_destroy(sc->status_tag);
2053 /* Destroy the statistics block. */
2054 if (sc->stats_tag != NULL) {
2055 if (sc->stats_block != NULL) {
2056 bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2057 bus_dmamem_free(sc->stats_tag, sc->stats_block,
2060 bus_dma_tag_destroy(sc->stats_tag);
2063 /* Destroy the CTX DMA stuffs. */
2064 if (sc->ctx_tag != NULL) {
2065 for (i = 0; i < sc->ctx_pages; i++) {
2066 if (sc->ctx_block[i] != NULL) {
2067 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2068 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2072 bus_dma_tag_destroy(sc->ctx_tag);
2075 /* Destroy the TX buffer descriptor DMA stuffs. */
2076 if (sc->tx_bd_chain_tag != NULL) {
2077 for (i = 0; i < sc->tx_pages; i++) {
2078 if (sc->tx_bd_chain[i] != NULL) {
2079 bus_dmamap_unload(sc->tx_bd_chain_tag,
2080 sc->tx_bd_chain_map[i]);
2081 bus_dmamem_free(sc->tx_bd_chain_tag,
2083 sc->tx_bd_chain_map[i]);
2086 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2089 /* Destroy the RX buffer descriptor DMA stuffs. */
2090 if (sc->rx_bd_chain_tag != NULL) {
2091 for (i = 0; i < sc->rx_pages; i++) {
2092 if (sc->rx_bd_chain[i] != NULL) {
2093 bus_dmamap_unload(sc->rx_bd_chain_tag,
2094 sc->rx_bd_chain_map[i]);
2095 bus_dmamem_free(sc->rx_bd_chain_tag,
2097 sc->rx_bd_chain_map[i]);
2100 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2103 /* Destroy the TX mbuf DMA stuffs. */
2104 if (sc->tx_mbuf_tag != NULL) {
2105 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2106 /* Must have been unloaded in bce_stop() */
2107 KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2108 bus_dmamap_destroy(sc->tx_mbuf_tag,
2109 sc->tx_mbuf_map[i]);
2111 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2114 /* Destroy the RX mbuf DMA stuffs. */
2115 if (sc->rx_mbuf_tag != NULL) {
2116 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2117 /* Must have been unloaded in bce_stop() */
2118 KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2119 bus_dmamap_destroy(sc->rx_mbuf_tag,
2120 sc->rx_mbuf_map[i]);
2122 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2123 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2126 /* Destroy the parent tag */
2127 if (sc->parent_tag != NULL)
2128 bus_dma_tag_destroy(sc->parent_tag);
2130 if (sc->tx_bd_chain_map != NULL)
2131 kfree(sc->tx_bd_chain_map, M_DEVBUF);
2132 if (sc->tx_bd_chain != NULL)
2133 kfree(sc->tx_bd_chain, M_DEVBUF);
2134 if (sc->tx_bd_chain_paddr != NULL)
2135 kfree(sc->tx_bd_chain_paddr, M_DEVBUF);
2137 if (sc->rx_bd_chain_map != NULL)
2138 kfree(sc->rx_bd_chain_map, M_DEVBUF);
2139 if (sc->rx_bd_chain != NULL)
2140 kfree(sc->rx_bd_chain, M_DEVBUF);
2141 if (sc->rx_bd_chain_paddr != NULL)
2142 kfree(sc->rx_bd_chain_paddr, M_DEVBUF);
2144 if (sc->tx_mbuf_map != NULL)
2145 kfree(sc->tx_mbuf_map, M_DEVBUF);
2146 if (sc->tx_mbuf_ptr != NULL)
2147 kfree(sc->tx_mbuf_ptr, M_DEVBUF);
2149 if (sc->rx_mbuf_map != NULL)
2150 kfree(sc->rx_mbuf_map, M_DEVBUF);
2151 if (sc->rx_mbuf_ptr != NULL)
2152 kfree(sc->rx_mbuf_ptr, M_DEVBUF);
2153 if (sc->rx_mbuf_paddr != NULL)
2154 kfree(sc->rx_mbuf_paddr, M_DEVBUF);
2158 /****************************************************************************/
2159 /* Get DMA memory from the OS. */
2161 /* Validates that the OS has provided DMA buffers in response to a */
2162 /* bus_dmamap_load() call and saves the physical address of those buffers. */
2163 /* When the callback is used the OS will return 0 for the mapping function */
2164 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
2165 /* failures back to the caller. */
2169 /****************************************************************************/
2171 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2173 bus_addr_t *busaddr = arg;
2176 * Simulate a mapping failure.
2179 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2180 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2181 __FILE__, __LINE__);
2184 /* Check for an error and signal the caller that an error occurred. */
2188 KASSERT(nseg == 1, ("only one segment is allowed"));
2189 *busaddr = segs->ds_addr;
2193 /****************************************************************************/
2194 /* Allocate any DMA memory needed by the driver. */
2196 /* Allocates DMA memory needed for the various global structures needed by */
2199 /* Memory alignment requirements: */
2200 /* -----------------+----------+----------+----------+----------+ */
2201 /* Data Structure | 5706 | 5708 | 5709 | 5716 | */
2202 /* -----------------+----------+----------+----------+----------+ */
2203 /* Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2204 /* Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2205 /* RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */
2206 /* PG Buffers | none | none | none | none | */
2207 /* TX Buffers | none | none | none | none | */
2208 /* Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */
2209 /* Context Pages(1) | N/A | N/A | 4KiB | 4KiB | */
2210 /* -----------------+----------+----------+----------+----------+ */
2212 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
2215 /* 0 for success, positive value for failure. */
2216 /****************************************************************************/
2218 bce_dma_alloc(struct bce_softc *sc)
2220 struct ifnet *ifp = &sc->arpcom.ac_if;
2221 int i, j, rc = 0, pages;
2222 bus_addr_t busaddr, max_busaddr;
2223 bus_size_t status_align, stats_align;
2225 pages = device_getenv_int(sc->bce_dev, "rx_pages", bce_rx_pages);
2226 if (pages <= 0 || pages > RX_PAGES_MAX || !powerof2(pages)) {
2227 device_printf(sc->bce_dev, "invalid # of RX pages\n");
2228 pages = RX_PAGES_DEFAULT;
2230 sc->rx_pages = pages;
2232 pages = device_getenv_int(sc->bce_dev, "tx_pages", bce_tx_pages);
2233 if (pages <= 0 || pages > TX_PAGES_MAX || !powerof2(pages)) {
2234 device_printf(sc->bce_dev, "invalid # of TX pages\n");
2235 pages = TX_PAGES_DEFAULT;
2237 sc->tx_pages = pages;
2239 sc->tx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->tx_pages,
2240 M_DEVBUF, M_WAITOK | M_ZERO);
2241 sc->tx_bd_chain = kmalloc(sizeof(struct tx_bd *) * sc->tx_pages,
2242 M_DEVBUF, M_WAITOK | M_ZERO);
2243 sc->tx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->tx_pages,
2244 M_DEVBUF, M_WAITOK | M_ZERO);
2246 sc->rx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->rx_pages,
2247 M_DEVBUF, M_WAITOK | M_ZERO);
2248 sc->rx_bd_chain = kmalloc(sizeof(struct rx_bd *) * sc->rx_pages,
2249 M_DEVBUF, M_WAITOK | M_ZERO);
2250 sc->rx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->rx_pages,
2251 M_DEVBUF, M_WAITOK | M_ZERO);
2253 sc->tx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_TX_BD(sc),
2254 M_DEVBUF, M_WAITOK | M_ZERO);
2255 sc->tx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_TX_BD(sc),
2256 M_DEVBUF, M_WAITOK | M_ZERO);
2258 sc->rx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_RX_BD(sc),
2259 M_DEVBUF, M_WAITOK | M_ZERO);
2260 sc->rx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_RX_BD(sc),
2261 M_DEVBUF, M_WAITOK | M_ZERO);
2262 sc->rx_mbuf_paddr = kmalloc(sizeof(bus_addr_t) * TOTAL_RX_BD(sc),
2263 M_DEVBUF, M_WAITOK | M_ZERO);
2266 * The embedded PCIe to PCI-X bridge (EPB)
2267 * in the 5708 cannot address memory above
2268 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2270 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2271 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2273 max_busaddr = BUS_SPACE_MAXADDR;
2276 * BCM5709 and BCM5716 uses host memory as cache for context memory.
2278 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2279 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2280 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2281 if (sc->ctx_pages == 0)
2283 if (sc->ctx_pages > BCE_CTX_PAGES) {
2284 device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2296 * Allocate the parent bus DMA tag appropriate for PCI.
2298 rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2299 max_busaddr, BUS_SPACE_MAXADDR,
2301 BUS_SPACE_MAXSIZE_32BIT, 0,
2302 BUS_SPACE_MAXSIZE_32BIT,
2303 0, &sc->parent_tag);
2305 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2310 * Allocate status block.
2312 sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2313 status_align, BCE_STATUS_BLK_SZ,
2314 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2315 &sc->status_tag, &sc->status_map,
2316 &sc->status_block_paddr);
2317 if (sc->status_block == NULL) {
2318 if_printf(ifp, "Could not allocate status block!\n");
2323 * Allocate statistics block.
2325 sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2326 stats_align, BCE_STATS_BLK_SZ,
2327 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2328 &sc->stats_tag, &sc->stats_map,
2329 &sc->stats_block_paddr);
2330 if (sc->stats_block == NULL) {
2331 if_printf(ifp, "Could not allocate statistics block!\n");
2336 * Allocate context block, if needed
2338 if (sc->ctx_pages != 0) {
2339 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2340 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2342 BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2345 if_printf(ifp, "Could not allocate "
2346 "context block DMA tag!\n");
2350 for (i = 0; i < sc->ctx_pages; i++) {
2351 rc = bus_dmamem_alloc(sc->ctx_tag,
2352 (void **)&sc->ctx_block[i],
2353 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2357 if_printf(ifp, "Could not allocate %dth context "
2358 "DMA memory!\n", i);
2362 rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2363 sc->ctx_block[i], BCM_PAGE_SIZE,
2364 bce_dma_map_addr, &busaddr,
2367 if (rc == EINPROGRESS) {
2368 panic("%s coherent memory loading "
2369 "is still in progress!", ifp->if_xname);
2371 if_printf(ifp, "Could not map %dth context "
2372 "DMA memory!\n", i);
2373 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2375 sc->ctx_block[i] = NULL;
2378 sc->ctx_paddr[i] = busaddr;
2383 * Create a DMA tag for the TX buffer descriptor chain,
2384 * allocate and clear the memory, and fetch the
2385 * physical address of the block.
2387 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2388 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2390 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2391 0, &sc->tx_bd_chain_tag);
2393 if_printf(ifp, "Could not allocate "
2394 "TX descriptor chain DMA tag!\n");
2398 for (i = 0; i < sc->tx_pages; i++) {
2399 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2400 (void **)&sc->tx_bd_chain[i],
2401 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2403 &sc->tx_bd_chain_map[i]);
2405 if_printf(ifp, "Could not allocate %dth TX descriptor "
2406 "chain DMA memory!\n", i);
2410 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2411 sc->tx_bd_chain_map[i],
2412 sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2413 bce_dma_map_addr, &busaddr,
2416 if (rc == EINPROGRESS) {
2417 panic("%s coherent memory loading "
2418 "is still in progress!", ifp->if_xname);
2420 if_printf(ifp, "Could not map %dth TX descriptor "
2421 "chain DMA memory!\n", i);
2422 bus_dmamem_free(sc->tx_bd_chain_tag,
2424 sc->tx_bd_chain_map[i]);
2425 sc->tx_bd_chain[i] = NULL;
2429 sc->tx_bd_chain_paddr[i] = busaddr;
2430 /* DRC - Fix for 64 bit systems. */
2431 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2432 i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2435 /* Create a DMA tag for TX mbufs. */
2436 rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2437 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2439 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2440 BCE_MAX_SEGMENTS, MCLBYTES,
2441 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2445 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2449 /* Create DMA maps for the TX mbufs clusters. */
2450 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2451 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2452 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2453 &sc->tx_mbuf_map[i]);
2455 for (j = 0; j < i; ++j) {
2456 bus_dmamap_destroy(sc->tx_mbuf_tag,
2457 sc->tx_mbuf_map[i]);
2459 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2460 sc->tx_mbuf_tag = NULL;
2462 if_printf(ifp, "Unable to create "
2463 "%dth TX mbuf DMA map!\n", i);
2469 * Create a DMA tag for the RX buffer descriptor chain,
2470 * allocate and clear the memory, and fetch the physical
2471 * address of the blocks.
2473 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2474 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2476 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2477 0, &sc->rx_bd_chain_tag);
2479 if_printf(ifp, "Could not allocate "
2480 "RX descriptor chain DMA tag!\n");
2484 for (i = 0; i < sc->rx_pages; i++) {
2485 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2486 (void **)&sc->rx_bd_chain[i],
2487 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2489 &sc->rx_bd_chain_map[i]);
2491 if_printf(ifp, "Could not allocate %dth RX descriptor "
2492 "chain DMA memory!\n", i);
2496 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2497 sc->rx_bd_chain_map[i],
2498 sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2499 bce_dma_map_addr, &busaddr,
2502 if (rc == EINPROGRESS) {
2503 panic("%s coherent memory loading "
2504 "is still in progress!", ifp->if_xname);
2506 if_printf(ifp, "Could not map %dth RX descriptor "
2507 "chain DMA memory!\n", i);
2508 bus_dmamem_free(sc->rx_bd_chain_tag,
2510 sc->rx_bd_chain_map[i]);
2511 sc->rx_bd_chain[i] = NULL;
2515 sc->rx_bd_chain_paddr[i] = busaddr;
2516 /* DRC - Fix for 64 bit systems. */
2517 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2518 i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2521 /* Create a DMA tag for RX mbufs. */
2522 rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2523 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2525 MCLBYTES, 1, MCLBYTES,
2526 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2530 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2534 /* Create tmp DMA map for RX mbuf clusters. */
2535 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2536 &sc->rx_mbuf_tmpmap);
2538 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2539 sc->rx_mbuf_tag = NULL;
2541 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2545 /* Create DMA maps for the RX mbuf clusters. */
2546 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2547 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2548 &sc->rx_mbuf_map[i]);
2550 for (j = 0; j < i; ++j) {
2551 bus_dmamap_destroy(sc->rx_mbuf_tag,
2552 sc->rx_mbuf_map[j]);
2554 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2555 sc->rx_mbuf_tag = NULL;
2557 if_printf(ifp, "Unable to create "
2558 "%dth RX mbuf DMA map!\n", i);
2566 /****************************************************************************/
2567 /* Firmware synchronization. */
2569 /* Before performing certain events such as a chip reset, synchronize with */
2570 /* the firmware first. */
2573 /* 0 for success, positive value for failure. */
2574 /****************************************************************************/
2576 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2581 /* Don't waste any time if we've timed out before. */
2582 if (sc->bce_fw_timed_out)
2585 /* Increment the message sequence number. */
2586 sc->bce_fw_wr_seq++;
2587 msg_data |= sc->bce_fw_wr_seq;
2589 DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2591 /* Send the message to the bootcode driver mailbox. */
2592 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2594 /* Wait for the bootcode to acknowledge the message. */
2595 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2596 /* Check for a response in the bootcode firmware mailbox. */
2597 val = bce_shmem_rd(sc, BCE_FW_MB);
2598 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2603 /* If we've timed out, tell the bootcode that we've stopped waiting. */
2604 if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2605 (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2606 if_printf(&sc->arpcom.ac_if,
2607 "Firmware synchronization timeout! "
2608 "msg_data = 0x%08X\n", msg_data);
2610 msg_data &= ~BCE_DRV_MSG_CODE;
2611 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2613 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2615 sc->bce_fw_timed_out = 1;
2622 /****************************************************************************/
2623 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
2627 /****************************************************************************/
2629 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2630 uint32_t rv2p_code_len, uint32_t rv2p_proc)
2635 for (i = 0; i < rv2p_code_len; i += 8) {
2636 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2638 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2641 if (rv2p_proc == RV2P_PROC1) {
2642 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2643 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2645 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2646 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2650 /* Reset the processor, un-stall is done later. */
2651 if (rv2p_proc == RV2P_PROC1)
2652 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2654 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2658 /****************************************************************************/
2659 /* Load RISC processor firmware. */
2661 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */
2662 /* associated with a particular processor. */
2666 /****************************************************************************/
2668 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2674 bce_halt_cpu(sc, cpu_reg);
2676 /* Load the Text area. */
2677 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2679 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2680 REG_WR_IND(sc, offset, fw->text[j]);
2683 /* Load the Data area. */
2684 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2686 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2687 REG_WR_IND(sc, offset, fw->data[j]);
2690 /* Load the SBSS area. */
2691 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2693 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2694 REG_WR_IND(sc, offset, fw->sbss[j]);
2697 /* Load the BSS area. */
2698 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2700 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2701 REG_WR_IND(sc, offset, fw->bss[j]);
2704 /* Load the Read-Only area. */
2705 offset = cpu_reg->spad_base +
2706 (fw->rodata_addr - cpu_reg->mips_view_base);
2708 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2709 REG_WR_IND(sc, offset, fw->rodata[j]);
2712 /* Clear the pre-fetch instruction and set the FW start address. */
2713 REG_WR_IND(sc, cpu_reg->inst, 0);
2714 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2718 /****************************************************************************/
2719 /* Starts the RISC processor. */
2721 /* Assumes the CPU starting address has already been set. */
2725 /****************************************************************************/
2727 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2731 /* Start the CPU. */
2732 val = REG_RD_IND(sc, cpu_reg->mode);
2733 val &= ~cpu_reg->mode_value_halt;
2734 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2735 REG_WR_IND(sc, cpu_reg->mode, val);
2739 /****************************************************************************/
2740 /* Halts the RISC processor. */
2744 /****************************************************************************/
2746 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2751 val = REG_RD_IND(sc, cpu_reg->mode);
2752 val |= cpu_reg->mode_value_halt;
2753 REG_WR_IND(sc, cpu_reg->mode, val);
2754 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2758 /****************************************************************************/
2759 /* Start the RX CPU. */
2763 /****************************************************************************/
2765 bce_start_rxp_cpu(struct bce_softc *sc)
2767 struct cpu_reg cpu_reg;
2769 cpu_reg.mode = BCE_RXP_CPU_MODE;
2770 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2771 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2772 cpu_reg.state = BCE_RXP_CPU_STATE;
2773 cpu_reg.state_value_clear = 0xffffff;
2774 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2775 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2776 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2777 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2778 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2779 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2780 cpu_reg.mips_view_base = 0x8000000;
2782 bce_start_cpu(sc, &cpu_reg);
2786 /****************************************************************************/
2787 /* Initialize the RX CPU. */
2791 /****************************************************************************/
2793 bce_init_rxp_cpu(struct bce_softc *sc)
2795 struct cpu_reg cpu_reg;
2798 cpu_reg.mode = BCE_RXP_CPU_MODE;
2799 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2800 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2801 cpu_reg.state = BCE_RXP_CPU_STATE;
2802 cpu_reg.state_value_clear = 0xffffff;
2803 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2804 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2805 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2806 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2807 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2808 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2809 cpu_reg.mips_view_base = 0x8000000;
2811 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2812 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2813 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2814 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2815 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2816 fw.start_addr = bce_RXP_b09FwStartAddr;
2818 fw.text_addr = bce_RXP_b09FwTextAddr;
2819 fw.text_len = bce_RXP_b09FwTextLen;
2821 fw.text = bce_RXP_b09FwText;
2823 fw.data_addr = bce_RXP_b09FwDataAddr;
2824 fw.data_len = bce_RXP_b09FwDataLen;
2826 fw.data = bce_RXP_b09FwData;
2828 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2829 fw.sbss_len = bce_RXP_b09FwSbssLen;
2831 fw.sbss = bce_RXP_b09FwSbss;
2833 fw.bss_addr = bce_RXP_b09FwBssAddr;
2834 fw.bss_len = bce_RXP_b09FwBssLen;
2836 fw.bss = bce_RXP_b09FwBss;
2838 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2839 fw.rodata_len = bce_RXP_b09FwRodataLen;
2840 fw.rodata_index = 0;
2841 fw.rodata = bce_RXP_b09FwRodata;
2843 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2844 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2845 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2846 fw.start_addr = bce_RXP_b06FwStartAddr;
2848 fw.text_addr = bce_RXP_b06FwTextAddr;
2849 fw.text_len = bce_RXP_b06FwTextLen;
2851 fw.text = bce_RXP_b06FwText;
2853 fw.data_addr = bce_RXP_b06FwDataAddr;
2854 fw.data_len = bce_RXP_b06FwDataLen;
2856 fw.data = bce_RXP_b06FwData;
2858 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2859 fw.sbss_len = bce_RXP_b06FwSbssLen;
2861 fw.sbss = bce_RXP_b06FwSbss;
2863 fw.bss_addr = bce_RXP_b06FwBssAddr;
2864 fw.bss_len = bce_RXP_b06FwBssLen;
2866 fw.bss = bce_RXP_b06FwBss;
2868 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2869 fw.rodata_len = bce_RXP_b06FwRodataLen;
2870 fw.rodata_index = 0;
2871 fw.rodata = bce_RXP_b06FwRodata;
2874 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2875 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2876 /* Delay RXP start until initialization is complete. */
2880 /****************************************************************************/
2881 /* Initialize the TX CPU. */
2885 /****************************************************************************/
2887 bce_init_txp_cpu(struct bce_softc *sc)
2889 struct cpu_reg cpu_reg;
2892 cpu_reg.mode = BCE_TXP_CPU_MODE;
2893 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2894 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2895 cpu_reg.state = BCE_TXP_CPU_STATE;
2896 cpu_reg.state_value_clear = 0xffffff;
2897 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2898 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2899 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2900 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2901 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2902 cpu_reg.spad_base = BCE_TXP_SCRATCH;
2903 cpu_reg.mips_view_base = 0x8000000;
2905 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2906 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2907 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2908 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2909 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2910 fw.start_addr = bce_TXP_b09FwStartAddr;
2912 fw.text_addr = bce_TXP_b09FwTextAddr;
2913 fw.text_len = bce_TXP_b09FwTextLen;
2915 fw.text = bce_TXP_b09FwText;
2917 fw.data_addr = bce_TXP_b09FwDataAddr;
2918 fw.data_len = bce_TXP_b09FwDataLen;
2920 fw.data = bce_TXP_b09FwData;
2922 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2923 fw.sbss_len = bce_TXP_b09FwSbssLen;
2925 fw.sbss = bce_TXP_b09FwSbss;
2927 fw.bss_addr = bce_TXP_b09FwBssAddr;
2928 fw.bss_len = bce_TXP_b09FwBssLen;
2930 fw.bss = bce_TXP_b09FwBss;
2932 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2933 fw.rodata_len = bce_TXP_b09FwRodataLen;
2934 fw.rodata_index = 0;
2935 fw.rodata = bce_TXP_b09FwRodata;
2937 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2938 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2939 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2940 fw.start_addr = bce_TXP_b06FwStartAddr;
2942 fw.text_addr = bce_TXP_b06FwTextAddr;
2943 fw.text_len = bce_TXP_b06FwTextLen;
2945 fw.text = bce_TXP_b06FwText;
2947 fw.data_addr = bce_TXP_b06FwDataAddr;
2948 fw.data_len = bce_TXP_b06FwDataLen;
2950 fw.data = bce_TXP_b06FwData;
2952 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2953 fw.sbss_len = bce_TXP_b06FwSbssLen;
2955 fw.sbss = bce_TXP_b06FwSbss;
2957 fw.bss_addr = bce_TXP_b06FwBssAddr;
2958 fw.bss_len = bce_TXP_b06FwBssLen;
2960 fw.bss = bce_TXP_b06FwBss;
2962 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2963 fw.rodata_len = bce_TXP_b06FwRodataLen;
2964 fw.rodata_index = 0;
2965 fw.rodata = bce_TXP_b06FwRodata;
2968 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2969 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2970 bce_start_cpu(sc, &cpu_reg);
2974 /****************************************************************************/
2975 /* Initialize the TPAT CPU. */
2979 /****************************************************************************/
2981 bce_init_tpat_cpu(struct bce_softc *sc)
2983 struct cpu_reg cpu_reg;
2986 cpu_reg.mode = BCE_TPAT_CPU_MODE;
2987 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2988 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2989 cpu_reg.state = BCE_TPAT_CPU_STATE;
2990 cpu_reg.state_value_clear = 0xffffff;
2991 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2992 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2993 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2994 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2995 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2996 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2997 cpu_reg.mips_view_base = 0x8000000;
2999 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3000 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3001 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
3002 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
3003 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
3004 fw.start_addr = bce_TPAT_b09FwStartAddr;
3006 fw.text_addr = bce_TPAT_b09FwTextAddr;
3007 fw.text_len = bce_TPAT_b09FwTextLen;
3009 fw.text = bce_TPAT_b09FwText;
3011 fw.data_addr = bce_TPAT_b09FwDataAddr;
3012 fw.data_len = bce_TPAT_b09FwDataLen;
3014 fw.data = bce_TPAT_b09FwData;
3016 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
3017 fw.sbss_len = bce_TPAT_b09FwSbssLen;
3019 fw.sbss = bce_TPAT_b09FwSbss;
3021 fw.bss_addr = bce_TPAT_b09FwBssAddr;
3022 fw.bss_len = bce_TPAT_b09FwBssLen;
3024 fw.bss = bce_TPAT_b09FwBss;
3026 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
3027 fw.rodata_len = bce_TPAT_b09FwRodataLen;
3028 fw.rodata_index = 0;
3029 fw.rodata = bce_TPAT_b09FwRodata;
3031 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3032 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3033 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3034 fw.start_addr = bce_TPAT_b06FwStartAddr;
3036 fw.text_addr = bce_TPAT_b06FwTextAddr;
3037 fw.text_len = bce_TPAT_b06FwTextLen;
3039 fw.text = bce_TPAT_b06FwText;
3041 fw.data_addr = bce_TPAT_b06FwDataAddr;
3042 fw.data_len = bce_TPAT_b06FwDataLen;
3044 fw.data = bce_TPAT_b06FwData;
3046 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3047 fw.sbss_len = bce_TPAT_b06FwSbssLen;
3049 fw.sbss = bce_TPAT_b06FwSbss;
3051 fw.bss_addr = bce_TPAT_b06FwBssAddr;
3052 fw.bss_len = bce_TPAT_b06FwBssLen;
3054 fw.bss = bce_TPAT_b06FwBss;
3056 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3057 fw.rodata_len = bce_TPAT_b06FwRodataLen;
3058 fw.rodata_index = 0;
3059 fw.rodata = bce_TPAT_b06FwRodata;
3062 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
3063 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3064 bce_start_cpu(sc, &cpu_reg);
3068 /****************************************************************************/
3069 /* Initialize the CP CPU. */
3073 /****************************************************************************/
3075 bce_init_cp_cpu(struct bce_softc *sc)
3077 struct cpu_reg cpu_reg;
3080 cpu_reg.mode = BCE_CP_CPU_MODE;
3081 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3082 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3083 cpu_reg.state = BCE_CP_CPU_STATE;
3084 cpu_reg.state_value_clear = 0xffffff;
3085 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3086 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3087 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3088 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3089 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3090 cpu_reg.spad_base = BCE_CP_SCRATCH;
3091 cpu_reg.mips_view_base = 0x8000000;
3093 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3094 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3095 fw.ver_major = bce_CP_b09FwReleaseMajor;
3096 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3097 fw.ver_fix = bce_CP_b09FwReleaseFix;
3098 fw.start_addr = bce_CP_b09FwStartAddr;
3100 fw.text_addr = bce_CP_b09FwTextAddr;
3101 fw.text_len = bce_CP_b09FwTextLen;
3103 fw.text = bce_CP_b09FwText;
3105 fw.data_addr = bce_CP_b09FwDataAddr;
3106 fw.data_len = bce_CP_b09FwDataLen;
3108 fw.data = bce_CP_b09FwData;
3110 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3111 fw.sbss_len = bce_CP_b09FwSbssLen;
3113 fw.sbss = bce_CP_b09FwSbss;
3115 fw.bss_addr = bce_CP_b09FwBssAddr;
3116 fw.bss_len = bce_CP_b09FwBssLen;
3118 fw.bss = bce_CP_b09FwBss;
3120 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3121 fw.rodata_len = bce_CP_b09FwRodataLen;
3122 fw.rodata_index = 0;
3123 fw.rodata = bce_CP_b09FwRodata;
3125 fw.ver_major = bce_CP_b06FwReleaseMajor;
3126 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3127 fw.ver_fix = bce_CP_b06FwReleaseFix;
3128 fw.start_addr = bce_CP_b06FwStartAddr;
3130 fw.text_addr = bce_CP_b06FwTextAddr;
3131 fw.text_len = bce_CP_b06FwTextLen;
3133 fw.text = bce_CP_b06FwText;
3135 fw.data_addr = bce_CP_b06FwDataAddr;
3136 fw.data_len = bce_CP_b06FwDataLen;
3138 fw.data = bce_CP_b06FwData;
3140 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3141 fw.sbss_len = bce_CP_b06FwSbssLen;
3143 fw.sbss = bce_CP_b06FwSbss;
3145 fw.bss_addr = bce_CP_b06FwBssAddr;
3146 fw.bss_len = bce_CP_b06FwBssLen;
3148 fw.bss = bce_CP_b06FwBss;
3150 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3151 fw.rodata_len = bce_CP_b06FwRodataLen;
3152 fw.rodata_index = 0;
3153 fw.rodata = bce_CP_b06FwRodata;
3156 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3157 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3158 bce_start_cpu(sc, &cpu_reg);
3162 /****************************************************************************/
3163 /* Initialize the COM CPU. */
3167 /****************************************************************************/
3169 bce_init_com_cpu(struct bce_softc *sc)
3171 struct cpu_reg cpu_reg;
3174 cpu_reg.mode = BCE_COM_CPU_MODE;
3175 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3176 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3177 cpu_reg.state = BCE_COM_CPU_STATE;
3178 cpu_reg.state_value_clear = 0xffffff;
3179 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3180 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3181 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3182 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3183 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3184 cpu_reg.spad_base = BCE_COM_SCRATCH;
3185 cpu_reg.mips_view_base = 0x8000000;
3187 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3188 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3189 fw.ver_major = bce_COM_b09FwReleaseMajor;
3190 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3191 fw.ver_fix = bce_COM_b09FwReleaseFix;
3192 fw.start_addr = bce_COM_b09FwStartAddr;
3194 fw.text_addr = bce_COM_b09FwTextAddr;
3195 fw.text_len = bce_COM_b09FwTextLen;
3197 fw.text = bce_COM_b09FwText;
3199 fw.data_addr = bce_COM_b09FwDataAddr;
3200 fw.data_len = bce_COM_b09FwDataLen;
3202 fw.data = bce_COM_b09FwData;
3204 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3205 fw.sbss_len = bce_COM_b09FwSbssLen;
3207 fw.sbss = bce_COM_b09FwSbss;
3209 fw.bss_addr = bce_COM_b09FwBssAddr;
3210 fw.bss_len = bce_COM_b09FwBssLen;
3212 fw.bss = bce_COM_b09FwBss;
3214 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3215 fw.rodata_len = bce_COM_b09FwRodataLen;
3216 fw.rodata_index = 0;
3217 fw.rodata = bce_COM_b09FwRodata;
3219 fw.ver_major = bce_COM_b06FwReleaseMajor;
3220 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3221 fw.ver_fix = bce_COM_b06FwReleaseFix;
3222 fw.start_addr = bce_COM_b06FwStartAddr;
3224 fw.text_addr = bce_COM_b06FwTextAddr;
3225 fw.text_len = bce_COM_b06FwTextLen;
3227 fw.text = bce_COM_b06FwText;
3229 fw.data_addr = bce_COM_b06FwDataAddr;
3230 fw.data_len = bce_COM_b06FwDataLen;
3232 fw.data = bce_COM_b06FwData;
3234 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3235 fw.sbss_len = bce_COM_b06FwSbssLen;
3237 fw.sbss = bce_COM_b06FwSbss;
3239 fw.bss_addr = bce_COM_b06FwBssAddr;
3240 fw.bss_len = bce_COM_b06FwBssLen;
3242 fw.bss = bce_COM_b06FwBss;
3244 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3245 fw.rodata_len = bce_COM_b06FwRodataLen;
3246 fw.rodata_index = 0;
3247 fw.rodata = bce_COM_b06FwRodata;
3250 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3251 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3252 bce_start_cpu(sc, &cpu_reg);
3256 /****************************************************************************/
3257 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
3259 /* Loads the firmware for each CPU and starts the CPU. */
3263 /****************************************************************************/
3265 bce_init_cpus(struct bce_softc *sc)
3267 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3268 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3269 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3270 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3271 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3272 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3273 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3275 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3276 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3277 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3278 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3281 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3282 sizeof(bce_rv2p_proc1), RV2P_PROC1);
3283 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3284 sizeof(bce_rv2p_proc2), RV2P_PROC2);
3287 bce_init_rxp_cpu(sc);
3288 bce_init_txp_cpu(sc);
3289 bce_init_tpat_cpu(sc);
3290 bce_init_com_cpu(sc);
3291 bce_init_cp_cpu(sc);
3295 /****************************************************************************/
3296 /* Initialize context memory. */
3298 /* Clears the memory associated with each Context ID (CID). */
3302 /****************************************************************************/
3304 bce_init_ctx(struct bce_softc *sc)
3306 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3307 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3308 /* DRC: Replace this constant value with a #define. */
3309 int i, retry_cnt = 10;
3313 * BCM5709 context memory may be cached
3314 * in host memory so prepare the host memory
3317 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3319 val |= (BCM_PAGE_BITS - 8) << 16;
3320 REG_WR(sc, BCE_CTX_COMMAND, val);
3322 /* Wait for mem init command to complete. */
3323 for (i = 0; i < retry_cnt; i++) {
3324 val = REG_RD(sc, BCE_CTX_COMMAND);
3325 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3329 if (i == retry_cnt) {
3330 device_printf(sc->bce_dev,
3331 "Context memory initialization failed!\n");
3335 for (i = 0; i < sc->ctx_pages; i++) {
3339 * Set the physical address of the context
3342 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3343 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3344 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3345 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3346 BCE_ADDR_HI(sc->ctx_paddr[i]));
3347 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3348 i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3351 * Verify that the context memory write was successful.
3353 for (j = 0; j < retry_cnt; j++) {
3354 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3356 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3360 if (j == retry_cnt) {
3361 device_printf(sc->bce_dev,
3362 "Failed to initialize context page!\n");
3367 uint32_t vcid_addr, offset;
3370 * For the 5706/5708, context memory is local to
3371 * the controller, so initialize the controller
3375 vcid_addr = GET_CID_ADDR(96);
3377 vcid_addr -= PHY_CTX_SIZE;
3379 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3380 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3382 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3383 CTX_WR(sc, 0x00, offset, 0);
3385 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3386 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3393 /****************************************************************************/
3394 /* Fetch the permanent MAC address of the controller. */
3398 /****************************************************************************/
3400 bce_get_mac_addr(struct bce_softc *sc)
3402 uint32_t mac_lo = 0, mac_hi = 0;
3405 * The NetXtreme II bootcode populates various NIC
3406 * power-on and runtime configuration items in a
3407 * shared memory area. The factory configured MAC
3408 * address is available from both NVRAM and the
3409 * shared memory area so we'll read the value from
3410 * shared memory for speed.
3413 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
3414 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3416 if (mac_lo == 0 && mac_hi == 0) {
3417 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3419 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3420 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3421 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3422 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3423 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3424 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3427 DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3431 /****************************************************************************/
3432 /* Program the MAC address. */
3436 /****************************************************************************/
3438 bce_set_mac_addr(struct bce_softc *sc)
3440 const uint8_t *mac_addr = sc->eaddr;
3443 DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3446 val = (mac_addr[0] << 8) | mac_addr[1];
3447 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3449 val = (mac_addr[2] << 24) |
3450 (mac_addr[3] << 16) |
3451 (mac_addr[4] << 8) |
3453 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3457 /****************************************************************************/
3458 /* Stop the controller. */
3462 /****************************************************************************/
3464 bce_stop(struct bce_softc *sc)
3466 struct ifnet *ifp = &sc->arpcom.ac_if;
3468 ASSERT_SERIALIZED(ifp->if_serializer);
3470 callout_stop(&sc->bce_tick_callout);
3472 /* Disable the transmit/receive blocks. */
3473 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3474 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3477 bce_disable_intr(sc);
3479 /* Free the RX lists. */
3480 bce_free_rx_chain(sc);
3482 /* Free TX buffers. */
3483 bce_free_tx_chain(sc);
3486 sc->bce_coalchg_mask = 0;
3488 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3494 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3499 /* Wait for pending PCI transactions to complete. */
3500 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3501 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3502 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3503 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3504 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3505 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3509 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3510 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3511 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3512 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3513 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3516 /* Assume bootcode is running. */
3517 sc->bce_fw_timed_out = 0;
3518 sc->bce_drv_cardiac_arrest = 0;
3520 /* Give the firmware a chance to prepare for the reset. */
3521 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3523 if_printf(&sc->arpcom.ac_if,
3524 "Firmware is not ready for reset\n");
3528 /* Set a firmware reminder that this is a soft reset. */
3529 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3530 BCE_DRV_RESET_SIGNATURE_MAGIC);
3532 /* Dummy read to force the chip to complete all current transactions. */
3533 val = REG_RD(sc, BCE_MISC_ID);
3536 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3537 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3538 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3539 REG_RD(sc, BCE_MISC_COMMAND);
3542 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3543 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3545 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3547 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3548 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3549 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3550 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3552 /* Allow up to 30us for reset to complete. */
3553 for (i = 0; i < 10; i++) {
3554 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3555 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3556 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3561 /* Check that reset completed successfully. */
3562 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3563 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3564 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3569 /* Make sure byte swapping is properly configured. */
3570 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3571 if (val != 0x01020304) {
3572 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3576 /* Just completed a reset, assume that firmware is running again. */
3577 sc->bce_fw_timed_out = 0;
3578 sc->bce_drv_cardiac_arrest = 0;
3580 /* Wait for the firmware to finish its initialization. */
3581 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3583 if_printf(&sc->arpcom.ac_if,
3584 "Firmware did not complete initialization!\n");
3591 bce_chipinit(struct bce_softc *sc)
3596 /* Make sure the interrupt is not active. */
3597 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3598 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3601 * Initialize DMA byte/word swapping, configure the number of DMA
3602 * channels and PCI clock compensation delay.
3604 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3605 BCE_DMA_CONFIG_DATA_WORD_SWAP |
3606 #if BYTE_ORDER == BIG_ENDIAN
3607 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3609 BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3610 DMA_READ_CHANS << 12 |
3611 DMA_WRITE_CHANS << 16;
3613 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3615 if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3616 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3619 * This setting resolves a problem observed on certain Intel PCI
3620 * chipsets that cannot handle multiple outstanding DMA operations.
3621 * See errata E9_5706A1_65.
3623 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3624 BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3625 !(sc->bce_flags & BCE_PCIX_FLAG))
3626 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3628 REG_WR(sc, BCE_DMA_CONFIG, val);
3630 /* Enable the RX_V2P and Context state machines before access. */
3631 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3632 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3633 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3634 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3636 /* Initialize context mapping and zero out the quick contexts. */
3637 rc = bce_init_ctx(sc);
3641 /* Initialize the on-boards CPUs */
3644 /* Enable management frames (NC-SI) to flow to the MCP. */
3645 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3646 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3647 BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3648 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3651 /* Prepare NVRAM for access. */
3652 rc = bce_init_nvram(sc);
3656 /* Set the kernel bypass block size */
3657 val = REG_RD(sc, BCE_MQ_CONFIG);
3658 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3659 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3661 /* Enable bins used on the 5709/5716. */
3662 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3663 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3664 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3665 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3666 val |= BCE_MQ_CONFIG_HALT_DIS;
3669 REG_WR(sc, BCE_MQ_CONFIG, val);
3671 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3672 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3673 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3675 /* Set the page size and clear the RV2P processor stall bits. */
3676 val = (BCM_PAGE_BITS - 8) << 24;
3677 REG_WR(sc, BCE_RV2P_CONFIG, val);
3679 /* Configure page size. */
3680 val = REG_RD(sc, BCE_TBDR_CONFIG);
3681 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3682 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3683 REG_WR(sc, BCE_TBDR_CONFIG, val);
3685 /* Set the perfect match control register to default. */
3686 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3692 /****************************************************************************/
3693 /* Initialize the controller in preparation to send/receive traffic. */
3696 /* 0 for success, positive value for failure. */
3697 /****************************************************************************/
3699 bce_blockinit(struct bce_softc *sc)
3704 /* Load the hardware default MAC address. */
3705 bce_set_mac_addr(sc);
3707 /* Set the Ethernet backoff seed value */
3708 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3709 sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3710 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3712 sc->last_status_idx = 0;
3713 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3715 sc->pulse_check_status_idx = 0xffff;
3717 /* Set up link change interrupt generation. */
3718 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3720 /* Program the physical address of the status block. */
3721 REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3722 REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3724 /* Program the physical address of the statistics block. */
3725 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3726 BCE_ADDR_LO(sc->stats_block_paddr));
3727 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3728 BCE_ADDR_HI(sc->stats_block_paddr));
3730 /* Program various host coalescing parameters. */
3731 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3732 (sc->bce_tx_quick_cons_trip_int << 16) |
3733 sc->bce_tx_quick_cons_trip);
3734 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3735 (sc->bce_rx_quick_cons_trip_int << 16) |
3736 sc->bce_rx_quick_cons_trip);
3737 REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3738 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3739 REG_WR(sc, BCE_HC_TX_TICKS,
3740 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3741 REG_WR(sc, BCE_HC_RX_TICKS,
3742 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3743 REG_WR(sc, BCE_HC_COM_TICKS,
3744 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3745 REG_WR(sc, BCE_HC_CMD_TICKS,
3746 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3747 REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3748 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3750 val = BCE_HC_CONFIG_TX_TMR_MODE | BCE_HC_CONFIG_COLLECT_STATS;
3751 if (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) {
3753 if_printf(&sc->arpcom.ac_if, "oneshot MSI\n");
3754 val |= BCE_HC_CONFIG_ONE_SHOT | BCE_HC_CONFIG_USE_INT_PARAM;
3756 REG_WR(sc, BCE_HC_CONFIG, val);
3758 /* Clear the internal statistics counters. */
3759 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3761 /* Verify that bootcode is running. */
3762 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3764 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3765 if_printf(&sc->arpcom.ac_if,
3766 "%s(%d): Simulating bootcode failure.\n",
3767 __FILE__, __LINE__);
3770 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3771 BCE_DEV_INFO_SIGNATURE_MAGIC) {
3772 if_printf(&sc->arpcom.ac_if,
3773 "Bootcode not running! Found: 0x%08X, "
3774 "Expected: 08%08X\n",
3775 reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3776 BCE_DEV_INFO_SIGNATURE_MAGIC);
3781 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3782 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3783 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3784 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3785 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3788 /* Allow bootcode to apply any additional fixes before enabling MAC. */
3789 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3791 /* Enable link state change interrupt generation. */
3792 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3794 /* Enable the RXP. */
3795 bce_start_rxp_cpu(sc);
3797 /* Disable management frames (NC-SI) from flowing to the MCP. */
3798 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3799 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3800 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3801 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3804 /* Enable all remaining blocks in the MAC. */
3805 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3806 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3807 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3808 BCE_MISC_ENABLE_DEFAULT_XI);
3810 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3812 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3815 /* Save the current host coalescing block settings. */
3816 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3822 /****************************************************************************/
3823 /* Encapsulate an mbuf cluster into the rx_bd chain. */
3825 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */
3826 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */
3830 /* 0 for success, positive value for failure. */
3831 /****************************************************************************/
3833 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3834 uint32_t *prod_bseq, int init)
3837 bus_dma_segment_t seg;
3841 uint16_t debug_chain_prod = *chain_prod;
3844 /* Make sure the inputs are valid. */
3845 DBRUNIF((*chain_prod > MAX_RX_BD(sc)),
3846 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3847 "RX producer out of range: 0x%04X > 0x%04X\n",
3849 *chain_prod, (uint16_t)MAX_RX_BD(sc)));
3851 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3852 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3854 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3855 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3856 "Simulating mbuf allocation failure.\n",
3857 __FILE__, __LINE__);
3858 sc->mbuf_alloc_failed++;
3861 /* This is a new mbuf allocation. */
3862 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3865 DBRUNIF(1, sc->rx_mbuf_alloc++);
3867 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3869 /* Map the mbuf cluster into device memory. */
3870 error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3871 sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3876 if_printf(&sc->arpcom.ac_if,
3877 "Error mapping mbuf into RX chain!\n");
3879 DBRUNIF(1, sc->rx_mbuf_alloc--);
3883 if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3884 bus_dmamap_unload(sc->rx_mbuf_tag,
3885 sc->rx_mbuf_map[*chain_prod]);
3888 map = sc->rx_mbuf_map[*chain_prod];
3889 sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3890 sc->rx_mbuf_tmpmap = map;
3892 /* Watch for overflow. */
3893 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD(sc)),
3894 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3895 "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3896 __FILE__, __LINE__, sc->free_rx_bd,
3897 (uint16_t)USABLE_RX_BD(sc)));
3899 /* Update some debug statistic counters */
3900 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3901 sc->rx_low_watermark = sc->free_rx_bd);
3902 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3904 /* Save the mbuf and update our counter. */
3905 sc->rx_mbuf_ptr[*chain_prod] = m_new;
3906 sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3909 bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3911 DBRUN(BCE_VERBOSE_RECV,
3912 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3914 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3915 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3922 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3928 paddr = sc->rx_mbuf_paddr[chain_prod];
3929 len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3931 /* Setup the rx_bd for the first segment. */
3932 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3934 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3935 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3936 rxbd->rx_bd_len = htole32(len);
3937 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3940 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3944 /****************************************************************************/
3945 /* Initialize the TX context memory. */
3949 /****************************************************************************/
3951 bce_init_tx_context(struct bce_softc *sc)
3955 /* Initialize the context ID for an L2 TX chain. */
3956 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3957 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3958 /* Set the CID type to support an L2 connection. */
3959 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3960 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3961 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3962 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3964 /* Point the hardware to the first page in the chain. */
3965 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3966 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3967 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3968 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3969 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3970 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3972 /* Set the CID type to support an L2 connection. */
3973 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3974 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3975 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3976 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3978 /* Point the hardware to the first page in the chain. */
3979 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3980 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3981 BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3982 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3983 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3984 BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3989 /****************************************************************************/
3990 /* Allocate memory and initialize the TX data structures. */
3993 /* 0 for success, positive value for failure. */
3994 /****************************************************************************/
3996 bce_init_tx_chain(struct bce_softc *sc)
4001 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4003 /* Set the initial TX producer/consumer indices. */
4006 sc->tx_prod_bseq = 0;
4008 sc->max_tx_bd = USABLE_TX_BD(sc);
4009 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD(sc));
4010 DBRUNIF(1, sc->tx_full_count = 0);
4013 * The NetXtreme II supports a linked-list structre called
4014 * a Buffer Descriptor Chain (or BD chain). A BD chain
4015 * consists of a series of 1 or more chain pages, each of which
4016 * consists of a fixed number of BD entries.
4017 * The last BD entry on each page is a pointer to the next page
4018 * in the chain, and the last pointer in the BD chain
4019 * points back to the beginning of the chain.
4022 /* Set the TX next pointer chain entries. */
4023 for (i = 0; i < sc->tx_pages; i++) {
4026 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
4028 /* Check if we've reached the last page. */
4029 if (i == (sc->tx_pages - 1))
4034 txbd->tx_bd_haddr_hi =
4035 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
4036 txbd->tx_bd_haddr_lo =
4037 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
4039 bce_init_tx_context(sc);
4045 /****************************************************************************/
4046 /* Free memory and clear the TX data structures. */
4050 /****************************************************************************/
4052 bce_free_tx_chain(struct bce_softc *sc)
4056 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4058 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
4059 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
4060 if (sc->tx_mbuf_ptr[i] != NULL) {
4061 bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
4062 m_freem(sc->tx_mbuf_ptr[i]);
4063 sc->tx_mbuf_ptr[i] = NULL;
4064 DBRUNIF(1, sc->tx_mbuf_alloc--);
4068 /* Clear each TX chain page. */
4069 for (i = 0; i < sc->tx_pages; i++)
4070 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
4073 /* Check if we lost any mbufs in the process. */
4074 DBRUNIF((sc->tx_mbuf_alloc),
4075 if_printf(&sc->arpcom.ac_if,
4076 "%s(%d): Memory leak! "
4077 "Lost %d mbufs from tx chain!\n",
4078 __FILE__, __LINE__, sc->tx_mbuf_alloc));
4080 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4084 /****************************************************************************/
4085 /* Initialize the RX context memory. */
4089 /****************************************************************************/
4091 bce_init_rx_context(struct bce_softc *sc)
4095 /* Initialize the context ID for an L2 RX chain. */
4096 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4097 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4100 * Set the level for generating pause frames
4101 * when the number of available rx_bd's gets
4102 * too low (the low watermark) and the level
4103 * when pause frames can be stopped (the high
4106 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4107 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4108 uint32_t lo_water, hi_water;
4110 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
4111 hi_water = USABLE_RX_BD(sc) / 4;
4113 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
4114 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
4118 else if (hi_water == 0)
4121 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
4124 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
4126 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
4127 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4128 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4129 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
4130 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
4133 /* Point the hardware to the first page in the chain. */
4134 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
4135 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
4136 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
4137 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
4141 /****************************************************************************/
4142 /* Allocate memory and initialize the RX data structures. */
4145 /* 0 for success, positive value for failure. */
4146 /****************************************************************************/
4148 bce_init_rx_chain(struct bce_softc *sc)
4152 uint16_t prod, chain_prod;
4155 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4157 /* Initialize the RX producer and consumer indices. */
4160 sc->rx_prod_bseq = 0;
4161 sc->free_rx_bd = USABLE_RX_BD(sc);
4162 sc->max_rx_bd = USABLE_RX_BD(sc);
4163 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD(sc));
4164 DBRUNIF(1, sc->rx_empty_count = 0);
4166 /* Initialize the RX next pointer chain entries. */
4167 for (i = 0; i < sc->rx_pages; i++) {
4170 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
4172 /* Check if we've reached the last page. */
4173 if (i == (sc->rx_pages - 1))
4178 /* Setup the chain page pointers. */
4179 rxbd->rx_bd_haddr_hi =
4180 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
4181 rxbd->rx_bd_haddr_lo =
4182 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
4185 /* Allocate mbuf clusters for the rx_bd chain. */
4186 prod = prod_bseq = 0;
4187 while (prod < TOTAL_RX_BD(sc)) {
4188 chain_prod = RX_CHAIN_IDX(sc, prod);
4189 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
4190 if_printf(&sc->arpcom.ac_if,
4191 "Error filling RX chain: rx_bd[0x%04X]!\n",
4196 prod = NEXT_RX_BD(prod);
4199 /* Save the RX chain producer index. */
4201 sc->rx_prod_bseq = prod_bseq;
4203 /* Tell the chip about the waiting rx_bd's. */
4204 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4206 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4209 bce_init_rx_context(sc);
4215 /****************************************************************************/
4216 /* Free memory and clear the RX data structures. */
4220 /****************************************************************************/
4222 bce_free_rx_chain(struct bce_softc *sc)
4226 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4228 /* Free any mbufs still in the RX mbuf chain. */
4229 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
4230 if (sc->rx_mbuf_ptr[i] != NULL) {
4231 bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
4232 m_freem(sc->rx_mbuf_ptr[i]);
4233 sc->rx_mbuf_ptr[i] = NULL;
4234 DBRUNIF(1, sc->rx_mbuf_alloc--);
4238 /* Clear each RX chain page. */
4239 for (i = 0; i < sc->rx_pages; i++)
4240 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
4242 /* Check if we lost any mbufs in the process. */
4243 DBRUNIF((sc->rx_mbuf_alloc),
4244 if_printf(&sc->arpcom.ac_if,
4245 "%s(%d): Memory leak! "
4246 "Lost %d mbufs from rx chain!\n",
4247 __FILE__, __LINE__, sc->rx_mbuf_alloc));
4249 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4253 /****************************************************************************/
4254 /* Set media options. */
4257 /* 0 for success, positive value for failure. */
4258 /****************************************************************************/
4260 bce_ifmedia_upd(struct ifnet *ifp)
4262 struct bce_softc *sc = ifp->if_softc;
4263 struct mii_data *mii = device_get_softc(sc->bce_miibus);
4267 * 'mii' will be NULL, when this function is called on following
4268 * code path: bce_attach() -> bce_mgmt_init()
4271 /* Make sure the MII bus has been enumerated. */
4273 if (mii->mii_instance) {
4274 struct mii_softc *miisc;
4276 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4277 mii_phy_reset(miisc);
4279 error = mii_mediachg(mii);
4285 /****************************************************************************/
4286 /* Reports current media status. */
4290 /****************************************************************************/
4292 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4294 struct bce_softc *sc = ifp->if_softc;
4295 struct mii_data *mii = device_get_softc(sc->bce_miibus);
4298 ifmr->ifm_active = mii->mii_media_active;
4299 ifmr->ifm_status = mii->mii_media_status;
4303 /****************************************************************************/
4304 /* Handles PHY generated interrupt events. */
4308 /****************************************************************************/
4310 bce_phy_intr(struct bce_softc *sc)
4312 uint32_t new_link_state, old_link_state;
4313 struct ifnet *ifp = &sc->arpcom.ac_if;
4315 ASSERT_SERIALIZED(ifp->if_serializer);
4317 new_link_state = sc->status_block->status_attn_bits &
4318 STATUS_ATTN_BITS_LINK_STATE;
4319 old_link_state = sc->status_block->status_attn_bits_ack &
4320 STATUS_ATTN_BITS_LINK_STATE;
4322 /* Handle any changes if the link state has changed. */
4323 if (new_link_state != old_link_state) { /* XXX redundant? */
4324 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4326 /* Update the status_attn_bits_ack field in the status block. */
4327 if (new_link_state) {
4328 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4329 STATUS_ATTN_BITS_LINK_STATE);
4331 if_printf(ifp, "Link is now UP.\n");
4333 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4334 STATUS_ATTN_BITS_LINK_STATE);
4336 if_printf(ifp, "Link is now DOWN.\n");
4340 * Assume link is down and allow tick routine to
4341 * update the state based on the actual media state.
4344 callout_stop(&sc->bce_tick_callout);
4345 bce_tick_serialized(sc);
4348 /* Acknowledge the link change interrupt. */
4349 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4353 /****************************************************************************/
4354 /* Reads the receive consumer value from the status block (skipping over */
4355 /* chain page pointer if necessary). */
4359 /****************************************************************************/
4360 static __inline uint16_t
4361 bce_get_hw_rx_cons(struct bce_softc *sc)
4363 uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4365 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4371 /****************************************************************************/
4372 /* Handles received frame interrupt events. */
4376 /****************************************************************************/
4378 bce_rx_intr(struct bce_softc *sc, int count, uint16_t hw_cons)
4380 struct ifnet *ifp = &sc->arpcom.ac_if;
4381 uint16_t sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4382 uint32_t sw_prod_bseq;
4384 ASSERT_SERIALIZED(ifp->if_serializer);
4386 /* Get working copies of the driver's view of the RX indices. */
4387 sw_cons = sc->rx_cons;
4388 sw_prod = sc->rx_prod;
4389 sw_prod_bseq = sc->rx_prod_bseq;
4391 /* Scan through the receive chain as long as there is work to do. */
4392 while (sw_cons != hw_cons) {
4393 struct mbuf *m = NULL;
4394 struct l2_fhdr *l2fhdr = NULL;
4397 uint32_t status = 0;
4399 #ifdef DEVICE_POLLING
4400 if (count >= 0 && count-- == 0)
4405 * Convert the producer/consumer indices
4406 * to an actual rx_bd index.
4408 sw_chain_cons = RX_CHAIN_IDX(sc, sw_cons);
4409 sw_chain_prod = RX_CHAIN_IDX(sc, sw_prod);
4411 /* Get the used rx_bd. */
4412 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4413 [RX_IDX(sw_chain_cons)];
4416 /* The mbuf is stored with the last rx_bd entry of a packet. */
4417 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4418 if (sw_chain_cons != sw_chain_prod) {
4419 if_printf(ifp, "RX cons(%d) != prod(%d), "
4420 "drop!\n", sw_chain_cons,
4424 bce_setup_rxdesc_std(sc, sw_chain_cons,
4427 goto bce_rx_int_next_rx;
4430 /* Unmap the mbuf from DMA space. */
4431 bus_dmamap_sync(sc->rx_mbuf_tag,
4432 sc->rx_mbuf_map[sw_chain_cons],
4433 BUS_DMASYNC_POSTREAD);
4435 /* Save the mbuf from the driver's chain. */
4436 m = sc->rx_mbuf_ptr[sw_chain_cons];
4439 * Frames received on the NetXteme II are prepended
4440 * with an l2_fhdr structure which provides status
4441 * information about the received frame (including
4442 * VLAN tags and checksum info). The frames are also
4443 * automatically adjusted to align the IP header
4444 * (i.e. two null bytes are inserted before the
4445 * Ethernet header). As a result the data DMA'd by
4446 * the controller into the mbuf is as follows:
4448 * +---------+-----+---------------------+-----+
4449 * | l2_fhdr | pad | packet data | FCS |
4450 * +---------+-----+---------------------+-----+
4452 * The l2_fhdr needs to be checked and skipped and the
4453 * FCS needs to be stripped before sending the packet
4456 l2fhdr = mtod(m, struct l2_fhdr *);
4458 len = l2fhdr->l2_fhdr_pkt_len;
4459 status = l2fhdr->l2_fhdr_status;
4461 len -= ETHER_CRC_LEN;
4463 /* Check the received frame for errors. */
4464 if (status & (L2_FHDR_ERRORS_BAD_CRC |
4465 L2_FHDR_ERRORS_PHY_DECODE |
4466 L2_FHDR_ERRORS_ALIGNMENT |
4467 L2_FHDR_ERRORS_TOO_SHORT |
4468 L2_FHDR_ERRORS_GIANT_FRAME)) {
4471 /* Reuse the mbuf for a new frame. */
4472 bce_setup_rxdesc_std(sc, sw_chain_prod,
4475 goto bce_rx_int_next_rx;
4479 * Get a new mbuf for the rx_bd. If no new
4480 * mbufs are available then reuse the current mbuf,
4481 * log an ierror on the interface, and generate
4482 * an error in the system log.
4484 if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4485 &sw_prod_bseq, 0)) {
4488 /* Try and reuse the exisitng mbuf. */
4489 bce_setup_rxdesc_std(sc, sw_chain_prod,
4492 goto bce_rx_int_next_rx;
4496 * Skip over the l2_fhdr when passing
4497 * the data up the stack.
4499 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4501 m->m_pkthdr.len = m->m_len = len;
4502 m->m_pkthdr.rcvif = ifp;
4504 /* Validate the checksum if offload enabled. */
4505 if (ifp->if_capenable & IFCAP_RXCSUM) {
4506 /* Check for an IP datagram. */
4507 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4508 m->m_pkthdr.csum_flags |=
4511 /* Check if the IP checksum is valid. */
4512 if ((l2fhdr->l2_fhdr_ip_xsum ^
4514 m->m_pkthdr.csum_flags |=
4519 /* Check for a valid TCP/UDP frame. */
4520 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4521 L2_FHDR_STATUS_UDP_DATAGRAM)) {
4523 /* Check for a good TCP/UDP checksum. */
4525 (L2_FHDR_ERRORS_TCP_XSUM |
4526 L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4527 m->m_pkthdr.csum_data =
4528 l2fhdr->l2_fhdr_tcp_udp_xsum;
4529 m->m_pkthdr.csum_flags |=
4538 sw_prod = NEXT_RX_BD(sw_prod);
4541 sw_cons = NEXT_RX_BD(sw_cons);
4543 /* If we have a packet, pass it up the stack */
4545 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4546 m->m_flags |= M_VLANTAG;
4547 m->m_pkthdr.ether_vlantag =
4548 l2fhdr->l2_fhdr_vlan_tag;
4550 ifp->if_input(ifp, m);
4554 sc->rx_cons = sw_cons;
4555 sc->rx_prod = sw_prod;
4556 sc->rx_prod_bseq = sw_prod_bseq;
4558 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4560 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4565 /****************************************************************************/
4566 /* Reads the transmit consumer value from the status block (skipping over */
4567 /* chain page pointer if necessary). */
4571 /****************************************************************************/
4572 static __inline uint16_t
4573 bce_get_hw_tx_cons(struct bce_softc *sc)
4575 uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4577 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4583 /****************************************************************************/
4584 /* Handles transmit completion interrupt events. */
4588 /****************************************************************************/
4590 bce_tx_intr(struct bce_softc *sc, uint16_t hw_tx_cons)
4592 struct ifnet *ifp = &sc->arpcom.ac_if;
4593 uint16_t sw_tx_cons, sw_tx_chain_cons;
4595 ASSERT_SERIALIZED(ifp->if_serializer);
4597 /* Get the hardware's view of the TX consumer index. */
4598 sw_tx_cons = sc->tx_cons;
4600 /* Cycle through any completed TX chain page entries. */
4601 while (sw_tx_cons != hw_tx_cons) {
4602 sw_tx_chain_cons = TX_CHAIN_IDX(sc, sw_tx_cons);
4605 * Free the associated mbuf. Remember
4606 * that only the last tx_bd of a packet
4607 * has an mbuf pointer and DMA map.
4609 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4610 /* Unmap the mbuf. */
4611 bus_dmamap_unload(sc->tx_mbuf_tag,
4612 sc->tx_mbuf_map[sw_tx_chain_cons]);
4614 /* Free the mbuf. */
4615 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4616 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4622 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4625 if (sc->used_tx_bd == 0) {
4626 /* Clear the TX timeout timer. */
4630 /* Clear the tx hardware queue full flag. */
4631 if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE)
4632 ifp->if_flags &= ~IFF_OACTIVE;
4633 sc->tx_cons = sw_tx_cons;
4637 /****************************************************************************/
4638 /* Disables interrupt generation. */
4642 /****************************************************************************/
4644 bce_disable_intr(struct bce_softc *sc)
4646 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4647 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4648 lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4652 /****************************************************************************/
4653 /* Enables interrupt generation. */
4657 /****************************************************************************/
4659 bce_enable_intr(struct bce_softc *sc)
4661 lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4663 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4664 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4665 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4666 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4667 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4669 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4673 /****************************************************************************/
4674 /* Reenables interrupt generation during interrupt handling. */
4678 /****************************************************************************/
4680 bce_reenable_intr(struct bce_softc *sc)
4682 if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
4683 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4684 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4685 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4687 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4688 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4691 /****************************************************************************/
4692 /* Handles controller initialization. */
4696 /****************************************************************************/
4700 struct bce_softc *sc = xsc;
4701 struct ifnet *ifp = &sc->arpcom.ac_if;
4705 ASSERT_SERIALIZED(ifp->if_serializer);
4707 /* Check if the driver is still running and bail out if it is. */
4708 if (ifp->if_flags & IFF_RUNNING)
4713 error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4715 if_printf(ifp, "Controller reset failed!\n");
4719 error = bce_chipinit(sc);
4721 if_printf(ifp, "Controller initialization failed!\n");
4725 error = bce_blockinit(sc);
4727 if_printf(ifp, "Block initialization failed!\n");
4731 /* Load our MAC address. */
4732 bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4733 bce_set_mac_addr(sc);
4735 /* Calculate and program the Ethernet MTU size. */
4736 ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4738 DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4741 * Program the mtu, enabling jumbo frame
4742 * support if necessary. Also set the mbuf
4743 * allocation count for RX frames.
4745 if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4747 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4748 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4749 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4750 sc->mbuf_alloc_size = MJUM9BYTES;
4752 panic("jumbo buffer is not supported yet");
4755 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4756 sc->mbuf_alloc_size = MCLBYTES;
4759 /* Calculate the RX Ethernet frame size for rx_bd's. */
4760 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4762 DBPRINT(sc, BCE_INFO,
4763 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4764 "max_frame_size = %d\n",
4765 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4766 sc->max_frame_size);
4768 /* Program appropriate promiscuous/multicast filtering. */
4769 bce_set_rx_mode(sc);
4771 /* Init RX buffer descriptor chain. */
4772 bce_init_rx_chain(sc); /* XXX return value */
4774 /* Init TX buffer descriptor chain. */
4775 bce_init_tx_chain(sc); /* XXX return value */
4777 #ifdef DEVICE_POLLING
4778 /* Disable interrupts if we are polling. */
4779 if (ifp->if_flags & IFF_POLLING) {
4780 bce_disable_intr(sc);
4782 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4783 (1 << 16) | sc->bce_rx_quick_cons_trip);
4784 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4785 (1 << 16) | sc->bce_tx_quick_cons_trip);
4788 /* Enable host interrupts. */
4789 bce_enable_intr(sc);
4791 bce_ifmedia_upd(ifp);
4793 ifp->if_flags |= IFF_RUNNING;
4794 ifp->if_flags &= ~IFF_OACTIVE;
4796 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4803 /****************************************************************************/
4804 /* Initialize the controller just enough so that any management firmware */
4805 /* running on the device will continue to operate corectly. */
4809 /****************************************************************************/
4811 bce_mgmt_init(struct bce_softc *sc)
4813 struct ifnet *ifp = &sc->arpcom.ac_if;
4815 /* Bail out if management firmware is not running. */
4816 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4819 /* Enable all critical blocks in the MAC. */
4820 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4821 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4822 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4823 BCE_MISC_ENABLE_DEFAULT_XI);
4825 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4827 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4830 bce_ifmedia_upd(ifp);
4834 /****************************************************************************/
4835 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4836 /* memory visible to the controller. */
4839 /* 0 for success, positive value for failure. */
4840 /****************************************************************************/
4842 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4844 bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4845 bus_dmamap_t map, tmp_map;
4846 struct mbuf *m0 = *m_head;
4847 struct tx_bd *txbd = NULL;
4848 uint16_t vlan_tag = 0, flags = 0;
4849 uint16_t chain_prod, chain_prod_start, prod;
4851 int i, error, maxsegs, nsegs;
4853 uint16_t debug_prod;
4856 /* Transfer any checksum offload flags to the bd. */
4857 if (m0->m_pkthdr.csum_flags) {
4858 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4859 flags |= TX_BD_FLAGS_IP_CKSUM;
4860 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4861 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4864 /* Transfer any VLAN tags to the bd. */
4865 if (m0->m_flags & M_VLANTAG) {
4866 flags |= TX_BD_FLAGS_VLAN_TAG;
4867 vlan_tag = m0->m_pkthdr.ether_vlantag;
4871 chain_prod_start = chain_prod = TX_CHAIN_IDX(sc, prod);
4873 /* Map the mbuf into DMAable memory. */
4874 map = sc->tx_mbuf_map[chain_prod_start];
4876 maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4877 KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4878 ("not enough segments %d", maxsegs));
4879 if (maxsegs > BCE_MAX_SEGMENTS)
4880 maxsegs = BCE_MAX_SEGMENTS;
4882 /* Map the mbuf into our DMA address space. */
4883 error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
4884 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4887 bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4892 /* prod points to an empty tx_bd at this point. */
4893 prod_bseq = sc->tx_prod_bseq;
4896 debug_prod = chain_prod;
4899 DBPRINT(sc, BCE_INFO_SEND,
4900 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4901 "prod_bseq = 0x%08X\n",
4902 __func__, prod, chain_prod, prod_bseq);
4905 * Cycle through each mbuf segment that makes up
4906 * the outgoing frame, gathering the mapping info
4907 * for that segment and creating a tx_bd to for
4910 for (i = 0; i < nsegs; i++) {
4911 chain_prod = TX_CHAIN_IDX(sc, prod);
4912 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4914 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4915 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4916 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4917 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4918 txbd->tx_bd_flags = htole16(flags);
4919 prod_bseq += segs[i].ds_len;
4921 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4922 prod = NEXT_TX_BD(prod);
4925 /* Set the END flag on the last TX buffer descriptor. */
4926 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4928 DBRUN(BCE_EXCESSIVE_SEND,
4929 bce_dump_tx_chain(sc, debug_prod, nsegs));
4931 DBPRINT(sc, BCE_INFO_SEND,
4932 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
4933 "prod_bseq = 0x%08X\n",
4934 __func__, prod, chain_prod, prod_bseq);
4937 * Ensure that the mbuf pointer for this transmission
4938 * is placed at the array index of the last
4939 * descriptor in this chain. This is done
4940 * because a single map is used for all
4941 * segments of the mbuf and we don't want to
4942 * unload the map before all of the segments
4945 sc->tx_mbuf_ptr[chain_prod] = m0;
4947 tmp_map = sc->tx_mbuf_map[chain_prod];
4948 sc->tx_mbuf_map[chain_prod] = map;
4949 sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4951 sc->used_tx_bd += nsegs;
4953 /* Update some debug statistic counters */
4954 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
4955 sc->tx_hi_watermark = sc->used_tx_bd);
4956 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
4957 DBRUNIF(1, sc->tx_mbuf_alloc++);
4959 DBRUN(BCE_VERBOSE_SEND,
4960 bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs));
4962 /* prod points to the next free tx_bd at this point. */
4964 sc->tx_prod_bseq = prod_bseq;
4974 /****************************************************************************/
4975 /* Main transmit routine when called from another routine with a lock. */
4979 /****************************************************************************/
4981 bce_start(struct ifnet *ifp)
4983 struct bce_softc *sc = ifp->if_softc;
4986 ASSERT_SERIALIZED(ifp->if_serializer);
4988 /* If there's no link or the transmit queue is empty then just exit. */
4989 if (!sc->bce_link) {
4990 ifq_purge(&ifp->if_snd);
4994 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
4997 DBPRINT(sc, BCE_INFO_SEND,
4998 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04zX, "
4999 "tx_prod_bseq = 0x%08X\n",
5001 sc->tx_prod, TX_CHAIN_IDX(sc, sc->tx_prod), sc->tx_prod_bseq);
5004 struct mbuf *m_head;
5007 * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
5010 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
5011 ifp->if_flags |= IFF_OACTIVE;
5015 /* Check for any frames to send. */
5016 m_head = ifq_dequeue(&ifp->if_snd, NULL);
5021 * Pack the data into the transmit ring. If we
5022 * don't have room, place the mbuf back at the
5023 * head of the queue and set the OACTIVE flag
5024 * to wait for the NIC to drain the chain.
5026 if (bce_encap(sc, &m_head)) {
5028 if (sc->used_tx_bd == 0) {
5031 ifp->if_flags |= IFF_OACTIVE;
5038 /* Send a copy of the frame to any BPF listeners. */
5039 ETHER_BPF_MTAP(ifp, m_head);
5043 /* no packets were dequeued */
5044 DBPRINT(sc, BCE_VERBOSE_SEND,
5045 "%s(): No packets were dequeued\n", __func__);
5049 DBPRINT(sc, BCE_INFO_SEND,
5050 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04zX, "
5051 "tx_prod_bseq = 0x%08X\n",
5053 sc->tx_prod, TX_CHAIN_IDX(sc, sc->tx_prod), sc->tx_prod_bseq);
5055 REG_WR(sc, BCE_MQ_COMMAND,
5056 REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
5058 /* Start the transmit. */
5059 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
5060 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
5062 /* Set the tx timeout. */
5063 ifp->if_timer = BCE_TX_TIMEOUT;
5067 /****************************************************************************/
5068 /* Handles any IOCTL calls from the operating system. */
5071 /* 0 for success, positive value for failure. */
5072 /****************************************************************************/
5074 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
5076 struct bce_softc *sc = ifp->if_softc;
5077 struct ifreq *ifr = (struct ifreq *)data;
5078 struct mii_data *mii;
5079 int mask, error = 0;
5081 ASSERT_SERIALIZED(ifp->if_serializer);
5085 /* Check that the MTU setting is supported. */
5086 if (ifr->ifr_mtu < BCE_MIN_MTU ||
5088 ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
5090 ifr->ifr_mtu > ETHERMTU
5097 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
5099 ifp->if_mtu = ifr->ifr_mtu;
5100 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
5105 if (ifp->if_flags & IFF_UP) {
5106 if (ifp->if_flags & IFF_RUNNING) {
5107 mask = ifp->if_flags ^ sc->bce_if_flags;
5109 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
5110 bce_set_rx_mode(sc);
5114 } else if (ifp->if_flags & IFF_RUNNING) {
5117 /* If MFW is running, restart the controller a bit. */
5118 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5119 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5124 sc->bce_if_flags = ifp->if_flags;
5129 if (ifp->if_flags & IFF_RUNNING)
5130 bce_set_rx_mode(sc);
5135 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
5137 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5139 mii = device_get_softc(sc->bce_miibus);
5140 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5144 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5145 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5148 if (mask & IFCAP_HWCSUM) {
5149 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5150 if (IFCAP_HWCSUM & ifp->if_capenable)
5151 ifp->if_hwassist = BCE_IF_HWASSIST;
5153 ifp->if_hwassist = 0;
5158 error = ether_ioctl(ifp, command, data);
5165 /****************************************************************************/
5166 /* Transmit timeout handler. */
5170 /****************************************************************************/
5172 bce_watchdog(struct ifnet *ifp)
5174 struct bce_softc *sc = ifp->if_softc;
5176 ASSERT_SERIALIZED(ifp->if_serializer);
5178 DBRUN(BCE_VERBOSE_SEND,
5179 bce_dump_driver_state(sc);
5180 bce_dump_status_block(sc));
5183 * If we are in this routine because of pause frames, then
5184 * don't reset the hardware.
5186 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5189 if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5191 /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5193 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
5198 if (!ifq_is_empty(&ifp->if_snd))
5203 #ifdef DEVICE_POLLING
5206 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5208 struct bce_softc *sc = ifp->if_softc;
5209 struct status_block *sblk = sc->status_block;
5210 uint16_t hw_tx_cons, hw_rx_cons;
5212 ASSERT_SERIALIZED(ifp->if_serializer);
5216 bce_disable_intr(sc);
5218 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5219 (1 << 16) | sc->bce_rx_quick_cons_trip);
5220 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5221 (1 << 16) | sc->bce_tx_quick_cons_trip);
5223 case POLL_DEREGISTER:
5224 bce_enable_intr(sc);
5226 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5227 (sc->bce_tx_quick_cons_trip_int << 16) |
5228 sc->bce_tx_quick_cons_trip);
5229 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5230 (sc->bce_rx_quick_cons_trip_int << 16) |
5231 sc->bce_rx_quick_cons_trip);
5238 * Save the status block index value for use when enabling
5241 sc->last_status_idx = sblk->status_idx;
5243 /* Make sure status index is extracted before rx/tx cons */
5246 if (cmd == POLL_AND_CHECK_STATUS) {
5247 uint32_t status_attn_bits;
5249 status_attn_bits = sblk->status_attn_bits;
5251 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5253 "Simulating unexpected status attention bit set.");
5254 status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5256 /* Was it a link change interrupt? */
5257 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5258 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5261 /* Clear any transient status updates during link state change. */
5262 REG_WR(sc, BCE_HC_COMMAND,
5263 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5264 REG_RD(sc, BCE_HC_COMMAND);
5267 * If any other attention is asserted then
5268 * the chip is toast.
5270 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5271 (sblk->status_attn_bits_ack &
5272 ~STATUS_ATTN_BITS_LINK_STATE)) {
5273 DBRUN(1, sc->unexpected_attentions++);
5275 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5276 sblk->status_attn_bits);
5279 if (bce_debug_unexpected_attention == 0)
5280 bce_breakpoint(sc));
5287 hw_rx_cons = bce_get_hw_rx_cons(sc);
5288 hw_tx_cons = bce_get_hw_tx_cons(sc);
5290 /* Check for any completed RX frames. */
5291 if (hw_rx_cons != sc->rx_cons)
5292 bce_rx_intr(sc, count, hw_rx_cons);
5294 /* Check for any completed TX frames. */
5295 if (hw_tx_cons != sc->tx_cons)
5296 bce_tx_intr(sc, hw_tx_cons);
5298 /* Check for new frames to transmit. */
5299 if (!ifq_is_empty(&ifp->if_snd))
5303 #endif /* DEVICE_POLLING */
5307 * Interrupt handler.
5309 /****************************************************************************/
5310 /* Main interrupt entry point. Verifies that the controller generated the */
5311 /* interrupt and then calls a separate routine for handle the various */
5312 /* interrupt causes (PHY, TX, RX). */
5315 /* 0 for success, positive value for failure. */
5316 /****************************************************************************/
5318 bce_intr(struct bce_softc *sc)
5320 struct ifnet *ifp = &sc->arpcom.ac_if;
5321 struct status_block *sblk;
5322 uint16_t hw_rx_cons, hw_tx_cons;
5323 uint32_t status_attn_bits;
5325 ASSERT_SERIALIZED(ifp->if_serializer);
5327 sblk = sc->status_block;
5330 * Save the status block index value for use during
5331 * the next interrupt.
5333 sc->last_status_idx = sblk->status_idx;
5335 /* Make sure status index is extracted before rx/tx cons */
5338 /* Check if the hardware has finished any work. */
5339 hw_rx_cons = bce_get_hw_rx_cons(sc);
5340 hw_tx_cons = bce_get_hw_tx_cons(sc);
5342 status_attn_bits = sblk->status_attn_bits;
5344 /* Was it a link change interrupt? */
5345 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5346 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5350 * Clear any transient status updates during link state
5353 REG_WR(sc, BCE_HC_COMMAND,
5354 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5355 REG_RD(sc, BCE_HC_COMMAND);
5359 * If any other attention is asserted then
5360 * the chip is toast.
5362 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5363 (sblk->status_attn_bits_ack & ~STATUS_ATTN_BITS_LINK_STATE)) {
5364 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5365 sblk->status_attn_bits);
5370 /* Check for any completed RX frames. */
5371 if (hw_rx_cons != sc->rx_cons)
5372 bce_rx_intr(sc, -1, hw_rx_cons);
5374 /* Check for any completed TX frames. */
5375 if (hw_tx_cons != sc->tx_cons)
5376 bce_tx_intr(sc, hw_tx_cons);
5378 /* Re-enable interrupts. */
5379 bce_reenable_intr(sc);
5381 if (sc->bce_coalchg_mask)
5382 bce_coal_change(sc);
5384 /* Handle any frames that arrived while handling the interrupt. */
5385 if (!ifq_is_empty(&ifp->if_snd))
5390 bce_intr_legacy(void *xsc)
5392 struct bce_softc *sc = xsc;
5393 struct status_block *sblk;
5395 sblk = sc->status_block;
5398 * If the hardware status block index matches the last value
5399 * read by the driver and we haven't asserted our interrupt
5400 * then there's nothing to do.
5402 if (sblk->status_idx == sc->last_status_idx &&
5403 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5404 BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5407 /* Ack the interrupt and stop others from occuring. */
5408 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5409 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5410 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5413 * Read back to deassert IRQ immediately to avoid too
5414 * many spurious interrupts.
5416 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
5422 bce_intr_msi(void *xsc)
5424 struct bce_softc *sc = xsc;
5426 /* Ack the interrupt and stop others from occuring. */
5427 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5428 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5429 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5435 bce_intr_msi_oneshot(void *xsc)
5441 /****************************************************************************/
5442 /* Programs the various packet receive modes (broadcast and multicast). */
5446 /****************************************************************************/
5448 bce_set_rx_mode(struct bce_softc *sc)
5450 struct ifnet *ifp = &sc->arpcom.ac_if;
5451 struct ifmultiaddr *ifma;
5452 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5453 uint32_t rx_mode, sort_mode;
5456 ASSERT_SERIALIZED(ifp->if_serializer);
5458 /* Initialize receive mode default settings. */
5459 rx_mode = sc->rx_mode &
5460 ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5461 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5462 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5465 * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5468 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5469 !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5470 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5473 * Check for promiscuous, all multicast, or selected
5474 * multicast address filtering.
5476 if (ifp->if_flags & IFF_PROMISC) {
5477 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5479 /* Enable promiscuous mode. */
5480 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5481 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5482 } else if (ifp->if_flags & IFF_ALLMULTI) {
5483 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5485 /* Enable all multicast addresses. */
5486 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5487 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5490 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5492 /* Accept one or more multicast(s). */
5493 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5495 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5496 if (ifma->ifma_addr->sa_family != AF_LINK)
5499 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5500 ETHER_ADDR_LEN) & 0xFF;
5501 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5504 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5505 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5508 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5511 /* Only make changes if the recive mode has actually changed. */
5512 if (rx_mode != sc->rx_mode) {
5513 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5516 sc->rx_mode = rx_mode;
5517 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5520 /* Disable and clear the exisitng sort before enabling a new sort. */
5521 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5522 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5523 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5527 /****************************************************************************/
5528 /* Called periodically to updates statistics from the controllers */
5529 /* statistics block. */
5533 /****************************************************************************/
5535 bce_stats_update(struct bce_softc *sc)
5537 struct ifnet *ifp = &sc->arpcom.ac_if;
5538 struct statistics_block *stats = sc->stats_block;
5540 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5542 ASSERT_SERIALIZED(ifp->if_serializer);
5545 * Certain controllers don't report carrier sense errors correctly.
5546 * See errata E11_5708CA0_1165.
5548 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5549 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5551 (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5555 * Update the sysctl statistics from the hardware statistics.
5557 sc->stat_IfHCInOctets =
5558 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5559 (uint64_t)stats->stat_IfHCInOctets_lo;
5561 sc->stat_IfHCInBadOctets =
5562 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5563 (uint64_t)stats->stat_IfHCInBadOctets_lo;
5565 sc->stat_IfHCOutOctets =
5566 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5567 (uint64_t)stats->stat_IfHCOutOctets_lo;
5569 sc->stat_IfHCOutBadOctets =
5570 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5571 (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5573 sc->stat_IfHCInUcastPkts =
5574 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5575 (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5577 sc->stat_IfHCInMulticastPkts =
5578 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5579 (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5581 sc->stat_IfHCInBroadcastPkts =
5582 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5583 (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5585 sc->stat_IfHCOutUcastPkts =
5586 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5587 (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5589 sc->stat_IfHCOutMulticastPkts =
5590 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5591 (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5593 sc->stat_IfHCOutBroadcastPkts =
5594 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5595 (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5597 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5598 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5600 sc->stat_Dot3StatsCarrierSenseErrors =
5601 stats->stat_Dot3StatsCarrierSenseErrors;
5603 sc->stat_Dot3StatsFCSErrors =
5604 stats->stat_Dot3StatsFCSErrors;
5606 sc->stat_Dot3StatsAlignmentErrors =
5607 stats->stat_Dot3StatsAlignmentErrors;
5609 sc->stat_Dot3StatsSingleCollisionFrames =
5610 stats->stat_Dot3StatsSingleCollisionFrames;
5612 sc->stat_Dot3StatsMultipleCollisionFrames =
5613 stats->stat_Dot3StatsMultipleCollisionFrames;
5615 sc->stat_Dot3StatsDeferredTransmissions =
5616 stats->stat_Dot3StatsDeferredTransmissions;
5618 sc->stat_Dot3StatsExcessiveCollisions =
5619 stats->stat_Dot3StatsExcessiveCollisions;
5621 sc->stat_Dot3StatsLateCollisions =
5622 stats->stat_Dot3StatsLateCollisions;
5624 sc->stat_EtherStatsCollisions =
5625 stats->stat_EtherStatsCollisions;
5627 sc->stat_EtherStatsFragments =
5628 stats->stat_EtherStatsFragments;
5630 sc->stat_EtherStatsJabbers =
5631 stats->stat_EtherStatsJabbers;
5633 sc->stat_EtherStatsUndersizePkts =
5634 stats->stat_EtherStatsUndersizePkts;
5636 sc->stat_EtherStatsOverrsizePkts =
5637 stats->stat_EtherStatsOverrsizePkts;
5639 sc->stat_EtherStatsPktsRx64Octets =
5640 stats->stat_EtherStatsPktsRx64Octets;
5642 sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5643 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5645 sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5646 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5648 sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5649 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5651 sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5652 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5654 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5655 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5657 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5658 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5660 sc->stat_EtherStatsPktsTx64Octets =
5661 stats->stat_EtherStatsPktsTx64Octets;
5663 sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5664 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5666 sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5667 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5669 sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5670 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5672 sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5673 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5675 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5676 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5678 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5679 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5681 sc->stat_XonPauseFramesReceived =
5682 stats->stat_XonPauseFramesReceived;
5684 sc->stat_XoffPauseFramesReceived =
5685 stats->stat_XoffPauseFramesReceived;
5687 sc->stat_OutXonSent =
5688 stats->stat_OutXonSent;
5690 sc->stat_OutXoffSent =
5691 stats->stat_OutXoffSent;
5693 sc->stat_FlowControlDone =
5694 stats->stat_FlowControlDone;
5696 sc->stat_MacControlFramesReceived =
5697 stats->stat_MacControlFramesReceived;
5699 sc->stat_XoffStateEntered =
5700 stats->stat_XoffStateEntered;
5702 sc->stat_IfInFramesL2FilterDiscards =
5703 stats->stat_IfInFramesL2FilterDiscards;
5705 sc->stat_IfInRuleCheckerDiscards =
5706 stats->stat_IfInRuleCheckerDiscards;
5708 sc->stat_IfInFTQDiscards =
5709 stats->stat_IfInFTQDiscards;
5711 sc->stat_IfInMBUFDiscards =
5712 stats->stat_IfInMBUFDiscards;
5714 sc->stat_IfInRuleCheckerP4Hit =
5715 stats->stat_IfInRuleCheckerP4Hit;
5717 sc->stat_CatchupInRuleCheckerDiscards =
5718 stats->stat_CatchupInRuleCheckerDiscards;
5720 sc->stat_CatchupInFTQDiscards =
5721 stats->stat_CatchupInFTQDiscards;
5723 sc->stat_CatchupInMBUFDiscards =
5724 stats->stat_CatchupInMBUFDiscards;
5726 sc->stat_CatchupInRuleCheckerP4Hit =
5727 stats->stat_CatchupInRuleCheckerP4Hit;
5729 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5732 * Update the interface statistics from the
5733 * hardware statistics.
5735 ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5737 ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5738 (u_long)sc->stat_EtherStatsOverrsizePkts +
5739 (u_long)sc->stat_IfInMBUFDiscards +
5740 (u_long)sc->stat_Dot3StatsAlignmentErrors +
5741 (u_long)sc->stat_Dot3StatsFCSErrors +
5742 (u_long)sc->stat_IfInRuleCheckerDiscards +
5743 (u_long)sc->stat_IfInFTQDiscards +
5744 (u_long)sc->com_no_buffers;
5747 (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5748 (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5749 (u_long)sc->stat_Dot3StatsLateCollisions;
5751 DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5755 /****************************************************************************/
5756 /* Periodic function to notify the bootcode that the driver is still */
5761 /****************************************************************************/
5763 bce_pulse(void *xsc)
5765 struct bce_softc *sc = xsc;
5766 struct ifnet *ifp = &sc->arpcom.ac_if;
5769 lwkt_serialize_enter(ifp->if_serializer);
5771 if (ifp->if_flags & IFF_RUNNING) {
5772 if (sc->bce_irq_type == PCI_INTR_TYPE_MSI &&
5773 (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) == 0)
5774 bce_pulse_check_msi(sc);
5777 /* Tell the firmware that the driver is still running. */
5778 msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5779 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
5781 /* Update the bootcode condition. */
5782 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
5784 /* Report whether the bootcode still knows the driver is running. */
5785 if (!sc->bce_drv_cardiac_arrest) {
5786 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
5787 sc->bce_drv_cardiac_arrest = 1;
5788 if_printf(ifp, "Bootcode lost the driver pulse! "
5789 "(bc_state = 0x%08X)\n", sc->bc_state);
5793 * Not supported by all bootcode versions.
5794 * (v5.0.11+ and v5.2.1+) Older bootcode
5795 * will require the driver to reset the
5796 * controller to clear this condition.
5798 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
5799 sc->bce_drv_cardiac_arrest = 0;
5800 if_printf(ifp, "Bootcode found the driver pulse! "
5801 "(bc_state = 0x%08X)\n", sc->bc_state);
5805 /* Schedule the next pulse. */
5806 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
5808 lwkt_serialize_exit(ifp->if_serializer);
5812 bce_pulse_check_msi(struct bce_softc *sc)
5816 if (bce_get_hw_rx_cons(sc) != sc->rx_cons) {
5818 } else if (bce_get_hw_tx_cons(sc) != sc->tx_cons) {
5821 struct status_block *sblk = sc->status_block;
5823 if ((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5824 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5831 msi_ctrl = REG_RD(sc, BCE_PCICFG_MSI_CONTROL);
5832 if ((msi_ctrl & BCE_PCICFG_MSI_CONTROL_ENABLE) == 0)
5835 if (sc->pulse_check_status_idx == sc->last_status_idx) {
5836 if_printf(&sc->arpcom.ac_if, "missing MSI\n");
5838 REG_WR(sc, BCE_PCICFG_MSI_CONTROL,
5839 msi_ctrl & ~BCE_PCICFG_MSI_CONTROL_ENABLE);
5840 REG_WR(sc, BCE_PCICFG_MSI_CONTROL, msi_ctrl);
5845 sc->pulse_check_status_idx = sc->last_status_idx;
5848 /****************************************************************************/
5849 /* Periodic function to perform maintenance tasks. */
5853 /****************************************************************************/
5855 bce_tick_serialized(struct bce_softc *sc)
5857 struct ifnet *ifp = &sc->arpcom.ac_if;
5858 struct mii_data *mii;
5860 ASSERT_SERIALIZED(ifp->if_serializer);
5862 /* Update the statistics from the hardware statistics block. */
5863 bce_stats_update(sc);
5865 /* Schedule the next tick. */
5866 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
5868 /* If link is up already up then we're done. */
5872 mii = device_get_softc(sc->bce_miibus);
5875 /* Check if the link has come up. */
5876 if ((mii->mii_media_status & IFM_ACTIVE) &&
5877 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5879 /* Now that link is up, handle any outstanding TX traffic. */
5880 if (!ifq_is_empty(&ifp->if_snd))
5889 struct bce_softc *sc = xsc;
5890 struct ifnet *ifp = &sc->arpcom.ac_if;
5892 lwkt_serialize_enter(ifp->if_serializer);
5893 bce_tick_serialized(sc);
5894 lwkt_serialize_exit(ifp->if_serializer);
5899 /****************************************************************************/
5900 /* Allows the driver state to be dumped through the sysctl interface. */
5903 /* 0 for success, positive value for failure. */
5904 /****************************************************************************/
5906 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5910 struct bce_softc *sc;
5913 error = sysctl_handle_int(oidp, &result, 0, req);
5915 if (error || !req->newptr)
5919 sc = (struct bce_softc *)arg1;
5920 bce_dump_driver_state(sc);
5927 /****************************************************************************/
5928 /* Allows the hardware state to be dumped through the sysctl interface. */
5931 /* 0 for success, positive value for failure. */
5932 /****************************************************************************/
5934 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5938 struct bce_softc *sc;
5941 error = sysctl_handle_int(oidp, &result, 0, req);
5943 if (error || !req->newptr)
5947 sc = (struct bce_softc *)arg1;
5948 bce_dump_hw_state(sc);
5955 /****************************************************************************/
5956 /* Provides a sysctl interface to allows dumping the RX chain. */
5959 /* 0 for success, positive value for failure. */
5960 /****************************************************************************/
5962 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
5966 struct bce_softc *sc;
5969 error = sysctl_handle_int(oidp, &result, 0, req);
5971 if (error || !req->newptr)
5975 sc = (struct bce_softc *)arg1;
5976 bce_dump_rx_chain(sc, 0, USABLE_RX_BD(sc));
5983 /****************************************************************************/
5984 /* Provides a sysctl interface to allows dumping the TX chain. */
5987 /* 0 for success, positive value for failure. */
5988 /****************************************************************************/
5990 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
5994 struct bce_softc *sc;
5997 error = sysctl_handle_int(oidp, &result, 0, req);
5999 if (error || !req->newptr)
6003 sc = (struct bce_softc *)arg1;
6004 bce_dump_tx_chain(sc, 0, USABLE_TX_BD(sc));
6011 /****************************************************************************/
6012 /* Provides a sysctl interface to allow reading arbitrary registers in the */
6013 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6016 /* 0 for success, positive value for failure. */
6017 /****************************************************************************/
6019 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6021 struct bce_softc *sc;
6023 uint32_t val, result;
6026 error = sysctl_handle_int(oidp, &result, 0, req);
6027 if (error || (req->newptr == NULL))
6030 /* Make sure the register is accessible. */
6031 if (result < 0x8000) {
6032 sc = (struct bce_softc *)arg1;
6033 val = REG_RD(sc, result);
6034 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6036 } else if (result < 0x0280000) {
6037 sc = (struct bce_softc *)arg1;
6038 val = REG_RD_IND(sc, result);
6039 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6046 /****************************************************************************/
6047 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */
6048 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6051 /* 0 for success, positive value for failure. */
6052 /****************************************************************************/
6054 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
6056 struct bce_softc *sc;
6062 error = sysctl_handle_int(oidp, &result, 0, req);
6063 if (error || (req->newptr == NULL))
6066 /* Make sure the register is accessible. */
6067 if (result < 0x20) {
6068 sc = (struct bce_softc *)arg1;
6070 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
6071 if_printf(&sc->arpcom.ac_if,
6072 "phy 0x%02X = 0x%04X\n", result, val);
6078 /****************************************************************************/
6079 /* Provides a sysctl interface to forcing the driver to dump state and */
6080 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6083 /* 0 for success, positive value for failure. */
6084 /****************************************************************************/
6086 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
6090 struct bce_softc *sc;
6093 error = sysctl_handle_int(oidp, &result, 0, req);
6095 if (error || !req->newptr)
6099 sc = (struct bce_softc *)arg1;
6108 /****************************************************************************/
6109 /* Adds any sysctl parameters for tuning or debugging purposes. */
6112 /* 0 for success, positive value for failure. */
6113 /****************************************************************************/
6115 bce_add_sysctls(struct bce_softc *sc)
6117 struct sysctl_ctx_list *ctx;
6118 struct sysctl_oid_list *children;
6120 sysctl_ctx_init(&sc->bce_sysctl_ctx);
6121 sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
6122 SYSCTL_STATIC_CHILDREN(_hw),
6124 device_get_nameunit(sc->bce_dev),
6126 if (sc->bce_sysctl_tree == NULL) {
6127 device_printf(sc->bce_dev, "can't add sysctl node\n");
6131 ctx = &sc->bce_sysctl_ctx;
6132 children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
6134 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
6135 CTLTYPE_INT | CTLFLAG_RW,
6136 sc, 0, bce_sysctl_tx_bds_int, "I",
6137 "Send max coalesced BD count during interrupt");
6138 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
6139 CTLTYPE_INT | CTLFLAG_RW,
6140 sc, 0, bce_sysctl_tx_bds, "I",
6141 "Send max coalesced BD count");
6142 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
6143 CTLTYPE_INT | CTLFLAG_RW,
6144 sc, 0, bce_sysctl_tx_ticks_int, "I",
6145 "Send coalescing ticks during interrupt");
6146 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
6147 CTLTYPE_INT | CTLFLAG_RW,
6148 sc, 0, bce_sysctl_tx_ticks, "I",
6149 "Send coalescing ticks");
6151 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
6152 CTLTYPE_INT | CTLFLAG_RW,
6153 sc, 0, bce_sysctl_rx_bds_int, "I",
6154 "Receive max coalesced BD count during interrupt");
6155 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
6156 CTLTYPE_INT | CTLFLAG_RW,
6157 sc, 0, bce_sysctl_rx_bds, "I",
6158 "Receive max coalesced BD count");
6159 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
6160 CTLTYPE_INT | CTLFLAG_RW,
6161 sc, 0, bce_sysctl_rx_ticks_int, "I",
6162 "Receive coalescing ticks during interrupt");
6163 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
6164 CTLTYPE_INT | CTLFLAG_RW,
6165 sc, 0, bce_sysctl_rx_ticks, "I",
6166 "Receive coalescing ticks");
6168 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_pages",
6169 CTLFLAG_RD, &sc->rx_pages, 0, "# of RX pages");
6170 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_pages",
6171 CTLFLAG_RD, &sc->tx_pages, 0, "# of TX pages");
6174 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6176 CTLFLAG_RD, &sc->rx_low_watermark,
6177 0, "Lowest level of free rx_bd's");
6179 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6181 CTLFLAG_RD, &sc->rx_empty_count,
6182 0, "Number of times the RX chain was empty");
6184 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6186 CTLFLAG_RD, &sc->tx_hi_watermark,
6187 0, "Highest level of used tx_bd's");
6189 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6191 CTLFLAG_RD, &sc->tx_full_count,
6192 0, "Number of times the TX chain was full");
6194 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6195 "l2fhdr_status_errors",
6196 CTLFLAG_RD, &sc->l2fhdr_status_errors,
6197 0, "l2_fhdr status errors");
6199 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6200 "unexpected_attentions",
6201 CTLFLAG_RD, &sc->unexpected_attentions,
6202 0, "unexpected attentions");
6204 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6205 "lost_status_block_updates",
6206 CTLFLAG_RD, &sc->lost_status_block_updates,
6207 0, "lost status block updates");
6209 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6210 "mbuf_alloc_failed",
6211 CTLFLAG_RD, &sc->mbuf_alloc_failed,
6212 0, "mbuf cluster allocation failures");
6215 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6216 "stat_IfHCInOctets",
6217 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6220 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6221 "stat_IfHCInBadOctets",
6222 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6223 "Bad bytes received");
6225 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6226 "stat_IfHCOutOctets",
6227 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6230 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6231 "stat_IfHCOutBadOctets",
6232 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6235 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6236 "stat_IfHCInUcastPkts",
6237 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6238 "Unicast packets received");
6240 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6241 "stat_IfHCInMulticastPkts",
6242 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6243 "Multicast packets received");
6245 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6246 "stat_IfHCInBroadcastPkts",
6247 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6248 "Broadcast packets received");
6250 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6251 "stat_IfHCOutUcastPkts",
6252 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6253 "Unicast packets sent");
6255 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6256 "stat_IfHCOutMulticastPkts",
6257 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6258 "Multicast packets sent");
6260 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6261 "stat_IfHCOutBroadcastPkts",
6262 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6263 "Broadcast packets sent");
6265 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6266 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6267 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6268 0, "Internal MAC transmit errors");
6270 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6271 "stat_Dot3StatsCarrierSenseErrors",
6272 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6273 0, "Carrier sense errors");
6275 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6276 "stat_Dot3StatsFCSErrors",
6277 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6278 0, "Frame check sequence errors");
6280 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6281 "stat_Dot3StatsAlignmentErrors",
6282 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6283 0, "Alignment errors");
6285 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6286 "stat_Dot3StatsSingleCollisionFrames",
6287 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6288 0, "Single Collision Frames");
6290 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6291 "stat_Dot3StatsMultipleCollisionFrames",
6292 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6293 0, "Multiple Collision Frames");
6295 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6296 "stat_Dot3StatsDeferredTransmissions",
6297 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6298 0, "Deferred Transmissions");
6300 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6301 "stat_Dot3StatsExcessiveCollisions",
6302 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6303 0, "Excessive Collisions");
6305 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6306 "stat_Dot3StatsLateCollisions",
6307 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6308 0, "Late Collisions");
6310 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6311 "stat_EtherStatsCollisions",
6312 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6315 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6316 "stat_EtherStatsFragments",
6317 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6320 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6321 "stat_EtherStatsJabbers",
6322 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6325 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6326 "stat_EtherStatsUndersizePkts",
6327 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6328 0, "Undersize packets");
6330 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6331 "stat_EtherStatsOverrsizePkts",
6332 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6333 0, "stat_EtherStatsOverrsizePkts");
6335 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6336 "stat_EtherStatsPktsRx64Octets",
6337 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6338 0, "Bytes received in 64 byte packets");
6340 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6341 "stat_EtherStatsPktsRx65Octetsto127Octets",
6342 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6343 0, "Bytes received in 65 to 127 byte packets");
6345 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6346 "stat_EtherStatsPktsRx128Octetsto255Octets",
6347 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6348 0, "Bytes received in 128 to 255 byte packets");
6350 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6351 "stat_EtherStatsPktsRx256Octetsto511Octets",
6352 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6353 0, "Bytes received in 256 to 511 byte packets");
6355 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6356 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6357 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6358 0, "Bytes received in 512 to 1023 byte packets");
6360 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6361 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6362 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6363 0, "Bytes received in 1024 t0 1522 byte packets");
6365 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6366 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6367 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6368 0, "Bytes received in 1523 to 9022 byte packets");
6370 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6371 "stat_EtherStatsPktsTx64Octets",
6372 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6373 0, "Bytes sent in 64 byte packets");
6375 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6376 "stat_EtherStatsPktsTx65Octetsto127Octets",
6377 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6378 0, "Bytes sent in 65 to 127 byte packets");
6380 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6381 "stat_EtherStatsPktsTx128Octetsto255Octets",
6382 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6383 0, "Bytes sent in 128 to 255 byte packets");
6385 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6386 "stat_EtherStatsPktsTx256Octetsto511Octets",
6387 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6388 0, "Bytes sent in 256 to 511 byte packets");
6390 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6391 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6392 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6393 0, "Bytes sent in 512 to 1023 byte packets");
6395 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6396 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6397 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6398 0, "Bytes sent in 1024 to 1522 byte packets");
6400 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6401 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6402 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6403 0, "Bytes sent in 1523 to 9022 byte packets");
6405 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6406 "stat_XonPauseFramesReceived",
6407 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6408 0, "XON pause frames receved");
6410 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6411 "stat_XoffPauseFramesReceived",
6412 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6413 0, "XOFF pause frames received");
6415 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6417 CTLFLAG_RD, &sc->stat_OutXonSent,
6418 0, "XON pause frames sent");
6420 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6422 CTLFLAG_RD, &sc->stat_OutXoffSent,
6423 0, "XOFF pause frames sent");
6425 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6426 "stat_FlowControlDone",
6427 CTLFLAG_RD, &sc->stat_FlowControlDone,
6428 0, "Flow control done");
6430 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6431 "stat_MacControlFramesReceived",
6432 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6433 0, "MAC control frames received");
6435 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6436 "stat_XoffStateEntered",
6437 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6438 0, "XOFF state entered");
6440 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6441 "stat_IfInFramesL2FilterDiscards",
6442 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6443 0, "Received L2 packets discarded");
6445 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6446 "stat_IfInRuleCheckerDiscards",
6447 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6448 0, "Received packets discarded by rule");
6450 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6451 "stat_IfInFTQDiscards",
6452 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6453 0, "Received packet FTQ discards");
6455 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6456 "stat_IfInMBUFDiscards",
6457 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6458 0, "Received packets discarded due to lack of controller buffer memory");
6460 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6461 "stat_IfInRuleCheckerP4Hit",
6462 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6463 0, "Received packets rule checker hits");
6465 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6466 "stat_CatchupInRuleCheckerDiscards",
6467 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6468 0, "Received packets discarded in Catchup path");
6470 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6471 "stat_CatchupInFTQDiscards",
6472 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6473 0, "Received packets discarded in FTQ in Catchup path");
6475 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6476 "stat_CatchupInMBUFDiscards",
6477 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6478 0, "Received packets discarded in controller buffer memory in Catchup path");
6480 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6481 "stat_CatchupInRuleCheckerP4Hit",
6482 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6483 0, "Received packets rule checker hits in Catchup path");
6485 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6487 CTLFLAG_RD, &sc->com_no_buffers,
6488 0, "Valid packets received but no RX buffers available");
6491 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6492 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6494 bce_sysctl_driver_state, "I", "Drive state information");
6496 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6497 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6499 bce_sysctl_hw_state, "I", "Hardware state information");
6501 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6502 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6504 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6506 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6507 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6509 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6511 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6512 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6514 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6516 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6517 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6519 bce_sysctl_reg_read, "I", "Register read");
6521 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6522 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6524 bce_sysctl_phy_read, "I", "PHY register read");
6531 /****************************************************************************/
6532 /* BCE Debug Routines */
6533 /****************************************************************************/
6536 /****************************************************************************/
6537 /* Freezes the controller to allow for a cohesive state dump. */
6541 /****************************************************************************/
6543 bce_freeze_controller(struct bce_softc *sc)
6547 val = REG_RD(sc, BCE_MISC_COMMAND);
6548 val |= BCE_MISC_COMMAND_DISABLE_ALL;
6549 REG_WR(sc, BCE_MISC_COMMAND, val);
6553 /****************************************************************************/
6554 /* Unfreezes the controller after a freeze operation. This may not always */
6555 /* work and the controller will require a reset! */
6559 /****************************************************************************/
6561 bce_unfreeze_controller(struct bce_softc *sc)
6565 val = REG_RD(sc, BCE_MISC_COMMAND);
6566 val |= BCE_MISC_COMMAND_ENABLE_ALL;
6567 REG_WR(sc, BCE_MISC_COMMAND, val);
6571 /****************************************************************************/
6572 /* Prints out information about an mbuf. */
6576 /****************************************************************************/
6578 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6580 struct ifnet *ifp = &sc->arpcom.ac_if;
6581 uint32_t val_hi, val_lo;
6582 struct mbuf *mp = m;
6585 /* Index out of range. */
6586 if_printf(ifp, "mbuf: null pointer\n");
6591 val_hi = BCE_ADDR_HI(mp);
6592 val_lo = BCE_ADDR_LO(mp);
6593 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6594 "m_flags = ( ", val_hi, val_lo, mp->m_len);
6596 if (mp->m_flags & M_EXT)
6598 if (mp->m_flags & M_PKTHDR)
6599 kprintf("M_PKTHDR ");
6600 if (mp->m_flags & M_EOR)
6603 if (mp->m_flags & M_RDONLY)
6604 kprintf("M_RDONLY ");
6607 val_hi = BCE_ADDR_HI(mp->m_data);
6608 val_lo = BCE_ADDR_LO(mp->m_data);
6609 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6611 if (mp->m_flags & M_PKTHDR) {
6612 if_printf(ifp, "- m_pkthdr: flags = ( ");
6613 if (mp->m_flags & M_BCAST)
6614 kprintf("M_BCAST ");
6615 if (mp->m_flags & M_MCAST)
6616 kprintf("M_MCAST ");
6617 if (mp->m_flags & M_FRAG)
6619 if (mp->m_flags & M_FIRSTFRAG)
6620 kprintf("M_FIRSTFRAG ");
6621 if (mp->m_flags & M_LASTFRAG)
6622 kprintf("M_LASTFRAG ");
6624 if (mp->m_flags & M_VLANTAG)
6625 kprintf("M_VLANTAG ");
6628 if (mp->m_flags & M_PROMISC)
6629 kprintf("M_PROMISC ");
6631 kprintf(") csum_flags = ( ");
6632 if (mp->m_pkthdr.csum_flags & CSUM_IP)
6633 kprintf("CSUM_IP ");
6634 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6635 kprintf("CSUM_TCP ");
6636 if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6637 kprintf("CSUM_UDP ");
6638 if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6639 kprintf("CSUM_IP_FRAGS ");
6640 if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6641 kprintf("CSUM_FRAGMENT ");
6643 if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6644 kprintf("CSUM_TSO ");
6646 if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6647 kprintf("CSUM_IP_CHECKED ");
6648 if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6649 kprintf("CSUM_IP_VALID ");
6650 if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6651 kprintf("CSUM_DATA_VALID ");
6655 if (mp->m_flags & M_EXT) {
6656 val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6657 val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6658 if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6660 val_hi, val_lo, mp->m_ext.ext_size);
6667 /****************************************************************************/
6668 /* Prints out the mbufs in the TX mbuf chain. */
6672 /****************************************************************************/
6674 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6676 struct ifnet *ifp = &sc->arpcom.ac_if;
6680 "----------------------------"
6682 "----------------------------\n");
6684 for (i = 0; i < count; i++) {
6685 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6686 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6687 chain_prod = TX_CHAIN_IDX(sc, NEXT_TX_BD(chain_prod));
6691 "----------------------------"
6693 "----------------------------\n");
6697 /****************************************************************************/
6698 /* Prints out the mbufs in the RX mbuf chain. */
6702 /****************************************************************************/
6704 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6706 struct ifnet *ifp = &sc->arpcom.ac_if;
6710 "----------------------------"
6712 "----------------------------\n");
6714 for (i = 0; i < count; i++) {
6715 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6716 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6717 chain_prod = RX_CHAIN_IDX(sc, NEXT_RX_BD(chain_prod));
6721 "----------------------------"
6723 "----------------------------\n");
6727 /****************************************************************************/
6728 /* Prints out a tx_bd structure. */
6732 /****************************************************************************/
6734 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6736 struct ifnet *ifp = &sc->arpcom.ac_if;
6738 if (idx > MAX_TX_BD(sc)) {
6739 /* Index out of range. */
6740 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6741 } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6742 /* TX Chain page pointer. */
6743 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6744 "chain page pointer\n",
6745 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6747 /* Normal tx_bd entry. */
6748 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6750 "vlan tag= 0x%04X, flags = 0x%04X (",
6751 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6752 txbd->tx_bd_mss_nbytes,
6753 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6755 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6756 kprintf(" CONN_FAULT");
6758 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6759 kprintf(" TCP_UDP_CKSUM");
6761 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6762 kprintf(" IP_CKSUM");
6764 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6767 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6768 kprintf(" COAL_NOW");
6770 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6771 kprintf(" DONT_GEN_CRC");
6773 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6776 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6779 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6782 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6783 kprintf(" OPTION_WORD");
6785 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6788 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6796 /****************************************************************************/
6797 /* Prints out a rx_bd structure. */
6801 /****************************************************************************/
6803 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6805 struct ifnet *ifp = &sc->arpcom.ac_if;
6807 if (idx > MAX_RX_BD(sc)) {
6808 /* Index out of range. */
6809 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6810 } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6811 /* TX Chain page pointer. */
6812 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6813 "chain page pointer\n",
6814 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6816 /* Normal tx_bd entry. */
6817 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6818 "nbytes = 0x%08X, flags = 0x%08X\n",
6819 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6820 rxbd->rx_bd_len, rxbd->rx_bd_flags);
6825 /****************************************************************************/
6826 /* Prints out a l2_fhdr structure. */
6830 /****************************************************************************/
6832 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6834 if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6835 "pkt_len = 0x%04X, vlan = 0x%04x, "
6836 "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6837 idx, l2fhdr->l2_fhdr_status,
6838 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6839 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6843 /****************************************************************************/
6844 /* Prints out the tx chain. */
6848 /****************************************************************************/
6850 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6852 struct ifnet *ifp = &sc->arpcom.ac_if;
6855 /* First some info about the tx_bd chain structure. */
6857 "----------------------------"
6859 "----------------------------\n");
6861 if_printf(ifp, "page size = 0x%08X, "
6862 "tx chain pages = 0x%08X\n",
6863 (uint32_t)BCM_PAGE_SIZE, (uint32_t)sc->tx_pages);
6865 if_printf(ifp, "tx_bd per page = 0x%08X, "
6866 "usable tx_bd per page = 0x%08X\n",
6867 (uint32_t)TOTAL_TX_BD_PER_PAGE,
6868 (uint32_t)USABLE_TX_BD_PER_PAGE);
6870 if_printf(ifp, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD(sc));
6873 "----------------------------"
6875 "----------------------------\n");
6877 /* Now print out the tx_bd's themselves. */
6878 for (i = 0; i < count; i++) {
6881 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6882 bce_dump_txbd(sc, tx_prod, txbd);
6883 tx_prod = TX_CHAIN_IDX(sc, NEXT_TX_BD(tx_prod));
6887 "----------------------------"
6889 "----------------------------\n");
6893 /****************************************************************************/
6894 /* Prints out the rx chain. */
6898 /****************************************************************************/
6900 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6902 struct ifnet *ifp = &sc->arpcom.ac_if;
6905 /* First some info about the tx_bd chain structure. */
6907 "----------------------------"
6909 "----------------------------\n");
6911 if_printf(ifp, "page size = 0x%08X, "
6912 "rx chain pages = 0x%08X\n",
6913 (uint32_t)BCM_PAGE_SIZE, (uint32_t)sc->rx_pages);
6915 if_printf(ifp, "rx_bd per page = 0x%08X, "
6916 "usable rx_bd per page = 0x%08X\n",
6917 (uint32_t)TOTAL_RX_BD_PER_PAGE,
6918 (uint32_t)USABLE_RX_BD_PER_PAGE);
6920 if_printf(ifp, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD(sc));
6923 "----------------------------"
6925 "----------------------------\n");
6927 /* Now print out the rx_bd's themselves. */
6928 for (i = 0; i < count; i++) {
6931 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6932 bce_dump_rxbd(sc, rx_prod, rxbd);
6933 rx_prod = RX_CHAIN_IDX(sc, NEXT_RX_BD(rx_prod));
6937 "----------------------------"
6939 "----------------------------\n");
6943 /****************************************************************************/
6944 /* Prints out the status block from host memory. */
6948 /****************************************************************************/
6950 bce_dump_status_block(struct bce_softc *sc)
6952 struct status_block *sblk = sc->status_block;
6953 struct ifnet *ifp = &sc->arpcom.ac_if;
6956 "----------------------------"
6958 "----------------------------\n");
6960 if_printf(ifp, " 0x%08X - attn_bits\n", sblk->status_attn_bits);
6962 if_printf(ifp, " 0x%08X - attn_bits_ack\n",
6963 sblk->status_attn_bits_ack);
6965 if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6966 sblk->status_rx_quick_consumer_index0,
6967 (uint16_t)RX_CHAIN_IDX(sc, sblk->status_rx_quick_consumer_index0));
6969 if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6970 sblk->status_tx_quick_consumer_index0,
6971 (uint16_t)TX_CHAIN_IDX(sc, sblk->status_tx_quick_consumer_index0));
6973 if_printf(ifp, " 0x%04X - status_idx\n", sblk->status_idx);
6975 /* Theses indices are not used for normal L2 drivers. */
6976 if (sblk->status_rx_quick_consumer_index1) {
6977 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6978 sblk->status_rx_quick_consumer_index1,
6979 (uint16_t)RX_CHAIN_IDX(sc,
6980 sblk->status_rx_quick_consumer_index1));
6983 if (sblk->status_tx_quick_consumer_index1) {
6984 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
6985 sblk->status_tx_quick_consumer_index1,
6986 (uint16_t)TX_CHAIN_IDX(sc,
6987 sblk->status_tx_quick_consumer_index1));
6990 if (sblk->status_rx_quick_consumer_index2) {
6991 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
6992 sblk->status_rx_quick_consumer_index2,
6993 (uint16_t)RX_CHAIN_IDX(sc,
6994 sblk->status_rx_quick_consumer_index2));
6997 if (sblk->status_tx_quick_consumer_index2) {
6998 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
6999 sblk->status_tx_quick_consumer_index2,
7000 (uint16_t)TX_CHAIN_IDX(sc,
7001 sblk->status_tx_quick_consumer_index2));
7004 if (sblk->status_rx_quick_consumer_index3) {
7005 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
7006 sblk->status_rx_quick_consumer_index3,
7007 (uint16_t)RX_CHAIN_IDX(sc,
7008 sblk->status_rx_quick_consumer_index3));
7011 if (sblk->status_tx_quick_consumer_index3) {
7012 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
7013 sblk->status_tx_quick_consumer_index3,
7014 (uint16_t)TX_CHAIN_IDX(sc,
7015 sblk->status_tx_quick_consumer_index3));
7018 if (sblk->status_rx_quick_consumer_index4 ||
7019 sblk->status_rx_quick_consumer_index5) {
7020 if_printf(ifp, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n",
7021 sblk->status_rx_quick_consumer_index4,
7022 sblk->status_rx_quick_consumer_index5);
7025 if (sblk->status_rx_quick_consumer_index6 ||
7026 sblk->status_rx_quick_consumer_index7) {
7027 if_printf(ifp, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n",
7028 sblk->status_rx_quick_consumer_index6,
7029 sblk->status_rx_quick_consumer_index7);
7032 if (sblk->status_rx_quick_consumer_index8 ||
7033 sblk->status_rx_quick_consumer_index9) {
7034 if_printf(ifp, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n",
7035 sblk->status_rx_quick_consumer_index8,
7036 sblk->status_rx_quick_consumer_index9);
7039 if (sblk->status_rx_quick_consumer_index10 ||
7040 sblk->status_rx_quick_consumer_index11) {
7041 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n",
7042 sblk->status_rx_quick_consumer_index10,
7043 sblk->status_rx_quick_consumer_index11);
7046 if (sblk->status_rx_quick_consumer_index12 ||
7047 sblk->status_rx_quick_consumer_index13) {
7048 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n",
7049 sblk->status_rx_quick_consumer_index12,
7050 sblk->status_rx_quick_consumer_index13);
7053 if (sblk->status_rx_quick_consumer_index14 ||
7054 sblk->status_rx_quick_consumer_index15) {
7055 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n",
7056 sblk->status_rx_quick_consumer_index14,
7057 sblk->status_rx_quick_consumer_index15);
7060 if (sblk->status_completion_producer_index ||
7061 sblk->status_cmd_consumer_index) {
7062 if_printf(ifp, "com_prod = 0x%08X, cmd_cons = 0x%08X\n",
7063 sblk->status_completion_producer_index,
7064 sblk->status_cmd_consumer_index);
7068 "----------------------------"
7070 "----------------------------\n");
7074 /****************************************************************************/
7075 /* Prints out the statistics block. */
7079 /****************************************************************************/
7081 bce_dump_stats_block(struct bce_softc *sc)
7083 struct statistics_block *sblk = sc->stats_block;
7084 struct ifnet *ifp = &sc->arpcom.ac_if;
7088 " Stats Block (All Stats Not Shown Are 0) "
7089 "---------------\n");
7091 if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
7092 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
7093 sblk->stat_IfHCInOctets_hi,
7094 sblk->stat_IfHCInOctets_lo);
7097 if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
7098 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
7099 sblk->stat_IfHCInBadOctets_hi,
7100 sblk->stat_IfHCInBadOctets_lo);
7103 if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
7104 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
7105 sblk->stat_IfHCOutOctets_hi,
7106 sblk->stat_IfHCOutOctets_lo);
7109 if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
7110 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
7111 sblk->stat_IfHCOutBadOctets_hi,
7112 sblk->stat_IfHCOutBadOctets_lo);
7115 if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
7116 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
7117 sblk->stat_IfHCInUcastPkts_hi,
7118 sblk->stat_IfHCInUcastPkts_lo);
7121 if (sblk->stat_IfHCInBroadcastPkts_hi ||
7122 sblk->stat_IfHCInBroadcastPkts_lo) {
7123 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
7124 sblk->stat_IfHCInBroadcastPkts_hi,
7125 sblk->stat_IfHCInBroadcastPkts_lo);
7128 if (sblk->stat_IfHCInMulticastPkts_hi ||
7129 sblk->stat_IfHCInMulticastPkts_lo) {
7130 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
7131 sblk->stat_IfHCInMulticastPkts_hi,
7132 sblk->stat_IfHCInMulticastPkts_lo);
7135 if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
7136 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
7137 sblk->stat_IfHCOutUcastPkts_hi,
7138 sblk->stat_IfHCOutUcastPkts_lo);
7141 if (sblk->stat_IfHCOutBroadcastPkts_hi ||
7142 sblk->stat_IfHCOutBroadcastPkts_lo) {
7143 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
7144 sblk->stat_IfHCOutBroadcastPkts_hi,
7145 sblk->stat_IfHCOutBroadcastPkts_lo);
7148 if (sblk->stat_IfHCOutMulticastPkts_hi ||
7149 sblk->stat_IfHCOutMulticastPkts_lo) {
7150 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
7151 sblk->stat_IfHCOutMulticastPkts_hi,
7152 sblk->stat_IfHCOutMulticastPkts_lo);
7155 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
7156 if_printf(ifp, " 0x%08X : "
7157 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
7158 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
7161 if (sblk->stat_Dot3StatsCarrierSenseErrors) {
7162 if_printf(ifp, " 0x%08X : "
7163 "Dot3StatsCarrierSenseErrors\n",
7164 sblk->stat_Dot3StatsCarrierSenseErrors);
7167 if (sblk->stat_Dot3StatsFCSErrors) {
7168 if_printf(ifp, " 0x%08X : Dot3StatsFCSErrors\n",
7169 sblk->stat_Dot3StatsFCSErrors);
7172 if (sblk->stat_Dot3StatsAlignmentErrors) {
7173 if_printf(ifp, " 0x%08X : Dot3StatsAlignmentErrors\n",
7174 sblk->stat_Dot3StatsAlignmentErrors);
7177 if (sblk->stat_Dot3StatsSingleCollisionFrames) {
7178 if_printf(ifp, " 0x%08X : "
7179 "Dot3StatsSingleCollisionFrames\n",
7180 sblk->stat_Dot3StatsSingleCollisionFrames);
7183 if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
7184 if_printf(ifp, " 0x%08X : "
7185 "Dot3StatsMultipleCollisionFrames\n",
7186 sblk->stat_Dot3StatsMultipleCollisionFrames);
7189 if (sblk->stat_Dot3StatsDeferredTransmissions) {
7190 if_printf(ifp, " 0x%08X : "
7191 "Dot3StatsDeferredTransmissions\n",
7192 sblk->stat_Dot3StatsDeferredTransmissions);
7195 if (sblk->stat_Dot3StatsExcessiveCollisions) {
7196 if_printf(ifp, " 0x%08X : "
7197 "Dot3StatsExcessiveCollisions\n",
7198 sblk->stat_Dot3StatsExcessiveCollisions);
7201 if (sblk->stat_Dot3StatsLateCollisions) {
7202 if_printf(ifp, " 0x%08X : Dot3StatsLateCollisions\n",
7203 sblk->stat_Dot3StatsLateCollisions);
7206 if (sblk->stat_EtherStatsCollisions) {
7207 if_printf(ifp, " 0x%08X : EtherStatsCollisions\n",
7208 sblk->stat_EtherStatsCollisions);
7211 if (sblk->stat_EtherStatsFragments) {
7212 if_printf(ifp, " 0x%08X : EtherStatsFragments\n",
7213 sblk->stat_EtherStatsFragments);
7216 if (sblk->stat_EtherStatsJabbers) {
7217 if_printf(ifp, " 0x%08X : EtherStatsJabbers\n",
7218 sblk->stat_EtherStatsJabbers);
7221 if (sblk->stat_EtherStatsUndersizePkts) {
7222 if_printf(ifp, " 0x%08X : EtherStatsUndersizePkts\n",
7223 sblk->stat_EtherStatsUndersizePkts);
7226 if (sblk->stat_EtherStatsOverrsizePkts) {
7227 if_printf(ifp, " 0x%08X : EtherStatsOverrsizePkts\n",
7228 sblk->stat_EtherStatsOverrsizePkts);
7231 if (sblk->stat_EtherStatsPktsRx64Octets) {
7232 if_printf(ifp, " 0x%08X : EtherStatsPktsRx64Octets\n",
7233 sblk->stat_EtherStatsPktsRx64Octets);
7236 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7237 if_printf(ifp, " 0x%08X : "
7238 "EtherStatsPktsRx65Octetsto127Octets\n",
7239 sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7242 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7243 if_printf(ifp, " 0x%08X : "
7244 "EtherStatsPktsRx128Octetsto255Octets\n",
7245 sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7248 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7249 if_printf(ifp, " 0x%08X : "
7250 "EtherStatsPktsRx256Octetsto511Octets\n",
7251 sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7254 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7255 if_printf(ifp, " 0x%08X : "
7256 "EtherStatsPktsRx512Octetsto1023Octets\n",
7257 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7260 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7261 if_printf(ifp, " 0x%08X : "
7262 "EtherStatsPktsRx1024Octetsto1522Octets\n",
7263 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7266 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7267 if_printf(ifp, " 0x%08X : "
7268 "EtherStatsPktsRx1523Octetsto9022Octets\n",
7269 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7272 if (sblk->stat_EtherStatsPktsTx64Octets) {
7273 if_printf(ifp, " 0x%08X : EtherStatsPktsTx64Octets\n",
7274 sblk->stat_EtherStatsPktsTx64Octets);
7277 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7278 if_printf(ifp, " 0x%08X : "
7279 "EtherStatsPktsTx65Octetsto127Octets\n",
7280 sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7283 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7284 if_printf(ifp, " 0x%08X : "
7285 "EtherStatsPktsTx128Octetsto255Octets\n",
7286 sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7289 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7290 if_printf(ifp, " 0x%08X : "
7291 "EtherStatsPktsTx256Octetsto511Octets\n",
7292 sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7295 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7296 if_printf(ifp, " 0x%08X : "
7297 "EtherStatsPktsTx512Octetsto1023Octets\n",
7298 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7301 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7302 if_printf(ifp, " 0x%08X : "
7303 "EtherStatsPktsTx1024Octetsto1522Octets\n",
7304 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7307 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7308 if_printf(ifp, " 0x%08X : "
7309 "EtherStatsPktsTx1523Octetsto9022Octets\n",
7310 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7313 if (sblk->stat_XonPauseFramesReceived) {
7314 if_printf(ifp, " 0x%08X : XonPauseFramesReceived\n",
7315 sblk->stat_XonPauseFramesReceived);
7318 if (sblk->stat_XoffPauseFramesReceived) {
7319 if_printf(ifp, " 0x%08X : XoffPauseFramesReceived\n",
7320 sblk->stat_XoffPauseFramesReceived);
7323 if (sblk->stat_OutXonSent) {
7324 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7325 sblk->stat_OutXonSent);
7328 if (sblk->stat_OutXoffSent) {
7329 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7330 sblk->stat_OutXoffSent);
7333 if (sblk->stat_FlowControlDone) {
7334 if_printf(ifp, " 0x%08X : FlowControlDone\n",
7335 sblk->stat_FlowControlDone);
7338 if (sblk->stat_MacControlFramesReceived) {
7339 if_printf(ifp, " 0x%08X : MacControlFramesReceived\n",
7340 sblk->stat_MacControlFramesReceived);
7343 if (sblk->stat_XoffStateEntered) {
7344 if_printf(ifp, " 0x%08X : XoffStateEntered\n",
7345 sblk->stat_XoffStateEntered);
7348 if (sblk->stat_IfInFramesL2FilterDiscards) {
7349 if_printf(ifp, " 0x%08X : IfInFramesL2FilterDiscards\n", sblk->stat_IfInFramesL2FilterDiscards);
7352 if (sblk->stat_IfInRuleCheckerDiscards) {
7353 if_printf(ifp, " 0x%08X : IfInRuleCheckerDiscards\n",
7354 sblk->stat_IfInRuleCheckerDiscards);
7357 if (sblk->stat_IfInFTQDiscards) {
7358 if_printf(ifp, " 0x%08X : IfInFTQDiscards\n",
7359 sblk->stat_IfInFTQDiscards);
7362 if (sblk->stat_IfInMBUFDiscards) {
7363 if_printf(ifp, " 0x%08X : IfInMBUFDiscards\n",
7364 sblk->stat_IfInMBUFDiscards);
7367 if (sblk->stat_IfInRuleCheckerP4Hit) {
7368 if_printf(ifp, " 0x%08X : IfInRuleCheckerP4Hit\n",
7369 sblk->stat_IfInRuleCheckerP4Hit);
7372 if (sblk->stat_CatchupInRuleCheckerDiscards) {
7373 if_printf(ifp, " 0x%08X : "
7374 "CatchupInRuleCheckerDiscards\n",
7375 sblk->stat_CatchupInRuleCheckerDiscards);
7378 if (sblk->stat_CatchupInFTQDiscards) {
7379 if_printf(ifp, " 0x%08X : CatchupInFTQDiscards\n",
7380 sblk->stat_CatchupInFTQDiscards);
7383 if (sblk->stat_CatchupInMBUFDiscards) {
7384 if_printf(ifp, " 0x%08X : CatchupInMBUFDiscards\n",
7385 sblk->stat_CatchupInMBUFDiscards);
7388 if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7389 if_printf(ifp, " 0x%08X : CatchupInRuleCheckerP4Hit\n",
7390 sblk->stat_CatchupInRuleCheckerP4Hit);
7394 "----------------------------"
7396 "----------------------------\n");
7400 /****************************************************************************/
7401 /* Prints out a summary of the driver state. */
7405 /****************************************************************************/
7407 bce_dump_driver_state(struct bce_softc *sc)
7409 struct ifnet *ifp = &sc->arpcom.ac_if;
7410 uint32_t val_hi, val_lo;
7413 "-----------------------------"
7415 "-----------------------------\n");
7417 val_hi = BCE_ADDR_HI(sc);
7418 val_lo = BCE_ADDR_LO(sc);
7419 if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7420 "virtual address\n", val_hi, val_lo);
7422 val_hi = BCE_ADDR_HI(sc->status_block);
7423 val_lo = BCE_ADDR_LO(sc->status_block);
7424 if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7425 "virtual address\n", val_hi, val_lo);
7427 val_hi = BCE_ADDR_HI(sc->stats_block);
7428 val_lo = BCE_ADDR_LO(sc->stats_block);
7429 if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7430 "virtual address\n", val_hi, val_lo);
7432 val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7433 val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7434 if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7435 "virtual adddress\n", val_hi, val_lo);
7437 val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7438 val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7439 if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7440 "virtual address\n", val_hi, val_lo);
7442 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7443 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7444 if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7445 "virtual address\n", val_hi, val_lo);
7447 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7448 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7449 if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7450 "virtual address\n", val_hi, val_lo);
7452 if_printf(ifp, " 0x%08X - (sc->interrupts_generated) "
7453 "h/w intrs\n", sc->interrupts_generated);
7455 if_printf(ifp, " 0x%08X - (sc->rx_interrupts) "
7456 "rx interrupts handled\n", sc->rx_interrupts);
7458 if_printf(ifp, " 0x%08X - (sc->tx_interrupts) "
7459 "tx interrupts handled\n", sc->tx_interrupts);
7461 if_printf(ifp, " 0x%08X - (sc->last_status_idx) "
7462 "status block index\n", sc->last_status_idx);
7464 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_prod) "
7465 "tx producer index\n",
7466 sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc, sc->tx_prod));
7468 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_cons) "
7469 "tx consumer index\n",
7470 sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc, sc->tx_cons));
7472 if_printf(ifp, " 0x%08X - (sc->tx_prod_bseq) "
7473 "tx producer bseq index\n", sc->tx_prod_bseq);
7475 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_prod) "
7476 "rx producer index\n",
7477 sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc, sc->rx_prod));
7479 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_cons) "
7480 "rx consumer index\n",
7481 sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc, sc->rx_cons));
7483 if_printf(ifp, " 0x%08X - (sc->rx_prod_bseq) "
7484 "rx producer bseq index\n", sc->rx_prod_bseq);
7486 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7487 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7489 if_printf(ifp, " 0x%08X - (sc->free_rx_bd) "
7490 "free rx_bd's\n", sc->free_rx_bd);
7492 if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7493 "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7495 if_printf(ifp, " 0x%08X - (sc->txmbuf_alloc) "
7496 "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7498 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7499 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7501 if_printf(ifp, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7504 if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7505 sc->tx_hi_watermark, sc->max_tx_bd);
7507 if_printf(ifp, " 0x%08X - (sc->mbuf_alloc_failed) "
7508 "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7511 "----------------------------"
7513 "----------------------------\n");
7517 /****************************************************************************/
7518 /* Prints out the hardware state through a summary of important registers, */
7519 /* followed by a complete register dump. */
7523 /****************************************************************************/
7525 bce_dump_hw_state(struct bce_softc *sc)
7527 struct ifnet *ifp = &sc->arpcom.ac_if;
7532 "----------------------------"
7534 "----------------------------\n");
7536 if_printf(ifp, "%s - bootcode version\n", sc->bce_bc_ver);
7538 val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7539 if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7540 val1, BCE_MISC_ENABLE_STATUS_BITS);
7542 val1 = REG_RD(sc, BCE_DMA_STATUS);
7543 if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7545 val1 = REG_RD(sc, BCE_CTX_STATUS);
7546 if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7548 val1 = REG_RD(sc, BCE_EMAC_STATUS);
7549 if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7550 val1, BCE_EMAC_STATUS);
7552 val1 = REG_RD(sc, BCE_RPM_STATUS);
7553 if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7555 val1 = REG_RD(sc, BCE_TBDR_STATUS);
7556 if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7557 val1, BCE_TBDR_STATUS);
7559 val1 = REG_RD(sc, BCE_TDMA_STATUS);
7560 if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7561 val1, BCE_TDMA_STATUS);
7563 val1 = REG_RD(sc, BCE_HC_STATUS);
7564 if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7566 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7567 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7568 val1, BCE_TXP_CPU_STATE);
7570 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7571 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7572 val1, BCE_TPAT_CPU_STATE);
7574 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7575 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7576 val1, BCE_RXP_CPU_STATE);
7578 val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7579 if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7580 val1, BCE_COM_CPU_STATE);
7582 val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7583 if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7584 val1, BCE_MCP_CPU_STATE);
7586 val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7587 if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7588 val1, BCE_CP_CPU_STATE);
7591 "----------------------------"
7593 "----------------------------\n");
7596 "----------------------------"
7598 "----------------------------\n");
7600 for (i = 0x400; i < 0x8000; i += 0x10) {
7601 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7603 REG_RD(sc, i + 0x4),
7604 REG_RD(sc, i + 0x8),
7605 REG_RD(sc, i + 0xc));
7609 "----------------------------"
7611 "----------------------------\n");
7615 /****************************************************************************/
7616 /* Prints out the TXP state. */
7620 /****************************************************************************/
7622 bce_dump_txp_state(struct bce_softc *sc)
7624 struct ifnet *ifp = &sc->arpcom.ac_if;
7629 "----------------------------"
7631 "----------------------------\n");
7633 val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7634 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7635 val1, BCE_TXP_CPU_MODE);
7637 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7638 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7639 val1, BCE_TXP_CPU_STATE);
7641 val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7642 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7643 val1, BCE_TXP_CPU_EVENT_MASK);
7646 "----------------------------"
7648 "----------------------------\n");
7650 for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7651 /* Skip the big blank spaces */
7652 if (i < 0x454000 && i > 0x5ffff) {
7653 if_printf(ifp, "0x%04X: "
7654 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7656 REG_RD_IND(sc, i + 0x4),
7657 REG_RD_IND(sc, i + 0x8),
7658 REG_RD_IND(sc, i + 0xc));
7663 "----------------------------"
7665 "----------------------------\n");
7669 /****************************************************************************/
7670 /* Prints out the RXP state. */
7674 /****************************************************************************/
7676 bce_dump_rxp_state(struct bce_softc *sc)
7678 struct ifnet *ifp = &sc->arpcom.ac_if;
7683 "----------------------------"
7685 "----------------------------\n");
7687 val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7688 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7689 val1, BCE_RXP_CPU_MODE);
7691 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7692 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7693 val1, BCE_RXP_CPU_STATE);
7695 val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7696 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7697 val1, BCE_RXP_CPU_EVENT_MASK);
7700 "----------------------------"
7702 "----------------------------\n");
7704 for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7705 /* Skip the big blank sapces */
7706 if (i < 0xc5400 && i > 0xdffff) {
7707 if_printf(ifp, "0x%04X: "
7708 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7710 REG_RD_IND(sc, i + 0x4),
7711 REG_RD_IND(sc, i + 0x8),
7712 REG_RD_IND(sc, i + 0xc));
7717 "----------------------------"
7719 "----------------------------\n");
7723 /****************************************************************************/
7724 /* Prints out the TPAT state. */
7728 /****************************************************************************/
7730 bce_dump_tpat_state(struct bce_softc *sc)
7732 struct ifnet *ifp = &sc->arpcom.ac_if;
7737 "----------------------------"
7739 "----------------------------\n");
7741 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7742 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7743 val1, BCE_TPAT_CPU_MODE);
7745 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7746 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7747 val1, BCE_TPAT_CPU_STATE);
7749 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7750 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7751 val1, BCE_TPAT_CPU_EVENT_MASK);
7754 "----------------------------"
7756 "----------------------------\n");
7758 for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7759 /* Skip the big blank spaces */
7760 if (i < 0x854000 && i > 0x9ffff) {
7761 if_printf(ifp, "0x%04X: "
7762 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7764 REG_RD_IND(sc, i + 0x4),
7765 REG_RD_IND(sc, i + 0x8),
7766 REG_RD_IND(sc, i + 0xc));
7771 "----------------------------"
7773 "----------------------------\n");
7777 /****************************************************************************/
7778 /* Prints out the driver state and then enters the debugger. */
7782 /****************************************************************************/
7784 bce_breakpoint(struct bce_softc *sc)
7787 bce_freeze_controller(sc);
7790 bce_dump_driver_state(sc);
7791 bce_dump_status_block(sc);
7792 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD(sc));
7793 bce_dump_hw_state(sc);
7794 bce_dump_txp_state(sc);
7797 bce_unfreeze_controller(sc);
7800 /* Call the debugger. */
7804 #endif /* BCE_DEBUG */
7807 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7809 struct bce_softc *sc = arg1;
7811 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7812 &sc->bce_tx_quick_cons_trip_int,
7813 BCE_COALMASK_TX_BDS_INT);
7817 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7819 struct bce_softc *sc = arg1;
7821 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7822 &sc->bce_tx_quick_cons_trip,
7823 BCE_COALMASK_TX_BDS);
7827 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7829 struct bce_softc *sc = arg1;
7831 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7832 &sc->bce_tx_ticks_int,
7833 BCE_COALMASK_TX_TICKS_INT);
7837 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7839 struct bce_softc *sc = arg1;
7841 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7843 BCE_COALMASK_TX_TICKS);
7847 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7849 struct bce_softc *sc = arg1;
7851 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7852 &sc->bce_rx_quick_cons_trip_int,
7853 BCE_COALMASK_RX_BDS_INT);
7857 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7859 struct bce_softc *sc = arg1;
7861 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7862 &sc->bce_rx_quick_cons_trip,
7863 BCE_COALMASK_RX_BDS);
7867 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7869 struct bce_softc *sc = arg1;
7871 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7872 &sc->bce_rx_ticks_int,
7873 BCE_COALMASK_RX_TICKS_INT);
7877 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7879 struct bce_softc *sc = arg1;
7881 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7883 BCE_COALMASK_RX_TICKS);
7887 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7888 uint32_t coalchg_mask)
7890 struct bce_softc *sc = arg1;
7891 struct ifnet *ifp = &sc->arpcom.ac_if;
7894 lwkt_serialize_enter(ifp->if_serializer);
7897 error = sysctl_handle_int(oidp, &v, 0, req);
7898 if (!error && req->newptr != NULL) {
7903 sc->bce_coalchg_mask |= coalchg_mask;
7907 lwkt_serialize_exit(ifp->if_serializer);
7912 bce_coal_change(struct bce_softc *sc)
7914 struct ifnet *ifp = &sc->arpcom.ac_if;
7916 ASSERT_SERIALIZED(ifp->if_serializer);
7918 if ((ifp->if_flags & IFF_RUNNING) == 0) {
7919 sc->bce_coalchg_mask = 0;
7923 if (sc->bce_coalchg_mask &
7924 (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
7925 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
7926 (sc->bce_tx_quick_cons_trip_int << 16) |
7927 sc->bce_tx_quick_cons_trip);
7929 if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
7930 sc->bce_tx_quick_cons_trip,
7931 sc->bce_tx_quick_cons_trip_int);
7935 if (sc->bce_coalchg_mask &
7936 (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
7937 REG_WR(sc, BCE_HC_TX_TICKS,
7938 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
7940 if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
7941 sc->bce_tx_ticks, sc->bce_tx_ticks_int);
7945 if (sc->bce_coalchg_mask &
7946 (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
7947 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
7948 (sc->bce_rx_quick_cons_trip_int << 16) |
7949 sc->bce_rx_quick_cons_trip);
7951 if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
7952 sc->bce_rx_quick_cons_trip,
7953 sc->bce_rx_quick_cons_trip_int);
7957 if (sc->bce_coalchg_mask &
7958 (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
7959 REG_WR(sc, BCE_HC_RX_TICKS,
7960 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
7962 if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
7963 sc->bce_rx_ticks, sc->bce_rx_ticks_int);
7967 sc->bce_coalchg_mask = 0;