1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/completion.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
39 #include <linux/kref.h>
40 #include <linux/workqueue.h>
44 /* General customization:
47 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
49 #define DRIVER_NAME "i915"
50 #define DRIVER_DESC "Intel Graphics"
51 #define DRIVER_DATE "20080730"
59 #define pipe_name(p) ((p) + 'A')
67 #define transcoder_name(t) ((t) + 'A')
74 #define plane_name(p) ((p) + 'A')
84 #define port_name(p) ((p) + 'A')
86 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
88 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
90 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
91 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
92 if ((intel_encoder)->base.crtc == (__crtc))
94 struct intel_pch_pll {
95 int refcount; /* count of number of CRTCs sharing this PLL */
96 int active; /* count of number of active CRTCs (i.e. DPMS on) */
97 bool on; /* is the PLL actually active? Disabled during modeset */
102 #define I915_NUM_PLLS 2
104 struct intel_ddi_plls {
110 /* Interface history:
113 * 1.2: Add Power Management
114 * 1.3: Add vblank support
115 * 1.4: Fix cmdbuffer path, add heap destroy
116 * 1.5: Add vblank pipe configuration
117 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
118 * - Support vertical blank on secondary display pipe
120 #define DRIVER_MAJOR 1
121 #define DRIVER_MINOR 6
122 #define DRIVER_PATCHLEVEL 0
124 #define WATCH_COHERENCY 0
125 #define WATCH_LISTS 0
128 #define I915_GEM_PHYS_CURSOR_0 1
129 #define I915_GEM_PHYS_CURSOR_1 2
130 #define I915_GEM_PHYS_OVERLAY_REGS 3
131 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
133 struct drm_i915_gem_phys_object {
135 drm_dma_handle_t *handle;
136 struct drm_i915_gem_object *cur_obj;
139 struct opregion_header;
140 struct opregion_acpi;
141 struct opregion_swsci;
142 struct opregion_asle;
143 struct drm_i915_private;
145 struct intel_opregion {
146 struct opregion_header __iomem *header;
147 struct opregion_acpi __iomem *acpi;
148 struct opregion_swsci __iomem *swsci;
149 struct opregion_asle __iomem *asle;
151 u32 __iomem *lid_state;
153 #define OPREGION_SIZE (8*1024)
155 struct intel_overlay;
156 struct intel_overlay_error_state;
158 struct drm_i915_master_private {
159 drm_local_map_t *sarea;
160 struct _drm_i915_sarea *sarea_priv;
162 #define I915_FENCE_REG_NONE -1
163 #define I915_MAX_NUM_FENCES 16
164 /* 16 fences + sign bit for FENCE_REG_NONE */
165 #define I915_MAX_NUM_FENCE_BITS 5
167 struct drm_i915_fence_reg {
168 struct list_head lru_list;
169 struct drm_i915_gem_object *obj;
173 struct sdvo_device_mapping {
182 struct intel_display_error_state;
184 struct drm_i915_error_state {
192 bool waiting[I915_NUM_RINGS];
193 u32 pipestat[I915_MAX_PIPES];
194 u32 tail[I915_NUM_RINGS];
195 u32 head[I915_NUM_RINGS];
196 u32 ctl[I915_NUM_RINGS];
197 u32 ipeir[I915_NUM_RINGS];
198 u32 ipehr[I915_NUM_RINGS];
199 u32 instdone[I915_NUM_RINGS];
200 u32 acthd[I915_NUM_RINGS];
201 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
202 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
203 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
204 /* our own tracking of ring head and tail */
205 u32 cpu_ring_head[I915_NUM_RINGS];
206 u32 cpu_ring_tail[I915_NUM_RINGS];
207 u32 error; /* gen6+ */
208 u32 err_int; /* gen7 */
209 u32 instpm[I915_NUM_RINGS];
210 u32 instps[I915_NUM_RINGS];
211 u32 extra_instdone[I915_NUM_INSTDONE_REG];
212 u32 seqno[I915_NUM_RINGS];
214 u32 fault_reg[I915_NUM_RINGS];
216 u32 faddr[I915_NUM_RINGS];
217 u64 fence[I915_MAX_NUM_FENCES];
219 struct drm_i915_error_ring {
220 struct drm_i915_error_object {
224 } *ringbuffer, *batchbuffer;
225 struct drm_i915_error_request {
231 } ring[I915_NUM_RINGS];
232 struct drm_i915_error_buffer {
239 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
246 } *active_bo, *pinned_bo;
247 u32 active_bo_count, pinned_bo_count;
248 struct intel_overlay_error_state *overlay;
249 struct intel_display_error_state *display;
252 struct drm_i915_display_funcs {
253 bool (*fbc_enabled)(struct drm_device *dev);
254 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
255 void (*disable_fbc)(struct drm_device *dev);
256 int (*get_display_clock_speed)(struct drm_device *dev);
257 int (*get_fifo_size)(struct drm_device *dev, int plane);
258 void (*update_wm)(struct drm_device *dev);
259 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
260 uint32_t sprite_width, int pixel_size);
261 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
262 struct drm_display_mode *mode);
263 void (*modeset_global_resources)(struct drm_device *dev);
264 int (*crtc_mode_set)(struct drm_crtc *crtc,
265 struct drm_display_mode *mode,
266 struct drm_display_mode *adjusted_mode,
268 struct drm_framebuffer *old_fb);
269 void (*crtc_enable)(struct drm_crtc *crtc);
270 void (*crtc_disable)(struct drm_crtc *crtc);
271 void (*off)(struct drm_crtc *crtc);
272 void (*write_eld)(struct drm_connector *connector,
273 struct drm_crtc *crtc);
274 void (*fdi_link_train)(struct drm_crtc *crtc);
275 void (*init_clock_gating)(struct drm_device *dev);
276 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
277 struct drm_framebuffer *fb,
278 struct drm_i915_gem_object *obj);
279 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
281 /* clock updates for mode set */
283 /* render clock increase/decrease */
284 /* display clock increase/decrease */
285 /* pll clock increase/decrease */
288 struct drm_i915_gt_funcs {
289 void (*force_wake_get)(struct drm_i915_private *dev_priv);
290 void (*force_wake_put)(struct drm_i915_private *dev_priv);
293 #define DEV_INFO_FLAGS \
294 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
295 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
296 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
297 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
298 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
299 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
300 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
301 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
302 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
303 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
304 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
305 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
306 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
307 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
308 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
309 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
310 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
311 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
312 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
313 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
314 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
315 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
316 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
317 DEV_INFO_FLAG(has_llc)
319 struct intel_device_info {
338 u8 cursor_needs_physical:1;
340 u8 overlay_needs_physical:1;
347 #define I915_PPGTT_PD_ENTRIES 512
348 #define I915_PPGTT_PT_ENTRIES 1024
349 struct i915_hw_ppgtt {
350 struct drm_device *dev;
351 unsigned num_pd_entries;
354 vm_paddr_t *pt_dma_addr;
355 vm_paddr_t scratch_page_dma_addr;
359 /* This must match up with the value previously used for execbuf2.rsvd1. */
360 #define DEFAULT_CONTEXT_ID 0
361 struct i915_hw_context {
364 struct drm_i915_file_private *file_priv;
365 struct intel_ring_buffer *ring;
366 struct drm_i915_gem_object *obj;
370 FBC_NO_OUTPUT, /* no outputs enabled to compress */
371 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
372 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
373 FBC_MODE_TOO_LARGE, /* mode too large for compression */
374 FBC_BAD_PLANE, /* fbc not supported on plane */
375 FBC_NOT_TILED, /* buffer not tiled */
376 FBC_MULTIPLE_PIPES, /* more than one pipe active */
381 PCH_NONE = 0, /* No PCH present */
382 PCH_IBX, /* Ibexpeak PCH */
383 PCH_CPT, /* Cougarpoint PCH */
384 PCH_LPT, /* Lynxpoint PCH */
387 enum intel_sbi_destination {
392 #define QUIRK_PIPEA_FORCE (1<<0)
393 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
394 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
397 struct intel_fbc_work;
403 struct drm_i915_private *dev_priv;
406 struct intel_iic_softc {
407 struct drm_device *drm_dev;
415 struct i915_suspend_saved_registers {
436 u32 saveTRANS_HTOTAL_A;
437 u32 saveTRANS_HBLANK_A;
438 u32 saveTRANS_HSYNC_A;
439 u32 saveTRANS_VTOTAL_A;
440 u32 saveTRANS_VBLANK_A;
441 u32 saveTRANS_VSYNC_A;
449 u32 savePFIT_PGM_RATIOS;
450 u32 saveBLC_HIST_CTL;
452 u32 saveBLC_PWM_CTL2;
453 u32 saveBLC_CPU_PWM_CTL;
454 u32 saveBLC_CPU_PWM_CTL2;
467 u32 saveTRANS_HTOTAL_B;
468 u32 saveTRANS_HBLANK_B;
469 u32 saveTRANS_HSYNC_B;
470 u32 saveTRANS_VTOTAL_B;
471 u32 saveTRANS_VBLANK_B;
472 u32 saveTRANS_VSYNC_B;
486 u32 savePP_ON_DELAYS;
487 u32 savePP_OFF_DELAYS;
495 u32 savePFIT_CONTROL;
496 u32 save_palette_a[256];
497 u32 save_palette_b[256];
498 u32 saveDPFC_CB_BASE;
499 u32 saveFBC_CFB_BASE;
502 u32 saveFBC_CONTROL2;
512 u32 saveCACHE_MODE_0;
513 u32 saveMI_ARB_STATE;
524 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
535 u32 savePIPEA_GMCH_DATA_M;
536 u32 savePIPEB_GMCH_DATA_M;
537 u32 savePIPEA_GMCH_DATA_N;
538 u32 savePIPEB_GMCH_DATA_N;
539 u32 savePIPEA_DP_LINK_M;
540 u32 savePIPEB_DP_LINK_M;
541 u32 savePIPEA_DP_LINK_N;
542 u32 savePIPEB_DP_LINK_N;
553 u32 savePCH_DREF_CONTROL;
554 u32 saveDISP_ARB_CTL;
555 u32 savePIPEA_DATA_M1;
556 u32 savePIPEA_DATA_N1;
557 u32 savePIPEA_LINK_M1;
558 u32 savePIPEA_LINK_N1;
559 u32 savePIPEB_DATA_M1;
560 u32 savePIPEB_DATA_N1;
561 u32 savePIPEB_LINK_M1;
562 u32 savePIPEB_LINK_N1;
563 u32 saveMCHBAR_RENDER_STANDBY;
564 u32 savePCH_PORT_HOTPLUG;
567 struct intel_gen6_power_mgmt {
568 struct work_struct work;
570 /* lock - irqsave spinlock that protectects the work_struct and
572 struct spinlock lock;
574 /* The below variables an all the rps hw state are protected by
575 * dev->struct mutext. */
580 struct delayed_work delayed_resume_work;
583 * Protects RPS/RC6 register access and PCU communication.
584 * Must be taken after struct_mutex if nested.
589 struct intel_ilk_power_mgmt {
597 unsigned long last_time1;
598 unsigned long chipset_power;
600 struct timespec last_time2;
601 unsigned long gfx_power;
607 struct drm_i915_gem_object *pwrctx;
608 struct drm_i915_gem_object *renderctx;
611 struct i915_dri1_state {
612 unsigned allow_batchbuffer : 1;
613 u32 __iomem *gfx_hws_cpu_addr;
624 struct intel_l3_parity {
626 struct work_struct error_work;
629 typedef struct drm_i915_private {
630 struct drm_device *dev;
632 const struct intel_device_info *info;
634 int relative_constants_mode;
636 device_t *gmbus_bridge;
637 device_t *bbbus_bridge;
640 drm_local_map_t *sarea;
641 drm_local_map_t *mmio_map;
644 struct drm_i915_gt_funcs gt;
645 /** gt_fifo_count and the subsequent register write are synchronized
646 * with dev->struct_mutex. */
647 unsigned gt_fifo_count;
648 /** forcewake_count is protected by gt_lock */
649 unsigned forcewake_count;
650 /** gt_lock is also taken in irq contexts. */
655 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
656 * controller on different i2c buses. */
657 struct lock gmbus_mutex;
659 drm_i915_sarea_t *sarea_priv;
661 * Base address of the gmbus and gpio block.
663 uint32_t gpio_mmio_base;
665 struct device *bridge_dev;
666 struct intel_ring_buffer ring[I915_NUM_RINGS];
669 drm_dma_handle_t *status_page_dmah;
670 struct resource *mch_res;
673 atomic_t irq_received;
675 /* protects the irq masks */
676 struct lock irq_lock;
678 /* DPIO indirect register protection */
679 struct spinlock dpio_lock;
681 /** Cached value of IMR to avoid reads in updating the bitfield */
687 u32 hotplug_supported_mask;
688 struct work_struct hotplug_work;
693 /* For hangcheck timer */
694 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
695 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
696 struct timer_list hangcheck_timer;
698 uint32_t last_acthd[I915_NUM_RINGS];
699 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
701 unsigned int stop_rings;
703 unsigned long cfb_size;
705 enum plane cfb_plane;
707 struct intel_fbc_work *fbc_work;
709 struct intel_opregion opregion;
712 struct intel_overlay *overlay;
713 bool sprite_scaling_enabled;
716 int backlight_level; /* restore backlight to this value */
717 bool backlight_enabled;
718 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
719 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
721 /* Feature bits from the VBIOS */
722 unsigned int int_tv_support:1;
723 unsigned int lvds_dither:1;
724 unsigned int lvds_vbt:1;
725 unsigned int int_crt_support:1;
726 unsigned int lvds_use_ssc:1;
727 unsigned int display_clock_mode:1;
728 unsigned int fdi_rx_polarity_inverted:1;
730 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
731 unsigned int lvds_val; /* used for checking LVDS channel mode */
741 struct edp_power_seq pps;
743 bool no_aux_handshake;
746 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
747 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
748 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
750 unsigned int fsb_freq, mem_freq, is_ddr3;
752 struct lock error_lock;
753 /* Protected by dev->error_lock. */
754 struct drm_i915_error_state *first_error;
755 struct work_struct error_work;
756 struct completion error_completion;
757 struct workqueue_struct *wq;
759 /* Display functions */
760 struct drm_i915_display_funcs display;
762 /* PCH chipset type */
763 enum intel_pch pch_type;
764 unsigned short pch_id;
766 unsigned long quirks;
772 /** Bridge to intel-gtt-ko */
773 const struct intel_gtt *gtt;
774 /** Memory allocator for GTT stolen memory */
775 struct drm_mm stolen;
776 /** Memory allocator for GTT */
777 struct drm_mm gtt_space;
778 /** List of all objects in gtt_space. Used to restore gtt
779 * mappings on resume */
780 struct list_head bound_list;
782 * List of objects which are not bound to the GTT (thus
783 * are idle and not used by the GPU) but still have
784 * (presumably uncached) pages still attached.
786 struct list_head unbound_list;
788 /** Usable portion of the GTT for GEM */
789 unsigned long gtt_start;
790 unsigned long gtt_mappable_end;
791 unsigned long gtt_end;
792 unsigned long stolen_base; /* limited to low memory (32-bit) */
794 struct io_mapping *gtt_mapping;
795 phys_addr_t gtt_base_addr;
798 /** PPGTT used for aliasing the PPGTT with the GTT */
799 struct i915_hw_ppgtt *aliasing_ppgtt;
801 bool shrinker_no_lock_stealing;
804 * List of objects currently involved in rendering.
806 * Includes buffers having the contents of their GPU caches
807 * flushed, not necessarily primitives. last_rendering_seqno
808 * represents when the rendering involved will be completed.
810 * A reference is held on the buffer while on this list.
812 struct list_head active_list;
815 * LRU list of objects which are not in the ringbuffer and
816 * are ready to unbind, but are still in the GTT.
818 * last_rendering_seqno is 0 while an object is in this list.
820 * A reference is not held on the buffer while on this list,
821 * as merely being GTT-bound shouldn't prevent its being
822 * freed, and we'll pull it off the list in the free path.
824 struct list_head inactive_list;
826 /** LRU list of objects with fence regs on them. */
827 struct list_head fence_list;
830 * We leave the user IRQ off as much as possible,
831 * but this means that requests will finish and never
832 * be retired once the system goes idle. Set a timer to
833 * fire periodically while the ring is running. When it
834 * fires, go retire requests.
836 struct delayed_work retire_work;
839 * Are we in a non-interruptible section of code like
845 * Flag if the X Server, and thus DRM, is not currently in
846 * control of the device.
848 * This is set between LeaveVT and EnterVT. It needs to be
849 * replaced with a semaphore. It also needs to be
850 * transitioned away from for kernel modesetting.
855 * Flag if the hardware appears to be wedged.
857 * This is set when attempts to idle the device timeout.
858 * It prevents command submission from occurring and makes
859 * every pending request fail
863 /** Bit 6 swizzling required for X tiling */
864 uint32_t bit_6_swizzle_x;
865 /** Bit 6 swizzling required for Y tiling */
866 uint32_t bit_6_swizzle_y;
868 /* storage for physical objects */
869 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
871 /* accounting, useful for userland debugging */
873 size_t mappable_gtt_total;
874 size_t object_memory;
877 eventhandler_tag i915_lowmem;
880 /* Kernel Modesetting */
882 struct sdvo_device_mapping sdvo_mappings[2];
883 /* indicate whether the LVDS_BORDER should be enabled or not */
884 unsigned int lvds_border_bits;
885 /* Panel fitter placement and size for Ironlake+ */
886 u32 pch_pf_pos, pch_pf_size;
888 struct drm_crtc *plane_to_crtc_mapping[3];
889 struct drm_crtc *pipe_to_crtc_mapping[3];
890 wait_queue_head_t pending_flip_queue;
892 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
893 struct intel_ddi_plls ddi_plls;
895 /* Reclocking support */
896 bool render_reclock_avail;
897 bool lvds_downclock_avail;
898 /* indicates the reduced downclock for LVDS*/
902 struct child_device_config *child_dev;
904 bool mchbar_need_disable;
906 struct intel_l3_parity l3_parity;
908 /* gen6+ rps state */
909 struct intel_gen6_power_mgmt rps;
911 /* ilk-only ips/rps state. Everything in here is protected by the global
912 * mchdev_lock in intel_pm.c */
913 struct intel_ilk_power_mgmt ips;
915 enum no_fbc_reason no_fbc_reason;
917 struct drm_mm_node *compressed_fb;
918 struct drm_mm_node *compressed_llb;
920 unsigned long last_gpu_reset;
922 /* list of fbdev register on this device */
923 struct intel_fbdev *fbdev;
926 * The console may be contended at resume, but we don't
927 * want it to block on it.
929 struct work_struct console_resume_work;
931 struct backlight_device *backlight;
933 struct drm_property *broadcast_rgb_property;
934 struct drm_property *force_audio_property;
936 bool hw_contexts_disabled;
937 uint32_t hw_context_size;
941 struct i915_suspend_saved_registers regfile;
943 /* Old dri1 support infrastructure, beware the dragons ya fools entering
945 struct i915_dri1_state dri1;
946 } drm_i915_private_t;
948 /* Iterate over initialised rings */
949 #define for_each_ring(ring__, dev_priv__, i__) \
950 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
951 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
953 enum hdmi_force_audio {
954 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
955 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
956 HDMI_AUDIO_AUTO, /* trust EDID */
957 HDMI_AUDIO_ON, /* force turn on HDMI audio */
960 enum i915_cache_level {
963 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
966 struct drm_i915_gem_object_ops {
967 /* Interface between the GEM object and its backing storage.
968 * get_pages() is called once prior to the use of the associated set
969 * of pages before to binding them into the GTT, and put_pages() is
970 * called after we no longer need them. As we expect there to be
971 * associated cost with migrating pages between the backing storage
972 * and making them available for the GPU (e.g. clflush), we may hold
973 * onto the pages after they are no longer referenced by the GPU
974 * in case they may be used again shortly (for example migrating the
975 * pages to a different memory domain within the GTT). put_pages()
976 * will therefore most likely be called when the object itself is
977 * being released or under memory pressure (where we attempt to
978 * reap pages for the shrinker).
980 int (*get_pages)(struct drm_i915_gem_object *);
981 void (*put_pages)(struct drm_i915_gem_object *);
984 struct drm_i915_gem_object {
985 struct drm_gem_object base;
987 const struct drm_i915_gem_object_ops *ops;
989 /** Current space allocated to this object in the GTT, if any. */
990 struct drm_mm_node *gtt_space;
991 struct list_head gtt_list;
993 /** This object's place on the active/inactive lists */
994 struct list_head ring_list;
995 struct list_head mm_list;
996 /** This object's place in the batchbuffer or on the eviction list */
997 struct list_head exec_list;
1000 * This is set if the object is on the active lists (has pending
1001 * rendering and so a non-zero seqno), and is not set if it i s on
1002 * inactive (ready to be unbound) list.
1004 unsigned int active:1;
1007 * This is set if the object has been written to since last bound
1010 unsigned int dirty:1;
1013 * Fence register bits (if any) for this object. Will be set
1014 * as needed when mapped into the GTT.
1015 * Protected by dev->struct_mutex.
1017 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1020 * Advice: are the backing pages purgeable?
1022 unsigned int madv:2;
1025 * Current tiling mode for the object.
1027 unsigned int tiling_mode:2;
1029 * Whether the tiling parameters for the currently associated fence
1030 * register have changed. Note that for the purposes of tracking
1031 * tiling changes we also treat the unfenced register, the register
1032 * slot that the object occupies whilst it executes a fenced
1033 * command (such as BLT on gen2/3), as a "fence".
1035 unsigned int fence_dirty:1;
1037 /** How many users have pinned this object in GTT space. The following
1038 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1039 * (via user_pin_count), execbuffer (objects are not allowed multiple
1040 * times for the same batchbuffer), and the framebuffer code. When
1041 * switching/pageflipping, the framebuffer code has at most two buffers
1044 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1045 * bits with absolutely no headroom. So use 4 bits. */
1046 unsigned int pin_count:4;
1047 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1050 * Is the object at the current location in the gtt mappable and
1051 * fenceable? Used to avoid costly recalculations.
1053 unsigned int map_and_fenceable:1;
1056 * Whether the current gtt mapping needs to be mappable (and isn't just
1057 * mappable by accident). Track pin and fault separate for a more
1058 * accurate mappable working set.
1060 unsigned int fault_mappable:1;
1061 unsigned int pin_mappable:1;
1064 * Is the GPU currently using a fence to access this buffer,
1066 unsigned int pending_fenced_gpu_access:1;
1067 unsigned int fenced_gpu_access:1;
1069 unsigned int cache_level:2;
1071 unsigned int has_aliasing_ppgtt_mapping:1;
1072 unsigned int has_global_gtt_mapping:1;
1073 unsigned int has_dma_mapping:1;
1076 int pages_pin_count;
1079 * Used for performing relocations during execbuffer insertion.
1081 struct hlist_node exec_node;
1082 unsigned long exec_handle;
1083 struct drm_i915_gem_exec_object2 *exec_entry;
1086 * Current offset of the object in GTT space.
1088 * This is the same as gtt_space->start
1090 uint32_t gtt_offset;
1092 struct intel_ring_buffer *ring;
1094 /** Breadcrumb of last rendering to the buffer. */
1095 uint32_t last_read_seqno;
1096 uint32_t last_write_seqno;
1097 /** Breadcrumb of last fenced GPU access to the buffer. */
1098 uint32_t last_fenced_seqno;
1100 /** Current tiling stride for the object, if it's tiled. */
1103 /** Record of address bit 17 of each page at last unbind. */
1104 unsigned long *bit_17;
1106 /** User space pin count and filp owning the pin */
1107 uint32_t user_pin_count;
1108 struct drm_file *pin_filp;
1110 /** for phy allocated objects */
1111 struct drm_i915_gem_phys_object *phys_obj;
1114 * Number of crtcs where this object is currently the fb, but
1115 * will be page flipped away on the next vblank. When it
1116 * reaches 0, dev_priv->pending_flip_queue will be woken up.
1118 atomic_t pending_flip;
1120 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1122 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1125 * Request queue structure.
1127 * The request queue allows us to note sequence numbers that have been emitted
1128 * and may be associated with active buffers to be retired.
1130 * By keeping this list, we can avoid having to do questionable
1131 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1132 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1134 struct drm_i915_gem_request {
1135 /** On Which ring this request was generated */
1136 struct intel_ring_buffer *ring;
1138 /** GEM sequence number associated with this request. */
1141 /** Postion in the ringbuffer of the end of the request */
1144 /** Time at which this request was emitted, in jiffies. */
1145 unsigned long emitted_jiffies;
1147 /** global list entry for this request */
1148 struct list_head list;
1150 struct drm_i915_file_private *file_priv;
1151 /** file_priv list entry for this request */
1152 struct list_head client_list;
1155 struct drm_i915_file_private {
1157 struct spinlock lock;
1158 struct list_head request_list;
1160 struct idr context_idr;
1163 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1165 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1166 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1167 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1168 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1169 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1170 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1171 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1172 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1173 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1174 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1175 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1176 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1177 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1178 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1179 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1180 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1181 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1182 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1183 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1184 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1185 (dev)->pci_device == 0x0152 || \
1186 (dev)->pci_device == 0x015a)
1187 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1188 (dev)->pci_device == 0x0106 || \
1189 (dev)->pci_device == 0x010A)
1190 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1191 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1192 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1193 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1194 ((dev)->pci_device & 0xFF00) == 0x0A00)
1197 * The genX designation typically refers to the render engine, so render
1198 * capability related checks should use IS_GEN, while display and other checks
1199 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1202 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1203 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1204 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1205 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1206 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1207 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1209 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1210 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1211 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1212 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1214 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1215 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1217 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1218 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1220 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1221 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1223 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1224 * rows, which changed the alignment requirements and fence programming.
1226 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1228 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1229 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1230 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1231 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1232 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1233 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1234 /* dsparb controlled by hw only */
1235 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1237 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1238 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1239 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1241 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1243 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1244 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1245 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1246 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1247 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1248 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1250 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1251 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1252 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1253 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1254 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1256 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1258 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1260 #define GT_FREQUENCY_MULTIPLIER 50
1263 * RC6 is a special power stage which allows the GPU to enter an very
1264 * low-voltage mode when idle, using down to 0V while at this stage. This
1265 * stage is entered automatically when the GPU is idle when RC6 support is
1266 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1268 * There are different RC6 modes available in Intel GPU, which differentiate
1269 * among each other with the latency required to enter and leave RC6 and
1270 * voltage consumed by the GPU in different states.
1272 * The combination of the following flags define which states GPU is allowed
1273 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1274 * RC6pp is deepest RC6. Their support by hardware varies according to the
1275 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1276 * which brings the most power savings; deeper states save more power, but
1277 * require higher latency to switch to and wake up.
1279 #define INTEL_RC6_ENABLE (1<<0)
1280 #define INTEL_RC6p_ENABLE (1<<1)
1281 #define INTEL_RC6pp_ENABLE (1<<2)
1283 extern int intel_iommu_enabled;
1284 extern struct drm_ioctl_desc i915_ioctls[];
1285 extern struct drm_driver i915_driver_info;
1286 extern struct cdev_pager_ops i915_gem_pager_ops;
1287 extern int i915_max_ioctl;
1288 extern unsigned int i915_fbpercrtc __always_unused;
1289 extern int i915_panel_ignore_lid __read_mostly;
1290 extern unsigned int i915_powersave __read_mostly;
1291 extern int i915_semaphores __read_mostly;
1292 extern unsigned int i915_lvds_downclock __read_mostly;
1293 extern int i915_lvds_channel_mode __read_mostly;
1294 extern int i915_panel_use_ssc __read_mostly;
1295 extern int i915_vbt_sdvo_panel_type __read_mostly;
1296 extern int i915_enable_rc6 __read_mostly;
1297 extern int i915_enable_fbc __read_mostly;
1298 extern int i915_enable_hangcheck;
1299 extern int i915_enable_ppgtt __read_mostly;
1300 extern unsigned int i915_preliminary_hw_support __read_mostly;
1303 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1304 extern void i915_kernel_lost_context(struct drm_device * dev);
1305 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1306 extern int i915_driver_unload(struct drm_device *);
1307 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1308 extern void i915_driver_lastclose(struct drm_device * dev);
1309 extern void i915_driver_preclose(struct drm_device *dev,
1310 struct drm_file *file_priv);
1311 extern void i915_driver_postclose(struct drm_device *dev,
1312 struct drm_file *file_priv);
1313 extern int i915_driver_device_is_agp(struct drm_device * dev);
1314 #ifdef CONFIG_COMPAT
1315 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1318 extern int i915_emit_box(struct drm_device *dev,
1319 struct drm_clip_rect *box,
1321 extern int intel_gpu_reset(struct drm_device *dev);
1322 extern int i915_reset(struct drm_device *dev);
1323 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1324 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1325 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1326 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1328 extern void intel_console_resume(struct work_struct *work);
1331 void i915_hangcheck_elapsed(unsigned long data);
1332 void i915_handle_error(struct drm_device *dev, bool wedged);
1334 extern void intel_irq_init(struct drm_device *dev);
1335 extern void intel_gt_init(struct drm_device *dev);
1336 extern void intel_gt_reset(struct drm_device *dev);
1338 void i915_error_state_free(struct kref *error_ref);
1341 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1344 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1346 void intel_enable_asle(struct drm_device *dev);
1348 #ifdef CONFIG_DEBUG_FS
1349 extern void i915_destroy_error_state(struct drm_device *dev);
1351 #define i915_destroy_error_state(x)
1356 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1357 struct drm_file *file_priv);
1358 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1359 struct drm_file *file_priv);
1360 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1361 struct drm_file *file_priv);
1362 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1363 struct drm_file *file_priv);
1364 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1365 struct drm_file *file_priv);
1366 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1367 struct drm_file *file_priv);
1368 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1369 struct drm_file *file_priv);
1370 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1371 struct drm_file *file_priv);
1372 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1373 struct drm_file *file_priv);
1374 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1375 struct drm_file *file_priv);
1376 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1377 struct drm_file *file_priv);
1378 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1379 struct drm_file *file_priv);
1380 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1381 struct drm_file *file_priv);
1382 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1383 struct drm_file *file);
1384 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1385 struct drm_file *file);
1386 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1387 struct drm_file *file_priv);
1388 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1389 struct drm_file *file_priv);
1390 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1391 struct drm_file *file_priv);
1392 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1393 struct drm_file *file_priv);
1394 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1395 struct drm_file *file_priv);
1396 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1397 struct drm_file *file_priv);
1398 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1399 struct drm_file *file_priv);
1400 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1401 struct drm_file *file_priv);
1402 void i915_gem_load(struct drm_device *dev);
1403 void i915_gem_unload(struct drm_device *dev);
1404 int i915_gem_init_object(struct drm_gem_object *obj);
1405 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1406 const struct drm_i915_gem_object_ops *ops);
1407 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1409 void i915_gem_free_object(struct drm_gem_object *obj);
1410 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1412 bool map_and_fenceable,
1414 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1415 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1416 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1417 void i915_gem_lastclose(struct drm_device *dev);
1419 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1420 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1421 struct intel_ring_buffer *to);
1422 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1423 struct intel_ring_buffer *ring);
1425 int i915_gem_dumb_create(struct drm_file *file_priv,
1426 struct drm_device *dev,
1427 struct drm_mode_create_dumb *args);
1428 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1429 uint32_t handle, uint64_t *offset);
1430 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1433 * Returns true if seq1 is later than seq2.
1436 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1438 return (int32_t)(seq1 - seq2) >= 0;
1441 extern int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1443 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1444 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1447 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1449 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1450 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1451 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1458 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1460 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1461 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1462 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1466 void i915_gem_retire_requests(struct drm_device *dev);
1467 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1468 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1469 bool interruptible);
1471 void i915_gem_reset(struct drm_device *dev);
1472 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1473 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
1474 unsigned long mappable_end, unsigned long end);
1475 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1476 uint32_t read_domains,
1477 uint32_t write_domain);
1478 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1479 int __must_check i915_gem_init(struct drm_device *dev);
1480 int __must_check i915_gem_init_hw(struct drm_device *dev);
1481 void i915_gem_l3_remap(struct drm_device *dev);
1482 void i915_gem_init_swizzling(struct drm_device *dev);
1483 void i915_gem_init_ppgtt(struct drm_device *dev);
1484 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1485 int __must_check i915_gpu_idle(struct drm_device *dev);
1486 int __must_check i915_gem_idle(struct drm_device *dev);
1487 int i915_add_request(struct intel_ring_buffer *ring,
1488 struct drm_file *file,
1490 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1492 int i915_gem_fault(struct drm_device *dev, uint64_t offset, int prot,
1495 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1498 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1500 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1502 struct intel_ring_buffer *pipelined);
1503 int i915_gem_attach_phys_object(struct drm_device *dev,
1504 struct drm_i915_gem_object *obj,
1507 void i915_gem_detach_phys_object(struct drm_device *dev,
1508 struct drm_i915_gem_object *obj);
1509 void i915_gem_free_all_phys_object(struct drm_device *dev);
1510 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1513 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1517 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1518 enum i915_cache_level cache_level);
1520 /* i915_gem_context.c */
1521 void i915_gem_context_init(struct drm_device *dev);
1522 void i915_gem_context_fini(struct drm_device *dev);
1523 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1524 int i915_switch_context(struct intel_ring_buffer *ring,
1525 struct drm_file *file, int to_id);
1526 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1527 struct drm_file *file);
1528 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1529 struct drm_file *file);
1531 /* i915_gem_gtt.c */
1532 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1533 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1534 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1535 struct drm_i915_gem_object *obj,
1536 enum i915_cache_level cache_level);
1537 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1538 struct drm_i915_gem_object *obj);
1540 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1541 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1542 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1543 enum i915_cache_level cache_level);
1544 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1545 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1546 void i915_gem_init_global_gtt(struct drm_device *dev,
1547 unsigned long start,
1548 unsigned long mappable_end,
1550 int i915_gem_gtt_init(struct drm_device *dev);
1551 void i915_gem_gtt_fini(struct drm_device *dev);
1552 static inline void i915_gem_chipset_flush(struct drm_device *dev)
1554 if (INTEL_INFO(dev)->gen < 6)
1555 intel_gtt_chipset_flush();
1559 /* i915_gem_evict.c */
1560 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1562 unsigned cache_level,
1565 int i915_gem_evict_everything(struct drm_device *dev);
1567 /* i915_gem_stolen.c */
1568 int i915_gem_init_stolen(struct drm_device *dev);
1569 void i915_gem_cleanup_stolen(struct drm_device *dev);
1571 /* i915_gem_tiling.c */
1572 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1573 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1574 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1576 /* i915_gem_debug.c */
1578 int i915_verify_lists(struct drm_device *dev);
1580 #define i915_verify_lists(dev) 0
1582 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1585 /* i915_debugfs.c */
1586 int i915_debugfs_init(struct drm_minor *minor);
1587 void i915_debugfs_cleanup(struct drm_minor *minor);
1589 /* i915_suspend.c */
1590 extern int i915_save_state(struct drm_device *dev);
1591 extern int i915_restore_state(struct drm_device *dev);
1594 void i915_setup_sysfs(struct drm_device *dev_priv);
1595 void i915_teardown_sysfs(struct drm_device *dev_priv);
1598 extern int intel_setup_gmbus(struct drm_device *dev);
1599 extern void intel_teardown_gmbus(struct drm_device *dev);
1600 static inline bool intel_gmbus_is_port_valid(unsigned port)
1602 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1605 extern struct device *intel_gmbus_get_adapter(
1606 struct drm_i915_private *dev_priv, unsigned port);
1607 extern void intel_gmbus_set_speed(device_t idev, int speed);
1608 extern void intel_gmbus_force_bit(device_t idev, bool force_bit);
1609 static inline bool intel_gmbus_is_forced_bit(struct device *adapter)
1611 struct intel_iic_softc *sc;
1612 sc = device_get_softc(device_get_parent(adapter));
1614 return sc->force_bit_dev;
1616 extern void intel_i2c_reset(struct drm_device *dev);
1618 /* intel_opregion.c */
1619 extern int intel_opregion_setup(struct drm_device *dev);
1621 extern void intel_opregion_init(struct drm_device *dev);
1622 extern void intel_opregion_fini(struct drm_device *dev);
1623 extern void intel_opregion_asle_intr(struct drm_device *dev);
1624 extern void intel_opregion_gse_intr(struct drm_device *dev);
1625 extern void intel_opregion_enable_asle(struct drm_device *dev);
1627 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1628 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1629 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1630 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1631 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1636 extern void intel_register_dsm_handler(void);
1637 extern void intel_unregister_dsm_handler(void);
1639 static inline void intel_register_dsm_handler(void) { return; }
1640 static inline void intel_unregister_dsm_handler(void) { return; }
1641 #endif /* CONFIG_ACPI */
1644 extern void intel_modeset_init_hw(struct drm_device *dev);
1645 extern void intel_modeset_init(struct drm_device *dev);
1646 extern void intel_modeset_gem_init(struct drm_device *dev);
1647 extern void intel_modeset_cleanup(struct drm_device *dev);
1648 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1649 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1650 bool force_restore);
1651 extern void intel_disable_fbc(struct drm_device *dev);
1652 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1653 extern void intel_init_pch_refclk(struct drm_device *dev);
1654 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1655 extern void intel_detect_pch(struct drm_device *dev);
1656 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1657 extern int intel_enable_rc6(const struct drm_device *dev);
1659 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1660 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1661 struct drm_file *file);
1663 extern void intel_overlay_print_error_state(struct sbuf *m,
1664 struct intel_overlay_error_state *error);
1665 extern void intel_display_print_error_state(struct sbuf *m,
1666 struct drm_device *dev, struct intel_display_error_state *error);
1669 trace_i915_reg_rw(boolean_t rw, int reg, uint64_t val, int sz)
1674 const struct intel_device_info *i915_get_device_id(int device);
1677 #ifdef CONFIG_DEBUG_FS
1678 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1679 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1681 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1682 extern void intel_display_print_error_state(struct seq_file *m,
1683 struct drm_device *dev,
1684 struct intel_display_error_state *error);
1687 /* On SNB platform, before reading ring registers forcewake bit
1688 * must be set to prevent GT core from power down and stale values being
1691 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1692 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1693 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1695 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1696 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1698 #define __i915_read(x, y) \
1699 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1707 #define __i915_write(x, y) \
1708 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1711 __i915_write(16, 16)
1712 __i915_write(32, 32)
1713 __i915_write(64, 64)
1716 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1717 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1719 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1720 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1721 #define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->mmio_map, (reg))
1722 #define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
1724 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1725 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1726 #define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->mmio_map, (reg))
1727 #define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
1729 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1730 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1732 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1733 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)