2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros
3 * Communications, Inc. All rights reserved.
5 * Redistribution and use in source and binary forms are permitted
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36 * $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/freebsd/ah_osdep.h#17 $
38 #ifndef _ATH_AH_OSDEP_H_
39 #define _ATH_AH_OSDEP_H_
41 * Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/endian.h>
47 #include <machine/bus.h>
49 typedef void* HAL_SOFTC;
50 typedef bus_space_tag_t HAL_BUS_TAG;
51 typedef bus_space_handle_t HAL_BUS_HANDLE;
52 typedef bus_addr_t HAL_BUS_ADDR;
55 * Delay n microseconds.
57 extern void ath_hal_delay(int);
58 #define OS_DELAY(_n) ath_hal_delay(_n)
60 #define OS_INLINE __inline
61 #define OS_MEMZERO(_a, _n) ath_hal_memzero((_a), (_n))
62 extern void ath_hal_memzero(void *, size_t);
63 #define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n)
64 extern void *ath_hal_memcpy(void *, const void *, size_t);
66 #define abs(_a) __builtin_abs(_a)
69 extern u_int32_t ath_hal_getuptime(struct ath_hal *);
70 #define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah)
73 * Register read/write; we assume the registers will always
74 * be memory-mapped. Note that register accesses are done
75 * using target-specific functions when debugging is enabled
76 * (AH_DEBUG) or we are explicitly configured this way. The
77 * latter is used on some platforms where the full i/o space
78 * cannot be directly mapped.
80 #if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
81 #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
82 #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
84 extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
85 extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
88 * The hardware registers are native little-endian byte order.
89 * Big-endian hosts are handled by enabling hardware byte-swap
90 * of register reads and writes at reset. But the PCI clock
91 * domain registers are not byte swapped! Thus, on big-endian
92 * platforms we have to byte-swap thoese registers specifically.
93 * Most of this code is collapsed at compile time because the
94 * register values are constants.
96 #define AH_LITTLE_ENDIAN 1234
97 #define AH_BIG_ENDIAN 4321
99 #if _BYTE_ORDER == _BIG_ENDIAN
100 #define OS_REG_WRITE(_ah, _reg, _val) do { \
101 if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \
102 bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \
103 (_reg), htole32(_val)); \
105 bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \
108 #define OS_REG_READ(_ah, _reg) \
109 (((_reg) >= 0x4000 && (_reg) < 0x5000) ? \
110 le32toh(bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, \
112 bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
113 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */
114 #define OS_REG_WRITE(_ah, _reg, _val) \
115 bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, (_reg), (_val))
116 #define OS_REG_READ(_ah, _reg) \
117 ((u_int32_t) bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
118 #endif /* _BYTE_ORDER */
119 #endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
122 extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
124 #define OS_MARK(_ah, _id, _v)
127 #endif /* _ATH_AH_OSDEP_H_ */