sys/dev/netif/bnx/if_bnx.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 #include "opt_bnx.h"
  37 #include "opt_ifpoll.h"
  38
  39 #include <sys/param.h>
  40 #include <sys/bus.h>
  41 #include <sys/endian.h>
  42 #include <sys/kernel.h>
  43 #include <sys/interrupt.h>
  44 #include <sys/mbuf.h>
  45 #include <sys/malloc.h>
  46 #include <sys/queue.h>
  47 #include <sys/rman.h>
  48 #include <sys/serialize.h>
  49 #include <sys/socket.h>
  50 #include <sys/sockio.h>
  51 #include <sys/sysctl.h>
  52
  53 #include <netinet/ip.h>
  54 #include <netinet/tcp.h>
  55
  56 #include <net/bpf.h>
  57 #include <net/ethernet.h>
  58 #include <net/if.h>
  59 #include <net/if_arp.h>
  60 #include <net/if_dl.h>
  61 #include <net/if_media.h>
  62 #include <net/if_poll.h>
  63 #include <net/if_types.h>
  64 #include <net/ifq_var.h>
  65 #include <net/vlan/if_vlan_var.h>
  66 #include <net/vlan/if_vlan_ether.h>
  67
  68 #include <dev/netif/mii_layer/mii.h>
  69 #include <dev/netif/mii_layer/miivar.h>
  70 #include <dev/netif/mii_layer/brgphyreg.h>
  71
  72 #include <bus/pci/pcidevs.h>
  73 #include <bus/pci/pcireg.h>
  74 #include <bus/pci/pcivar.h>
  75
  76 #include <dev/netif/bge/if_bgereg.h>
  77 #include <dev/netif/bnx/if_bnxvar.h>
  78
  79 /* "device miibus" required.  See GENERIC if you get errors here. */
  80 #include "miibus_if.h"
  81
  82 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  83
  84 #define BNX_INTR_CKINTVL        ((10 * hz) / 1000)      /* 10ms */
  85
  86 static const struct bnx_type {
  87         uint16_t                bnx_vid;
  88         uint16_t                bnx_did;
  89         char                    *bnx_name;
  90 } bnx_devs[] = {
  91         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
  92                 "Broadcom BCM5717 Gigabit Ethernet" },
  93         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C,
  94                 "Broadcom BCM5717C Gigabit Ethernet" },
  95         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
  96                 "Broadcom BCM5718 Gigabit Ethernet" },
  97         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
  98                 "Broadcom BCM5719 Gigabit Ethernet" },
  99         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
 100                 "Broadcom BCM5720 Gigabit Ethernet" },
 101
 102         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725,
 103                 "Broadcom BCM5725 Gigabit Ethernet" },
 104         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727,
 105                 "Broadcom BCM5727 Gigabit Ethernet" },
 106         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762,
 107                 "Broadcom BCM5762 Gigabit Ethernet" },
 108
 109         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
 110                 "Broadcom BCM57761 Gigabit Ethernet" },
 111         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
 112                 "Broadcom BCM57762 Gigabit Ethernet" },
 113         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
 114                 "Broadcom BCM57765 Gigabit Ethernet" },
 115         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
 116                 "Broadcom BCM57766 Gigabit Ethernet" },
 117         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
 118                 "Broadcom BCM57781 Gigabit Ethernet" },
 119         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
 120                 "Broadcom BCM57782 Gigabit Ethernet" },
 121         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
 122                 "Broadcom BCM57785 Gigabit Ethernet" },
 123         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
 124                 "Broadcom BCM57786 Gigabit Ethernet" },
 125         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
 126                 "Broadcom BCM57791 Fast Ethernet" },
 127         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
 128                 "Broadcom BCM57795 Fast Ethernet" },
 129
 130         { 0, 0, NULL }
 131 };
 132
 133 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
 134 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
 135 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
 136 #define BNX_IS_57765_FAMILY(sc)  \
 137         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
 138
 139 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
 140
 141 static int      bnx_probe(device_t);
 142 static int      bnx_attach(device_t);
 143 static int      bnx_detach(device_t);
 144 static void     bnx_shutdown(device_t);
 145 static int      bnx_suspend(device_t);
 146 static int      bnx_resume(device_t);
 147 static int      bnx_miibus_readreg(device_t, int, int);
 148 static int      bnx_miibus_writereg(device_t, int, int, int);
 149 static void     bnx_miibus_statchg(device_t);
 150
 151 #ifdef IFPOLL_ENABLE
 152 static void     bnx_npoll(struct ifnet *, struct ifpoll_info *);
 153 static void     bnx_npoll_compat(struct ifnet *, void *, int);
 154 #endif
 155 static void     bnx_intr_legacy(void *);
 156 static void     bnx_msi(void *);
 157 static void     bnx_msi_oneshot(void *);
 158 static void     bnx_intr(struct bnx_softc *);
 159 static void     bnx_enable_intr(struct bnx_softc *);
 160 static void     bnx_disable_intr(struct bnx_softc *);
 161 static void     bnx_txeof(struct bnx_tx_ring *, uint16_t);
 162 static void     bnx_rxeof(struct bnx_rx_ret_ring *, uint16_t, int);
 163 static int      bnx_alloc_intr(struct bnx_softc *);
 164 static int      bnx_setup_intr(struct bnx_softc *);
 165 static void     bnx_free_intr(struct bnx_softc *);
 166
 167 static void     bnx_start(struct ifnet *, struct ifaltq_subque *);
 168 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 169 static void     bnx_init(void *);
 170 static void     bnx_stop(struct bnx_softc *);
 171 static void     bnx_watchdog(struct ifnet *);
 172 static int      bnx_ifmedia_upd(struct ifnet *);
 173 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 174 static void     bnx_tick(void *);
 175
 176 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
 177 static void     bnx_free_jumbo_mem(struct bnx_softc *);
 178 static struct bnx_jslot
 179                 *bnx_jalloc(struct bnx_softc *);
 180 static void     bnx_jfree(void *);
 181 static void     bnx_jref(void *);
 182 static int      bnx_newbuf_std(struct bnx_rx_ret_ring *, int, int);
 183 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
 184 static void     bnx_setup_rxdesc_std(struct bnx_rx_std_ring *, int);
 185 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
 186 static int      bnx_init_rx_ring_std(struct bnx_rx_std_ring *);
 187 static void     bnx_free_rx_ring_std(struct bnx_rx_std_ring *);
 188 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
 189 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
 190 static void     bnx_free_tx_ring(struct bnx_tx_ring *);
 191 static int      bnx_init_tx_ring(struct bnx_tx_ring *);
 192 static int      bnx_create_tx_ring(struct bnx_tx_ring *);
 193 static void     bnx_destroy_tx_ring(struct bnx_tx_ring *);
 194 static int      bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *);
 195 static void     bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *);
 196 static int      bnx_dma_alloc(device_t);
 197 static void     bnx_dma_free(struct bnx_softc *);
 198 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
 199                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
 200 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 201 static struct mbuf *
 202                 bnx_defrag_shortdma(struct mbuf *);
 203 static int      bnx_encap(struct bnx_tx_ring *, struct mbuf **,
 204                     uint32_t *, int *);
 205 static int      bnx_setup_tso(struct bnx_tx_ring *, struct mbuf **,
 206                     uint16_t *, uint16_t *);
 207
 208 static void     bnx_reset(struct bnx_softc *);
 209 static int      bnx_chipinit(struct bnx_softc *);
 210 static int      bnx_blockinit(struct bnx_softc *);
 211 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
 212 static void     bnx_enable_msi(struct bnx_softc *sc);
 213 static void     bnx_setmulti(struct bnx_softc *);
 214 static void     bnx_setpromisc(struct bnx_softc *);
 215 static void     bnx_stats_update_regs(struct bnx_softc *);
 216 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
 217
 218 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
 219 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
 220 #ifdef notdef
 221 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
 222 #endif
 223 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
 224 static void     bnx_writembx(struct bnx_softc *, int, int);
 225 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
 226 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
 227 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
 228
 229 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
 230 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
 231 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
 232 static void     bnx_link_poll(struct bnx_softc *);
 233
 234 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
 235 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
 236 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
 237 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
 238
 239 static void     bnx_coal_change(struct bnx_softc *);
 240 static int      bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS);
 241 static int      bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS);
 242 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 243 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 244 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
 245 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
 246 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 247 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 248 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
 249                     int, int, uint32_t);
 250
 251 static int      bnx_msi_enable = 1;
 252 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
 253
 254 static device_method_t bnx_methods[] = {
 255         /* Device interface */
 256         DEVMETHOD(device_probe,         bnx_probe),
 257         DEVMETHOD(device_attach,        bnx_attach),
 258         DEVMETHOD(device_detach,        bnx_detach),
 259         DEVMETHOD(device_shutdown,      bnx_shutdown),
 260         DEVMETHOD(device_suspend,       bnx_suspend),
 261         DEVMETHOD(device_resume,        bnx_resume),
 262
 263         /* bus interface */
 264         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 265         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 266
 267         /* MII interface */
 268         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
 269         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
 270         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
 271
 272         DEVMETHOD_END
 273 };
 274
 275 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
 276 static devclass_t bnx_devclass;
 277
 278 DECLARE_DUMMY_MODULE(if_bnx);
 279 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
 280 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
 281
 282 static uint32_t
 283 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
 284 {
 285         device_t dev = sc->bnx_dev;
 286         uint32_t val;
 287
 288         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 289         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 290         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 291         return (val);
 292 }
 293
 294 static void
 295 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 296 {
 297         device_t dev = sc->bnx_dev;
 298
 299         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 300         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 301         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 302 }
 303
 304 static void
 305 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
 306 {
 307         CSR_WRITE_4(sc, off, val);
 308 }
 309
 310 static void
 311 bnx_writembx(struct bnx_softc *sc, int off, int val)
 312 {
 313         CSR_WRITE_4(sc, off, val);
 314 }
 315
 316 /*
 317  * Read a sequence of bytes from NVRAM.
 318  */
 319 static int
 320 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
 321 {
 322         return (1);
 323 }
 324
 325 /*
 326  * Read a byte of data stored in the EEPROM at address 'addr.' The
 327  * BCM570x supports both the traditional bitbang interface and an
 328  * auto access interface for reading the EEPROM. We use the auto
 329  * access method.
 330  */
 331 static uint8_t
 332 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
 333 {
 334         int i;
 335         uint32_t byte = 0;
 336
 337         /*
 338          * Enable use of auto EEPROM access so we can avoid
 339          * having to use the bitbang method.
 340          */
 341         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 342
 343         /* Reset the EEPROM, load the clock period. */
 344         CSR_WRITE_4(sc, BGE_EE_ADDR,
 345             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 346         DELAY(20);
 347
 348         /* Issue the read EEPROM command. */
 349         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 350
 351         /* Wait for completion */
 352         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
 353                 DELAY(10);
 354                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 355                         break;
 356         }
 357
 358         if (i == BNX_TIMEOUT) {
 359                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 360                 return(1);
 361         }
 362
 363         /* Get result. */
 364         byte = CSR_READ_4(sc, BGE_EE_DATA);
 365
 366         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 367
 368         return(0);
 369 }
 370
 371 /*
 372  * Read a sequence of bytes from the EEPROM.
 373  */
 374 static int
 375 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
 376 {
 377         size_t i;
 378         int err;
 379         uint8_t byte;
 380
 381         for (byte = 0, err = 0, i = 0; i < len; i++) {
 382                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
 383                 if (err)
 384                         break;
 385                 *(dest + i) = byte;
 386         }
 387
 388         return(err ? 1 : 0);
 389 }
 390
 391 static int
 392 bnx_miibus_readreg(device_t dev, int phy, int reg)
 393 {
 394         struct bnx_softc *sc = device_get_softc(dev);
 395         uint32_t val;
 396         int i;
 397
 398         KASSERT(phy == sc->bnx_phyno,
 399             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 400
 401         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 402         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 403                 CSR_WRITE_4(sc, BGE_MI_MODE,
 404                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 405                 DELAY(80);
 406         }
 407
 408         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 409             BGE_MIPHY(phy) | BGE_MIREG(reg));
 410
 411         /* Poll for the PHY register access to complete. */
 412         for (i = 0; i < BNX_TIMEOUT; i++) {
 413                 DELAY(10);
 414                 val = CSR_READ_4(sc, BGE_MI_COMM);
 415                 if ((val & BGE_MICOMM_BUSY) == 0) {
 416                         DELAY(5);
 417                         val = CSR_READ_4(sc, BGE_MI_COMM);
 418                         break;
 419                 }
 420         }
 421         if (i == BNX_TIMEOUT) {
 422                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 423                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 424                 val = 0;
 425         }
 426
 427         /* Restore the autopoll bit if necessary. */
 428         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 429                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 430                 DELAY(80);
 431         }
 432
 433         if (val & BGE_MICOMM_READFAIL)
 434                 return 0;
 435
 436         return (val & 0xFFFF);
 437 }
 438
 439 static int
 440 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
 441 {
 442         struct bnx_softc *sc = device_get_softc(dev);
 443         int i;
 444
 445         KASSERT(phy == sc->bnx_phyno,
 446             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 447
 448         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 449         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 450                 CSR_WRITE_4(sc, BGE_MI_MODE,
 451                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 452                 DELAY(80);
 453         }
 454
 455         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 456             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 457
 458         for (i = 0; i < BNX_TIMEOUT; i++) {
 459                 DELAY(10);
 460                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 461                         DELAY(5);
 462                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 463                         break;
 464                 }
 465         }
 466         if (i == BNX_TIMEOUT) {
 467                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 468                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 469         }
 470
 471         /* Restore the autopoll bit if necessary. */
 472         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 473                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 474                 DELAY(80);
 475         }
 476
 477         return 0;
 478 }
 479
 480 static void
 481 bnx_miibus_statchg(device_t dev)
 482 {
 483         struct bnx_softc *sc;
 484         struct mii_data *mii;
 485
 486         sc = device_get_softc(dev);
 487         mii = device_get_softc(sc->bnx_miibus);
 488
 489         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 490             (IFM_ACTIVE | IFM_AVALID)) {
 491                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 492                 case IFM_10_T:
 493                 case IFM_100_TX:
 494                         sc->bnx_link = 1;
 495                         break;
 496                 case IFM_1000_T:
 497                 case IFM_1000_SX:
 498                 case IFM_2500_SX:
 499                         sc->bnx_link = 1;
 500                         break;
 501                 default:
 502                         sc->bnx_link = 0;
 503                         break;
 504                 }
 505         } else {
 506                 sc->bnx_link = 0;
 507         }
 508         if (sc->bnx_link == 0)
 509                 return;
 510
 511         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 512         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 513             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 514                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 515         } else {
 516                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 517         }
 518
 519         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 520                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 521         } else {
 522                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 523         }
 524 }
 525
 526 /*
 527  * Memory management for jumbo frames.
 528  */
 529 static int
 530 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
 531 {
 532         struct ifnet *ifp = &sc->arpcom.ac_if;
 533         struct bnx_jslot *entry;
 534         uint8_t *ptr;
 535         bus_addr_t paddr;
 536         int i, error;
 537
 538         /*
 539          * Create tag for jumbo mbufs.
 540          * This is really a bit of a kludge. We allocate a special
 541          * jumbo buffer pool which (thanks to the way our DMA
 542          * memory allocation works) will consist of contiguous
 543          * pages. This means that even though a jumbo buffer might
 544          * be larger than a page size, we don't really need to
 545          * map it into more than one DMA segment. However, the
 546          * default mbuf tag will result in multi-segment mappings,
 547          * so we have to create a special jumbo mbuf tag that
 548          * lets us get away with mapping the jumbo buffers as
 549          * a single segment. I think eventually the driver should
 550          * be changed so that it uses ordinary mbufs and cluster
 551          * buffers, i.e. jumbo frames can span multiple DMA
 552          * descriptors. But that's a project for another day.
 553          */
 554
 555         /*
 556          * Create DMA stuffs for jumbo RX ring.
 557          */
 558         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 559                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 560                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 561                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
 562                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
 563         if (error) {
 564                 if_printf(ifp, "could not create jumbo RX ring\n");
 565                 return error;
 566         }
 567
 568         /*
 569          * Create DMA stuffs for jumbo buffer block.
 570          */
 571         error = bnx_dma_block_alloc(sc, BNX_JMEM,
 572                                     &sc->bnx_cdata.bnx_jumbo_tag,
 573                                     &sc->bnx_cdata.bnx_jumbo_map,
 574                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
 575                                     &paddr);
 576         if (error) {
 577                 if_printf(ifp, "could not create jumbo buffer\n");
 578                 return error;
 579         }
 580
 581         SLIST_INIT(&sc->bnx_jfree_listhead);
 582
 583         /*
 584          * Now divide it up into 9K pieces and save the addresses
 585          * in an array. Note that we play an evil trick here by using
 586          * the first few bytes in the buffer to hold the the address
 587          * of the softc structure for this interface. This is because
 588          * bnx_jfree() needs it, but it is called by the mbuf management
 589          * code which will not pass it to us explicitly.
 590          */
 591         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
 592                 entry = &sc->bnx_cdata.bnx_jslots[i];
 593                 entry->bnx_sc = sc;
 594                 entry->bnx_buf = ptr;
 595                 entry->bnx_paddr = paddr;
 596                 entry->bnx_inuse = 0;
 597                 entry->bnx_slot = i;
 598                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
 599
 600                 ptr += BNX_JLEN;
 601                 paddr += BNX_JLEN;
 602         }
 603         return 0;
 604 }
 605
 606 static void
 607 bnx_free_jumbo_mem(struct bnx_softc *sc)
 608 {
 609         /* Destroy jumbo RX ring. */
 610         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 611                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 612                            sc->bnx_ldata.bnx_rx_jumbo_ring);
 613
 614         /* Destroy jumbo buffer block. */
 615         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
 616                            sc->bnx_cdata.bnx_jumbo_map,
 617                            sc->bnx_ldata.bnx_jumbo_buf);
 618 }
 619
 620 /*
 621  * Allocate a jumbo buffer.
 622  */
 623 static struct bnx_jslot *
 624 bnx_jalloc(struct bnx_softc *sc)
 625 {
 626         struct bnx_jslot *entry;
 627
 628         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 629         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
 630         if (entry) {
 631                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
 632                 entry->bnx_inuse = 1;
 633         } else {
 634                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 635         }
 636         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 637         return(entry);
 638 }
 639
 640 /*
 641  * Adjust usage count on a jumbo buffer.
 642  */
 643 static void
 644 bnx_jref(void *arg)
 645 {
 646         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 647         struct bnx_softc *sc = entry->bnx_sc;
 648
 649         if (sc == NULL)
 650                 panic("bnx_jref: can't find softc pointer!");
 651
 652         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 653                 panic("bnx_jref: asked to reference buffer "
 654                     "that we don't manage!");
 655         } else if (entry->bnx_inuse == 0) {
 656                 panic("bnx_jref: buffer already free!");
 657         } else {
 658                 atomic_add_int(&entry->bnx_inuse, 1);
 659         }
 660 }
 661
 662 /*
 663  * Release a jumbo buffer.
 664  */
 665 static void
 666 bnx_jfree(void *arg)
 667 {
 668         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 669         struct bnx_softc *sc = entry->bnx_sc;
 670
 671         if (sc == NULL)
 672                 panic("bnx_jfree: can't find softc pointer!");
 673
 674         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 675                 panic("bnx_jfree: asked to free buffer that we don't manage!");
 676         } else if (entry->bnx_inuse == 0) {
 677                 panic("bnx_jfree: buffer already free!");
 678         } else {
 679                 /*
 680                  * Possible MP race to 0, use the serializer.  The atomic insn
 681                  * is still needed for races against bnx_jref().
 682                  */
 683                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 684                 atomic_subtract_int(&entry->bnx_inuse, 1);
 685                 if (entry->bnx_inuse == 0) {
 686                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead,
 687                                           entry, jslot_link);
 688                 }
 689                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 690         }
 691 }
 692
 693
 694 /*
 695  * Intialize a standard receive ring descriptor.
 696  */
 697 static int
 698 bnx_newbuf_std(struct bnx_rx_ret_ring *ret, int i, int init)
 699 {
 700         struct mbuf *m_new = NULL;
 701         bus_dma_segment_t seg;
 702         bus_dmamap_t map;
 703         int error, nsegs;
 704         struct bnx_rx_buf *rb;
 705
 706         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 707         if (m_new == NULL)
 708                 return ENOBUFS;
 709         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 710         m_adj(m_new, ETHER_ALIGN);
 711
 712         error = bus_dmamap_load_mbuf_segment(ret->bnx_rx_mtag,
 713             ret->bnx_rx_tmpmap, m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 714         if (error) {
 715                 m_freem(m_new);
 716                 return error;
 717         }
 718
 719         rb = &ret->bnx_std->bnx_rx_std_buf[i];
 720
 721         if (!init) {
 722                 bus_dmamap_sync(ret->bnx_rx_mtag, rb->bnx_rx_dmamap,
 723                     BUS_DMASYNC_POSTREAD);
 724                 bus_dmamap_unload(ret->bnx_rx_mtag, rb->bnx_rx_dmamap);
 725         }
 726
 727         map = ret->bnx_rx_tmpmap;
 728         ret->bnx_rx_tmpmap = rb->bnx_rx_dmamap;
 729         rb->bnx_rx_dmamap = map;
 730
 731         rb->bnx_rx_mbuf = m_new;
 732         rb->bnx_rx_paddr = seg.ds_addr;
 733
 734         bnx_setup_rxdesc_std(ret->bnx_std, i);
 735         return 0;
 736 }
 737
 738 static void
 739 bnx_setup_rxdesc_std(struct bnx_rx_std_ring *std, int i)
 740 {
 741         const struct bnx_rx_buf *rb;
 742         struct bge_rx_bd *r;
 743
 744         rb = &std->bnx_rx_std_buf[i];
 745         r = &std->bnx_rx_std_ring[i];
 746
 747         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rb->bnx_rx_paddr);
 748         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rb->bnx_rx_paddr);
 749         r->bge_len = rb->bnx_rx_mbuf->m_len;
 750         r->bge_idx = i;
 751         r->bge_flags = BGE_RXBDFLAG_END;
 752 }
 753
 754 /*
 755  * Initialize a jumbo receive ring descriptor. This allocates
 756  * a jumbo buffer from the pool managed internally by the driver.
 757  */
 758 static int
 759 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
 760 {
 761         struct mbuf *m_new = NULL;
 762         struct bnx_jslot *buf;
 763         bus_addr_t paddr;
 764
 765         /* Allocate the mbuf. */
 766         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 767         if (m_new == NULL)
 768                 return ENOBUFS;
 769
 770         /* Allocate the jumbo buffer */
 771         buf = bnx_jalloc(sc);
 772         if (buf == NULL) {
 773                 m_freem(m_new);
 774                 return ENOBUFS;
 775         }
 776
 777         /* Attach the buffer to the mbuf. */
 778         m_new->m_ext.ext_arg = buf;
 779         m_new->m_ext.ext_buf = buf->bnx_buf;
 780         m_new->m_ext.ext_free = bnx_jfree;
 781         m_new->m_ext.ext_ref = bnx_jref;
 782         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
 783
 784         m_new->m_flags |= M_EXT;
 785
 786         m_new->m_data = m_new->m_ext.ext_buf;
 787         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 788
 789         paddr = buf->bnx_paddr;
 790         m_adj(m_new, ETHER_ALIGN);
 791         paddr += ETHER_ALIGN;
 792
 793         /* Save necessary information */
 794         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_mbuf = m_new;
 795         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_paddr = paddr;
 796
 797         /* Set up the descriptor. */
 798         bnx_setup_rxdesc_jumbo(sc, i);
 799         return 0;
 800 }
 801
 802 static void
 803 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
 804 {
 805         struct bge_rx_bd *r;
 806         struct bnx_rx_buf *rc;
 807
 808         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
 809         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 810
 811         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_rx_paddr);
 812         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_rx_paddr);
 813         r->bge_len = rc->bnx_rx_mbuf->m_len;
 814         r->bge_idx = i;
 815         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 816 }
 817
 818 static int
 819 bnx_init_rx_ring_std(struct bnx_rx_std_ring *std)
 820 {
 821         int i, error;
 822
 823         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 824                 /* Use the first RX return ring's tmp RX mbuf DMA map */
 825                 error = bnx_newbuf_std(&std->bnx_sc->bnx_rx_ret_ring[0], i, 1);
 826                 if (error)
 827                         return error;
 828         }
 829
 830         std->bnx_rx_std = BGE_STD_RX_RING_CNT - 1;
 831         bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO, std->bnx_rx_std);
 832
 833         return(0);
 834 }
 835
 836 static void
 837 bnx_free_rx_ring_std(struct bnx_rx_std_ring *std)
 838 {
 839         int i;
 840
 841         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 842                 struct bnx_rx_buf *rb = &std->bnx_rx_std_buf[i];
 843
 844                 if (rb->bnx_rx_mbuf != NULL) {
 845                         bus_dmamap_unload(std->bnx_rx_mtag, rb->bnx_rx_dmamap);
 846                         m_freem(rb->bnx_rx_mbuf);
 847                         rb->bnx_rx_mbuf = NULL;
 848                 }
 849                 bzero(&std->bnx_rx_std_ring[i], sizeof(struct bge_rx_bd));
 850         }
 851 }
 852
 853 static int
 854 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
 855 {
 856         struct bge_rcb *rcb;
 857         int i, error;
 858
 859         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 860                 error = bnx_newbuf_jumbo(sc, i, 1);
 861                 if (error)
 862                         return error;
 863         }
 864
 865         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
 866
 867         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
 868         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 869         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 870
 871         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
 872
 873         return(0);
 874 }
 875
 876 static void
 877 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
 878 {
 879         int i;
 880
 881         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 882                 struct bnx_rx_buf *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 883
 884                 if (rc->bnx_rx_mbuf != NULL) {
 885                         m_freem(rc->bnx_rx_mbuf);
 886                         rc->bnx_rx_mbuf = NULL;
 887                 }
 888                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
 889                     sizeof(struct bge_rx_bd));
 890         }
 891 }
 892
 893 static void
 894 bnx_free_tx_ring(struct bnx_tx_ring *txr)
 895 {
 896         int i;
 897
 898         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 899                 struct bnx_tx_buf *buf = &txr->bnx_tx_buf[i];
 900
 901                 if (buf->bnx_tx_mbuf != NULL) {
 902                         bus_dmamap_unload(txr->bnx_tx_mtag,
 903                             buf->bnx_tx_dmamap);
 904                         m_freem(buf->bnx_tx_mbuf);
 905                         buf->bnx_tx_mbuf = NULL;
 906                 }
 907                 bzero(&txr->bnx_tx_ring[i], sizeof(struct bge_tx_bd));
 908         }
 909         txr->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
 910 }
 911
 912 static int
 913 bnx_init_tx_ring(struct bnx_tx_ring *txr)
 914 {
 915         txr->bnx_tx_cnt = 0;
 916         txr->bnx_tx_saved_considx = 0;
 917         txr->bnx_tx_prodidx = 0;
 918
 919         /* Initialize transmit producer index for host-memory send ring. */
 920         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, txr->bnx_tx_prodidx);
 921
 922         return(0);
 923 }
 924
 925 static void
 926 bnx_setmulti(struct bnx_softc *sc)
 927 {
 928         struct ifnet *ifp;
 929         struct ifmultiaddr *ifma;
 930         uint32_t hashes[4] = { 0, 0, 0, 0 };
 931         int h, i;
 932
 933         ifp = &sc->arpcom.ac_if;
 934
 935         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 936                 for (i = 0; i < 4; i++)
 937                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
 938                 return;
 939         }
 940
 941         /* First, zot all the existing filters. */
 942         for (i = 0; i < 4; i++)
 943                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
 944
 945         /* Now program new ones. */
 946         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 947                 if (ifma->ifma_addr->sa_family != AF_LINK)
 948                         continue;
 949                 h = ether_crc32_le(
 950                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 951                     ETHER_ADDR_LEN) & 0x7f;
 952                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
 953         }
 954
 955         for (i = 0; i < 4; i++)
 956                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
 957 }
 958
 959 /*
 960  * Do endian, PCI and DMA initialization. Also check the on-board ROM
 961  * self-test results.
 962  */
 963 static int
 964 bnx_chipinit(struct bnx_softc *sc)
 965 {
 966         uint32_t dma_rw_ctl, mode_ctl;
 967         int i;
 968
 969         /* Set endian type before we access any non-PCI registers. */
 970         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
 971             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
 972
 973         /* Clear the MAC control register */
 974         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
 975
 976         /*
 977          * Clear the MAC statistics block in the NIC's
 978          * internal memory.
 979          */
 980         for (i = BGE_STATS_BLOCK;
 981             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
 982                 BNX_MEMWIN_WRITE(sc, i, 0);
 983
 984         for (i = BGE_STATUS_BLOCK;
 985             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
 986                 BNX_MEMWIN_WRITE(sc, i, 0);
 987
 988         if (BNX_IS_57765_FAMILY(sc)) {
 989                 uint32_t val;
 990
 991                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
 992                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
 993                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
 994
 995                         /* Access the lower 1K of PL PCI-E block registers. */
 996                         CSR_WRITE_4(sc, BGE_MODE_CTL,
 997                             val | BGE_MODECTL_PCIE_PL_SEL);
 998
 999                         val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
1000                         val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
1001                         CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
1002
1003                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1004                 }
1005                 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1006                         /* Fix transmit hangs */
1007                         val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
1008                         val |= BGE_CPMU_PADRNG_CTL_RDIV2;
1009                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val);
1010
1011                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1012                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1013
1014                         /* Access the lower 1K of DL PCI-E block registers. */
1015                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1016                             val | BGE_MODECTL_PCIE_DL_SEL);
1017
1018                         val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1019                         val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1020                         val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1021                         CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1022
1023                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1024                 }
1025
1026                 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1027                 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1028                 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1029                 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1030         }
1031
1032         /*
1033          * Set up the PCI DMA control register.
1034          */
1035         dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1036         /*
1037          * Disable 32bytes cache alignment for DMA write to host memory
1038          *
1039          * NOTE:
1040          * 64bytes cache alignment for DMA write to host memory is still
1041          * enabled.
1042          */
1043         dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1044         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1045                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1046         /*
1047          * Enable HW workaround for controllers that misinterpret
1048          * a status tag update and leave interrupts permanently
1049          * disabled.
1050          */
1051         if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1052             sc->bnx_asicrev != BGE_ASICREV_BCM5762 &&
1053             !BNX_IS_57765_FAMILY(sc))
1054                 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1055         if (bootverbose) {
1056                 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1057                     dma_rw_ctl);
1058         }
1059         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1060
1061         /*
1062          * Set up general mode register.
1063          */
1064         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1065             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1066         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1067
1068         /*
1069          * Disable memory write invalidate.  Apparently it is not supported
1070          * properly by these devices.  Also ensure that INTx isn't disabled,
1071          * as these chips need it even when using MSI.
1072          */
1073         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1074             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1075
1076         /* Set the timer prescaler (always 66Mhz) */
1077         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1078
1079         return(0);
1080 }
1081
1082 static int
1083 bnx_blockinit(struct bnx_softc *sc)
1084 {
1085         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
1086         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
1087         struct bge_rcb *rcb;
1088         bus_size_t vrcb;
1089         bge_hostaddr taddr;
1090         uint32_t val;
1091         int i, limit;
1092
1093         /*
1094          * Initialize the memory window pointer register so that
1095          * we can access the first 32K of internal NIC RAM. This will
1096          * allow us to set up the TX send ring RCBs and the RX return
1097          * ring RCBs, plus other things which live in NIC memory.
1098          */
1099         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1100
1101         /* Configure mbuf pool watermarks */
1102         if (BNX_IS_57765_PLUS(sc)) {
1103                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1104                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1105                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1106                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1107                 } else {
1108                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1109                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1110                 }
1111         } else {
1112                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1113                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1114                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1115         }
1116
1117         /* Configure DMA resource watermarks */
1118         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1119         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1120
1121         /* Enable buffer manager */
1122         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1123         /*
1124          * Change the arbitration algorithm of TXMBUF read request to
1125          * round-robin instead of priority based for BCM5719.  When
1126          * TXFIFO is almost empty, RDMA will hold its request until
1127          * TXFIFO is not almost empty.
1128          */
1129         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1130                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1131         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1132             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1133             sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1134                 val |= BGE_BMANMODE_LOMBUF_ATTN;
1135         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1136
1137         /* Poll for buffer manager start indication */
1138         for (i = 0; i < BNX_TIMEOUT; i++) {
1139                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1140                         break;
1141                 DELAY(10);
1142         }
1143
1144         if (i == BNX_TIMEOUT) {
1145                 if_printf(&sc->arpcom.ac_if,
1146                           "buffer manager failed to start\n");
1147                 return(ENXIO);
1148         }
1149
1150         /* Enable flow-through queues */
1151         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1152         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1153
1154         /* Wait until queue initialization is complete */
1155         for (i = 0; i < BNX_TIMEOUT; i++) {
1156                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1157                         break;
1158                 DELAY(10);
1159         }
1160
1161         if (i == BNX_TIMEOUT) {
1162                 if_printf(&sc->arpcom.ac_if,
1163                           "flow-through queue init failed\n");
1164                 return(ENXIO);
1165         }
1166
1167         /*
1168          * Summary of rings supported by the controller:
1169          *
1170          * Standard Receive Producer Ring
1171          * - This ring is used to feed receive buffers for "standard"
1172          *   sized frames (typically 1536 bytes) to the controller.
1173          *
1174          * Jumbo Receive Producer Ring
1175          * - This ring is used to feed receive buffers for jumbo sized
1176          *   frames (i.e. anything bigger than the "standard" frames)
1177          *   to the controller.
1178          *
1179          * Mini Receive Producer Ring
1180          * - This ring is used to feed receive buffers for "mini"
1181          *   sized frames to the controller.
1182          * - This feature required external memory for the controller
1183          *   but was never used in a production system.  Should always
1184          *   be disabled.
1185          *
1186          * Receive Return Ring
1187          * - After the controller has placed an incoming frame into a
1188          *   receive buffer that buffer is moved into a receive return
1189          *   ring.  The driver is then responsible to passing the
1190          *   buffer up to the stack.  Many versions of the controller
1191          *   support multiple RR rings.
1192          *
1193          * Send Ring
1194          * - This ring is used for outgoing frames.  Many versions of
1195          *   the controller support multiple send rings.
1196          */
1197
1198         /* Initialize the standard receive producer ring control block. */
1199         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1200         rcb->bge_hostaddr.bge_addr_lo =
1201             BGE_ADDR_LO(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1202         rcb->bge_hostaddr.bge_addr_hi =
1203             BGE_ADDR_HI(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1204         if (BNX_IS_57765_PLUS(sc)) {
1205                 /*
1206                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1207                  * Bits 15-2 : Maximum RX frame size
1208                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1209                  * Bit 0     : Reserved
1210                  */
1211                 rcb->bge_maxlen_flags =
1212                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1213         } else {
1214                 /*
1215                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1216                  * Bits 15-2 : Reserved (should be 0)
1217                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1218                  * Bit 0     : Reserved
1219                  */
1220                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1221         }
1222         if (BNX_IS_5717_PLUS(sc))
1223                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1224         else
1225                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1226         /* Write the standard receive producer ring control block. */
1227         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1228         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1229         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1230         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1231         /* Reset the standard receive producer ring producer index. */
1232         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1233
1234         /*
1235          * Initialize the jumbo RX producer ring control
1236          * block.  We set the 'ring disabled' bit in the
1237          * flags field until we're actually ready to start
1238          * using this ring (i.e. once we set the MTU
1239          * high enough to require it).
1240          */
1241         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1242                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1243                 /* Get the jumbo receive producer ring RCB parameters. */
1244                 rcb->bge_hostaddr.bge_addr_lo =
1245                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1246                 rcb->bge_hostaddr.bge_addr_hi =
1247                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1248                 rcb->bge_maxlen_flags =
1249                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1250                     BGE_RCB_FLAG_RING_DISABLED);
1251                 if (BNX_IS_5717_PLUS(sc))
1252                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1253                 else
1254                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1255                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1256                     rcb->bge_hostaddr.bge_addr_hi);
1257                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1258                     rcb->bge_hostaddr.bge_addr_lo);
1259                 /* Program the jumbo receive producer ring RCB parameters. */
1260                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1261                     rcb->bge_maxlen_flags);
1262                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1263                 /* Reset the jumbo receive producer ring producer index. */
1264                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1265         }
1266
1267         /*
1268          * The BD ring replenish thresholds control how often the
1269          * hardware fetches new BD's from the producer rings in host
1270          * memory.  Setting the value too low on a busy system can
1271          * starve the hardware and recue the throughpout.
1272          *
1273          * Set the BD ring replentish thresholds. The recommended
1274          * values are 1/8th the number of descriptors allocated to
1275          * each ring.
1276          */
1277         val = 8;
1278         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1279         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1280                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1281                     BGE_JUMBO_RX_RING_CNT/8);
1282         }
1283         if (BNX_IS_57765_PLUS(sc)) {
1284                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1285                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1286         }
1287
1288         /*
1289          * Disable all send rings by setting the 'ring disabled' bit
1290          * in the flags field of all the TX send ring control blocks,
1291          * located in NIC memory.
1292          */
1293         if (BNX_IS_5717_PLUS(sc))
1294                 limit = 4;
1295         else if (BNX_IS_57765_FAMILY(sc) ||
1296             sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1297                 limit = 2;
1298         else
1299                 limit = 1;
1300         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1301         for (i = 0; i < limit; i++) {
1302                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1303                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1304                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1305                 vrcb += sizeof(struct bge_rcb);
1306         }
1307
1308         /* Configure send ring RCB 0 (we use only the first ring) */
1309         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1310         BGE_HOSTADDR(taddr, txr->bnx_tx_ring_paddr);
1311         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1312         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1313         if (BNX_IS_5717_PLUS(sc)) {
1314                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1315         } else {
1316                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1317                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1318         }
1319         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1320             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1321
1322         /*
1323          * Disable all receive return rings by setting the
1324          * 'ring disabled' bit in the flags field of all the receive
1325          * return ring control blocks, located in NIC memory.
1326          */
1327         if (BNX_IS_5717_PLUS(sc)) {
1328                 /* Should be 17, use 16 until we get an SRAM map. */
1329                 limit = 16;
1330         } else if (BNX_IS_57765_FAMILY(sc) ||
1331             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1332                 limit = 4;
1333         } else {
1334                 limit = 1;
1335         }
1336         /* Disable all receive return rings. */
1337         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1338         for (i = 0; i < limit; i++) {
1339                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1340                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1341                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1342                     BGE_RCB_FLAG_RING_DISABLED);
1343                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1344                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1345                     (i * (sizeof(uint64_t))), 0);
1346                 vrcb += sizeof(struct bge_rcb);
1347         }
1348
1349         /*
1350          * Set up receive return ring 0.  Note that the NIC address
1351          * for RX return rings is 0x0.  The return rings live entirely
1352          * within the host, so the nicaddr field in the RCB isn't used.
1353          */
1354         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1355         BGE_HOSTADDR(taddr, ret->bnx_rx_ret_ring_paddr);
1356         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1357         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1358         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1359         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1360             BGE_RCB_MAXLEN_FLAGS(BNX_RETURN_RING_CNT, 0));
1361
1362         /* Set random backoff seed for TX */
1363         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1364             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1365             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1366             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1367             BGE_TX_BACKOFF_SEED_MASK);
1368
1369         /* Set inter-packet gap */
1370         val = 0x2620;
1371         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1372             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1373                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1374                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1375         }
1376         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1377
1378         /*
1379          * Specify which ring to use for packets that don't match
1380          * any RX rules.
1381          */
1382         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1383
1384         /*
1385          * Configure number of RX lists. One interrupt distribution
1386          * list, sixteen active lists, one bad frames class.
1387          */
1388         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1389
1390         /* Inialize RX list placement stats mask. */
1391         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1392         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1393
1394         /* Disable host coalescing until we get it set up */
1395         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1396
1397         /* Poll to make sure it's shut down. */
1398         for (i = 0; i < BNX_TIMEOUT; i++) {
1399                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1400                         break;
1401                 DELAY(10);
1402         }
1403
1404         if (i == BNX_TIMEOUT) {
1405                 if_printf(&sc->arpcom.ac_if,
1406                           "host coalescing engine failed to idle\n");
1407                 return(ENXIO);
1408         }
1409
1410         /* Set up host coalescing defaults */
1411         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bnx_rx_coal_ticks);
1412         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bnx_tx_coal_ticks);
1413         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bnx_rx_coal_bds);
1414         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bnx_tx_coal_bds);
1415         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bnx_rx_coal_bds_int);
1416         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bnx_tx_coal_bds_int);
1417
1418         /* Set up address of status block */
1419         bzero(sc->bnx_ldata.bnx_status_block, BGE_STATUS_BLK_SZ);
1420         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1421             BGE_ADDR_HI(sc->bnx_ldata.bnx_status_block_paddr));
1422         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1423             BGE_ADDR_LO(sc->bnx_ldata.bnx_status_block_paddr));
1424
1425         /* Set up status block partail update size. */
1426         val = BGE_STATBLKSZ_32BYTE;
1427 #if 0
1428         /*
1429          * Does not seem to have visible effect in both
1430          * bulk data (1472B UDP datagram) and tiny data
1431          * (18B UDP datagram) TX tests.
1432          */
1433         val |= BGE_HCCMODE_CLRTICK_TX;
1434 #endif
1435         /* Turn on host coalescing state machine */
1436         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1437
1438         /* Turn on RX BD completion state machine and enable attentions */
1439         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1440             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1441
1442         /* Turn on RX list placement state machine */
1443         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1444
1445         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1446             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1447             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1448             BGE_MACMODE_FRMHDR_DMA_ENB;
1449
1450         if (sc->bnx_flags & BNX_FLAG_TBI)
1451                 val |= BGE_PORTMODE_TBI;
1452         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1453                 val |= BGE_PORTMODE_GMII;
1454         else
1455                 val |= BGE_PORTMODE_MII;
1456
1457         /* Turn on DMA, clear stats */
1458         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1459
1460         /* Set misc. local control, enable interrupts on attentions */
1461         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1462
1463 #ifdef notdef
1464         /* Assert GPIO pins for PHY reset */
1465         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1466             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1467         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1468             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1469 #endif
1470
1471         /* Turn on write DMA state machine */
1472         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1473         /* Enable host coalescing bug fix. */
1474         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1475         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1476                 /* Request larger DMA burst size to get better performance. */
1477                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1478         }
1479         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1480         DELAY(40);
1481
1482         if (BNX_IS_57765_PLUS(sc)) {
1483                 uint32_t dmactl, dmactl_reg;
1484
1485                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1486                         dmactl_reg = BGE_RDMA_RSRVCTRL2;
1487                 else
1488                         dmactl_reg = BGE_RDMA_RSRVCTRL;
1489
1490                 dmactl = CSR_READ_4(sc, dmactl_reg);
1491                 /*
1492                  * Adjust tx margin to prevent TX data corruption and
1493                  * fix internal FIFO overflow.
1494                  */
1495                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1496                     sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1497                     sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1498                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1499                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1500                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1501                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1502                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1503                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1504                 }
1505                 /*
1506                  * Enable fix for read DMA FIFO overruns.
1507                  * The fix is to limit the number of RX BDs
1508                  * the hardware would fetch at a fime.
1509                  */
1510                 CSR_WRITE_4(sc, dmactl_reg,
1511                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1512         }
1513
1514         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1515                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1516                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1517                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1518                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1519         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1520             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1521                 uint32_t ctrl_reg;
1522
1523                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1524                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2;
1525                 else
1526                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL;
1527
1528                 /*
1529                  * Allow 4KB burst length reads for non-LSO frames.
1530                  * Enable 512B burst length reads for buffer descriptors.
1531                  */
1532                 CSR_WRITE_4(sc, ctrl_reg,
1533                     CSR_READ_4(sc, ctrl_reg) |
1534                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1535                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1536         }
1537
1538         /* Turn on read DMA state machine */
1539         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1540         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1541                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1542         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1543             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1544             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1545                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1546                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1547                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1548         }
1549         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1550             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1551                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1552                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1553                 /*
1554                  * Allow multiple outstanding read requests from
1555                  * non-LSO read DMA engine.
1556                  */
1557                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1558         }
1559         if (sc->bnx_asicrev == BGE_ASICREV_BCM57766)
1560                 val |= BGE_RDMAMODE_JMB_2K_MMRR;
1561         if (sc->bnx_flags & BNX_FLAG_TSO)
1562                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1563         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1564         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1565         DELAY(40);
1566
1567         /* Turn on RX data completion state machine */
1568         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1569
1570         /* Turn on RX BD initiator state machine */
1571         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1572
1573         /* Turn on RX data and RX BD initiator state machine */
1574         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1575
1576         /* Turn on send BD completion state machine */
1577         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1578
1579         /* Turn on send data completion state machine */
1580         val = BGE_SDCMODE_ENABLE;
1581         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1582                 val |= BGE_SDCMODE_CDELAY;
1583         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1584
1585         /* Turn on send data initiator state machine */
1586         if (sc->bnx_flags & BNX_FLAG_TSO) {
1587                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1588                     BGE_SDIMODE_HW_LSO_PRE_DMA);
1589         } else {
1590                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1591         }
1592
1593         /* Turn on send BD initiator state machine */
1594         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1595
1596         /* Turn on send BD selector state machine */
1597         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1598
1599         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1600         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1601             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1602
1603         /* ack/clear link change events */
1604         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1605             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1606             BGE_MACSTAT_LINK_CHANGED);
1607         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1608
1609         /*
1610          * Enable attention when the link has changed state for
1611          * devices that use auto polling.
1612          */
1613         if (sc->bnx_flags & BNX_FLAG_TBI) {
1614                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1615         } else {
1616                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1617                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1618                         DELAY(80);
1619                 }
1620         }
1621
1622         /*
1623          * Clear any pending link state attention.
1624          * Otherwise some link state change events may be lost until attention
1625          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1626          * It's not necessary on newer BCM chips - perhaps enabling link
1627          * state change attentions implies clearing pending attention.
1628          */
1629         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1630             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1631             BGE_MACSTAT_LINK_CHANGED);
1632
1633         /* Enable link state change attentions. */
1634         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1635
1636         return(0);
1637 }
1638
1639 /*
1640  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1641  * against our list and return its name if we find a match. Note
1642  * that since the Broadcom controller contains VPD support, we
1643  * can get the device name string from the controller itself instead
1644  * of the compiled-in string. This is a little slow, but it guarantees
1645  * we'll always announce the right product name.
1646  */
1647 static int
1648 bnx_probe(device_t dev)
1649 {
1650         const struct bnx_type *t;
1651         uint16_t product, vendor;
1652
1653         if (!pci_is_pcie(dev))
1654                 return ENXIO;
1655
1656         product = pci_get_device(dev);
1657         vendor = pci_get_vendor(dev);
1658
1659         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1660                 if (vendor == t->bnx_vid && product == t->bnx_did)
1661                         break;
1662         }
1663         if (t->bnx_name == NULL)
1664                 return ENXIO;
1665
1666         device_set_desc(dev, t->bnx_name);
1667         return 0;
1668 }
1669
1670 static int
1671 bnx_attach(device_t dev)
1672 {
1673         struct ifnet *ifp;
1674         struct bnx_softc *sc;
1675         uint32_t hwcfg = 0;
1676         int error = 0, rid, capmask;
1677         uint8_t ether_addr[ETHER_ADDR_LEN];
1678         uint16_t product;
1679         uintptr_t mii_priv = 0;
1680 #ifdef BNX_TSO_DEBUG
1681         char desc[32];
1682         int i;
1683 #endif
1684
1685         sc = device_get_softc(dev);
1686         sc->bnx_dev = dev;
1687         callout_init_mp(&sc->bnx_stat_timer);
1688         callout_init_mp(&sc->bnx_intr_timer);
1689         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1690
1691         product = pci_get_device(dev);
1692
1693 #ifndef BURN_BRIDGES
1694         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1695                 uint32_t irq, mem;
1696
1697                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1698                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1699
1700                 device_printf(dev, "chip is in D%d power mode "
1701                     "-- setting to D0\n", pci_get_powerstate(dev));
1702
1703                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1704
1705                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1706                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1707         }
1708 #endif  /* !BURN_BRIDGE */
1709
1710         /*
1711          * Map control/status registers.
1712          */
1713         pci_enable_busmaster(dev);
1714
1715         rid = BGE_PCI_BAR0;
1716         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1717             RF_ACTIVE);
1718
1719         if (sc->bnx_res == NULL) {
1720                 device_printf(dev, "couldn't map memory\n");
1721                 return ENXIO;
1722         }
1723
1724         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1725         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1726
1727         /* Save various chip information */
1728         sc->bnx_chipid =
1729             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1730             BGE_PCIMISCCTL_ASICREV_SHIFT;
1731         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1732                 /* All chips having dedicated ASICREV register have CPMU */
1733                 sc->bnx_flags |= BNX_FLAG_CPMU;
1734
1735                 switch (product) {
1736                 case PCI_PRODUCT_BROADCOM_BCM5717:
1737                 case PCI_PRODUCT_BROADCOM_BCM5717C:
1738                 case PCI_PRODUCT_BROADCOM_BCM5718:
1739                 case PCI_PRODUCT_BROADCOM_BCM5719:
1740                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1741                 case PCI_PRODUCT_BROADCOM_BCM5725:
1742                 case PCI_PRODUCT_BROADCOM_BCM5727:
1743                 case PCI_PRODUCT_BROADCOM_BCM5762:
1744                         sc->bnx_chipid = pci_read_config(dev,
1745                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1746                         break;
1747
1748                 case PCI_PRODUCT_BROADCOM_BCM57761:
1749                 case PCI_PRODUCT_BROADCOM_BCM57762:
1750                 case PCI_PRODUCT_BROADCOM_BCM57765:
1751                 case PCI_PRODUCT_BROADCOM_BCM57766:
1752                 case PCI_PRODUCT_BROADCOM_BCM57781:
1753                 case PCI_PRODUCT_BROADCOM_BCM57782:
1754                 case PCI_PRODUCT_BROADCOM_BCM57785:
1755                 case PCI_PRODUCT_BROADCOM_BCM57786:
1756                 case PCI_PRODUCT_BROADCOM_BCM57791:
1757                 case PCI_PRODUCT_BROADCOM_BCM57795:
1758                         sc->bnx_chipid = pci_read_config(dev,
1759                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1760                         break;
1761
1762                 default:
1763                         sc->bnx_chipid = pci_read_config(dev,
1764                             BGE_PCI_PRODID_ASICREV, 4);
1765                         break;
1766                 }
1767         }
1768         if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0)
1769                 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0;
1770
1771         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1772         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1773
1774         switch (sc->bnx_asicrev) {
1775         case BGE_ASICREV_BCM5717:
1776         case BGE_ASICREV_BCM5719:
1777         case BGE_ASICREV_BCM5720:
1778                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1779                 break;
1780
1781         case BGE_ASICREV_BCM5762:
1782                 sc->bnx_flags |= BNX_FLAG_57765_PLUS;
1783                 break;
1784
1785         case BGE_ASICREV_BCM57765:
1786         case BGE_ASICREV_BCM57766:
1787                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1788                 break;
1789         }
1790
1791         sc->bnx_flags |= BNX_FLAG_TSO;
1792         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1793             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1794                 sc->bnx_flags &= ~BNX_FLAG_TSO;
1795
1796         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1797             BNX_IS_57765_FAMILY(sc)) {
1798                 /*
1799                  * All BCM57785 and BCM5718 families chips have a bug that
1800                  * under certain situation interrupt will not be enabled
1801                  * even if status tag is written to BGE_MBX_IRQ0_LO mailbox.
1802                  *
1803                  * While BCM5719 and BCM5720 have a hardware workaround
1804                  * which could fix the above bug.
1805                  * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1806                  * bnx_chipinit().
1807                  *
1808                  * For the rest of the chips in these two families, we will
1809                  * have to poll the status block at high rate (10ms currently)
1810                  * to check whether the interrupt is hosed or not.
1811                  * See bnx_intr_check() for details.
1812                  */
1813                 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1814         }
1815
1816         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1817         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1818             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1819                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1820         else
1821                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1822         device_printf(dev, "CHIP ID 0x%08x; "
1823                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1824                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1825
1826         /*
1827          * Set various PHY quirk flags.
1828          */
1829
1830         capmask = MII_CAPMASK_DEFAULT;
1831         if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1832             product == PCI_PRODUCT_BROADCOM_BCM57795) {
1833                 /* 10/100 only */
1834                 capmask &= ~BMSR_EXTSTAT;
1835         }
1836
1837         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1838         if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0)
1839                 mii_priv |= BRGPHY_FLAG_5762_A0;
1840
1841         /* Initialize if_name earlier, so if_printf could be used */
1842         ifp = &sc->arpcom.ac_if;
1843         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1844
1845         /* Try to reset the chip. */
1846         bnx_reset(sc);
1847
1848         if (bnx_chipinit(sc)) {
1849                 device_printf(dev, "chip initialization failed\n");
1850                 error = ENXIO;
1851                 goto fail;
1852         }
1853
1854         /*
1855          * Get station address
1856          */
1857         error = bnx_get_eaddr(sc, ether_addr);
1858         if (error) {
1859                 device_printf(dev, "failed to read station address\n");
1860                 goto fail;
1861         }
1862
1863         /* XXX */
1864         sc->bnx_tx_ringcnt = 1;
1865         sc->bnx_rx_retcnt = 1;
1866
1867         error = bnx_dma_alloc(dev);
1868         if (error)
1869                 goto fail;
1870
1871         /*
1872          * Allocate interrupt
1873          */
1874         error = bnx_alloc_intr(sc);
1875         if (error)
1876                 goto fail;
1877
1878         /* Set default tuneable values. */
1879         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
1880         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
1881         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
1882         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
1883         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
1884         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
1885
1886         /* Set up ifnet structure */
1887         ifp->if_softc = sc;
1888         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1889         ifp->if_ioctl = bnx_ioctl;
1890         ifp->if_start = bnx_start;
1891 #ifdef IFPOLL_ENABLE
1892         ifp->if_npoll = bnx_npoll;
1893 #endif
1894         ifp->if_watchdog = bnx_watchdog;
1895         ifp->if_init = bnx_init;
1896         ifp->if_mtu = ETHERMTU;
1897         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1898         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1899         ifq_set_ready(&ifp->if_snd);
1900
1901         ifp->if_capabilities |= IFCAP_HWCSUM;
1902         ifp->if_hwassist = BNX_CSUM_FEATURES;
1903         if (sc->bnx_flags & BNX_FLAG_TSO) {
1904                 ifp->if_capabilities |= IFCAP_TSO;
1905                 ifp->if_hwassist |= CSUM_TSO;
1906         }
1907         ifp->if_capenable = ifp->if_capabilities;
1908
1909         /*
1910          * Figure out what sort of media we have by checking the
1911          * hardware config word in the first 32k of NIC internal memory,
1912          * or fall back to examining the EEPROM if necessary.
1913          * Note: on some BCM5700 cards, this value appears to be unset.
1914          * If that's the case, we have to rely on identifying the NIC
1915          * by its PCI subsystem ID, as we do below for the SysKonnect
1916          * SK-9D41.
1917          */
1918         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
1919                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1920         } else {
1921                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1922                                     sizeof(hwcfg))) {
1923                         device_printf(dev, "failed to read EEPROM\n");
1924                         error = ENXIO;
1925                         goto fail;
1926                 }
1927                 hwcfg = ntohl(hwcfg);
1928         }
1929
1930         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1931         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
1932             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1933                 sc->bnx_flags |= BNX_FLAG_TBI;
1934
1935         /* Setup MI MODE */
1936         if (sc->bnx_flags & BNX_FLAG_CPMU)
1937                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
1938         else
1939                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
1940
1941         /* Setup link status update stuffs */
1942         if (sc->bnx_flags & BNX_FLAG_TBI) {
1943                 sc->bnx_link_upd = bnx_tbi_link_upd;
1944                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1945         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1946                 sc->bnx_link_upd = bnx_autopoll_link_upd;
1947                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1948         } else {
1949                 sc->bnx_link_upd = bnx_copper_link_upd;
1950                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1951         }
1952
1953         /* Set default PHY address */
1954         sc->bnx_phyno = 1;
1955
1956         /*
1957          * PHY address mapping for various devices.
1958          *
1959          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
1960          * ---------+-------+-------+-------+-------+
1961          * BCM57XX  |   1   |   X   |   X   |   X   |
1962          * BCM5704  |   1   |   X   |   1   |   X   |
1963          * BCM5717  |   1   |   8   |   2   |   9   |
1964          * BCM5719  |   1   |   8   |   2   |   9   |
1965          * BCM5720  |   1   |   8   |   2   |   9   |
1966          *
1967          * Other addresses may respond but they are not
1968          * IEEE compliant PHYs and should be ignored.
1969          */
1970         if (BNX_IS_5717_PLUS(sc)) {
1971                 int f;
1972
1973                 f = pci_get_function(dev);
1974                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
1975                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
1976                             BGE_SGDIGSTS_IS_SERDES)
1977                                 sc->bnx_phyno = f + 8;
1978                         else
1979                                 sc->bnx_phyno = f + 1;
1980                 } else {
1981                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
1982                             BGE_CPMU_PHY_STRAP_IS_SERDES)
1983                                 sc->bnx_phyno = f + 8;
1984                         else
1985                                 sc->bnx_phyno = f + 1;
1986                 }
1987         }
1988
1989         if (sc->bnx_flags & BNX_FLAG_TBI) {
1990                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
1991                     bnx_ifmedia_upd, bnx_ifmedia_sts);
1992                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1993                 ifmedia_add(&sc->bnx_ifmedia,
1994                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1995                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1996                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
1997                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
1998         } else {
1999                 struct mii_probe_args mii_args;
2000
2001                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2002                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2003                 mii_args.mii_capmask = capmask;
2004                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2005                 mii_args.mii_priv = mii_priv;
2006
2007                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2008                 if (error) {
2009                         device_printf(dev, "MII without any PHY!\n");
2010                         goto fail;
2011                 }
2012         }
2013
2014         /*
2015          * Create sysctl nodes.
2016          */
2017         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2018         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2019                                               SYSCTL_STATIC_CHILDREN(_hw),
2020                                               OID_AUTO,
2021                                               device_get_nameunit(dev),
2022                                               CTLFLAG_RD, 0, "");
2023         if (sc->bnx_sysctl_tree == NULL) {
2024                 device_printf(dev, "can't add sysctl node\n");
2025                 error = ENXIO;
2026                 goto fail;
2027         }
2028
2029         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2030                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2031                         OID_AUTO, "rx_coal_ticks",
2032                         CTLTYPE_INT | CTLFLAG_RW,
2033                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2034                         "Receive coalescing ticks (usec).");
2035         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2036                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2037                         OID_AUTO, "tx_coal_ticks",
2038                         CTLTYPE_INT | CTLFLAG_RW,
2039                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2040                         "Transmit coalescing ticks (usec).");
2041         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2042                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2043                         OID_AUTO, "rx_coal_bds",
2044                         CTLTYPE_INT | CTLFLAG_RW,
2045                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2046                         "Receive max coalesced BD count.");
2047         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2048                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2049                         OID_AUTO, "tx_coal_bds",
2050                         CTLTYPE_INT | CTLFLAG_RW,
2051                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2052                         "Transmit max coalesced BD count.");
2053         /*
2054          * A common design characteristic for many Broadcom
2055          * client controllers is that they only support a
2056          * single outstanding DMA read operation on the PCIe
2057          * bus. This means that it will take twice as long to
2058          * fetch a TX frame that is split into header and
2059          * payload buffers as it does to fetch a single,
2060          * contiguous TX frame (2 reads vs. 1 read). For these
2061          * controllers, coalescing buffers to reduce the number
2062          * of memory reads is effective way to get maximum
2063          * performance(about 940Mbps).  Without collapsing TX
2064          * buffers the maximum TCP bulk transfer performance
2065          * is about 850Mbps. However forcing coalescing mbufs
2066          * consumes a lot of CPU cycles, so leave it off by
2067          * default.
2068          */
2069         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2070             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2071             "force_defrag", CTLTYPE_INT | CTLFLAG_RW,
2072             sc, 0, bnx_sysctl_force_defrag, "I",
2073             "Force defragment on TX path");
2074
2075         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2076             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2077             "tx_wreg", CTLTYPE_INT | CTLFLAG_RW,
2078             sc, 0, bnx_sysctl_tx_wreg, "I",
2079             "# of segments before writing to hardware register");
2080
2081         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2082             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2083             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2084             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2085             "Receive max coalesced BD count during interrupt.");
2086         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2087             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2088             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2089             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2090             "Transmit max coalesced BD count during interrupt.");
2091
2092 #ifdef BNX_TSO_DEBUG
2093         for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2094                 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2095                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2096                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2097                     desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2098         }
2099 #endif
2100
2101         /*
2102          * Call MI attach routine.
2103          */
2104         ether_ifattach(ifp, ether_addr, NULL);
2105
2106         ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2107
2108 #ifdef IFPOLL_ENABLE
2109         ifpoll_compat_setup(&sc->bnx_npoll,
2110             &sc->bnx_sysctl_ctx, sc->bnx_sysctl_tree,
2111             device_get_unit(dev), ifp->if_serializer);
2112 #endif
2113
2114         error = bnx_setup_intr(sc);
2115         if (error) {
2116                 ether_ifdetach(ifp);
2117                 goto fail;
2118         }
2119
2120         sc->bnx_intr_cpuid = rman_get_cpuid(sc->bnx_irq);
2121         sc->bnx_stat_cpuid = sc->bnx_intr_cpuid;
2122
2123         return(0);
2124 fail:
2125         bnx_detach(dev);
2126         return(error);
2127 }
2128
2129 static int
2130 bnx_detach(device_t dev)
2131 {
2132         struct bnx_softc *sc = device_get_softc(dev);
2133
2134         if (device_is_attached(dev)) {
2135                 struct ifnet *ifp = &sc->arpcom.ac_if;
2136
2137                 lwkt_serialize_enter(ifp->if_serializer);
2138                 bnx_stop(sc);
2139                 bnx_reset(sc);
2140                 bus_teardown_intr(dev, sc->bnx_irq, sc->bnx_intrhand);
2141                 lwkt_serialize_exit(ifp->if_serializer);
2142
2143                 ether_ifdetach(ifp);
2144         }
2145
2146         if (sc->bnx_flags & BNX_FLAG_TBI)
2147                 ifmedia_removeall(&sc->bnx_ifmedia);
2148         if (sc->bnx_miibus)
2149                 device_delete_child(dev, sc->bnx_miibus);
2150         bus_generic_detach(dev);
2151
2152         bnx_free_intr(sc);
2153
2154         if (sc->bnx_res != NULL) {
2155                 bus_release_resource(dev, SYS_RES_MEMORY,
2156                     BGE_PCI_BAR0, sc->bnx_res);
2157         }
2158
2159         if (sc->bnx_sysctl_tree != NULL)
2160                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2161
2162         bnx_dma_free(sc);
2163
2164         return 0;
2165 }
2166
2167 static void
2168 bnx_reset(struct bnx_softc *sc)
2169 {
2170         device_t dev;
2171         uint32_t cachesize, command, pcistate, reset;
2172         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2173         int i, val = 0;
2174         uint16_t devctl;
2175
2176         dev = sc->bnx_dev;
2177
2178         write_op = bnx_writemem_direct;
2179
2180         /* Save some important PCI state. */
2181         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2182         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2183         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2184
2185         pci_write_config(dev, BGE_PCI_MISC_CTL,
2186             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2187             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2188             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2189
2190         /* Disable fastboot on controllers that support it. */
2191         if (bootverbose)
2192                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2193         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2194
2195         /*
2196          * Write the magic number to SRAM at offset 0xB50.
2197          * When firmware finishes its initialization it will
2198          * write ~BGE_MAGIC_NUMBER to the same location.
2199          */
2200         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2201
2202         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2203
2204         /* XXX: Broadcom Linux driver. */
2205         /* Force PCI-E 1.0a mode */
2206         if (!BNX_IS_57765_PLUS(sc) &&
2207             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2208             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2209              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2210                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2211                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2212         }
2213         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2214                 /* Prevent PCIE link training during global reset */
2215                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2216                 reset |= (1<<29);
2217         }
2218
2219         /*
2220          * Set GPHY Power Down Override to leave GPHY
2221          * powered up in D0 uninitialized.
2222          */
2223         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2224                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2225
2226         /* Issue global reset */
2227         write_op(sc, BGE_MISC_CFG, reset);
2228
2229         DELAY(1000);
2230
2231         /* XXX: Broadcom Linux driver. */
2232         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2233                 uint32_t v;
2234
2235                 DELAY(500000); /* wait for link training to complete */
2236                 v = pci_read_config(dev, 0xc4, 4);
2237                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2238         }
2239
2240         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2241
2242         /* Disable no snoop and disable relaxed ordering. */
2243         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2244
2245         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2246         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2247                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2248                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2249         }
2250
2251         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2252             devctl, 2);
2253
2254         /* Clear error status. */
2255         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2256             PCIEM_DEVSTS_CORR_ERR |
2257             PCIEM_DEVSTS_NFATAL_ERR |
2258             PCIEM_DEVSTS_FATAL_ERR |
2259             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2260
2261         /* Reset some of the PCI state that got zapped by reset */
2262         pci_write_config(dev, BGE_PCI_MISC_CTL,
2263             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2264             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2265             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2266         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2267         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2268         write_op(sc, BGE_MISC_CFG, (65 << 1));
2269
2270         /* Enable memory arbiter */
2271         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2272
2273         /*
2274          * Poll until we see the 1's complement of the magic number.
2275          * This indicates that the firmware initialization is complete.
2276          */
2277         for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2278                 val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2279                 if (val == ~BGE_MAGIC_NUMBER)
2280                         break;
2281                 DELAY(10);
2282         }
2283         if (i == BNX_FIRMWARE_TIMEOUT) {
2284                 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2285                           "timed out, found 0x%08x\n", val);
2286         }
2287
2288         /* BCM57765 A0 needs additional time before accessing. */
2289         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2290                 DELAY(10 * 1000);
2291
2292         /*
2293          * XXX Wait for the value of the PCISTATE register to
2294          * return to its original pre-reset state. This is a
2295          * fairly good indicator of reset completion. If we don't
2296          * wait for the reset to fully complete, trying to read
2297          * from the device's non-PCI registers may yield garbage
2298          * results.
2299          */
2300         for (i = 0; i < BNX_TIMEOUT; i++) {
2301                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2302                         break;
2303                 DELAY(10);
2304         }
2305
2306         /* Fix up byte swapping */
2307         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2308
2309         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2310
2311         /*
2312          * The 5704 in TBI mode apparently needs some special
2313          * adjustment to insure the SERDES drive level is set
2314          * to 1.2V.
2315          */
2316         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2317             (sc->bnx_flags & BNX_FLAG_TBI)) {
2318                 uint32_t serdescfg;
2319
2320                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2321                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2322                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2323         }
2324
2325         CSR_WRITE_4(sc, BGE_MI_MODE,
2326             sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2327         DELAY(80);
2328
2329         /* XXX: Broadcom Linux driver. */
2330         if (!BNX_IS_57765_PLUS(sc)) {
2331                 uint32_t v;
2332
2333                 /* Enable Data FIFO protection. */
2334                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2335                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2336         }
2337
2338         DELAY(10000);
2339
2340         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2341                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2342                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2343         }
2344 }
2345
2346 /*
2347  * Frame reception handling. This is called if there's a frame
2348  * on the receive return list.
2349  *
2350  * Note: we have to be able to handle two possibilities here:
2351  * 1) the frame is from the jumbo recieve ring
2352  * 2) the frame is from the standard receive ring
2353  */
2354
2355 static void
2356 bnx_rxeof(struct bnx_rx_ret_ring *ret, uint16_t rx_prod, int count)
2357 {
2358         struct bnx_softc *sc = ret->bnx_sc;
2359         struct bnx_rx_std_ring *std = ret->bnx_std;
2360         struct ifnet *ifp = &sc->arpcom.ac_if;
2361         int stdcnt = 0, jumbocnt = 0;
2362
2363         while (ret->bnx_rx_saved_considx != rx_prod && count != 0) {
2364                 struct bge_rx_bd        *cur_rx;
2365                 uint32_t                rxidx;
2366                 struct mbuf             *m = NULL;
2367                 uint16_t                vlan_tag = 0;
2368                 int                     have_tag = 0;
2369
2370                 --count;
2371
2372                 cur_rx = &ret->bnx_rx_ret_ring[ret->bnx_rx_saved_considx];
2373
2374                 rxidx = cur_rx->bge_idx;
2375                 BNX_INC(ret->bnx_rx_saved_considx, BNX_RETURN_RING_CNT);
2376
2377                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2378                         have_tag = 1;
2379                         vlan_tag = cur_rx->bge_vlan_tag;
2380                 }
2381
2382                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2383                         BNX_INC(sc->bnx_jumbo, BGE_JUMBO_RX_RING_CNT);
2384                         jumbocnt++;
2385
2386                         if (rxidx != sc->bnx_jumbo) {
2387                                 IFNET_STAT_INC(ifp, ierrors, 1);
2388                                 if_printf(ifp, "sw jumbo index(%d) "
2389                                     "and hw jumbo index(%d) mismatch, drop!\n",
2390                                     sc->bnx_jumbo, rxidx);
2391                                 bnx_setup_rxdesc_jumbo(sc, rxidx);
2392                                 continue;
2393                         }
2394
2395                         m = sc->bnx_cdata.bnx_rx_jumbo_chain[rxidx].bnx_rx_mbuf;
2396                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2397                                 IFNET_STAT_INC(ifp, ierrors, 1);
2398                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2399                                 continue;
2400                         }
2401                         if (bnx_newbuf_jumbo(sc, sc->bnx_jumbo, 0)) {
2402                                 IFNET_STAT_INC(ifp, ierrors, 1);
2403                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2404                                 continue;
2405                         }
2406                 } else {
2407                         BNX_INC(std->bnx_rx_std, BGE_STD_RX_RING_CNT);
2408                         stdcnt++;
2409
2410                         if (rxidx != std->bnx_rx_std) {
2411                                 IFNET_STAT_INC(ifp, ierrors, 1);
2412                                 if_printf(ifp, "sw std index(%d) "
2413                                     "and hw std index(%d) mismatch, drop!\n",
2414                                     std->bnx_rx_std, rxidx);
2415                                 bnx_setup_rxdesc_std(std, rxidx);
2416                                 continue;
2417                         }
2418
2419                         m = std->bnx_rx_std_buf[rxidx].bnx_rx_mbuf;
2420                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2421                                 IFNET_STAT_INC(ifp, ierrors, 1);
2422                                 bnx_setup_rxdesc_std(std, std->bnx_rx_std);
2423                                 continue;
2424                         }
2425                         if (bnx_newbuf_std(ret, std->bnx_rx_std, 0)) {
2426                                 IFNET_STAT_INC(ifp, ierrors, 1);
2427                                 bnx_setup_rxdesc_std(std, std->bnx_rx_std);
2428                                 continue;
2429                         }
2430                 }
2431
2432                 IFNET_STAT_INC(ifp, ipackets, 1);
2433                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2434                 m->m_pkthdr.rcvif = ifp;
2435
2436                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2437                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2438                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2439                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2440                                 if ((cur_rx->bge_error_flag &
2441                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2442                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2443                         }
2444                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2445                                 m->m_pkthdr.csum_data =
2446                                     cur_rx->bge_tcp_udp_csum;
2447                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2448                                     CSUM_PSEUDO_HDR;
2449                         }
2450                 }
2451
2452                 /*
2453                  * If we received a packet with a vlan tag, pass it
2454                  * to vlan_input() instead of ether_input().
2455                  */
2456                 if (have_tag) {
2457                         m->m_flags |= M_VLANTAG;
2458                         m->m_pkthdr.ether_vlantag = vlan_tag;
2459                 }
2460                 ifp->if_input(ifp, m);
2461         }
2462
2463         bnx_writembx(sc, BGE_MBX_RX_CONS0_LO, ret->bnx_rx_saved_considx);
2464         if (stdcnt)
2465                 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, std->bnx_rx_std);
2466         if (jumbocnt)
2467                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
2468 }
2469
2470 static void
2471 bnx_txeof(struct bnx_tx_ring *txr, uint16_t tx_cons)
2472 {
2473         struct ifnet *ifp = &txr->bnx_sc->arpcom.ac_if;
2474
2475         /*
2476          * Go through our tx ring and free mbufs for those
2477          * frames that have been sent.
2478          */
2479         while (txr->bnx_tx_saved_considx != tx_cons) {
2480                 struct bnx_tx_buf *buf;
2481                 uint32_t idx = 0;
2482
2483                 idx = txr->bnx_tx_saved_considx;
2484                 buf = &txr->bnx_tx_buf[idx];
2485                 if (buf->bnx_tx_mbuf != NULL) {
2486                         IFNET_STAT_INC(ifp, opackets, 1);
2487                         bus_dmamap_unload(txr->bnx_tx_mtag,
2488                             buf->bnx_tx_dmamap);
2489                         m_freem(buf->bnx_tx_mbuf);
2490                         buf->bnx_tx_mbuf = NULL;
2491                 }
2492                 txr->bnx_tx_cnt--;
2493                 BNX_INC(txr->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2494         }
2495
2496         if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) >=
2497             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2498                 ifq_clr_oactive(&ifp->if_snd);
2499
2500         if (txr->bnx_tx_cnt == 0)
2501                 ifp->if_timer = 0;
2502
2503         if (!ifq_is_empty(&ifp->if_snd))
2504                 if_devstart(ifp);
2505 }
2506
2507 #ifdef IFPOLL_ENABLE
2508
2509 static void
2510 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2511 {
2512         struct bnx_softc *sc = ifp->if_softc;
2513
2514         ASSERT_SERIALIZED(ifp->if_serializer);
2515
2516         if (info != NULL) {
2517                 int cpuid = sc->bnx_npoll.ifpc_cpuid;
2518
2519                 info->ifpi_rx[cpuid].poll_func = bnx_npoll_compat;
2520                 info->ifpi_rx[cpuid].arg = NULL;
2521                 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
2522
2523                 if (ifp->if_flags & IFF_RUNNING)
2524                         bnx_disable_intr(sc);
2525                 ifq_set_cpuid(&ifp->if_snd, cpuid);
2526         } else {
2527                 if (ifp->if_flags & IFF_RUNNING)
2528                         bnx_enable_intr(sc);
2529                 ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2530         }
2531 }
2532
2533 static void
2534 bnx_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycle)
2535 {
2536         struct bnx_softc *sc = ifp->if_softc;
2537         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2538         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0]; /* XXX */
2539         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2540         uint16_t rx_prod, tx_cons;
2541
2542         ASSERT_SERIALIZED(ifp->if_serializer);
2543
2544         if (sc->bnx_npoll.ifpc_stcount-- == 0) {
2545                 sc->bnx_npoll.ifpc_stcount = sc->bnx_npoll.ifpc_stfrac;
2546                 /*
2547                  * Process link state changes.
2548                  */
2549                 bnx_link_poll(sc);
2550         }
2551
2552         sc->bnx_status_tag = sblk->bge_status_tag;
2553
2554         /*
2555          * Use a load fence to ensure that status_tag is saved
2556          * before rx_prod and tx_cons.
2557          */
2558         cpu_lfence();
2559
2560         rx_prod = *ret->bnx_rx_considx;
2561         tx_cons = *txr->bnx_tx_considx;
2562
2563         if (ret->bnx_rx_saved_considx != rx_prod)
2564                 bnx_rxeof(ret, rx_prod, cycle);
2565
2566         if (txr->bnx_tx_saved_considx != tx_cons)
2567                 bnx_txeof(txr, tx_cons);
2568 }
2569
2570 #endif  /* IFPOLL_ENABLE */
2571
2572 static void
2573 bnx_intr_legacy(void *xsc)
2574 {
2575         struct bnx_softc *sc = xsc;
2576         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2577
2578         if (sc->bnx_status_tag == sblk->bge_status_tag) {
2579                 uint32_t val;
2580
2581                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
2582                 if (val & BGE_PCISTAT_INTR_NOTACT)
2583                         return;
2584         }
2585
2586         /*
2587          * NOTE:
2588          * Interrupt will have to be disabled if tagged status
2589          * is used, else interrupt will always be asserted on
2590          * certain chips (at least on BCM5750 AX/BX).
2591          */
2592         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2593
2594         bnx_intr(sc);
2595 }
2596
2597 static void
2598 bnx_msi(void *xsc)
2599 {
2600         struct bnx_softc *sc = xsc;
2601
2602         /* Disable interrupt first */
2603         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2604         bnx_intr(sc);
2605 }
2606
2607 static void
2608 bnx_msi_oneshot(void *xsc)
2609 {
2610         bnx_intr(xsc);
2611 }
2612
2613 static void
2614 bnx_intr(struct bnx_softc *sc)
2615 {
2616         struct ifnet *ifp = &sc->arpcom.ac_if;
2617         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2618         uint32_t status;
2619
2620         sc->bnx_status_tag = sblk->bge_status_tag;
2621         /*
2622          * Use a load fence to ensure that status_tag is saved
2623          * before rx_prod, tx_cons and status.
2624          */
2625         cpu_lfence();
2626
2627         status = sblk->bge_status;
2628
2629         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2630                 bnx_link_poll(sc);
2631
2632         if (ifp->if_flags & IFF_RUNNING) {
2633                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2634                 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0]; /* XXX */
2635                 uint16_t rx_prod, tx_cons;
2636
2637                 rx_prod = *ret->bnx_rx_considx;
2638                 tx_cons = *txr->bnx_tx_considx;
2639
2640                 if (ret->bnx_rx_saved_considx != rx_prod)
2641                         bnx_rxeof(ret, rx_prod, -1);
2642
2643                 if (txr->bnx_tx_saved_considx != tx_cons)
2644                         bnx_txeof(txr, tx_cons);
2645         }
2646
2647         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
2648 }
2649
2650 static void
2651 bnx_tick(void *xsc)
2652 {
2653         struct bnx_softc *sc = xsc;
2654         struct ifnet *ifp = &sc->arpcom.ac_if;
2655
2656         lwkt_serialize_enter(ifp->if_serializer);
2657
2658         KKASSERT(mycpuid == sc->bnx_stat_cpuid);
2659
2660         bnx_stats_update_regs(sc);
2661
2662         if (sc->bnx_flags & BNX_FLAG_TBI) {
2663                 /*
2664                  * Since in TBI mode auto-polling can't be used we should poll
2665                  * link status manually. Here we register pending link event
2666                  * and trigger interrupt.
2667                  */
2668                 sc->bnx_link_evt++;
2669                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2670         } else if (!sc->bnx_link) {
2671                 mii_tick(device_get_softc(sc->bnx_miibus));
2672         }
2673
2674         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
2675
2676         lwkt_serialize_exit(ifp->if_serializer);
2677 }
2678
2679 static void
2680 bnx_stats_update_regs(struct bnx_softc *sc)
2681 {
2682         struct ifnet *ifp = &sc->arpcom.ac_if;
2683         struct bge_mac_stats_regs stats;
2684         uint32_t *s;
2685         int i;
2686
2687         s = (uint32_t *)&stats;
2688         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2689                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2690                 s++;
2691         }
2692
2693         IFNET_STAT_SET(ifp, collisions,
2694            (stats.dot3StatsSingleCollisionFrames +
2695            stats.dot3StatsMultipleCollisionFrames +
2696            stats.dot3StatsExcessiveCollisions +
2697            stats.dot3StatsLateCollisions));
2698 }
2699
2700 /*
2701  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2702  * pointers to descriptors.
2703  */
2704 static int
2705 bnx_encap(struct bnx_tx_ring *txr, struct mbuf **m_head0, uint32_t *txidx,
2706     int *segs_used)
2707 {
2708         struct bge_tx_bd *d = NULL;
2709         uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
2710         bus_dma_segment_t segs[BNX_NSEG_NEW];
2711         bus_dmamap_t map;
2712         int error, maxsegs, nsegs, idx, i;
2713         struct mbuf *m_head = *m_head0, *m_new;
2714
2715         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2716 #ifdef BNX_TSO_DEBUG
2717                 int tso_nsegs;
2718 #endif
2719
2720                 error = bnx_setup_tso(txr, m_head0, &mss, &csum_flags);
2721                 if (error)
2722                         return error;
2723                 m_head = *m_head0;
2724
2725 #ifdef BNX_TSO_DEBUG
2726                 tso_nsegs = (m_head->m_pkthdr.len /
2727                     m_head->m_pkthdr.tso_segsz) - 1;
2728                 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
2729                         tso_nsegs = BNX_TSO_NSTATS - 1;
2730                 else if (tso_nsegs < 0)
2731                         tso_nsegs = 0;
2732                 txr->bnx_sc->bnx_tsosegs[tso_nsegs]++;
2733 #endif
2734         } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
2735                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2736                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2737                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2738                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2739                 if (m_head->m_flags & M_LASTFRAG)
2740                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2741                 else if (m_head->m_flags & M_FRAG)
2742                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2743         }
2744         if (m_head->m_flags & M_VLANTAG) {
2745                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
2746                 vlan_tag = m_head->m_pkthdr.ether_vlantag;
2747         }
2748
2749         idx = *txidx;
2750         map = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
2751
2752         maxsegs = (BGE_TX_RING_CNT - txr->bnx_tx_cnt) - BNX_NSEG_RSVD;
2753         KASSERT(maxsegs >= BNX_NSEG_SPARE,
2754                 ("not enough segments %d", maxsegs));
2755
2756         if (maxsegs > BNX_NSEG_NEW)
2757                 maxsegs = BNX_NSEG_NEW;
2758
2759         /*
2760          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
2761          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
2762          * but when such padded frames employ the bge IP/TCP checksum
2763          * offload, the hardware checksum assist gives incorrect results
2764          * (possibly from incorporating its own padding into the UDP/TCP
2765          * checksum; who knows).  If we pad such runts with zeros, the
2766          * onboard checksum comes out correct.
2767          */
2768         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2769             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
2770                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
2771                 if (error)
2772                         goto back;
2773         }
2774
2775         if ((txr->bnx_tx_flags & BNX_TX_FLAG_SHORTDMA) &&
2776             m_head->m_next != NULL) {
2777                 m_new = bnx_defrag_shortdma(m_head);
2778                 if (m_new == NULL) {
2779                         error = ENOBUFS;
2780                         goto back;
2781                 }
2782                 *m_head0 = m_head = m_new;
2783         }
2784         if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
2785             (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG) &&
2786             m_head->m_next != NULL) {
2787                 /*
2788                  * Forcefully defragment mbuf chain to overcome hardware
2789                  * limitation which only support a single outstanding
2790                  * DMA read operation.  If it fails, keep moving on using
2791                  * the original mbuf chain.
2792                  */
2793                 m_new = m_defrag(m_head, MB_DONTWAIT);
2794                 if (m_new != NULL)
2795                         *m_head0 = m_head = m_new;
2796         }
2797
2798         error = bus_dmamap_load_mbuf_defrag(txr->bnx_tx_mtag, map,
2799             m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2800         if (error)
2801                 goto back;
2802         *segs_used += nsegs;
2803
2804         m_head = *m_head0;
2805         bus_dmamap_sync(txr->bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2806
2807         for (i = 0; ; i++) {
2808                 d = &txr->bnx_tx_ring[idx];
2809
2810                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2811                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2812                 d->bge_len = segs[i].ds_len;
2813                 d->bge_flags = csum_flags;
2814                 d->bge_vlan_tag = vlan_tag;
2815                 d->bge_mss = mss;
2816
2817                 if (i == nsegs - 1)
2818                         break;
2819                 BNX_INC(idx, BGE_TX_RING_CNT);
2820         }
2821         /* Mark the last segment as end of packet... */
2822         d->bge_flags |= BGE_TXBDFLAG_END;
2823
2824         /*
2825          * Insure that the map for this transmission is placed at
2826          * the array index of the last descriptor in this chain.
2827          */
2828         txr->bnx_tx_buf[*txidx].bnx_tx_dmamap = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
2829         txr->bnx_tx_buf[idx].bnx_tx_dmamap = map;
2830         txr->bnx_tx_buf[idx].bnx_tx_mbuf = m_head;
2831         txr->bnx_tx_cnt += nsegs;
2832
2833         BNX_INC(idx, BGE_TX_RING_CNT);
2834         *txidx = idx;
2835 back:
2836         if (error) {
2837                 m_freem(*m_head0);
2838                 *m_head0 = NULL;
2839         }
2840         return error;
2841 }
2842
2843 /*
2844  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2845  * to the mbuf data regions directly in the transmit descriptors.
2846  */
2847 static void
2848 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
2849 {
2850         struct bnx_softc *sc = ifp->if_softc;
2851         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2852         struct mbuf *m_head = NULL;
2853         uint32_t prodidx;
2854         int nsegs = 0;
2855
2856         ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
2857
2858         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
2859                 return;
2860
2861         prodidx = txr->bnx_tx_prodidx;
2862
2863         while (txr->bnx_tx_buf[prodidx].bnx_tx_mbuf == NULL) {
2864                 /*
2865                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2866                  * descriptors of the end of the ring.  Also make
2867                  * sure there are BGE_NSEG_SPARE descriptors for
2868                  * jumbo buffers' or TSO segments' defragmentation.
2869                  */
2870                 if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) <
2871                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
2872                         ifq_set_oactive(&ifp->if_snd);
2873                         break;
2874                 }
2875
2876                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2877                 if (m_head == NULL)
2878                         break;
2879
2880                 /*
2881                  * Pack the data into the transmit ring. If we
2882                  * don't have room, set the OACTIVE flag and wait
2883                  * for the NIC to drain the ring.
2884                  */
2885                 if (bnx_encap(txr, &m_head, &prodidx, &nsegs)) {
2886                         ifq_set_oactive(&ifp->if_snd);
2887                         IFNET_STAT_INC(ifp, oerrors, 1);
2888                         break;
2889                 }
2890
2891                 if (nsegs >= txr->bnx_tx_wreg) {
2892                         /* Transmit */
2893                         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
2894                         nsegs = 0;
2895                 }
2896
2897                 ETHER_BPF_MTAP(ifp, m_head);
2898
2899                 /*
2900                  * Set a timeout in case the chip goes out to lunch.
2901                  */
2902                 ifp->if_timer = 5;
2903         }
2904
2905         if (nsegs > 0) {
2906                 /* Transmit */
2907                 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
2908         }
2909         txr->bnx_tx_prodidx = prodidx;
2910 }
2911
2912 static void
2913 bnx_init(void *xsc)
2914 {
2915         struct bnx_softc *sc = xsc;
2916         struct ifnet *ifp = &sc->arpcom.ac_if;
2917         uint16_t *m;
2918         uint32_t mode;
2919         int i;
2920
2921         ASSERT_SERIALIZED(ifp->if_serializer);
2922
2923         /* Cancel pending I/O and flush buffers. */
2924         bnx_stop(sc);
2925         bnx_reset(sc);
2926         bnx_chipinit(sc);
2927
2928         /*
2929          * Init the various state machines, ring
2930          * control blocks and firmware.
2931          */
2932         if (bnx_blockinit(sc)) {
2933                 if_printf(ifp, "initialization failure\n");
2934                 bnx_stop(sc);
2935                 return;
2936         }
2937
2938         /* Specify MTU. */
2939         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2940             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2941
2942         /* Load our MAC address. */
2943         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2944         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2945         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2946
2947         /* Enable or disable promiscuous mode as needed. */
2948         bnx_setpromisc(sc);
2949
2950         /* Program multicast filter. */
2951         bnx_setmulti(sc);
2952
2953         /* Init RX ring. */
2954         if (bnx_init_rx_ring_std(&sc->bnx_rx_std_ring)) {
2955                 if_printf(ifp, "RX ring initialization failed\n");
2956                 bnx_stop(sc);
2957                 return;
2958         }
2959
2960         /* Init jumbo RX ring. */
2961         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
2962                 if (bnx_init_rx_ring_jumbo(sc)) {
2963                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
2964                         bnx_stop(sc);
2965                         return;
2966                 }
2967         }
2968
2969         /* Init our RX return ring index */
2970         for (i = 0; i < sc->bnx_rx_retcnt; ++i)
2971                 sc->bnx_rx_ret_ring[i].bnx_rx_saved_considx = 0;
2972
2973         /* Init TX ring. */
2974         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
2975                 bnx_init_tx_ring(&sc->bnx_tx_ring[i]);
2976
2977         /* Enable TX MAC state machine lockup fix. */
2978         mode = CSR_READ_4(sc, BGE_TX_MODE);
2979         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
2980         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
2981             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
2982                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
2983                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
2984                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
2985         }
2986         /* Turn on transmitter */
2987         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
2988
2989         /* Turn on receiver */
2990         BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2991
2992         /*
2993          * Set the number of good frames to receive after RX MBUF
2994          * Low Watermark has been reached.  After the RX MAC receives
2995          * this number of frames, it will drop subsequent incoming
2996          * frames until the MBUF High Watermark is reached.
2997          */
2998         if (BNX_IS_57765_FAMILY(sc))
2999                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3000         else
3001                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3002
3003         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
3004                 if (bootverbose) {
3005                         if_printf(ifp, "MSI_MODE: %#x\n",
3006                             CSR_READ_4(sc, BGE_MSI_MODE));
3007                 }
3008         }
3009
3010         /* Tell firmware we're alive. */
3011         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3012
3013         /* Enable host interrupts if polling(4) is not enabled. */
3014         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3015 #ifdef IFPOLL_ENABLE
3016         if (ifp->if_flags & IFF_NPOLLING)
3017                 bnx_disable_intr(sc);
3018         else
3019 #endif
3020         bnx_enable_intr(sc);
3021
3022         bnx_ifmedia_upd(ifp);
3023
3024         ifp->if_flags |= IFF_RUNNING;
3025         ifq_clr_oactive(&ifp->if_snd);
3026
3027         callout_reset_bycpu(&sc->bnx_stat_timer, hz, bnx_tick, sc,
3028             sc->bnx_stat_cpuid);
3029 }
3030
3031 /*
3032  * Set media options.
3033  */
3034 static int
3035 bnx_ifmedia_upd(struct ifnet *ifp)
3036 {
3037         struct bnx_softc *sc = ifp->if_softc;
3038
3039         /* If this is a 1000baseX NIC, enable the TBI port. */
3040         if (sc->bnx_flags & BNX_FLAG_TBI) {
3041                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3042
3043                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3044                         return(EINVAL);
3045
3046                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3047                 case IFM_AUTO:
3048                         break;
3049
3050                 case IFM_1000_SX:
3051                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3052                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3053                                     BGE_MACMODE_HALF_DUPLEX);
3054                         } else {
3055                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3056                                     BGE_MACMODE_HALF_DUPLEX);
3057                         }
3058                         break;
3059                 default:
3060                         return(EINVAL);
3061                 }
3062         } else {
3063                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3064
3065                 sc->bnx_link_evt++;
3066                 sc->bnx_link = 0;
3067                 if (mii->mii_instance) {
3068                         struct mii_softc *miisc;
3069
3070                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3071                                 mii_phy_reset(miisc);
3072                 }
3073                 mii_mediachg(mii);
3074
3075                 /*
3076                  * Force an interrupt so that we will call bnx_link_upd
3077                  * if needed and clear any pending link state attention.
3078                  * Without this we are not getting any further interrupts
3079                  * for link state changes and thus will not UP the link and
3080                  * not be able to send in bnx_start.  The only way to get
3081                  * things working was to receive a packet and get an RX
3082                  * intr.
3083                  *
3084                  * bnx_tick should help for fiber cards and we might not
3085                  * need to do this here if BNX_FLAG_TBI is set but as
3086                  * we poll for fiber anyway it should not harm.
3087                  */
3088                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3089         }
3090         return(0);
3091 }
3092
3093 /*
3094  * Report current media status.
3095  */
3096 static void
3097 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3098 {
3099         struct bnx_softc *sc = ifp->if_softc;
3100
3101         if (sc->bnx_flags & BNX_FLAG_TBI) {
3102                 ifmr->ifm_status = IFM_AVALID;
3103                 ifmr->ifm_active = IFM_ETHER;
3104                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3105                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3106                         ifmr->ifm_status |= IFM_ACTIVE;
3107                 } else {
3108                         ifmr->ifm_active |= IFM_NONE;
3109                         return;
3110                 }
3111
3112                 ifmr->ifm_active |= IFM_1000_SX;
3113                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3114                         ifmr->ifm_active |= IFM_HDX;
3115                 else
3116                         ifmr->ifm_active |= IFM_FDX;
3117         } else {
3118                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3119
3120                 mii_pollstat(mii);
3121                 ifmr->ifm_active = mii->mii_media_active;
3122                 ifmr->ifm_status = mii->mii_media_status;
3123         }
3124 }
3125
3126 static int
3127 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3128 {
3129         struct bnx_softc *sc = ifp->if_softc;
3130         struct ifreq *ifr = (struct ifreq *)data;
3131         int mask, error = 0;
3132
3133         ASSERT_SERIALIZED(ifp->if_serializer);
3134
3135         switch (command) {
3136         case SIOCSIFMTU:
3137                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3138                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3139                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3140                         error = EINVAL;
3141                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3142                         ifp->if_mtu = ifr->ifr_mtu;
3143                         if (ifp->if_flags & IFF_RUNNING)
3144                                 bnx_init(sc);
3145                 }
3146                 break;
3147         case SIOCSIFFLAGS:
3148                 if (ifp->if_flags & IFF_UP) {
3149                         if (ifp->if_flags & IFF_RUNNING) {
3150                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3151
3152                                 /*
3153                                  * If only the state of the PROMISC flag
3154                                  * changed, then just use the 'set promisc
3155                                  * mode' command instead of reinitializing
3156                                  * the entire NIC. Doing a full re-init
3157                                  * means reloading the firmware and waiting
3158                                  * for it to start up, which may take a
3159                                  * second or two.  Similarly for ALLMULTI.
3160                                  */
3161                                 if (mask & IFF_PROMISC)
3162                                         bnx_setpromisc(sc);
3163                                 if (mask & IFF_ALLMULTI)
3164                                         bnx_setmulti(sc);
3165                         } else {
3166                                 bnx_init(sc);
3167                         }
3168                 } else if (ifp->if_flags & IFF_RUNNING) {
3169                         bnx_stop(sc);
3170                 }
3171                 sc->bnx_if_flags = ifp->if_flags;
3172                 break;
3173         case SIOCADDMULTI:
3174         case SIOCDELMULTI:
3175                 if (ifp->if_flags & IFF_RUNNING)
3176                         bnx_setmulti(sc);
3177                 break;
3178         case SIOCSIFMEDIA:
3179         case SIOCGIFMEDIA:
3180                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3181                         error = ifmedia_ioctl(ifp, ifr,
3182                             &sc->bnx_ifmedia, command);
3183                 } else {
3184                         struct mii_data *mii;
3185
3186                         mii = device_get_softc(sc->bnx_miibus);
3187                         error = ifmedia_ioctl(ifp, ifr,
3188                                               &mii->mii_media, command);
3189                 }
3190                 break;
3191         case SIOCSIFCAP:
3192                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3193                 if (mask & IFCAP_HWCSUM) {
3194                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3195                         if (ifp->if_capenable & IFCAP_TXCSUM)
3196                                 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3197                         else
3198                                 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3199                 }
3200                 if (mask & IFCAP_TSO) {
3201                         ifp->if_capenable ^= (mask & IFCAP_TSO);
3202                         if (ifp->if_capenable & IFCAP_TSO)
3203                                 ifp->if_hwassist |= CSUM_TSO;
3204                         else
3205                                 ifp->if_hwassist &= ~CSUM_TSO;
3206                 }
3207                 break;
3208         default:
3209                 error = ether_ioctl(ifp, command, data);
3210                 break;
3211         }
3212         return error;
3213 }
3214
3215 static void
3216 bnx_watchdog(struct ifnet *ifp)
3217 {
3218         struct bnx_softc *sc = ifp->if_softc;
3219
3220         if_printf(ifp, "watchdog timeout -- resetting\n");
3221
3222         bnx_init(sc);
3223
3224         IFNET_STAT_INC(ifp, oerrors, 1);
3225
3226         if (!ifq_is_empty(&ifp->if_snd))
3227                 if_devstart(ifp);
3228 }
3229
3230 /*
3231  * Stop the adapter and free any mbufs allocated to the
3232  * RX and TX lists.
3233  */
3234 static void
3235 bnx_stop(struct bnx_softc *sc)
3236 {
3237         struct ifnet *ifp = &sc->arpcom.ac_if;
3238         int i;
3239
3240         ASSERT_SERIALIZED(ifp->if_serializer);
3241
3242         callout_stop(&sc->bnx_stat_timer);
3243
3244         /*
3245          * Disable all of the receiver blocks
3246          */
3247         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3248         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3249         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3250         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3251         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3252         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3253
3254         /*
3255          * Disable all of the transmit blocks
3256          */
3257         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3258         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3259         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3260         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3261         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3262         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3263
3264         /*
3265          * Shut down all of the memory managers and related
3266          * state machines.
3267          */
3268         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3269         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3270         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3271         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3272
3273         /* Disable host interrupts. */
3274         bnx_disable_intr(sc);
3275
3276         /*
3277          * Tell firmware we're shutting down.
3278          */
3279         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3280
3281         /* Free the RX lists. */
3282         bnx_free_rx_ring_std(&sc->bnx_rx_std_ring);
3283
3284         /* Free jumbo RX list. */
3285         if (BNX_IS_JUMBO_CAPABLE(sc))
3286                 bnx_free_rx_ring_jumbo(sc);
3287
3288         /* Free TX buffers. */
3289         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3290                 bnx_free_tx_ring(&sc->bnx_tx_ring[i]);
3291
3292         sc->bnx_status_tag = 0;
3293         sc->bnx_link = 0;
3294         sc->bnx_coal_chg = 0;
3295
3296         ifp->if_flags &= ~IFF_RUNNING;
3297         ifq_clr_oactive(&ifp->if_snd);
3298         ifp->if_timer = 0;
3299 }
3300
3301 /*
3302  * Stop all chip I/O so that the kernel's probe routines don't
3303  * get confused by errant DMAs when rebooting.
3304  */
3305 static void
3306 bnx_shutdown(device_t dev)
3307 {
3308         struct bnx_softc *sc = device_get_softc(dev);
3309         struct ifnet *ifp = &sc->arpcom.ac_if;
3310
3311         lwkt_serialize_enter(ifp->if_serializer);
3312         bnx_stop(sc);
3313         bnx_reset(sc);
3314         lwkt_serialize_exit(ifp->if_serializer);
3315 }
3316
3317 static int
3318 bnx_suspend(device_t dev)
3319 {
3320         struct bnx_softc *sc = device_get_softc(dev);
3321         struct ifnet *ifp = &sc->arpcom.ac_if;
3322
3323         lwkt_serialize_enter(ifp->if_serializer);
3324         bnx_stop(sc);
3325         lwkt_serialize_exit(ifp->if_serializer);
3326
3327         return 0;
3328 }
3329
3330 static int
3331 bnx_resume(device_t dev)
3332 {
3333         struct bnx_softc *sc = device_get_softc(dev);
3334         struct ifnet *ifp = &sc->arpcom.ac_if;
3335
3336         lwkt_serialize_enter(ifp->if_serializer);
3337
3338         if (ifp->if_flags & IFF_UP) {
3339                 bnx_init(sc);
3340
3341                 if (!ifq_is_empty(&ifp->if_snd))
3342                         if_devstart(ifp);
3343         }
3344
3345         lwkt_serialize_exit(ifp->if_serializer);
3346
3347         return 0;
3348 }
3349
3350 static void
3351 bnx_setpromisc(struct bnx_softc *sc)
3352 {
3353         struct ifnet *ifp = &sc->arpcom.ac_if;
3354
3355         if (ifp->if_flags & IFF_PROMISC)
3356                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3357         else
3358                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3359 }
3360
3361 static void
3362 bnx_dma_free(struct bnx_softc *sc)
3363 {
3364         struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
3365         int i;
3366
3367         /* Destroy RX return rings */
3368         if (sc->bnx_rx_ret_ring != NULL) {
3369                 for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3370                         bnx_destroy_rx_ret_ring(&sc->bnx_rx_ret_ring[i]);
3371                 kfree(sc->bnx_rx_ret_ring, M_DEVBUF);
3372         }
3373
3374         /* Destroy RX mbuf DMA stuffs. */
3375         if (std->bnx_rx_mtag != NULL) {
3376                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3377                         KKASSERT(std->bnx_rx_std_buf[i].bnx_rx_mbuf == NULL);
3378                         bus_dmamap_destroy(std->bnx_rx_mtag,
3379                             std->bnx_rx_std_buf[i].bnx_rx_dmamap);
3380                 }
3381                 bus_dma_tag_destroy(std->bnx_rx_mtag);
3382         }
3383
3384         /* Destroy standard RX ring */
3385         bnx_dma_block_free(std->bnx_rx_std_ring_tag,
3386             std->bnx_rx_std_ring_map, std->bnx_rx_std_ring);
3387
3388         /* Destroy TX rings */
3389         if (sc->bnx_tx_ring != NULL) {
3390                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3391                         bnx_destroy_tx_ring(&sc->bnx_tx_ring[i]);
3392                 kfree(sc->bnx_tx_ring, M_DEVBUF);
3393         }
3394
3395         if (BNX_IS_JUMBO_CAPABLE(sc))
3396                 bnx_free_jumbo_mem(sc);
3397
3398         /* Destroy status block */
3399         bnx_dma_block_free(sc->bnx_cdata.bnx_status_tag,
3400             sc->bnx_cdata.bnx_status_map,
3401             sc->bnx_ldata.bnx_status_block);
3402
3403         /* Destroy the parent tag */
3404         if (sc->bnx_cdata.bnx_parent_tag != NULL)
3405                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3406 }
3407
3408 static int
3409 bnx_dma_alloc(device_t dev)
3410 {
3411         struct bnx_softc *sc = device_get_softc(dev);
3412         struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
3413         int i, error, mbx;
3414
3415         /*
3416          * Allocate the parent bus DMA tag appropriate for PCI.
3417          *
3418          * All of the NetExtreme/NetLink controllers have 4GB boundary
3419          * DMA bug.
3420          * Whenever an address crosses a multiple of the 4GB boundary
3421          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3422          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3423          * state machine will lockup and cause the device to hang.
3424          */
3425         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3426             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3427             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3428             0, &sc->bnx_cdata.bnx_parent_tag);
3429         if (error) {
3430                 device_printf(dev, "could not create parent DMA tag\n");
3431                 return error;
3432         }
3433
3434         /*
3435          * Create DMA stuffs for status block.
3436          */
3437         error = bnx_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3438             &sc->bnx_cdata.bnx_status_tag,
3439             &sc->bnx_cdata.bnx_status_map,
3440             (void *)&sc->bnx_ldata.bnx_status_block,
3441             &sc->bnx_ldata.bnx_status_block_paddr);
3442         if (error) {
3443                 device_printf(dev, "could not create status block\n");
3444                 return error;
3445         }
3446
3447         /*
3448          * Create DMA tag and maps for RX mbufs.
3449          */
3450         std->bnx_sc = sc;
3451         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3452             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3453             NULL, NULL, MCLBYTES, 1, MCLBYTES,
3454             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, &std->bnx_rx_mtag);
3455         if (error) {
3456                 device_printf(dev, "could not create RX mbuf DMA tag\n");
3457                 return error;
3458         }
3459
3460         for (i = 0; i < BGE_STD_RX_RING_CNT; ++i) {
3461                 error = bus_dmamap_create(std->bnx_rx_mtag, BUS_DMA_WAITOK,
3462                     &std->bnx_rx_std_buf[i].bnx_rx_dmamap);
3463                 if (error) {
3464                         int j;
3465
3466                         for (j = 0; j < i; ++j) {
3467                                 bus_dmamap_destroy(std->bnx_rx_mtag,
3468                                     std->bnx_rx_std_buf[j].bnx_rx_dmamap);
3469                         }
3470                         bus_dma_tag_destroy(std->bnx_rx_mtag);
3471                         std->bnx_rx_mtag = NULL;
3472
3473                         device_printf(dev,
3474                             "could not create %dth RX mbuf DMA map\n", i);
3475                         return error;
3476                 }
3477         }
3478
3479         /*
3480          * Create DMA stuffs for standard RX ring.
3481          */
3482         error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3483             &std->bnx_rx_std_ring_tag,
3484             &std->bnx_rx_std_ring_map,
3485             (void *)&std->bnx_rx_std_ring,
3486             &std->bnx_rx_std_ring_paddr);
3487         if (error) {
3488                 device_printf(dev, "could not create std RX ring\n");
3489                 return error;
3490         }
3491
3492         /*
3493          * Create RX return rings
3494          */
3495         sc->bnx_rx_ret_ring = kmalloc_cachealign(
3496             sizeof(struct bnx_rx_ret_ring) * sc->bnx_rx_retcnt, M_DEVBUF,
3497             M_WAITOK | M_ZERO);
3498         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
3499                 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
3500
3501                 ret->bnx_sc = sc;
3502                 ret->bnx_std = std;
3503
3504                 /* XXX */
3505                 ret->bnx_rx_considx =
3506                 &sc->bnx_ldata.bnx_status_block->bge_idx[0].bge_rx_prod_idx;
3507
3508                 error = bnx_create_rx_ret_ring(ret);
3509                 if (error) {
3510                         device_printf(dev,
3511                             "could not create %dth RX ret ring\n", i);
3512                         return error;
3513                 }
3514         }
3515
3516         /*
3517          * Create TX rings
3518          */
3519         mbx = BGE_MBX_TX_HOST_PROD0_LO;
3520         sc->bnx_tx_ring = kmalloc_cachealign(
3521             sizeof(struct bnx_tx_ring) * sc->bnx_tx_ringcnt, M_DEVBUF,
3522             M_WAITOK | M_ZERO);
3523         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3524                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3525
3526                 txr->bnx_sc = sc;
3527                 txr->bnx_tx_mbx = mbx;
3528
3529                 if (mbx & 0x4)
3530                         mbx -= 0x4;
3531                 else
3532                         mbx += 0xc;
3533
3534                 /* XXX */
3535                 txr->bnx_tx_considx =
3536                 &sc->bnx_ldata.bnx_status_block->bge_idx[0].bge_tx_cons_idx;
3537
3538                 error = bnx_create_tx_ring(txr);
3539                 if (error) {
3540                         device_printf(dev,
3541                             "could not create %dth TX ring\n", i);
3542                         return error;
3543                 }
3544         }
3545
3546         /*
3547          * Create jumbo buffer pool.
3548          */
3549         if (BNX_IS_JUMBO_CAPABLE(sc)) {
3550                 error = bnx_alloc_jumbo_mem(sc);
3551                 if (error) {
3552                         device_printf(dev,
3553                             "could not create jumbo buffer pool\n");
3554                         return error;
3555                 }
3556         }
3557
3558         return 0;
3559 }
3560
3561 static int
3562 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3563                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3564 {
3565         bus_dmamem_t dmem;
3566         int error;
3567
3568         error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
3569                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3570                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3571         if (error)
3572                 return error;
3573
3574         *tag = dmem.dmem_tag;
3575         *map = dmem.dmem_map;
3576         *addr = dmem.dmem_addr;
3577         *paddr = dmem.dmem_busaddr;
3578
3579         return 0;
3580 }
3581
3582 static void
3583 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3584 {
3585         if (tag != NULL) {
3586                 bus_dmamap_unload(tag, map);
3587                 bus_dmamem_free(tag, addr, map);
3588                 bus_dma_tag_destroy(tag);
3589         }
3590 }
3591
3592 static void
3593 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
3594 {
3595         struct ifnet *ifp = &sc->arpcom.ac_if;
3596
3597 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3598
3599         /*
3600          * Sometimes PCS encoding errors are detected in
3601          * TBI mode (on fiber NICs), and for some reason
3602          * the chip will signal them as link changes.
3603          * If we get a link change event, but the 'PCS
3604          * encoding error' bit in the MAC status register
3605          * is set, don't bother doing a link check.
3606          * This avoids spurious "gigabit link up" messages
3607          * that sometimes appear on fiber NICs during
3608          * periods of heavy traffic.
3609          */
3610         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3611                 if (!sc->bnx_link) {
3612                         sc->bnx_link++;
3613                         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
3614                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3615                                     BGE_MACMODE_TBI_SEND_CFGS);
3616                         }
3617                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3618
3619                         if (bootverbose)
3620                                 if_printf(ifp, "link UP\n");
3621
3622                         ifp->if_link_state = LINK_STATE_UP;
3623                         if_link_state_change(ifp);
3624                 }
3625         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3626                 if (sc->bnx_link) {
3627                         sc->bnx_link = 0;
3628
3629                         if (bootverbose)
3630                                 if_printf(ifp, "link DOWN\n");
3631
3632                         ifp->if_link_state = LINK_STATE_DOWN;
3633                         if_link_state_change(ifp);
3634                 }
3635         }
3636
3637 #undef PCS_ENCODE_ERR
3638
3639         /* Clear the attention. */
3640         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3641             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3642             BGE_MACSTAT_LINK_CHANGED);
3643 }
3644
3645 static void
3646 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3647 {
3648         struct ifnet *ifp = &sc->arpcom.ac_if;
3649         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3650
3651         mii_pollstat(mii);
3652         bnx_miibus_statchg(sc->bnx_dev);
3653
3654         if (bootverbose) {
3655                 if (sc->bnx_link)
3656                         if_printf(ifp, "link UP\n");
3657                 else
3658                         if_printf(ifp, "link DOWN\n");
3659         }
3660
3661         /* Clear the attention. */
3662         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3663             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3664             BGE_MACSTAT_LINK_CHANGED);
3665 }
3666
3667 static void
3668 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3669 {
3670         struct ifnet *ifp = &sc->arpcom.ac_if;
3671         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3672
3673         mii_pollstat(mii);
3674
3675         if (!sc->bnx_link &&
3676             (mii->mii_media_status & IFM_ACTIVE) &&
3677             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3678                 sc->bnx_link++;
3679                 if (bootverbose)
3680                         if_printf(ifp, "link UP\n");
3681         } else if (sc->bnx_link &&
3682             (!(mii->mii_media_status & IFM_ACTIVE) ||
3683             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3684                 sc->bnx_link = 0;
3685                 if (bootverbose)
3686                         if_printf(ifp, "link DOWN\n");
3687         }
3688
3689         /* Clear the attention. */
3690         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3691             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3692             BGE_MACSTAT_LINK_CHANGED);
3693 }
3694
3695 static int
3696 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3697 {
3698         struct bnx_softc *sc = arg1;
3699
3700         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3701             &sc->bnx_rx_coal_ticks,
3702             BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
3703             BNX_RX_COAL_TICKS_CHG);
3704 }
3705
3706 static int
3707 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3708 {
3709         struct bnx_softc *sc = arg1;
3710
3711         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3712             &sc->bnx_tx_coal_ticks,
3713             BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
3714             BNX_TX_COAL_TICKS_CHG);
3715 }
3716
3717 static int
3718 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
3719 {
3720         struct bnx_softc *sc = arg1;
3721
3722         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3723             &sc->bnx_rx_coal_bds,
3724             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3725             BNX_RX_COAL_BDS_CHG);
3726 }
3727
3728 static int
3729 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
3730 {
3731         struct bnx_softc *sc = arg1;
3732
3733         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3734             &sc->bnx_tx_coal_bds,
3735             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3736             BNX_TX_COAL_BDS_CHG);
3737 }
3738
3739 static int
3740 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3741 {
3742         struct bnx_softc *sc = arg1;
3743
3744         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3745             &sc->bnx_rx_coal_bds_int,
3746             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3747             BNX_RX_COAL_BDS_INT_CHG);
3748 }
3749
3750 static int
3751 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3752 {
3753         struct bnx_softc *sc = arg1;
3754
3755         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3756             &sc->bnx_tx_coal_bds_int,
3757             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3758             BNX_TX_COAL_BDS_INT_CHG);
3759 }
3760
3761 static int
3762 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3763     int coal_min, int coal_max, uint32_t coal_chg_mask)
3764 {
3765         struct bnx_softc *sc = arg1;
3766         struct ifnet *ifp = &sc->arpcom.ac_if;
3767         int error = 0, v;
3768
3769         lwkt_serialize_enter(ifp->if_serializer);
3770
3771         v = *coal;
3772         error = sysctl_handle_int(oidp, &v, 0, req);
3773         if (!error && req->newptr != NULL) {
3774                 if (v < coal_min || v > coal_max) {
3775                         error = EINVAL;
3776                 } else {
3777                         *coal = v;
3778                         sc->bnx_coal_chg |= coal_chg_mask;
3779
3780                         /* Commit changes */
3781                         bnx_coal_change(sc);
3782                 }
3783         }
3784
3785         lwkt_serialize_exit(ifp->if_serializer);
3786         return error;
3787 }
3788
3789 static void
3790 bnx_coal_change(struct bnx_softc *sc)
3791 {
3792         struct ifnet *ifp = &sc->arpcom.ac_if;
3793
3794         ASSERT_SERIALIZED(ifp->if_serializer);
3795
3796         if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
3797                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3798                             sc->bnx_rx_coal_ticks);
3799                 DELAY(10);
3800                 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3801
3802                 if (bootverbose) {
3803                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3804                                   sc->bnx_rx_coal_ticks);
3805                 }
3806         }
3807
3808         if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
3809                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3810                             sc->bnx_tx_coal_ticks);
3811                 DELAY(10);
3812                 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3813
3814                 if (bootverbose) {
3815                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3816                                   sc->bnx_tx_coal_ticks);
3817                 }
3818         }
3819
3820         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
3821                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3822                             sc->bnx_rx_coal_bds);
3823                 DELAY(10);
3824                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3825
3826                 if (bootverbose) {
3827                         if_printf(ifp, "rx_coal_bds -> %u\n",
3828                                   sc->bnx_rx_coal_bds);
3829                 }
3830         }
3831
3832         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
3833                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3834                             sc->bnx_tx_coal_bds);
3835                 DELAY(10);
3836                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3837
3838                 if (bootverbose) {
3839                         if_printf(ifp, "tx_coal_bds -> %u\n",
3840                                   sc->bnx_tx_coal_bds);
3841                 }
3842         }
3843
3844         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
3845                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
3846                     sc->bnx_rx_coal_bds_int);
3847                 DELAY(10);
3848                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
3849
3850                 if (bootverbose) {
3851                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
3852                             sc->bnx_rx_coal_bds_int);
3853                 }
3854         }
3855
3856         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
3857                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
3858                     sc->bnx_tx_coal_bds_int);
3859                 DELAY(10);
3860                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
3861
3862                 if (bootverbose) {
3863                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
3864                             sc->bnx_tx_coal_bds_int);
3865                 }
3866         }
3867
3868         sc->bnx_coal_chg = 0;
3869 }
3870
3871 static void
3872 bnx_intr_check(void *xsc)
3873 {
3874         struct bnx_softc *sc = xsc;
3875         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
3876         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0]; /* XXX */
3877         struct ifnet *ifp = &sc->arpcom.ac_if;
3878
3879         lwkt_serialize_enter(ifp->if_serializer);
3880
3881         KKASSERT(mycpuid == sc->bnx_intr_cpuid);
3882
3883         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
3884                 lwkt_serialize_exit(ifp->if_serializer);
3885                 return;
3886         }
3887
3888         if (*ret->bnx_rx_considx != ret->bnx_rx_saved_considx ||
3889             *txr->bnx_tx_considx != txr->bnx_tx_saved_considx) {
3890                 if (sc->bnx_rx_check_considx == ret->bnx_rx_saved_considx &&
3891                     sc->bnx_tx_check_considx == txr->bnx_tx_saved_considx) {
3892                         if (!sc->bnx_intr_maylose) {
3893                                 sc->bnx_intr_maylose = TRUE;
3894                                 goto done;
3895                         }
3896                         if (bootverbose)
3897                                 if_printf(ifp, "lost interrupt\n");
3898                         bnx_msi(sc);
3899                 }
3900         }
3901         sc->bnx_intr_maylose = FALSE;
3902         sc->bnx_rx_check_considx = ret->bnx_rx_saved_considx;
3903         sc->bnx_tx_check_considx = txr->bnx_tx_saved_considx;
3904
3905 done:
3906         callout_reset(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
3907             bnx_intr_check, sc);
3908         lwkt_serialize_exit(ifp->if_serializer);
3909 }
3910
3911 static void
3912 bnx_enable_intr(struct bnx_softc *sc)
3913 {
3914         struct ifnet *ifp = &sc->arpcom.ac_if;
3915
3916         lwkt_serialize_handler_enable(ifp->if_serializer);
3917
3918         /*
3919          * Enable interrupt.
3920          */
3921         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3922         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
3923                 /* XXX Linux driver */
3924                 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3925         }
3926
3927         /*
3928          * Unmask the interrupt when we stop polling.
3929          */
3930         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3931             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3932
3933         /*
3934          * Trigger another interrupt, since above writing
3935          * to interrupt mailbox0 may acknowledge pending
3936          * interrupt.
3937          */
3938         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3939
3940         if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) {
3941                 sc->bnx_intr_maylose = FALSE;
3942                 sc->bnx_rx_check_considx = 0;
3943                 sc->bnx_tx_check_considx = 0;
3944
3945                 if (bootverbose)
3946                         if_printf(ifp, "status tag bug workaround\n");
3947
3948                 /* 10ms check interval */
3949                 callout_reset_bycpu(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
3950                     bnx_intr_check, sc, sc->bnx_intr_cpuid);
3951         }
3952 }
3953
3954 static void
3955 bnx_disable_intr(struct bnx_softc *sc)
3956 {
3957         struct ifnet *ifp = &sc->arpcom.ac_if;
3958
3959         /*
3960          * Mask the interrupt when we start polling.
3961          */
3962         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3963             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3964
3965         /*
3966          * Acknowledge possible asserted interrupt.
3967          */
3968         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3969
3970         callout_stop(&sc->bnx_intr_timer);
3971         sc->bnx_intr_maylose = FALSE;
3972         sc->bnx_rx_check_considx = 0;
3973         sc->bnx_tx_check_considx = 0;
3974
3975         sc->bnx_npoll.ifpc_stcount = 0;
3976
3977         lwkt_serialize_handler_disable(ifp->if_serializer);
3978 }
3979
3980 static int
3981 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
3982 {
3983         uint32_t mac_addr;
3984         int ret = 1;
3985
3986         mac_addr = bnx_readmem_ind(sc, 0x0c14);
3987         if ((mac_addr >> 16) == 0x484b) {
3988                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
3989                 ether_addr[1] = (uint8_t)mac_addr;
3990                 mac_addr = bnx_readmem_ind(sc, 0x0c18);
3991                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
3992                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
3993                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
3994                 ether_addr[5] = (uint8_t)mac_addr;
3995                 ret = 0;
3996         }
3997         return ret;
3998 }
3999
4000 static int
4001 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
4002 {
4003         int mac_offset = BGE_EE_MAC_OFFSET;
4004
4005         if (BNX_IS_5717_PLUS(sc)) {
4006                 int f;
4007
4008                 f = pci_get_function(sc->bnx_dev);
4009                 if (f & 1)
4010                         mac_offset = BGE_EE_MAC_OFFSET_5717;
4011                 if (f > 1)
4012                         mac_offset += BGE_EE_MAC_OFFSET_5717_OFF;
4013         }
4014
4015         return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4016 }
4017
4018 static int
4019 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[])
4020 {
4021         if (sc->bnx_flags & BNX_FLAG_NO_EEPROM)
4022                 return 1;
4023
4024         return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4025                                ETHER_ADDR_LEN);
4026 }
4027
4028 static int
4029 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[])
4030 {
4031         static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = {
4032                 /* NOTE: Order is critical */
4033                 bnx_get_eaddr_mem,
4034                 bnx_get_eaddr_nvram,
4035                 bnx_get_eaddr_eeprom,
4036                 NULL
4037         };
4038         const bnx_eaddr_fcn_t *func;
4039
4040         for (func = bnx_eaddr_funcs; *func != NULL; ++func) {
4041                 if ((*func)(sc, eaddr) == 0)
4042                         break;
4043         }
4044         return (*func == NULL ? ENXIO : 0);
4045 }
4046
4047 /*
4048  * NOTE: 'm' is not freed upon failure
4049  */
4050 struct mbuf *
4051 bnx_defrag_shortdma(struct mbuf *m)
4052 {
4053         struct mbuf *n;
4054         int found;
4055
4056         /*
4057          * If device receive two back-to-back send BDs with less than
4058          * or equal to 8 total bytes then the device may hang.  The two
4059          * back-to-back send BDs must in the same frame for this failure
4060          * to occur.  Scan mbuf chains and see whether two back-to-back
4061          * send BDs are there.  If this is the case, allocate new mbuf
4062          * and copy the frame to workaround the silicon bug.
4063          */
4064         for (n = m, found = 0; n != NULL; n = n->m_next) {
4065                 if (n->m_len < 8) {
4066                         found++;
4067                         if (found > 1)
4068                                 break;
4069                         continue;
4070                 }
4071                 found = 0;
4072         }
4073
4074         if (found > 1)
4075                 n = m_defrag(m, MB_DONTWAIT);
4076         else
4077                 n = m;
4078         return n;
4079 }
4080
4081 static void
4082 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)
4083 {
4084         int i;
4085
4086         BNX_CLRBIT(sc, reg, bit);
4087         for (i = 0; i < BNX_TIMEOUT; i++) {
4088                 if ((CSR_READ_4(sc, reg) & bit) == 0)
4089                         return;
4090                 DELAY(100);
4091         }
4092 }
4093
4094 static void
4095 bnx_link_poll(struct bnx_softc *sc)
4096 {
4097         uint32_t status;
4098
4099         status = CSR_READ_4(sc, BGE_MAC_STS);
4100         if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) {
4101                 sc->bnx_link_evt = 0;
4102                 sc->bnx_link_upd(sc, status);
4103         }
4104 }
4105
4106 static void
4107 bnx_enable_msi(struct bnx_softc *sc)
4108 {
4109         uint32_t msi_mode;
4110
4111         msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4112         msi_mode |= BGE_MSIMODE_ENABLE;
4113         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4114                 /*
4115                  * NOTE:
4116                  * 5718-PG105-R says that "one shot" mode
4117                  * does not work if MSI is used, however,
4118                  * it obviously works.
4119                  */
4120                 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4121         }
4122         CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4123 }
4124
4125 static uint32_t
4126 bnx_dma_swap_options(struct bnx_softc *sc)
4127 {
4128         uint32_t dma_options;
4129
4130         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
4131             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
4132 #if BYTE_ORDER == BIG_ENDIAN
4133         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
4134 #endif
4135         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
4136             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
4137                 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
4138                     BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
4139                     BGE_MODECTL_HTX2B_ENABLE;
4140         }
4141         return dma_options;
4142 }
4143
4144 static int
4145 bnx_setup_tso(struct bnx_tx_ring *txr, struct mbuf **mp,
4146     uint16_t *mss0, uint16_t *flags0)
4147 {
4148         struct mbuf *m;
4149         struct ip *ip;
4150         struct tcphdr *th;
4151         int thoff, iphlen, hoff, hlen;
4152         uint16_t flags, mss;
4153
4154         m = *mp;
4155         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4156
4157         hoff = m->m_pkthdr.csum_lhlen;
4158         iphlen = m->m_pkthdr.csum_iphlen;
4159         thoff = m->m_pkthdr.csum_thlen;
4160
4161         KASSERT(hoff > 0, ("invalid ether header len"));
4162         KASSERT(iphlen > 0, ("invalid ip header len"));
4163         KASSERT(thoff > 0, ("invalid tcp header len"));
4164
4165         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4166                 m = m_pullup(m, hoff + iphlen + thoff);
4167                 if (m == NULL) {
4168                         *mp = NULL;
4169                         return ENOBUFS;
4170                 }
4171                 *mp = m;
4172         }
4173         ip = mtodoff(m, struct ip *, hoff);
4174         th = mtodoff(m, struct tcphdr *, hoff + iphlen);
4175
4176         mss = m->m_pkthdr.tso_segsz;
4177         flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
4178
4179         ip->ip_len = htons(mss + iphlen + thoff);
4180         th->th_sum = 0;
4181
4182         hlen = (iphlen + thoff) >> 2;
4183         mss |= ((hlen & 0x3) << 14);
4184         flags |= ((hlen & 0xf8) << 7) | ((hlen & 0x4) << 2);
4185
4186         *mss0 = mss;
4187         *flags0 = flags;
4188
4189         return 0;
4190 }
4191
4192 static int
4193 bnx_create_tx_ring(struct bnx_tx_ring *txr)
4194 {
4195         bus_size_t txmaxsz, txmaxsegsz;
4196         int i, error;
4197
4198         /*
4199          * Create DMA tag and maps for TX mbufs.
4200          */
4201         if (txr->bnx_sc->bnx_flags & BNX_FLAG_TSO)
4202                 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
4203         else
4204                 txmaxsz = BNX_JUMBO_FRAMELEN;
4205         if (txr->bnx_sc->bnx_asicrev == BGE_ASICREV_BCM57766)
4206                 txmaxsegsz = MCLBYTES;
4207         else
4208                 txmaxsegsz = PAGE_SIZE;
4209         error = bus_dma_tag_create(txr->bnx_sc->bnx_cdata.bnx_parent_tag,
4210             1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
4211             txmaxsz, BNX_NSEG_NEW, txmaxsegsz,
4212             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
4213             &txr->bnx_tx_mtag);
4214         if (error) {
4215                 device_printf(txr->bnx_sc->bnx_dev,
4216                     "could not create TX mbuf DMA tag\n");
4217                 return error;
4218         }
4219
4220         for (i = 0; i < BGE_TX_RING_CNT; i++) {
4221                 error = bus_dmamap_create(txr->bnx_tx_mtag,
4222                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
4223                     &txr->bnx_tx_buf[i].bnx_tx_dmamap);
4224                 if (error) {
4225                         int j;
4226
4227                         for (j = 0; j < i; ++j) {
4228                                 bus_dmamap_destroy(txr->bnx_tx_mtag,
4229                                     txr->bnx_tx_buf[j].bnx_tx_dmamap);
4230                         }
4231                         bus_dma_tag_destroy(txr->bnx_tx_mtag);
4232                         txr->bnx_tx_mtag = NULL;
4233
4234                         device_printf(txr->bnx_sc->bnx_dev,
4235                             "could not create TX mbuf DMA map\n");
4236                         return error;
4237                 }
4238         }
4239
4240         /*
4241          * Create DMA stuffs for TX ring.
4242          */
4243         error = bnx_dma_block_alloc(txr->bnx_sc, BGE_TX_RING_SZ,
4244             &txr->bnx_tx_ring_tag,
4245             &txr->bnx_tx_ring_map,
4246             (void *)&txr->bnx_tx_ring,
4247             &txr->bnx_tx_ring_paddr);
4248         if (error) {
4249                 device_printf(txr->bnx_sc->bnx_dev,
4250                     "could not create TX ring\n");
4251                 return error;
4252         }
4253
4254         txr->bnx_tx_flags |= BNX_TX_FLAG_SHORTDMA;
4255         txr->bnx_tx_wreg = BNX_TX_WREG_NSEGS;
4256
4257         return 0;
4258 }
4259
4260 static void
4261 bnx_destroy_tx_ring(struct bnx_tx_ring *txr)
4262 {
4263         /* Destroy TX mbuf DMA stuffs. */
4264         if (txr->bnx_tx_mtag != NULL) {
4265                 int i;
4266
4267                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
4268                         KKASSERT(txr->bnx_tx_buf[i].bnx_tx_mbuf == NULL);
4269                         bus_dmamap_destroy(txr->bnx_tx_mtag,
4270                             txr->bnx_tx_buf[i].bnx_tx_dmamap);
4271                 }
4272                 bus_dma_tag_destroy(txr->bnx_tx_mtag);
4273         }
4274
4275         /* Destroy TX ring */
4276         bnx_dma_block_free(txr->bnx_tx_ring_tag,
4277             txr->bnx_tx_ring_map, txr->bnx_tx_ring);
4278 }
4279
4280 static int
4281 bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS)
4282 {
4283         struct bnx_softc *sc = (void *)arg1;
4284         struct ifnet *ifp = &sc->arpcom.ac_if;
4285         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
4286         int error, defrag, i;
4287
4288         if (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG)
4289                 defrag = 1;
4290         else
4291                 defrag = 0;
4292
4293         error = sysctl_handle_int(oidp, &defrag, 0, req);
4294         if (error || req->newptr == NULL)
4295                 return error;
4296
4297         lwkt_serialize_enter(ifp->if_serializer);
4298         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4299                 txr = &sc->bnx_tx_ring[i];
4300                 if (defrag)
4301                         txr->bnx_tx_flags |= BNX_TX_FLAG_FORCE_DEFRAG;
4302                 else
4303                         txr->bnx_tx_flags &= ~BNX_TX_FLAG_FORCE_DEFRAG;
4304         }
4305         lwkt_serialize_exit(ifp->if_serializer);
4306
4307         return 0;
4308 }
4309
4310 static int
4311 bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS)
4312 {
4313         struct bnx_softc *sc = (void *)arg1;
4314         struct ifnet *ifp = &sc->arpcom.ac_if;
4315         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
4316         int error, tx_wreg, i;
4317
4318         tx_wreg = txr->bnx_tx_wreg;
4319         error = sysctl_handle_int(oidp, &tx_wreg, 0, req);
4320         if (error || req->newptr == NULL)
4321                 return error;
4322
4323         lwkt_serialize_enter(ifp->if_serializer);
4324         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
4325                 sc->bnx_tx_ring[i].bnx_tx_wreg = tx_wreg;
4326         lwkt_serialize_exit(ifp->if_serializer);
4327
4328         return 0;
4329 }
4330
4331 static int
4332 bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *ret)
4333 {
4334         int error;
4335
4336         /*
4337          * Create DMA stuffs for RX return ring.
4338          */
4339         error = bnx_dma_block_alloc(ret->bnx_sc,
4340             BGE_RX_RTN_RING_SZ(BNX_RETURN_RING_CNT),
4341             &ret->bnx_rx_ret_ring_tag,
4342             &ret->bnx_rx_ret_ring_map,
4343             (void *)&ret->bnx_rx_ret_ring,
4344             &ret->bnx_rx_ret_ring_paddr);
4345         if (error) {
4346                 device_printf(ret->bnx_sc->bnx_dev,
4347                     "could not create RX ret ring\n");
4348                 return error;
4349         }
4350
4351         /* Shadow standard ring's RX mbuf DMA tag */
4352         ret->bnx_rx_mtag = ret->bnx_std->bnx_rx_mtag;
4353
4354         /*
4355          * Create tmp DMA map for RX mbufs.
4356          */
4357         error = bus_dmamap_create(ret->bnx_rx_mtag, BUS_DMA_WAITOK,
4358             &ret->bnx_rx_tmpmap);
4359         if (error) {
4360                 device_printf(ret->bnx_sc->bnx_dev,
4361                     "could not create tmp RX mbuf DMA map\n");
4362                 ret->bnx_rx_mtag = NULL;
4363                 return error;
4364         }
4365         return 0;
4366 }
4367
4368 static void
4369 bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *ret)
4370 {
4371         /* Destroy tmp RX mbuf DMA map */
4372         if (ret->bnx_rx_mtag != NULL)
4373                 bus_dmamap_destroy(ret->bnx_rx_mtag, ret->bnx_rx_tmpmap);
4374
4375         /* Destroy RX return ring */
4376         bnx_dma_block_free(ret->bnx_rx_ret_ring_tag,
4377             ret->bnx_rx_ret_ring_map, ret->bnx_rx_ret_ring);
4378 }
4379
4380 static int
4381 bnx_alloc_intr(struct bnx_softc *sc)
4382 {
4383         u_int intr_flags;
4384
4385         sc->bnx_irq_type = pci_alloc_1intr(sc->bnx_dev, bnx_msi_enable,
4386             &sc->bnx_irq_rid, &intr_flags);
4387
4388         sc->bnx_irq = bus_alloc_resource_any(sc->bnx_dev, SYS_RES_IRQ,
4389             &sc->bnx_irq_rid, intr_flags);
4390         if (sc->bnx_irq == NULL) {
4391                 device_printf(sc->bnx_dev, "could not alloc interrupt\n");
4392                 return ENXIO;
4393         }
4394
4395         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
4396                 sc->bnx_flags |= BNX_FLAG_ONESHOT_MSI;
4397                 bnx_enable_msi(sc);
4398         }
4399         return 0;
4400 }
4401
4402 static int
4403 bnx_setup_intr(struct bnx_softc *sc)
4404 {
4405         driver_intr_t *intr_func;
4406         int error;
4407
4408         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
4409                 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4410                         intr_func = bnx_msi_oneshot;
4411                         if (bootverbose)
4412                                 device_printf(sc->bnx_dev, "oneshot MSI\n");
4413                 } else {
4414                         intr_func = bnx_msi;
4415                 }
4416         } else {
4417                 intr_func = bnx_intr_legacy;
4418         }
4419         error = bus_setup_intr(sc->bnx_dev, sc->bnx_irq, INTR_MPSAFE,
4420             intr_func, sc, &sc->bnx_intrhand, sc->arpcom.ac_if.if_serializer);
4421         if (error) {
4422                 device_printf(sc->bnx_dev, "could not set up irq\n");
4423                 return error;
4424         }
4425         return 0;
4426 }
4427
4428 static void
4429 bnx_free_intr(struct bnx_softc *sc)
4430 {
4431         if (sc->bnx_irq != NULL) {
4432                 bus_release_resource(sc->bnx_dev, SYS_RES_IRQ,
4433                     sc->bnx_irq_rid, sc->bnx_irq);
4434         }
4435         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI)
4436                 pci_release_msi(sc->bnx_dev);
4437 }