2 * Copyright (c) 1993 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * $FreeBSD: src/sys/i386/include/cpufunc.h,v 1.96.2.3 2002/04/28 22:50:54 dwmalone Exp $
37 * Functions to provide access to special i386 instructions.
40 #ifndef _CPU_CPUFUNC_H_
41 #define _CPU_CPUFUNC_H_
44 #include <sys/types.h>
47 #include <sys/cdefs.h>
51 #define readb(va) (*(volatile u_int8_t *) (va))
52 #define readw(va) (*(volatile u_int16_t *) (va))
53 #define readl(va) (*(volatile u_int32_t *) (va))
55 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
56 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
57 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
61 #include <machine/lock.h> /* XXX */
63 #ifdef SWTCH_OPTIM_STATS
64 extern int tlb_flush_count; /* XXX */
70 __asm __volatile("int $3");
76 __asm __volatile("pause");
80 * Find the first 1 in mask, starting with bit 0 and return the
81 * bit number. If mask is 0 the result is undefined.
88 __asm __volatile("bsfl %0,%0" : "=r" (result) : "0" (mask));
97 __asm __volatile("bsfl %0,%0" : "=r" (result) : "0" (mask));
102 * Find the last 1 in mask, starting with bit 31 and return the
103 * bit number. If mask is 0 the result is undefined.
105 static __inline u_int
110 __asm __volatile("bsrl %0,%0" : "=r" (result) : "0" (mask));
115 * Test and set the specified bit (1 << bit) in the integer. The
116 * previous value of the bit is returned (0 or 1).
119 btsl(u_int *mask, int bit)
123 __asm __volatile("btsl %2,%1; movl $0,%0; adcl $0,%0" :
124 "=r"(result), "=m"(*mask) : "r" (bit));
129 * Test and clear the specified bit (1 << bit) in the integer. The
130 * previous value of the bit is returned (0 or 1).
133 btrl(u_int *mask, int bit)
137 __asm __volatile("btrl %2,%1; movl $0,%0; adcl $0,%0" :
138 "=r"(result), "=m"(*mask) : "r" (bit));
145 __asm __volatile("clflush %0" : : "m" (*(char *) addr));
149 do_cpuid(u_int ax, u_int *p)
151 __asm __volatile("cpuid"
152 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
157 cpuid_count(u_int ax, u_int cx, u_int *p)
159 __asm __volatile("cpuid"
160 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
161 : "0" (ax), "c" (cx));
164 #ifndef _CPU_DISABLE_INTR_DEFINED
167 cpu_disable_intr(void)
169 __asm __volatile("cli" : : : "memory");
174 #ifndef _CPU_ENABLE_INTR_DEFINED
177 cpu_enable_intr(void)
179 __asm __volatile("sti");
185 * Cpu and compiler memory ordering fence. mfence ensures strong read and
188 * A serializing or fence instruction is required here. A locked bus
189 * cycle on data for which we already own cache mastership is the most
196 __asm __volatile("mfence" : : : "memory");
198 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
203 * cpu_lfence() ensures strong read ordering for reads issued prior
204 * to the instruction verses reads issued afterwords.
206 * A serializing or fence instruction is required here. A locked bus
207 * cycle on data for which we already own cache mastership is the most
214 __asm __volatile("lfence" : : : "memory");
216 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
221 * cpu_sfence() ensures strong write ordering for writes issued prior
222 * to the instruction verses writes issued afterwords. Writes are
223 * ordered on intel cpus so we do not actually have to do anything.
230 * Don't use 'sfence' here, as it will create a lot of
231 * unnecessary stalls.
233 __asm __volatile("" : : : "memory");
237 * cpu_ccfence() prevents the compiler from reordering instructions, in
238 * particular stores, relative to the current cpu. Use cpu_sfence() if
239 * you need to guarentee ordering by both the compiler and by the cpu.
241 * This also prevents the compiler from caching memory loads into local
242 * variables across the routine.
247 __asm __volatile("" : : : "memory");
251 * This is a horrible, horrible hack that might have to be put at the
252 * end of certain procedures (on a case by case basis), just before it
253 * returns to avoid what we believe to be an unreported AMD cpu bug.
254 * Found to occur on both a Phenom II X4 820 (two of them), as well
255 * as a 48-core built around an Opteron 6168 (Id = 0x100f91 Stepping = 1).
256 * The problem does not appear to occur w/Intel cpus.
258 * The bug is likely related to either a write combining issue or the
259 * Return Address Stack (RAS) hardware cache.
261 * In particular, we had to do this for GCC's fill_sons_in_loop() routine
262 * which due to its deep recursion and stack flow appears to be able to
263 * tickle the amd cpu bug (w/ gcc-4.4.7). Adding a single 'nop' to the
264 * end of the routine just before it returns works around the bug.
266 * The bug appears to be extremely sensitive to %rip and %rsp values, to
267 * the point where even just inserting an instruction in an unrelated
268 * procedure (shifting the entire code base being run) effects the outcome.
269 * DragonFly is probably able to more readily reproduce the bug due to
270 * the stackgap randomization code. We would expect OpenBSD (where we got
271 * the stackgap randomization code from) to also be able to reproduce the
272 * issue. To date we have only reproduced the issue in DragonFly.
274 #define __AMDCPUBUG_DFLY01_AVAILABLE__
277 cpu_amdcpubug_dfly01(void)
279 __asm __volatile("nop" : : : "memory");
284 #define HAVE_INLINE_FFS
290 * Note that gcc-2's builtin ffs would be used if we didn't declare
291 * this inline or turn off the builtin. The builtin is faster but
292 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
295 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
298 #define HAVE_INLINE_FLS
303 return (mask == 0 ? mask : (int) bsrl((u_int)mask) + 1);
309 * The following complications are to get around gcc not having a
310 * constraint letter for the range 0..255. We still put "d" in the
311 * constraint because "i" isn't a valid constraint when the port
312 * isn't constant. This only matters for -O0 because otherwise
313 * the non-working version gets optimized away.
315 * Use an expression-statement instead of a conditional expression
316 * because gcc-2.6.0 would promote the operands of the conditional
317 * and produce poor code for "if ((inb(var) & const1) == const2)".
319 * The unnecessary test `(port) < 0x10000' is to generate a warning if
320 * the `port' has type u_short or smaller. Such types are pessimal.
321 * This actually only works for signed types. The range check is
322 * careful to avoid generating warnings.
324 #define inb(port) __extension__ ({ \
326 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
327 && (port) < 0x10000) \
328 _data = inbc(port); \
330 _data = inbv(port); \
333 #define outb(port, data) ( \
334 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
335 && (port) < 0x10000 \
336 ? outbc(port, data) : outbv(port, data))
338 static __inline u_char
343 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
348 outbc(u_int port, u_char data)
350 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
353 static __inline u_char
358 * We use %%dx and not %1 here because i/o is done at %dx and not at
359 * %edx, while gcc generates inferior code (movw instead of movl)
360 * if we tell it to load (u_short) port.
362 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
366 static __inline u_int
371 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
376 insb(u_int port, void *addr, size_t cnt)
378 __asm __volatile("cld; rep; insb"
379 : "=D" (addr), "=c" (cnt)
380 : "0" (addr), "1" (cnt), "d" (port)
385 insw(u_int port, void *addr, size_t cnt)
387 __asm __volatile("cld; rep; insw"
388 : "=D" (addr), "=c" (cnt)
389 : "0" (addr), "1" (cnt), "d" (port)
394 insl(u_int port, void *addr, size_t cnt)
396 __asm __volatile("cld; rep; insl"
397 : "=D" (addr), "=c" (cnt)
398 : "0" (addr), "1" (cnt), "d" (port)
405 __asm __volatile("invd");
411 * If we are not a true-SMP box then smp_invltlb() is a NOP. Note that this
412 * will cause the invl*() functions to be equivalent to the cpu_invl*()
415 void smp_invltlb(void);
416 void smp_invltlb_intr(void);
418 #ifndef _CPU_INVLPG_DEFINED
421 * Invalidate a patricular VA on this cpu only
424 cpu_invlpg(void *addr)
426 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
431 #ifndef _CPU_INVLTLB_DEFINED
434 * Invalidate the TLB on this cpu only
441 * This should be implemented as load_cr3(rcr3()) when load_cr3()
444 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp)
446 #if defined(SWTCH_OPTIM_STATS)
456 __asm __volatile("rep; nop");
461 static __inline u_short
466 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
470 static __inline u_int
471 loadandclear(volatile u_int *addr)
475 __asm __volatile("xorl %0,%0; xchgl %1,%0"
476 : "=&r" (result) : "m" (*addr));
481 outbv(u_int port, u_char data)
485 * Use an unnecessary assignment to help gcc's register allocator.
486 * This make a large difference for gcc-1.40 and a tiny difference
487 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
488 * best results. gcc-2.6.0 can't handle this.
491 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
495 outl(u_int port, u_int data)
498 * outl() and outw() aren't used much so we haven't looked at
499 * possible micro-optimizations such as the unnecessary
500 * assignment for them.
502 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
506 outsb(u_int port, const void *addr, size_t cnt)
508 __asm __volatile("cld; rep; outsb"
509 : "=S" (addr), "=c" (cnt)
510 : "0" (addr), "1" (cnt), "d" (port));
514 outsw(u_int port, const void *addr, size_t cnt)
516 __asm __volatile("cld; rep; outsw"
517 : "=S" (addr), "=c" (cnt)
518 : "0" (addr), "1" (cnt), "d" (port));
522 outsl(u_int port, const void *addr, size_t cnt)
524 __asm __volatile("cld; rep; outsl"
525 : "=S" (addr), "=c" (cnt)
526 : "0" (addr), "1" (cnt), "d" (port));
530 outw(u_int port, u_short data)
532 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
535 static __inline u_int
540 __asm __volatile("movl %%cr2,%0" : "=r" (data));
544 static __inline u_int
549 __asm __volatile("pushfl; popl %0" : "=r" (ef));
553 static __inline u_int64_t
558 __asm __volatile("rdmsr" : "=A" (rv) : "c" (msr));
562 static __inline u_int64_t
567 __asm __volatile("rdpmc" : "=A" (rv) : "c" (pmc));
571 #define _RDTSC_SUPPORTED_
573 static __inline u_int64_t
578 __asm __volatile("rdtsc" : "=A" (rv));
585 __asm __volatile("wbinvd");
589 write_eflags(u_int ef)
591 __asm __volatile("pushl %0; popfl" : : "r" (ef));
595 wrmsr(u_int msr, u_int64_t newval)
597 __asm __volatile("wrmsr" : : "A" (newval), "c" (msr));
600 static __inline u_short
604 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
608 static __inline u_short
612 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
619 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
625 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
628 static __inline u_int
632 __asm __volatile("movl %%dr0,%0" : "=r" (data));
639 __asm __volatile("movl %0,%%dr0" : : "r" (sel));
642 static __inline u_int
646 __asm __volatile("movl %%dr1,%0" : "=r" (data));
653 __asm __volatile("movl %0,%%dr1" : : "r" (sel));
656 static __inline u_int
660 __asm __volatile("movl %%dr2,%0" : "=r" (data));
667 __asm __volatile("movl %0,%%dr2" : : "r" (sel));
670 static __inline u_int
674 __asm __volatile("movl %%dr3,%0" : "=r" (data));
681 __asm __volatile("movl %0,%%dr3" : : "r" (sel));
684 static __inline u_int
688 __asm __volatile("movl %%dr4,%0" : "=r" (data));
695 __asm __volatile("movl %0,%%dr4" : : "r" (sel));
698 static __inline u_int
702 __asm __volatile("movl %%dr5,%0" : "=r" (data));
709 __asm __volatile("movl %0,%%dr5" : : "r" (sel));
712 static __inline u_int
716 __asm __volatile("movl %%dr6,%0" : "=r" (data));
723 __asm __volatile("movl %0,%%dr6" : : "r" (sel));
726 static __inline u_int
730 __asm __volatile("movl %%dr7,%0" : "=r" (data));
737 __asm __volatile("movl %0,%%dr7" : : "r" (sel));
740 #else /* !__GNUC__ */
742 int breakpoint (void);
743 void cpu_pause (void);
744 u_int bsfl (u_int mask);
745 u_int bsrl (u_int mask);
746 void cpu_disable_intr (void);
747 void do_cpuid (u_int ax, u_int *p);
748 void cpu_enable_intr (void);
749 u_char inb (u_int port);
750 u_int inl (u_int port);
751 void insb (u_int port, void *addr, size_t cnt);
752 void insl (u_int port, void *addr, size_t cnt);
753 void insw (u_int port, void *addr, size_t cnt);
755 u_short inw (u_int port);
756 u_int loadandclear (u_int *addr);
757 void outb (u_int port, u_char data);
758 void outl (u_int port, u_int data);
759 void outsb (u_int port, void *addr, size_t cnt);
760 void outsl (u_int port, void *addr, size_t cnt);
761 void outsw (u_int port, void *addr, size_t cnt);
762 void outw (u_int port, u_short data);
764 u_int64_t rdmsr (u_int msr);
765 u_int64_t rdpmc (u_int pmc);
766 u_int64_t rdtsc (void);
767 u_int read_eflags (void);
769 void write_eflags (u_int ef);
770 void wrmsr (u_int msr, u_int64_t newval);
773 void load_fs (u_short sel);
774 void load_gs (u_short sel);
776 #endif /* __GNUC__ */
778 void load_cr0 (u_int cr0);
779 void load_cr3 (u_int cr3);
780 void load_cr4 (u_int cr4);
781 void ltr (u_short sel);
785 int rdmsr_safe (u_int msr, uint64_t *val);
786 void reset_dbregs (void);
789 #endif /* !_CPU_CPUFUNC_H_ */