sys/dev/netif/bnx/if_bnx.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36
  37 #include "opt_polling.h"
  38
  39 #include <sys/param.h>
  40 #include <sys/bus.h>
  41 #include <sys/endian.h>
  42 #include <sys/kernel.h>
  43 #include <sys/interrupt.h>
  44 #include <sys/mbuf.h>
  45 #include <sys/malloc.h>
  46 #include <sys/queue.h>
  47 #include <sys/rman.h>
  48 #include <sys/serialize.h>
  49 #include <sys/socket.h>
  50 #include <sys/sockio.h>
  51 #include <sys/sysctl.h>
  52
  53 #include <net/bpf.h>
  54 #include <net/ethernet.h>
  55 #include <net/if.h>
  56 #include <net/if_arp.h>
  57 #include <net/if_dl.h>
  58 #include <net/if_media.h>
  59 #include <net/if_types.h>
  60 #include <net/ifq_var.h>
  61 #include <net/vlan/if_vlan_var.h>
  62 #include <net/vlan/if_vlan_ether.h>
  63
  64 #include <dev/netif/mii_layer/mii.h>
  65 #include <dev/netif/mii_layer/miivar.h>
  66 #include <dev/netif/mii_layer/brgphyreg.h>
  67
  68 #include <bus/pci/pcidevs.h>
  69 #include <bus/pci/pcireg.h>
  70 #include <bus/pci/pcivar.h>
  71
  72 #include <dev/netif/bge/if_bgereg.h>
  73 #include <dev/netif/bnx/if_bnxvar.h>
  74
  75 /* "device miibus" required.  See GENERIC if you get errors here. */
  76 #include "miibus_if.h"
  77
  78 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  79
  80 static const struct bnx_type {
  81         uint16_t                bnx_vid;
  82         uint16_t                bnx_did;
  83         char                    *bnx_name;
  84 } bnx_devs[] = {
  85         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
  86                 "Broadcom BCM5717 Gigabit Ethernet" },
  87         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
  88                 "Broadcom BCM5718 Gigabit Ethernet" },
  89         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
  90                 "Broadcom BCM5719 Gigabit Ethernet" },
  91         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
  92                 "Broadcom BCM5720 Gigabit Ethernet" },
  93
  94         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
  95                 "Broadcom BCM57761 Gigabit Ethernet" },
  96         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
  97                 "Broadcom BCM57781 Gigabit Ethernet" },
  98         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
  99                 "Broadcom BCM57791 Fast Ethernet" },
 100         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
 101                 "Broadcom BCM57765 Gigabit Ethernet" },
 102         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
 103                 "Broadcom BCM57785 Gigabit Ethernet" },
 104         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
 105                 "Broadcom BCM57795 Fast Ethernet" },
 106
 107         { 0, 0, NULL }
 108 };
 109
 110 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
 111 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
 112 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
 113 #define BNX_IS_57765_FAMILY(sc)  \
 114         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
 115
 116 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
 117
 118 static int      bnx_probe(device_t);
 119 static int      bnx_attach(device_t);
 120 static int      bnx_detach(device_t);
 121 static void     bnx_shutdown(device_t);
 122 static int      bnx_suspend(device_t);
 123 static int      bnx_resume(device_t);
 124 static int      bnx_miibus_readreg(device_t, int, int);
 125 static int      bnx_miibus_writereg(device_t, int, int, int);
 126 static void     bnx_miibus_statchg(device_t);
 127
 128 #ifdef DEVICE_POLLING
 129 static void     bnx_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 130 #endif
 131 static void     bnx_intr_legacy(void *);
 132 static void     bnx_msi(void *);
 133 static void     bnx_msi_oneshot(void *);
 134 static void     bnx_intr(struct bnx_softc *);
 135 static void     bnx_enable_intr(struct bnx_softc *);
 136 static void     bnx_disable_intr(struct bnx_softc *);
 137 static void     bnx_txeof(struct bnx_softc *, uint16_t);
 138 static void     bnx_rxeof(struct bnx_softc *, uint16_t);
 139
 140 static void     bnx_start(struct ifnet *);
 141 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 142 static void     bnx_init(void *);
 143 static void     bnx_stop(struct bnx_softc *);
 144 static void     bnx_watchdog(struct ifnet *);
 145 static int      bnx_ifmedia_upd(struct ifnet *);
 146 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 147 static void     bnx_tick(void *);
 148
 149 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
 150 static void     bnx_free_jumbo_mem(struct bnx_softc *);
 151 static struct bnx_jslot
 152                 *bnx_jalloc(struct bnx_softc *);
 153 static void     bnx_jfree(void *);
 154 static void     bnx_jref(void *);
 155 static int      bnx_newbuf_std(struct bnx_softc *, int, int);
 156 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
 157 static void     bnx_setup_rxdesc_std(struct bnx_softc *, int);
 158 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
 159 static int      bnx_init_rx_ring_std(struct bnx_softc *);
 160 static void     bnx_free_rx_ring_std(struct bnx_softc *);
 161 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
 162 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
 163 static void     bnx_free_tx_ring(struct bnx_softc *);
 164 static int      bnx_init_tx_ring(struct bnx_softc *);
 165 static int      bnx_dma_alloc(struct bnx_softc *);
 166 static void     bnx_dma_free(struct bnx_softc *);
 167 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
 168                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
 169 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 170 static struct mbuf *
 171                 bnx_defrag_shortdma(struct mbuf *);
 172 static int      bnx_encap(struct bnx_softc *, struct mbuf **, uint32_t *);
 173
 174 static void     bnx_reset(struct bnx_softc *);
 175 static int      bnx_chipinit(struct bnx_softc *);
 176 static int      bnx_blockinit(struct bnx_softc *);
 177 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
 178 static void     bnx_enable_msi(struct bnx_softc *sc);
 179 static void     bnx_setmulti(struct bnx_softc *);
 180 static void     bnx_setpromisc(struct bnx_softc *);
 181 static void     bnx_stats_update_regs(struct bnx_softc *);
 182 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
 183
 184 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
 185 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
 186 #ifdef notdef
 187 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
 188 #endif
 189 static void     bnx_writereg_ind(struct bnx_softc *, uint32_t, uint32_t);
 190 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
 191 static void     bnx_writembx(struct bnx_softc *, int, int);
 192 static uint8_t  bnx_nvram_getbyte(struct bnx_softc *, int, uint8_t *);
 193 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
 194 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
 195 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
 196
 197 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
 198 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
 199 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
 200 static void     bnx_link_poll(struct bnx_softc *);
 201
 202 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
 203 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
 204 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
 205 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
 206
 207 static void     bnx_coal_change(struct bnx_softc *);
 208 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 209 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 210 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
 211 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
 212 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 213 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 214 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
 215                     int, int, uint32_t);
 216
 217 static int      bnx_msi_enable = 1;
 218 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
 219
 220 static device_method_t bnx_methods[] = {
 221         /* Device interface */
 222         DEVMETHOD(device_probe,         bnx_probe),
 223         DEVMETHOD(device_attach,        bnx_attach),
 224         DEVMETHOD(device_detach,        bnx_detach),
 225         DEVMETHOD(device_shutdown,      bnx_shutdown),
 226         DEVMETHOD(device_suspend,       bnx_suspend),
 227         DEVMETHOD(device_resume,        bnx_resume),
 228
 229         /* bus interface */
 230         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 231         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 232
 233         /* MII interface */
 234         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
 235         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
 236         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
 237
 238         { 0, 0 }
 239 };
 240
 241 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
 242 static devclass_t bnx_devclass;
 243
 244 DECLARE_DUMMY_MODULE(if_bnx);
 245 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
 246 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
 247
 248 static uint32_t
 249 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
 250 {
 251         device_t dev = sc->bnx_dev;
 252         uint32_t val;
 253
 254         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 255             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 256                 return 0;
 257
 258         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 259         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 260         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 261         return (val);
 262 }
 263
 264 static void
 265 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 266 {
 267         device_t dev = sc->bnx_dev;
 268
 269         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 270             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 271                 return;
 272
 273         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 274         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 275         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 276 }
 277
 278 #ifdef notdef
 279 static uint32_t
 280 bnx_readreg_ind(struct bnx_softc *sc, uin32_t off)
 281 {
 282         device_t dev = sc->bnx_dev;
 283
 284         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 285         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 286 }
 287 #endif
 288
 289 static void
 290 bnx_writereg_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 291 {
 292         device_t dev = sc->bnx_dev;
 293
 294         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 295         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 296 }
 297
 298 static void
 299 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
 300 {
 301         CSR_WRITE_4(sc, off, val);
 302 }
 303
 304 static void
 305 bnx_writembx(struct bnx_softc *sc, int off, int val)
 306 {
 307         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906)
 308                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 309
 310         CSR_WRITE_4(sc, off, val);
 311 }
 312
 313 static uint8_t
 314 bnx_nvram_getbyte(struct bnx_softc *sc, int addr, uint8_t *dest)
 315 {
 316         uint32_t access, byte = 0;
 317         int i;
 318
 319         /* Lock. */
 320         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 321         for (i = 0; i < 8000; i++) {
 322                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 323                         break;
 324                 DELAY(20);
 325         }
 326         if (i == 8000)
 327                 return (1);
 328
 329         /* Enable access. */
 330         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 331         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 332
 333         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 334         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 335         for (i = 0; i < BNX_TIMEOUT * 10; i++) {
 336                 DELAY(10);
 337                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 338                         DELAY(10);
 339                         break;
 340                 }
 341         }
 342
 343         if (i == BNX_TIMEOUT * 10) {
 344                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 345                 return (1);
 346         }
 347
 348         /* Get result. */
 349         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 350
 351         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 352
 353         /* Disable access. */
 354         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 355
 356         /* Unlock. */
 357         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 358         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 359
 360         return (0);
 361 }
 362
 363 /*
 364  * Read a sequence of bytes from NVRAM.
 365  */
 366 static int
 367 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
 368 {
 369         int err = 0, i;
 370         uint8_t byte = 0;
 371
 372         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
 373                 return (1);
 374
 375         for (i = 0; i < cnt; i++) {
 376                 err = bnx_nvram_getbyte(sc, off + i, &byte);
 377                 if (err)
 378                         break;
 379                 *(dest + i) = byte;
 380         }
 381
 382         return (err ? 1 : 0);
 383 }
 384
 385 /*
 386  * Read a byte of data stored in the EEPROM at address 'addr.' The
 387  * BCM570x supports both the traditional bitbang interface and an
 388  * auto access interface for reading the EEPROM. We use the auto
 389  * access method.
 390  */
 391 static uint8_t
 392 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
 393 {
 394         int i;
 395         uint32_t byte = 0;
 396
 397         /*
 398          * Enable use of auto EEPROM access so we can avoid
 399          * having to use the bitbang method.
 400          */
 401         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 402
 403         /* Reset the EEPROM, load the clock period. */
 404         CSR_WRITE_4(sc, BGE_EE_ADDR,
 405             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 406         DELAY(20);
 407
 408         /* Issue the read EEPROM command. */
 409         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 410
 411         /* Wait for completion */
 412         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
 413                 DELAY(10);
 414                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 415                         break;
 416         }
 417
 418         if (i == BNX_TIMEOUT) {
 419                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 420                 return(1);
 421         }
 422
 423         /* Get result. */
 424         byte = CSR_READ_4(sc, BGE_EE_DATA);
 425
 426         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 427
 428         return(0);
 429 }
 430
 431 /*
 432  * Read a sequence of bytes from the EEPROM.
 433  */
 434 static int
 435 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
 436 {
 437         size_t i;
 438         int err;
 439         uint8_t byte;
 440
 441         for (byte = 0, err = 0, i = 0; i < len; i++) {
 442                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
 443                 if (err)
 444                         break;
 445                 *(dest + i) = byte;
 446         }
 447
 448         return(err ? 1 : 0);
 449 }
 450
 451 static int
 452 bnx_miibus_readreg(device_t dev, int phy, int reg)
 453 {
 454         struct bnx_softc *sc = device_get_softc(dev);
 455         uint32_t val;
 456         int i;
 457
 458         KASSERT(phy == sc->bnx_phyno,
 459             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 460
 461         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 462         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 463                 CSR_WRITE_4(sc, BGE_MI_MODE,
 464                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 465                 DELAY(80);
 466         }
 467
 468         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 469             BGE_MIPHY(phy) | BGE_MIREG(reg));
 470
 471         /* Poll for the PHY register access to complete. */
 472         for (i = 0; i < BNX_TIMEOUT; i++) {
 473                 DELAY(10);
 474                 val = CSR_READ_4(sc, BGE_MI_COMM);
 475                 if ((val & BGE_MICOMM_BUSY) == 0) {
 476                         DELAY(5);
 477                         val = CSR_READ_4(sc, BGE_MI_COMM);
 478                         break;
 479                 }
 480         }
 481         if (i == BNX_TIMEOUT) {
 482                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 483                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 484                 val = 0;
 485         }
 486
 487         /* Restore the autopoll bit if necessary. */
 488         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 489                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 490                 DELAY(80);
 491         }
 492
 493         if (val & BGE_MICOMM_READFAIL)
 494                 return 0;
 495
 496         return (val & 0xFFFF);
 497 }
 498
 499 static int
 500 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
 501 {
 502         struct bnx_softc *sc = device_get_softc(dev);
 503         int i;
 504
 505         KASSERT(phy == sc->bnx_phyno,
 506             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 507
 508         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 509             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 510                return 0;
 511
 512         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 513         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 514                 CSR_WRITE_4(sc, BGE_MI_MODE,
 515                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 516                 DELAY(80);
 517         }
 518
 519         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 520             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 521
 522         for (i = 0; i < BNX_TIMEOUT; i++) {
 523                 DELAY(10);
 524                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 525                         DELAY(5);
 526                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 527                         break;
 528                 }
 529         }
 530         if (i == BNX_TIMEOUT) {
 531                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 532                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 533         }
 534
 535         /* Restore the autopoll bit if necessary. */
 536         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 537                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 538                 DELAY(80);
 539         }
 540
 541         return 0;
 542 }
 543
 544 static void
 545 bnx_miibus_statchg(device_t dev)
 546 {
 547         struct bnx_softc *sc;
 548         struct mii_data *mii;
 549
 550         sc = device_get_softc(dev);
 551         mii = device_get_softc(sc->bnx_miibus);
 552
 553         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 554             (IFM_ACTIVE | IFM_AVALID)) {
 555                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 556                 case IFM_10_T:
 557                 case IFM_100_TX:
 558                         sc->bnx_link = 1;
 559                         break;
 560                 case IFM_1000_T:
 561                 case IFM_1000_SX:
 562                 case IFM_2500_SX:
 563                         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
 564                                 sc->bnx_link = 1;
 565                         else
 566                                 sc->bnx_link = 0;
 567                         break;
 568                 default:
 569                         sc->bnx_link = 0;
 570                         break;
 571                 }
 572         } else {
 573                 sc->bnx_link = 0;
 574         }
 575         if (sc->bnx_link == 0)
 576                 return;
 577
 578         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 579         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 580             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 581                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 582         } else {
 583                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 584         }
 585
 586         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 587                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 588         } else {
 589                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 590         }
 591 }
 592
 593 /*
 594  * Memory management for jumbo frames.
 595  */
 596 static int
 597 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
 598 {
 599         struct ifnet *ifp = &sc->arpcom.ac_if;
 600         struct bnx_jslot *entry;
 601         uint8_t *ptr;
 602         bus_addr_t paddr;
 603         int i, error;
 604
 605         /*
 606          * Create tag for jumbo mbufs.
 607          * This is really a bit of a kludge. We allocate a special
 608          * jumbo buffer pool which (thanks to the way our DMA
 609          * memory allocation works) will consist of contiguous
 610          * pages. This means that even though a jumbo buffer might
 611          * be larger than a page size, we don't really need to
 612          * map it into more than one DMA segment. However, the
 613          * default mbuf tag will result in multi-segment mappings,
 614          * so we have to create a special jumbo mbuf tag that
 615          * lets us get away with mapping the jumbo buffers as
 616          * a single segment. I think eventually the driver should
 617          * be changed so that it uses ordinary mbufs and cluster
 618          * buffers, i.e. jumbo frames can span multiple DMA
 619          * descriptors. But that's a project for another day.
 620          */
 621
 622         /*
 623          * Create DMA stuffs for jumbo RX ring.
 624          */
 625         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 626                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 627                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 628                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
 629                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
 630         if (error) {
 631                 if_printf(ifp, "could not create jumbo RX ring\n");
 632                 return error;
 633         }
 634
 635         /*
 636          * Create DMA stuffs for jumbo buffer block.
 637          */
 638         error = bnx_dma_block_alloc(sc, BNX_JMEM,
 639                                     &sc->bnx_cdata.bnx_jumbo_tag,
 640                                     &sc->bnx_cdata.bnx_jumbo_map,
 641                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
 642                                     &paddr);
 643         if (error) {
 644                 if_printf(ifp, "could not create jumbo buffer\n");
 645                 return error;
 646         }
 647
 648         SLIST_INIT(&sc->bnx_jfree_listhead);
 649
 650         /*
 651          * Now divide it up into 9K pieces and save the addresses
 652          * in an array. Note that we play an evil trick here by using
 653          * the first few bytes in the buffer to hold the the address
 654          * of the softc structure for this interface. This is because
 655          * bnx_jfree() needs it, but it is called by the mbuf management
 656          * code which will not pass it to us explicitly.
 657          */
 658         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
 659                 entry = &sc->bnx_cdata.bnx_jslots[i];
 660                 entry->bnx_sc = sc;
 661                 entry->bnx_buf = ptr;
 662                 entry->bnx_paddr = paddr;
 663                 entry->bnx_inuse = 0;
 664                 entry->bnx_slot = i;
 665                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
 666
 667                 ptr += BNX_JLEN;
 668                 paddr += BNX_JLEN;
 669         }
 670         return 0;
 671 }
 672
 673 static void
 674 bnx_free_jumbo_mem(struct bnx_softc *sc)
 675 {
 676         /* Destroy jumbo RX ring. */
 677         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 678                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 679                            sc->bnx_ldata.bnx_rx_jumbo_ring);
 680
 681         /* Destroy jumbo buffer block. */
 682         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
 683                            sc->bnx_cdata.bnx_jumbo_map,
 684                            sc->bnx_ldata.bnx_jumbo_buf);
 685 }
 686
 687 /*
 688  * Allocate a jumbo buffer.
 689  */
 690 static struct bnx_jslot *
 691 bnx_jalloc(struct bnx_softc *sc)
 692 {
 693         struct bnx_jslot *entry;
 694
 695         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 696         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
 697         if (entry) {
 698                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
 699                 entry->bnx_inuse = 1;
 700         } else {
 701                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 702         }
 703         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 704         return(entry);
 705 }
 706
 707 /*
 708  * Adjust usage count on a jumbo buffer.
 709  */
 710 static void
 711 bnx_jref(void *arg)
 712 {
 713         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 714         struct bnx_softc *sc = entry->bnx_sc;
 715
 716         if (sc == NULL)
 717                 panic("bnx_jref: can't find softc pointer!");
 718
 719         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 720                 panic("bnx_jref: asked to reference buffer "
 721                     "that we don't manage!");
 722         } else if (entry->bnx_inuse == 0) {
 723                 panic("bnx_jref: buffer already free!");
 724         } else {
 725                 atomic_add_int(&entry->bnx_inuse, 1);
 726         }
 727 }
 728
 729 /*
 730  * Release a jumbo buffer.
 731  */
 732 static void
 733 bnx_jfree(void *arg)
 734 {
 735         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 736         struct bnx_softc *sc = entry->bnx_sc;
 737
 738         if (sc == NULL)
 739                 panic("bnx_jfree: can't find softc pointer!");
 740
 741         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 742                 panic("bnx_jfree: asked to free buffer that we don't manage!");
 743         } else if (entry->bnx_inuse == 0) {
 744                 panic("bnx_jfree: buffer already free!");
 745         } else {
 746                 /*
 747                  * Possible MP race to 0, use the serializer.  The atomic insn
 748                  * is still needed for races against bnx_jref().
 749                  */
 750                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 751                 atomic_subtract_int(&entry->bnx_inuse, 1);
 752                 if (entry->bnx_inuse == 0) {
 753                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead,
 754                                           entry, jslot_link);
 755                 }
 756                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 757         }
 758 }
 759
 760
 761 /*
 762  * Intialize a standard receive ring descriptor.
 763  */
 764 static int
 765 bnx_newbuf_std(struct bnx_softc *sc, int i, int init)
 766 {
 767         struct mbuf *m_new = NULL;
 768         bus_dma_segment_t seg;
 769         bus_dmamap_t map;
 770         int error, nsegs;
 771
 772         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 773         if (m_new == NULL)
 774                 return ENOBUFS;
 775         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 776         m_adj(m_new, ETHER_ALIGN);
 777
 778         error = bus_dmamap_load_mbuf_segment(sc->bnx_cdata.bnx_rx_mtag,
 779                         sc->bnx_cdata.bnx_rx_tmpmap, m_new,
 780                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 781         if (error) {
 782                 m_freem(m_new);
 783                 return error;
 784         }
 785
 786         if (!init) {
 787                 bus_dmamap_sync(sc->bnx_cdata.bnx_rx_mtag,
 788                                 sc->bnx_cdata.bnx_rx_std_dmamap[i],
 789                                 BUS_DMASYNC_POSTREAD);
 790                 bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
 791                         sc->bnx_cdata.bnx_rx_std_dmamap[i]);
 792         }
 793
 794         map = sc->bnx_cdata.bnx_rx_tmpmap;
 795         sc->bnx_cdata.bnx_rx_tmpmap = sc->bnx_cdata.bnx_rx_std_dmamap[i];
 796         sc->bnx_cdata.bnx_rx_std_dmamap[i] = map;
 797
 798         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_mbuf = m_new;
 799         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_paddr = seg.ds_addr;
 800
 801         bnx_setup_rxdesc_std(sc, i);
 802         return 0;
 803 }
 804
 805 static void
 806 bnx_setup_rxdesc_std(struct bnx_softc *sc, int i)
 807 {
 808         struct bnx_rxchain *rc;
 809         struct bge_rx_bd *r;
 810
 811         rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
 812         r = &sc->bnx_ldata.bnx_rx_std_ring[i];
 813
 814         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
 815         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
 816         r->bge_len = rc->bnx_mbuf->m_len;
 817         r->bge_idx = i;
 818         r->bge_flags = BGE_RXBDFLAG_END;
 819 }
 820
 821 /*
 822  * Initialize a jumbo receive ring descriptor. This allocates
 823  * a jumbo buffer from the pool managed internally by the driver.
 824  */
 825 static int
 826 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
 827 {
 828         struct mbuf *m_new = NULL;
 829         struct bnx_jslot *buf;
 830         bus_addr_t paddr;
 831
 832         /* Allocate the mbuf. */
 833         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 834         if (m_new == NULL)
 835                 return ENOBUFS;
 836
 837         /* Allocate the jumbo buffer */
 838         buf = bnx_jalloc(sc);
 839         if (buf == NULL) {
 840                 m_freem(m_new);
 841                 return ENOBUFS;
 842         }
 843
 844         /* Attach the buffer to the mbuf. */
 845         m_new->m_ext.ext_arg = buf;
 846         m_new->m_ext.ext_buf = buf->bnx_buf;
 847         m_new->m_ext.ext_free = bnx_jfree;
 848         m_new->m_ext.ext_ref = bnx_jref;
 849         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
 850
 851         m_new->m_flags |= M_EXT;
 852
 853         m_new->m_data = m_new->m_ext.ext_buf;
 854         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 855
 856         paddr = buf->bnx_paddr;
 857         m_adj(m_new, ETHER_ALIGN);
 858         paddr += ETHER_ALIGN;
 859
 860         /* Save necessary information */
 861         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_mbuf = m_new;
 862         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_paddr = paddr;
 863
 864         /* Set up the descriptor. */
 865         bnx_setup_rxdesc_jumbo(sc, i);
 866         return 0;
 867 }
 868
 869 static void
 870 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
 871 {
 872         struct bge_rx_bd *r;
 873         struct bnx_rxchain *rc;
 874
 875         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
 876         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 877
 878         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
 879         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
 880         r->bge_len = rc->bnx_mbuf->m_len;
 881         r->bge_idx = i;
 882         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 883 }
 884
 885 static int
 886 bnx_init_rx_ring_std(struct bnx_softc *sc)
 887 {
 888         int i, error;
 889
 890         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 891                 error = bnx_newbuf_std(sc, i, 1);
 892                 if (error)
 893                         return error;
 894         };
 895
 896         sc->bnx_std = BGE_STD_RX_RING_CNT - 1;
 897         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
 898
 899         return(0);
 900 }
 901
 902 static void
 903 bnx_free_rx_ring_std(struct bnx_softc *sc)
 904 {
 905         int i;
 906
 907         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 908                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
 909
 910                 if (rc->bnx_mbuf != NULL) {
 911                         bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
 912                                           sc->bnx_cdata.bnx_rx_std_dmamap[i]);
 913                         m_freem(rc->bnx_mbuf);
 914                         rc->bnx_mbuf = NULL;
 915                 }
 916                 bzero(&sc->bnx_ldata.bnx_rx_std_ring[i],
 917                     sizeof(struct bge_rx_bd));
 918         }
 919 }
 920
 921 static int
 922 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
 923 {
 924         struct bge_rcb *rcb;
 925         int i, error;
 926
 927         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 928                 error = bnx_newbuf_jumbo(sc, i, 1);
 929                 if (error)
 930                         return error;
 931         };
 932
 933         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
 934
 935         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
 936         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 937         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 938
 939         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
 940
 941         return(0);
 942 }
 943
 944 static void
 945 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
 946 {
 947         int i;
 948
 949         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 950                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 951
 952                 if (rc->bnx_mbuf != NULL) {
 953                         m_freem(rc->bnx_mbuf);
 954                         rc->bnx_mbuf = NULL;
 955                 }
 956                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
 957                     sizeof(struct bge_rx_bd));
 958         }
 959 }
 960
 961 static void
 962 bnx_free_tx_ring(struct bnx_softc *sc)
 963 {
 964         int i;
 965
 966         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 967                 if (sc->bnx_cdata.bnx_tx_chain[i] != NULL) {
 968                         bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
 969                                           sc->bnx_cdata.bnx_tx_dmamap[i]);
 970                         m_freem(sc->bnx_cdata.bnx_tx_chain[i]);
 971                         sc->bnx_cdata.bnx_tx_chain[i] = NULL;
 972                 }
 973                 bzero(&sc->bnx_ldata.bnx_tx_ring[i],
 974                     sizeof(struct bge_tx_bd));
 975         }
 976 }
 977
 978 static int
 979 bnx_init_tx_ring(struct bnx_softc *sc)
 980 {
 981         sc->bnx_txcnt = 0;
 982         sc->bnx_tx_saved_considx = 0;
 983         sc->bnx_tx_prodidx = 0;
 984
 985         /* Initialize transmit producer index for host-memory send ring. */
 986         bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bnx_tx_prodidx);
 987         bnx_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 988
 989         return(0);
 990 }
 991
 992 static void
 993 bnx_setmulti(struct bnx_softc *sc)
 994 {
 995         struct ifnet *ifp;
 996         struct ifmultiaddr *ifma;
 997         uint32_t hashes[4] = { 0, 0, 0, 0 };
 998         int h, i;
 999
1000         ifp = &sc->arpcom.ac_if;
1001
1002         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1003                 for (i = 0; i < 4; i++)
1004                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1005                 return;
1006         }
1007
1008         /* First, zot all the existing filters. */
1009         for (i = 0; i < 4; i++)
1010                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1011
1012         /* Now program new ones. */
1013         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1014                 if (ifma->ifma_addr->sa_family != AF_LINK)
1015                         continue;
1016                 h = ether_crc32_le(
1017                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1018                     ETHER_ADDR_LEN) & 0x7f;
1019                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1020         }
1021
1022         for (i = 0; i < 4; i++)
1023                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1024 }
1025
1026 /*
1027  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1028  * self-test results.
1029  */
1030 static int
1031 bnx_chipinit(struct bnx_softc *sc)
1032 {
1033         uint32_t dma_rw_ctl, mode_ctl;
1034         int i;
1035
1036         /* Set endian type before we access any non-PCI registers. */
1037         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
1038             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
1039
1040         /* Clear the MAC control register */
1041         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1042
1043         /*
1044          * Clear the MAC statistics block in the NIC's
1045          * internal memory.
1046          */
1047         for (i = BGE_STATS_BLOCK;
1048             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1049                 BNX_MEMWIN_WRITE(sc, i, 0);
1050
1051         for (i = BGE_STATUS_BLOCK;
1052             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1053                 BNX_MEMWIN_WRITE(sc, i, 0);
1054
1055         /* Set up the PCI DMA control register. */
1056         dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
1057             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1058
1059         if (BNX_IS_57765_PLUS(sc)) {
1060                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1061                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1062                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1063                 /*
1064                  * Enable HW workaround for controllers that misinterpret
1065                  * a status tag update and leave interrupts permanently
1066                  * disabled.
1067                  */
1068                 if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1069                     sc->bnx_asicrev != BGE_ASICREV_BCM57765)
1070                         dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1071         }
1072         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1073
1074         /*
1075          * Set up general mode register.
1076          */
1077         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1078             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1079         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1080
1081         /*
1082          * Disable memory write invalidate.  Apparently it is not supported
1083          * properly by these devices.  Also ensure that INTx isn't disabled,
1084          * as these chips need it even when using MSI.
1085          */
1086         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1087             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1088
1089         /* Set the timer prescaler (always 66Mhz) */
1090         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1091
1092         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1093                 DELAY(40);      /* XXX */
1094
1095                 /* Put PHY into ready state */
1096                 BNX_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1097                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1098                 DELAY(40);
1099         }
1100
1101         return(0);
1102 }
1103
1104 static int
1105 bnx_blockinit(struct bnx_softc *sc)
1106 {
1107         struct bge_rcb *rcb;
1108         bus_size_t vrcb;
1109         bge_hostaddr taddr;
1110         uint32_t val;
1111         int i, limit;
1112
1113         /*
1114          * Initialize the memory window pointer register so that
1115          * we can access the first 32K of internal NIC RAM. This will
1116          * allow us to set up the TX send ring RCBs and the RX return
1117          * ring RCBs, plus other things which live in NIC memory.
1118          */
1119         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1120
1121         /* Configure mbuf pool watermarks */
1122         if (BNX_IS_57765_PLUS(sc)) {
1123                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1124                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1125                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1126                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1127                 } else {
1128                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1129                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1130                 }
1131         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1132                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1133                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1134                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1135         } else {
1136                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1137                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1138                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1139         }
1140
1141         /* Configure DMA resource watermarks */
1142         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1143         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1144
1145         /* Enable buffer manager */
1146         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1147         /*
1148          * Change the arbitration algorithm of TXMBUF read request to
1149          * round-robin instead of priority based for BCM5719.  When
1150          * TXFIFO is almost empty, RDMA will hold its request until
1151          * TXFIFO is not almost empty.
1152          */
1153         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1154                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1155         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1156
1157         /* Poll for buffer manager start indication */
1158         for (i = 0; i < BNX_TIMEOUT; i++) {
1159                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1160                         break;
1161                 DELAY(10);
1162         }
1163
1164         if (i == BNX_TIMEOUT) {
1165                 if_printf(&sc->arpcom.ac_if,
1166                           "buffer manager failed to start\n");
1167                 return(ENXIO);
1168         }
1169
1170         /* Enable flow-through queues */
1171         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1172         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1173
1174         /* Wait until queue initialization is complete */
1175         for (i = 0; i < BNX_TIMEOUT; i++) {
1176                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1177                         break;
1178                 DELAY(10);
1179         }
1180
1181         if (i == BNX_TIMEOUT) {
1182                 if_printf(&sc->arpcom.ac_if,
1183                           "flow-through queue init failed\n");
1184                 return(ENXIO);
1185         }
1186
1187         /*
1188          * Summary of rings supported by the controller:
1189          *
1190          * Standard Receive Producer Ring
1191          * - This ring is used to feed receive buffers for "standard"
1192          *   sized frames (typically 1536 bytes) to the controller.
1193          *
1194          * Jumbo Receive Producer Ring
1195          * - This ring is used to feed receive buffers for jumbo sized
1196          *   frames (i.e. anything bigger than the "standard" frames)
1197          *   to the controller.
1198          *
1199          * Mini Receive Producer Ring
1200          * - This ring is used to feed receive buffers for "mini"
1201          *   sized frames to the controller.
1202          * - This feature required external memory for the controller
1203          *   but was never used in a production system.  Should always
1204          *   be disabled.
1205          *
1206          * Receive Return Ring
1207          * - After the controller has placed an incoming frame into a
1208          *   receive buffer that buffer is moved into a receive return
1209          *   ring.  The driver is then responsible to passing the
1210          *   buffer up to the stack.  Many versions of the controller
1211          *   support multiple RR rings.
1212          *
1213          * Send Ring
1214          * - This ring is used for outgoing frames.  Many versions of
1215          *   the controller support multiple send rings.
1216          */
1217
1218         /* Initialize the standard receive producer ring control block. */
1219         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1220         rcb->bge_hostaddr.bge_addr_lo =
1221             BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1222         rcb->bge_hostaddr.bge_addr_hi =
1223             BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1224         if (BNX_IS_57765_PLUS(sc)) {
1225                 /*
1226                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1227                  * Bits 15-2 : Maximum RX frame size
1228                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1229                  * Bit 0     : Reserved
1230                  */
1231                 rcb->bge_maxlen_flags =
1232                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1233         } else {
1234                 /*
1235                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1236                  * Bits 15-2 : Reserved (should be 0)
1237                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1238                  * Bit 0     : Reserved
1239                  */
1240                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1241         }
1242         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1243             sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1244             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1245                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1246         else
1247                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1248         /* Write the standard receive producer ring control block. */
1249         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1250         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1251         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1252         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1253         /* Reset the standard receive producer ring producer index. */
1254         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1255
1256         /*
1257          * Initialize the jumbo RX producer ring control
1258          * block.  We set the 'ring disabled' bit in the
1259          * flags field until we're actually ready to start
1260          * using this ring (i.e. once we set the MTU
1261          * high enough to require it).
1262          */
1263         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1264                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1265                 /* Get the jumbo receive producer ring RCB parameters. */
1266                 rcb->bge_hostaddr.bge_addr_lo =
1267                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1268                 rcb->bge_hostaddr.bge_addr_hi =
1269                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1270                 rcb->bge_maxlen_flags =
1271                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1272                     BGE_RCB_FLAG_RING_DISABLED);
1273                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1274                     sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1275                     sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1276                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1277                 else
1278                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1279                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1280                     rcb->bge_hostaddr.bge_addr_hi);
1281                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1282                     rcb->bge_hostaddr.bge_addr_lo);
1283                 /* Program the jumbo receive producer ring RCB parameters. */
1284                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1285                     rcb->bge_maxlen_flags);
1286                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1287                 /* Reset the jumbo receive producer ring producer index. */
1288                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1289         }
1290
1291         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1292         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
1293             (sc->bnx_chipid == BGE_CHIPID_BCM5906_A0 ||
1294              sc->bnx_chipid == BGE_CHIPID_BCM5906_A1 ||
1295              sc->bnx_chipid == BGE_CHIPID_BCM5906_A2)) {
1296                 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1297                     (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1298         }
1299
1300         /*
1301          * The BD ring replenish thresholds control how often the
1302          * hardware fetches new BD's from the producer rings in host
1303          * memory.  Setting the value too low on a busy system can
1304          * starve the hardware and recue the throughpout.
1305          *
1306          * Set the BD ring replentish thresholds. The recommended
1307          * values are 1/8th the number of descriptors allocated to
1308          * each ring.
1309          */
1310         val = 8;
1311         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1312         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1313                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1314                     BGE_JUMBO_RX_RING_CNT/8);
1315         }
1316         if (BNX_IS_57765_PLUS(sc)) {
1317                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1318                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1319         }
1320
1321         /*
1322          * Disable all send rings by setting the 'ring disabled' bit
1323          * in the flags field of all the TX send ring control blocks,
1324          * located in NIC memory.
1325          */
1326         if (BNX_IS_5717_PLUS(sc))
1327                 limit = 4;
1328         else if (BNX_IS_57765_FAMILY(sc))
1329                 limit = 2;
1330         else
1331                 limit = 1;
1332         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1333         for (i = 0; i < limit; i++) {
1334                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1335                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1336                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1337                 vrcb += sizeof(struct bge_rcb);
1338         }
1339
1340         /* Configure send ring RCB 0 (we use only the first ring) */
1341         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1342         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_tx_ring_paddr);
1343         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1344         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1345         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1346             sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1347             sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1348                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1349         } else {
1350                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1351                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1352         }
1353         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1354             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1355
1356         /*
1357          * Disable all receive return rings by setting the
1358          * 'ring disabled' bit in the flags field of all the receive
1359          * return ring control blocks, located in NIC memory.
1360          */
1361         if (BNX_IS_5717_PLUS(sc)) {
1362                 /* Should be 17, use 16 until we get an SRAM map. */
1363                 limit = 16;
1364         } else if (BNX_IS_57765_FAMILY(sc)) {
1365                 limit = 4;
1366         } else {
1367                 limit = 1;
1368         }
1369         /* Disable all receive return rings. */
1370         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1371         for (i = 0; i < limit; i++) {
1372                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1373                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1374                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1375                     BGE_RCB_FLAG_RING_DISABLED);
1376                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1377                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1378                     (i * (sizeof(uint64_t))), 0);
1379                 vrcb += sizeof(struct bge_rcb);
1380         }
1381
1382         /*
1383          * Set up receive return ring 0.  Note that the NIC address
1384          * for RX return rings is 0x0.  The return rings live entirely
1385          * within the host, so the nicaddr field in the RCB isn't used.
1386          */
1387         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1388         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_rx_return_ring_paddr);
1389         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1390         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1391         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1392         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1393             BGE_RCB_MAXLEN_FLAGS(sc->bnx_return_ring_cnt, 0));
1394
1395         /* Set random backoff seed for TX */
1396         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1397             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1398             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1399             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1400             BGE_TX_BACKOFF_SEED_MASK);
1401
1402         /* Set inter-packet gap */
1403         val = 0x2620;
1404         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1405                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1406                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1407         }
1408         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1409
1410         /*
1411          * Specify which ring to use for packets that don't match
1412          * any RX rules.
1413          */
1414         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1415
1416         /*
1417          * Configure number of RX lists. One interrupt distribution
1418          * list, sixteen active lists, one bad frames class.
1419          */
1420         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1421
1422         /* Inialize RX list placement stats mask. */
1423         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1424         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1425
1426         /* Disable host coalescing until we get it set up */
1427         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1428
1429         /* Poll to make sure it's shut down. */
1430         for (i = 0; i < BNX_TIMEOUT; i++) {
1431                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1432                         break;
1433                 DELAY(10);
1434         }
1435
1436         if (i == BNX_TIMEOUT) {
1437                 if_printf(&sc->arpcom.ac_if,
1438                           "host coalescing engine failed to idle\n");
1439                 return(ENXIO);
1440         }
1441
1442         /* Set up host coalescing defaults */
1443         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bnx_rx_coal_ticks);
1444         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bnx_tx_coal_ticks);
1445         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bnx_rx_coal_bds);
1446         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bnx_tx_coal_bds);
1447         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bnx_rx_coal_bds_int);
1448         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bnx_tx_coal_bds_int);
1449
1450         /* Set up address of status block */
1451         bzero(sc->bnx_ldata.bnx_status_block, BGE_STATUS_BLK_SZ);
1452         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1453             BGE_ADDR_HI(sc->bnx_ldata.bnx_status_block_paddr));
1454         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1455             BGE_ADDR_LO(sc->bnx_ldata.bnx_status_block_paddr));
1456
1457         /* Set up status block partail update size. */
1458         val = BGE_STATBLKSZ_32BYTE;
1459 #if 0
1460         /*
1461          * Does not seem to have visible effect in both
1462          * bulk data (1472B UDP datagram) and tiny data
1463          * (18B UDP datagram) TX tests.
1464          */
1465         val |= BGE_HCCMODE_CLRTICK_TX;
1466 #endif
1467         /* Turn on host coalescing state machine */
1468         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1469
1470         /* Turn on RX BD completion state machine and enable attentions */
1471         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1472             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1473
1474         /* Turn on RX list placement state machine */
1475         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1476
1477         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1478             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1479             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1480             BGE_MACMODE_FRMHDR_DMA_ENB;
1481
1482         if (sc->bnx_flags & BNX_FLAG_TBI)
1483                 val |= BGE_PORTMODE_TBI;
1484         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1485                 val |= BGE_PORTMODE_GMII;
1486         else
1487                 val |= BGE_PORTMODE_MII;
1488
1489         /* Turn on DMA, clear stats */
1490         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1491
1492         /* Set misc. local control, enable interrupts on attentions */
1493         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1494
1495 #ifdef notdef
1496         /* Assert GPIO pins for PHY reset */
1497         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1498             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1499         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1500             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1501 #endif
1502
1503         /* Turn on write DMA state machine */
1504         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1505         /* Enable host coalescing bug fix. */
1506         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1507         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1508                 /* Request larger DMA burst size to get better performance. */
1509                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1510         }
1511         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1512         DELAY(40);
1513
1514         if (BNX_IS_57765_PLUS(sc)) {
1515                 uint32_t dmactl;
1516
1517                 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1518                 /*
1519                  * Adjust tx margin to prevent TX data corruption and
1520                  * fix internal FIFO overflow.
1521                  */
1522                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1523                     sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1524                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1525                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1526                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1527                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1528                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1529                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1530                 }
1531                 /*
1532                  * Enable fix for read DMA FIFO overruns.
1533                  * The fix is to limit the number of RX BDs
1534                  * the hardware would fetch at a fime.
1535                  */
1536                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1537                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1538         }
1539
1540         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1541                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1542                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1543                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1544                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1545         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1546                 /*
1547                  * Allow 4KB burst length reads for non-LSO frames.
1548                  * Enable 512B burst length reads for buffer descriptors.
1549                  */
1550                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1551                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1552                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1553                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1554         }
1555
1556         /* Turn on read DMA state machine */
1557         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1558         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1559                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1560         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1561             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1562             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1563                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1564                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1565                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1566         }
1567         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1568                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1569                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1570                 /*
1571                  * Allow multiple outstanding read requests from
1572                  * non-LSO read DMA engine.
1573                  */
1574                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1575         }
1576         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1577         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1578         DELAY(40);
1579
1580         /* Turn on RX data completion state machine */
1581         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1582
1583         /* Turn on RX BD initiator state machine */
1584         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1585
1586         /* Turn on RX data and RX BD initiator state machine */
1587         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1588
1589         /* Turn on send BD completion state machine */
1590         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1591
1592         /* Turn on send data completion state machine */
1593         val = BGE_SDCMODE_ENABLE;
1594         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1595                 val |= BGE_SDCMODE_CDELAY;
1596         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1597
1598         /* Turn on send data initiator state machine */
1599         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1600
1601         /* Turn on send BD initiator state machine */
1602         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1603
1604         /* Turn on send BD selector state machine */
1605         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1606
1607         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1608         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1609             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1610
1611         /* ack/clear link change events */
1612         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1613             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1614             BGE_MACSTAT_LINK_CHANGED);
1615         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1616
1617         /*
1618          * Enable attention when the link has changed state for
1619          * devices that use auto polling.
1620          */
1621         if (sc->bnx_flags & BNX_FLAG_TBI) {
1622                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1623         } else {
1624                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1625                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1626                         DELAY(80);
1627                 }
1628         }
1629
1630         /*
1631          * Clear any pending link state attention.
1632          * Otherwise some link state change events may be lost until attention
1633          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1634          * It's not necessary on newer BCM chips - perhaps enabling link
1635          * state change attentions implies clearing pending attention.
1636          */
1637         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1638             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1639             BGE_MACSTAT_LINK_CHANGED);
1640
1641         /* Enable link state change attentions. */
1642         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1643
1644         return(0);
1645 }
1646
1647 /*
1648  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1649  * against our list and return its name if we find a match. Note
1650  * that since the Broadcom controller contains VPD support, we
1651  * can get the device name string from the controller itself instead
1652  * of the compiled-in string. This is a little slow, but it guarantees
1653  * we'll always announce the right product name.
1654  */
1655 static int
1656 bnx_probe(device_t dev)
1657 {
1658         const struct bnx_type *t;
1659         uint16_t product, vendor;
1660
1661         if (!pci_is_pcie(dev))
1662                 return ENXIO;
1663
1664         product = pci_get_device(dev);
1665         vendor = pci_get_vendor(dev);
1666
1667         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1668                 if (vendor == t->bnx_vid && product == t->bnx_did)
1669                         break;
1670         }
1671         if (t->bnx_name == NULL)
1672                 return ENXIO;
1673
1674         device_set_desc(dev, t->bnx_name);
1675         return 0;
1676 }
1677
1678 static int
1679 bnx_attach(device_t dev)
1680 {
1681         struct ifnet *ifp;
1682         struct bnx_softc *sc;
1683         uint32_t hwcfg = 0, misccfg;
1684         int error = 0, rid, capmask;
1685         uint8_t ether_addr[ETHER_ADDR_LEN];
1686         uint16_t product, vendor;
1687         driver_intr_t *intr_func;
1688         uintptr_t mii_priv = 0;
1689         u_int intr_flags;
1690
1691         sc = device_get_softc(dev);
1692         sc->bnx_dev = dev;
1693         callout_init(&sc->bnx_stat_timer);
1694         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1695
1696         product = pci_get_device(dev);
1697         vendor = pci_get_vendor(dev);
1698
1699 #ifndef BURN_BRIDGES
1700         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1701                 uint32_t irq, mem;
1702
1703                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1704                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1705
1706                 device_printf(dev, "chip is in D%d power mode "
1707                     "-- setting to D0\n", pci_get_powerstate(dev));
1708
1709                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1710
1711                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1712                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1713         }
1714 #endif  /* !BURN_BRIDGE */
1715
1716         /*
1717          * Map control/status registers.
1718          */
1719         pci_enable_busmaster(dev);
1720
1721         rid = BGE_PCI_BAR0;
1722         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1723             RF_ACTIVE);
1724
1725         if (sc->bnx_res == NULL) {
1726                 device_printf(dev, "couldn't map memory\n");
1727                 return ENXIO;
1728         }
1729
1730         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1731         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1732
1733         /* Save various chip information */
1734         sc->bnx_chipid =
1735             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1736             BGE_PCIMISCCTL_ASICREV_SHIFT;
1737         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1738                 /* All chips having dedicated ASICREV register have CPMU */
1739                 sc->bnx_flags |= BNX_FLAG_CPMU;
1740
1741                 switch (product) {
1742                 case PCI_PRODUCT_BROADCOM_BCM5717:
1743                 case PCI_PRODUCT_BROADCOM_BCM5718:
1744                 case PCI_PRODUCT_BROADCOM_BCM5719:
1745                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1746                         sc->bnx_chipid = pci_read_config(dev,
1747                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1748                         break;
1749
1750                 case PCI_PRODUCT_BROADCOM_BCM57761:
1751                 case PCI_PRODUCT_BROADCOM_BCM57765:
1752                 case PCI_PRODUCT_BROADCOM_BCM57781:
1753                 case PCI_PRODUCT_BROADCOM_BCM57785:
1754                 case PCI_PRODUCT_BROADCOM_BCM57791:
1755                 case PCI_PRODUCT_BROADCOM_BCM57795:
1756                         sc->bnx_chipid = pci_read_config(dev,
1757                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1758                         break;
1759
1760                 default:
1761                         sc->bnx_chipid = pci_read_config(dev,
1762                             BGE_PCI_PRODID_ASICREV, 4);
1763                         break;
1764                 }
1765         }
1766         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1767         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1768
1769         switch (sc->bnx_asicrev) {
1770         case BGE_ASICREV_BCM5717:
1771         case BGE_ASICREV_BCM5719:
1772         case BGE_ASICREV_BCM5720:
1773                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1774                 break;
1775
1776         case BGE_ASICREV_BCM57765:
1777                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1778                 break;
1779         }
1780         sc->bnx_flags |= BNX_FLAG_SHORTDMA;
1781
1782         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906)
1783                 sc->bnx_flags |= BNX_FLAG_NO_EEPROM;
1784
1785         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
1786
1787         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1788         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1789             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1790                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1791         else
1792                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1793         device_printf(dev, "CHIP ID 0x%08x; "
1794                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1795                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1796
1797         /*
1798          * Set various PHY quirk flags.
1799          */
1800
1801         capmask = MII_CAPMASK_DEFAULT;
1802         if ((sc->bnx_asicrev == BGE_ASICREV_BCM5703 &&
1803              (misccfg == 0x4000 || misccfg == 0x8000)) ||
1804             (sc->bnx_asicrev == BGE_ASICREV_BCM5705 &&
1805              vendor == PCI_VENDOR_BROADCOM &&
1806              (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
1807               product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
1808               product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
1809             (vendor == PCI_VENDOR_BROADCOM &&
1810              (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
1811               product == PCI_PRODUCT_BROADCOM_BCM5753F ||
1812               product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
1813             product == PCI_PRODUCT_BROADCOM_BCM57790 ||
1814             sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1815                 /* 10/100 only */
1816                 capmask &= ~BMSR_EXTSTAT;
1817         }
1818
1819         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1820
1821         /*
1822          * Allocate interrupt
1823          */
1824         sc->bnx_irq_type = pci_alloc_1intr(dev, bnx_msi_enable, &sc->bnx_irq_rid,
1825             &intr_flags);
1826
1827         sc->bnx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bnx_irq_rid,
1828             intr_flags);
1829         if (sc->bnx_irq == NULL) {
1830                 device_printf(dev, "couldn't map interrupt\n");
1831                 error = ENXIO;
1832                 goto fail;
1833         }
1834
1835         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
1836                 sc->bnx_flags |= BNX_FLAG_ONESHOT_MSI;
1837                 bnx_enable_msi(sc);
1838         }
1839
1840         /* Initialize if_name earlier, so if_printf could be used */
1841         ifp = &sc->arpcom.ac_if;
1842         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1843
1844         /* Try to reset the chip. */
1845         bnx_reset(sc);
1846
1847         if (bnx_chipinit(sc)) {
1848                 device_printf(dev, "chip initialization failed\n");
1849                 error = ENXIO;
1850                 goto fail;
1851         }
1852
1853         /*
1854          * Get station address
1855          */
1856         error = bnx_get_eaddr(sc, ether_addr);
1857         if (error) {
1858                 device_printf(dev, "failed to read station address\n");
1859                 goto fail;
1860         }
1861
1862         if (BNX_IS_57765_PLUS(sc)) {
1863                 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT;
1864         } else {
1865                 /* 5705/5750 limits RX return ring to 512 entries. */
1866                 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1867         }
1868
1869         error = bnx_dma_alloc(sc);
1870         if (error)
1871                 goto fail;
1872
1873         /* Set default tuneable values. */
1874         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
1875         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
1876         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
1877         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
1878         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_DEF;
1879         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_DEF;
1880
1881         /* Set up ifnet structure */
1882         ifp->if_softc = sc;
1883         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1884         ifp->if_ioctl = bnx_ioctl;
1885         ifp->if_start = bnx_start;
1886 #ifdef DEVICE_POLLING
1887         ifp->if_poll = bnx_poll;
1888 #endif
1889         ifp->if_watchdog = bnx_watchdog;
1890         ifp->if_init = bnx_init;
1891         ifp->if_mtu = ETHERMTU;
1892         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1893         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1894         ifq_set_ready(&ifp->if_snd);
1895
1896         ifp->if_capabilities |= IFCAP_HWCSUM;
1897         ifp->if_hwassist = BNX_CSUM_FEATURES;
1898         ifp->if_capenable = ifp->if_capabilities;
1899
1900         /*
1901          * Figure out what sort of media we have by checking the
1902          * hardware config word in the first 32k of NIC internal memory,
1903          * or fall back to examining the EEPROM if necessary.
1904          * Note: on some BCM5700 cards, this value appears to be unset.
1905          * If that's the case, we have to rely on identifying the NIC
1906          * by its PCI subsystem ID, as we do below for the SysKonnect
1907          * SK-9D41.
1908          */
1909         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
1910                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1911         } else {
1912                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1913                                     sizeof(hwcfg))) {
1914                         device_printf(dev, "failed to read EEPROM\n");
1915                         error = ENXIO;
1916                         goto fail;
1917                 }
1918                 hwcfg = ntohl(hwcfg);
1919         }
1920
1921         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1922         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
1923             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1924                 sc->bnx_flags |= BNX_FLAG_TBI;
1925
1926         /* Setup MI MODE */
1927         if (sc->bnx_flags & BNX_FLAG_CPMU)
1928                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
1929         else
1930                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
1931
1932         /* Setup link status update stuffs */
1933         if (sc->bnx_flags & BNX_FLAG_TBI) {
1934                 sc->bnx_link_upd = bnx_tbi_link_upd;
1935                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1936         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1937                 sc->bnx_link_upd = bnx_autopoll_link_upd;
1938                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1939         } else {
1940                 sc->bnx_link_upd = bnx_copper_link_upd;
1941                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1942         }
1943
1944         /* Set default PHY address */
1945         sc->bnx_phyno = 1;
1946
1947         /*
1948          * PHY address mapping for various devices.
1949          *
1950          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
1951          * ---------+-------+-------+-------+-------+
1952          * BCM57XX  |   1   |   X   |   X   |   X   |
1953          * BCM5704  |   1   |   X   |   1   |   X   |
1954          * BCM5717  |   1   |   8   |   2   |   9   |
1955          * BCM5719  |   1   |   8   |   2   |   9   |
1956          * BCM5720  |   1   |   8   |   2   |   9   |
1957          *
1958          * Other addresses may respond but they are not
1959          * IEEE compliant PHYs and should be ignored.
1960          */
1961         if (BNX_IS_5717_PLUS(sc)) {
1962                 int f;
1963
1964                 f = pci_get_function(dev);
1965                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
1966                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
1967                             BGE_SGDIGSTS_IS_SERDES)
1968                                 sc->bnx_phyno = f + 8;
1969                         else
1970                                 sc->bnx_phyno = f + 1;
1971                 } else {
1972                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
1973                             BGE_CPMU_PHY_STRAP_IS_SERDES)
1974                                 sc->bnx_phyno = f + 8;
1975                         else
1976                                 sc->bnx_phyno = f + 1;
1977                 }
1978         }
1979
1980         if (sc->bnx_flags & BNX_FLAG_TBI) {
1981                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
1982                     bnx_ifmedia_upd, bnx_ifmedia_sts);
1983                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1984                 ifmedia_add(&sc->bnx_ifmedia,
1985                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1986                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1987                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
1988                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
1989         } else {
1990                 struct mii_probe_args mii_args;
1991
1992                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
1993                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
1994                 mii_args.mii_capmask = capmask;
1995                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
1996                 mii_args.mii_priv = mii_priv;
1997
1998                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
1999                 if (error) {
2000                         device_printf(dev, "MII without any PHY!\n");
2001                         goto fail;
2002                 }
2003         }
2004
2005         /*
2006          * Create sysctl nodes.
2007          */
2008         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2009         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2010                                               SYSCTL_STATIC_CHILDREN(_hw),
2011                                               OID_AUTO,
2012                                               device_get_nameunit(dev),
2013                                               CTLFLAG_RD, 0, "");
2014         if (sc->bnx_sysctl_tree == NULL) {
2015                 device_printf(dev, "can't add sysctl node\n");
2016                 error = ENXIO;
2017                 goto fail;
2018         }
2019
2020         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2021                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2022                         OID_AUTO, "rx_coal_ticks",
2023                         CTLTYPE_INT | CTLFLAG_RW,
2024                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2025                         "Receive coalescing ticks (usec).");
2026         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2027                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2028                         OID_AUTO, "tx_coal_ticks",
2029                         CTLTYPE_INT | CTLFLAG_RW,
2030                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2031                         "Transmit coalescing ticks (usec).");
2032         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2033                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2034                         OID_AUTO, "rx_coal_bds",
2035                         CTLTYPE_INT | CTLFLAG_RW,
2036                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2037                         "Receive max coalesced BD count.");
2038         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2039                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2040                         OID_AUTO, "tx_coal_bds",
2041                         CTLTYPE_INT | CTLFLAG_RW,
2042                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2043                         "Transmit max coalesced BD count.");
2044         /*
2045          * A common design characteristic for many Broadcom
2046          * client controllers is that they only support a
2047          * single outstanding DMA read operation on the PCIe
2048          * bus. This means that it will take twice as long to
2049          * fetch a TX frame that is split into header and
2050          * payload buffers as it does to fetch a single,
2051          * contiguous TX frame (2 reads vs. 1 read). For these
2052          * controllers, coalescing buffers to reduce the number
2053          * of memory reads is effective way to get maximum
2054          * performance(about 940Mbps).  Without collapsing TX
2055          * buffers the maximum TCP bulk transfer performance
2056          * is about 850Mbps. However forcing coalescing mbufs
2057          * consumes a lot of CPU cycles, so leave it off by
2058          * default.
2059          */
2060         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2061             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2062             "force_defrag", CTLFLAG_RW, &sc->bnx_force_defrag, 0,
2063             "Force defragment on TX path");
2064
2065         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2066             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2067             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2068             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2069             "Receive max coalesced BD count during interrupt.");
2070         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2071             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2072             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2073             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2074             "Transmit max coalesced BD count during interrupt.");
2075
2076         /*
2077          * Call MI attach routine.
2078          */
2079         ether_ifattach(ifp, ether_addr, NULL);
2080
2081         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
2082                 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
2083                         intr_func = bnx_msi_oneshot;
2084                         if (bootverbose)
2085                                 device_printf(dev, "oneshot MSI\n");
2086                 } else {
2087                         intr_func = bnx_msi;
2088                 }
2089         } else {
2090                 intr_func = bnx_intr_legacy;
2091         }
2092         error = bus_setup_intr(dev, sc->bnx_irq, INTR_MPSAFE, intr_func, sc,
2093             &sc->bnx_intrhand, ifp->if_serializer);
2094         if (error) {
2095                 ether_ifdetach(ifp);
2096                 device_printf(dev, "couldn't set up irq\n");
2097                 goto fail;
2098         }
2099
2100         ifp->if_cpuid = rman_get_cpuid(sc->bnx_irq);
2101         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2102
2103         return(0);
2104 fail:
2105         bnx_detach(dev);
2106         return(error);
2107 }
2108
2109 static int
2110 bnx_detach(device_t dev)
2111 {
2112         struct bnx_softc *sc = device_get_softc(dev);
2113
2114         if (device_is_attached(dev)) {
2115                 struct ifnet *ifp = &sc->arpcom.ac_if;
2116
2117                 lwkt_serialize_enter(ifp->if_serializer);
2118                 bnx_stop(sc);
2119                 bnx_reset(sc);
2120                 bus_teardown_intr(dev, sc->bnx_irq, sc->bnx_intrhand);
2121                 lwkt_serialize_exit(ifp->if_serializer);
2122
2123                 ether_ifdetach(ifp);
2124         }
2125
2126         if (sc->bnx_flags & BNX_FLAG_TBI)
2127                 ifmedia_removeall(&sc->bnx_ifmedia);
2128         if (sc->bnx_miibus)
2129                 device_delete_child(dev, sc->bnx_miibus);
2130         bus_generic_detach(dev);
2131
2132         if (sc->bnx_irq != NULL) {
2133                 bus_release_resource(dev, SYS_RES_IRQ, sc->bnx_irq_rid,
2134                     sc->bnx_irq);
2135         }
2136         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI)
2137                 pci_release_msi(dev);
2138
2139         if (sc->bnx_res != NULL) {
2140                 bus_release_resource(dev, SYS_RES_MEMORY,
2141                     BGE_PCI_BAR0, sc->bnx_res);
2142         }
2143
2144         if (sc->bnx_sysctl_tree != NULL)
2145                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2146
2147         bnx_dma_free(sc);
2148
2149         return 0;
2150 }
2151
2152 static void
2153 bnx_reset(struct bnx_softc *sc)
2154 {
2155         device_t dev;
2156         uint32_t cachesize, command, pcistate, reset;
2157         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2158         int i, val = 0;
2159         uint16_t devctl;
2160
2161         dev = sc->bnx_dev;
2162
2163         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
2164                 write_op = bnx_writemem_direct;
2165         else
2166                 write_op = bnx_writereg_ind;
2167
2168         /* Save some important PCI state. */
2169         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2170         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2171         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2172
2173         pci_write_config(dev, BGE_PCI_MISC_CTL,
2174             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2175             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2176             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2177
2178         /* Disable fastboot on controllers that support it. */
2179         if (bootverbose)
2180                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2181         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2182
2183         /*
2184          * Write the magic number to SRAM at offset 0xB50.
2185          * When firmware finishes its initialization it will
2186          * write ~BGE_MAGIC_NUMBER to the same location.
2187          */
2188         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2189
2190         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2191
2192         /* XXX: Broadcom Linux driver. */
2193         /* Force PCI-E 1.0a mode */
2194         if (!BNX_IS_57765_PLUS(sc) &&
2195             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2196             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2197              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2198                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2199                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2200         }
2201         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2202                 /* Prevent PCIE link training during global reset */
2203                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2204                 reset |= (1<<29);
2205         }
2206
2207         /*
2208          * Set GPHY Power Down Override to leave GPHY
2209          * powered up in D0 uninitialized.
2210          */
2211         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2212                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2213
2214         /* Issue global reset */
2215         write_op(sc, BGE_MISC_CFG, reset);
2216
2217         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
2218                 uint32_t status, ctrl;
2219
2220                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2221                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2222                     status | BGE_VCPU_STATUS_DRV_RESET);
2223                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2224                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2225                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2226         }
2227
2228         DELAY(1000);
2229
2230         /* XXX: Broadcom Linux driver. */
2231         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2232                 uint32_t v;
2233
2234                 DELAY(500000); /* wait for link training to complete */
2235                 v = pci_read_config(dev, 0xc4, 4);
2236                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2237         }
2238
2239         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2240
2241         /* Disable no snoop and disable relaxed ordering. */
2242         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2243
2244         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2245         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2246                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2247                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2248         }
2249
2250         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2251             devctl, 2);
2252
2253         /* Clear error status. */
2254         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2255             PCIEM_DEVSTS_CORR_ERR |
2256             PCIEM_DEVSTS_NFATAL_ERR |
2257             PCIEM_DEVSTS_FATAL_ERR |
2258             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2259
2260         /* Reset some of the PCI state that got zapped by reset */
2261         pci_write_config(dev, BGE_PCI_MISC_CTL,
2262             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2263             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2264             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2265         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2266         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2267         write_op(sc, BGE_MISC_CFG, (65 << 1));
2268
2269         /* Enable memory arbiter */
2270         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2271
2272         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
2273                 for (i = 0; i < BNX_TIMEOUT; i++) {
2274                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2275                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2276                                 break;
2277                         DELAY(100);
2278                 }
2279                 if (i == BNX_TIMEOUT) {
2280                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2281                         return;
2282                 }
2283         } else {
2284                 /*
2285                  * Poll until we see the 1's complement of the magic number.
2286                  * This indicates that the firmware initialization
2287                  * is complete.
2288                  */
2289                 for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2290                         val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2291                         if (val == ~BGE_MAGIC_NUMBER)
2292                                 break;
2293                         DELAY(10);
2294                 }
2295                 if (i == BNX_FIRMWARE_TIMEOUT) {
2296                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2297                                   "timed out, found 0x%08x\n", val);
2298                 }
2299
2300                 /* BCM57765 A0 needs additional time before accessing. */
2301                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2302                         DELAY(10 * 1000);
2303         }
2304
2305         /*
2306          * XXX Wait for the value of the PCISTATE register to
2307          * return to its original pre-reset state. This is a
2308          * fairly good indicator of reset completion. If we don't
2309          * wait for the reset to fully complete, trying to read
2310          * from the device's non-PCI registers may yield garbage
2311          * results.
2312          */
2313         for (i = 0; i < BNX_TIMEOUT; i++) {
2314                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2315                         break;
2316                 DELAY(10);
2317         }
2318
2319         /* Fix up byte swapping */
2320         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2321
2322         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2323
2324         /*
2325          * The 5704 in TBI mode apparently needs some special
2326          * adjustment to insure the SERDES drive level is set
2327          * to 1.2V.
2328          */
2329         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2330             (sc->bnx_flags & BNX_FLAG_TBI)) {
2331                 uint32_t serdescfg;
2332
2333                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2334                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2335                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2336         }
2337
2338         /* XXX: Broadcom Linux driver. */
2339         if (!BNX_IS_57765_PLUS(sc)) {
2340                 uint32_t v;
2341
2342                 /* Enable Data FIFO protection. */
2343                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2344                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2345         }
2346
2347         DELAY(10000);
2348
2349         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2350                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2351                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2352         }
2353 }
2354
2355 /*
2356  * Frame reception handling. This is called if there's a frame
2357  * on the receive return list.
2358  *
2359  * Note: we have to be able to handle two possibilities here:
2360  * 1) the frame is from the jumbo recieve ring
2361  * 2) the frame is from the standard receive ring
2362  */
2363
2364 static void
2365 bnx_rxeof(struct bnx_softc *sc, uint16_t rx_prod)
2366 {
2367         struct ifnet *ifp;
2368         int stdcnt = 0, jumbocnt = 0;
2369
2370         ifp = &sc->arpcom.ac_if;
2371
2372         while (sc->bnx_rx_saved_considx != rx_prod) {
2373                 struct bge_rx_bd        *cur_rx;
2374                 uint32_t                rxidx;
2375                 struct mbuf             *m = NULL;
2376                 uint16_t                vlan_tag = 0;
2377                 int                     have_tag = 0;
2378
2379                 cur_rx =
2380             &sc->bnx_ldata.bnx_rx_return_ring[sc->bnx_rx_saved_considx];
2381
2382                 rxidx = cur_rx->bge_idx;
2383                 BNX_INC(sc->bnx_rx_saved_considx, sc->bnx_return_ring_cnt);
2384
2385                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2386                         have_tag = 1;
2387                         vlan_tag = cur_rx->bge_vlan_tag;
2388                 }
2389
2390                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2391                         BNX_INC(sc->bnx_jumbo, BGE_JUMBO_RX_RING_CNT);
2392                         jumbocnt++;
2393
2394                         if (rxidx != sc->bnx_jumbo) {
2395                                 ifp->if_ierrors++;
2396                                 if_printf(ifp, "sw jumbo index(%d) "
2397                                     "and hw jumbo index(%d) mismatch, drop!\n",
2398                                     sc->bnx_jumbo, rxidx);
2399                                 bnx_setup_rxdesc_jumbo(sc, rxidx);
2400                                 continue;
2401                         }
2402
2403                         m = sc->bnx_cdata.bnx_rx_jumbo_chain[rxidx].bnx_mbuf;
2404                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2405                                 ifp->if_ierrors++;
2406                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2407                                 continue;
2408                         }
2409                         if (bnx_newbuf_jumbo(sc, sc->bnx_jumbo, 0)) {
2410                                 ifp->if_ierrors++;
2411                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2412                                 continue;
2413                         }
2414                 } else {
2415                         BNX_INC(sc->bnx_std, BGE_STD_RX_RING_CNT);
2416                         stdcnt++;
2417
2418                         if (rxidx != sc->bnx_std) {
2419                                 ifp->if_ierrors++;
2420                                 if_printf(ifp, "sw std index(%d) "
2421                                     "and hw std index(%d) mismatch, drop!\n",
2422                                     sc->bnx_std, rxidx);
2423                                 bnx_setup_rxdesc_std(sc, rxidx);
2424                                 continue;
2425                         }
2426
2427                         m = sc->bnx_cdata.bnx_rx_std_chain[rxidx].bnx_mbuf;
2428                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2429                                 ifp->if_ierrors++;
2430                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2431                                 continue;
2432                         }
2433                         if (bnx_newbuf_std(sc, sc->bnx_std, 0)) {
2434                                 ifp->if_ierrors++;
2435                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2436                                 continue;
2437                         }
2438                 }
2439
2440                 ifp->if_ipackets++;
2441                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2442                 m->m_pkthdr.rcvif = ifp;
2443
2444                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2445                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2446                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2447                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2448                                 if ((cur_rx->bge_error_flag &
2449                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2450                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2451                         }
2452                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2453                                 m->m_pkthdr.csum_data =
2454                                     cur_rx->bge_tcp_udp_csum;
2455                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2456                                     CSUM_PSEUDO_HDR;
2457                         }
2458                 }
2459
2460                 /*
2461                  * If we received a packet with a vlan tag, pass it
2462                  * to vlan_input() instead of ether_input().
2463                  */
2464                 if (have_tag) {
2465                         m->m_flags |= M_VLANTAG;
2466                         m->m_pkthdr.ether_vlantag = vlan_tag;
2467                         have_tag = vlan_tag = 0;
2468                 }
2469                 ifp->if_input(ifp, m);
2470         }
2471
2472         bnx_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bnx_rx_saved_considx);
2473         if (stdcnt)
2474                 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
2475         if (jumbocnt)
2476                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
2477 }
2478
2479 static void
2480 bnx_txeof(struct bnx_softc *sc, uint16_t tx_cons)
2481 {
2482         struct bge_tx_bd *cur_tx = NULL;
2483         struct ifnet *ifp;
2484
2485         ifp = &sc->arpcom.ac_if;
2486
2487         /*
2488          * Go through our tx ring and free mbufs for those
2489          * frames that have been sent.
2490          */
2491         while (sc->bnx_tx_saved_considx != tx_cons) {
2492                 uint32_t idx = 0;
2493
2494                 idx = sc->bnx_tx_saved_considx;
2495                 cur_tx = &sc->bnx_ldata.bnx_tx_ring[idx];
2496                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2497                         ifp->if_opackets++;
2498                 if (sc->bnx_cdata.bnx_tx_chain[idx] != NULL) {
2499                         bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
2500                             sc->bnx_cdata.bnx_tx_dmamap[idx]);
2501                         m_freem(sc->bnx_cdata.bnx_tx_chain[idx]);
2502                         sc->bnx_cdata.bnx_tx_chain[idx] = NULL;
2503                 }
2504                 sc->bnx_txcnt--;
2505                 BNX_INC(sc->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2506         }
2507
2508         if (cur_tx != NULL &&
2509             (BGE_TX_RING_CNT - sc->bnx_txcnt) >=
2510             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2511                 ifp->if_flags &= ~IFF_OACTIVE;
2512
2513         if (sc->bnx_txcnt == 0)
2514                 ifp->if_timer = 0;
2515
2516         if (!ifq_is_empty(&ifp->if_snd))
2517                 if_devstart(ifp);
2518 }
2519
2520 #ifdef DEVICE_POLLING
2521
2522 static void
2523 bnx_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2524 {
2525         struct bnx_softc *sc = ifp->if_softc;
2526         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2527         uint16_t rx_prod, tx_cons;
2528
2529         switch(cmd) {
2530         case POLL_REGISTER:
2531                 bnx_disable_intr(sc);
2532                 break;
2533         case POLL_DEREGISTER:
2534                 bnx_enable_intr(sc);
2535                 break;
2536         case POLL_AND_CHECK_STATUS:
2537                 /*
2538                  * Process link state changes.
2539                  */
2540                 bnx_link_poll(sc);
2541                 /* Fall through */
2542         case POLL_ONLY:
2543                 sc->bnx_status_tag = sblk->bge_status_tag;
2544                 /*
2545                  * Use a load fence to ensure that status_tag
2546                  * is saved  before rx_prod and tx_cons.
2547                  */
2548                 cpu_lfence();
2549
2550                 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2551                 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2552                 if (ifp->if_flags & IFF_RUNNING) {
2553                         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2554                         if (sc->bnx_rx_saved_considx != rx_prod)
2555                                 bnx_rxeof(sc, rx_prod);
2556
2557                         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2558                         if (sc->bnx_tx_saved_considx != tx_cons)
2559                                 bnx_txeof(sc, tx_cons);
2560                 }
2561                 break;
2562         }
2563 }
2564
2565 #endif
2566
2567 static void
2568 bnx_intr_legacy(void *xsc)
2569 {
2570         struct bnx_softc *sc = xsc;
2571         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2572
2573         if (sc->bnx_status_tag == sblk->bge_status_tag) {
2574                 uint32_t val;
2575
2576                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
2577                 if (val & BGE_PCISTAT_INTR_NOTACT)
2578                         return;
2579         }
2580
2581         /*
2582          * NOTE:
2583          * Interrupt will have to be disabled if tagged status
2584          * is used, else interrupt will always be asserted on
2585          * certain chips (at least on BCM5750 AX/BX).
2586          */
2587         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2588
2589         bnx_intr(sc);
2590 }
2591
2592 static void
2593 bnx_msi(void *xsc)
2594 {
2595         struct bnx_softc *sc = xsc;
2596
2597         /* Disable interrupt first */
2598         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2599         bnx_intr(sc);
2600 }
2601
2602 static void
2603 bnx_msi_oneshot(void *xsc)
2604 {
2605         bnx_intr(xsc);
2606 }
2607
2608 static void
2609 bnx_intr(struct bnx_softc *sc)
2610 {
2611         struct ifnet *ifp = &sc->arpcom.ac_if;
2612         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2613         uint16_t rx_prod, tx_cons;
2614         uint32_t status;
2615
2616         sc->bnx_status_tag = sblk->bge_status_tag;
2617         /*
2618          * Use a load fence to ensure that status_tag is saved
2619          * before rx_prod, tx_cons and status.
2620          */
2621         cpu_lfence();
2622
2623         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2624         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2625         status = sblk->bge_status;
2626
2627         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2628                 bnx_link_poll(sc);
2629
2630         if (ifp->if_flags & IFF_RUNNING) {
2631                 if (sc->bnx_rx_saved_considx != rx_prod)
2632                         bnx_rxeof(sc, rx_prod);
2633
2634                 if (sc->bnx_tx_saved_considx != tx_cons)
2635                         bnx_txeof(sc, tx_cons);
2636         }
2637
2638         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
2639
2640         if (sc->bnx_coal_chg)
2641                 bnx_coal_change(sc);
2642 }
2643
2644 static void
2645 bnx_tick(void *xsc)
2646 {
2647         struct bnx_softc *sc = xsc;
2648         struct ifnet *ifp = &sc->arpcom.ac_if;
2649
2650         lwkt_serialize_enter(ifp->if_serializer);
2651
2652         bnx_stats_update_regs(sc);
2653
2654         if (sc->bnx_flags & BNX_FLAG_TBI) {
2655                 /*
2656                  * Since in TBI mode auto-polling can't be used we should poll
2657                  * link status manually. Here we register pending link event
2658                  * and trigger interrupt.
2659                  */
2660                 sc->bnx_link_evt++;
2661                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2662         } else if (!sc->bnx_link) {
2663                 mii_tick(device_get_softc(sc->bnx_miibus));
2664         }
2665
2666         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
2667
2668         lwkt_serialize_exit(ifp->if_serializer);
2669 }
2670
2671 static void
2672 bnx_stats_update_regs(struct bnx_softc *sc)
2673 {
2674         struct ifnet *ifp = &sc->arpcom.ac_if;
2675         struct bge_mac_stats_regs stats;
2676         uint32_t *s;
2677         int i;
2678
2679         s = (uint32_t *)&stats;
2680         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2681                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2682                 s++;
2683         }
2684
2685         ifp->if_collisions +=
2686            (stats.dot3StatsSingleCollisionFrames +
2687            stats.dot3StatsMultipleCollisionFrames +
2688            stats.dot3StatsExcessiveCollisions +
2689            stats.dot3StatsLateCollisions) -
2690            ifp->if_collisions;
2691 }
2692
2693 /*
2694  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2695  * pointers to descriptors.
2696  */
2697 static int
2698 bnx_encap(struct bnx_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2699 {
2700         struct bge_tx_bd *d = NULL;
2701         uint16_t csum_flags = 0;
2702         bus_dma_segment_t segs[BNX_NSEG_NEW];
2703         bus_dmamap_t map;
2704         int error, maxsegs, nsegs, idx, i;
2705         struct mbuf *m_head = *m_head0, *m_new;
2706
2707         if (m_head->m_pkthdr.csum_flags) {
2708                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2709                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2710                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2711                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2712                 if (m_head->m_flags & M_LASTFRAG)
2713                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2714                 else if (m_head->m_flags & M_FRAG)
2715                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2716         }
2717
2718         idx = *txidx;
2719         map = sc->bnx_cdata.bnx_tx_dmamap[idx];
2720
2721         maxsegs = (BGE_TX_RING_CNT - sc->bnx_txcnt) - BNX_NSEG_RSVD;
2722         KASSERT(maxsegs >= BNX_NSEG_SPARE,
2723                 ("not enough segments %d", maxsegs));
2724
2725         if (maxsegs > BNX_NSEG_NEW)
2726                 maxsegs = BNX_NSEG_NEW;
2727
2728         /*
2729          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
2730          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
2731          * but when such padded frames employ the bge IP/TCP checksum
2732          * offload, the hardware checksum assist gives incorrect results
2733          * (possibly from incorporating its own padding into the UDP/TCP
2734          * checksum; who knows).  If we pad such runts with zeros, the
2735          * onboard checksum comes out correct.
2736          */
2737         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2738             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
2739                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
2740                 if (error)
2741                         goto back;
2742         }
2743
2744         if ((sc->bnx_flags & BNX_FLAG_SHORTDMA) && m_head->m_next != NULL) {
2745                 m_new = bnx_defrag_shortdma(m_head);
2746                 if (m_new == NULL) {
2747                         error = ENOBUFS;
2748                         goto back;
2749                 }
2750                 *m_head0 = m_head = m_new;
2751         }
2752         if (sc->bnx_force_defrag && m_head->m_next != NULL) {
2753                 /*
2754                  * Forcefully defragment mbuf chain to overcome hardware
2755                  * limitation which only support a single outstanding
2756                  * DMA read operation.  If it fails, keep moving on using
2757                  * the original mbuf chain.
2758                  */
2759                 m_new = m_defrag(m_head, MB_DONTWAIT);
2760                 if (m_new != NULL)
2761                         *m_head0 = m_head = m_new;
2762         }
2763
2764         error = bus_dmamap_load_mbuf_defrag(sc->bnx_cdata.bnx_tx_mtag, map,
2765                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2766         if (error)
2767                 goto back;
2768
2769         m_head = *m_head0;
2770         bus_dmamap_sync(sc->bnx_cdata.bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2771
2772         for (i = 0; ; i++) {
2773                 d = &sc->bnx_ldata.bnx_tx_ring[idx];
2774
2775                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2776                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2777                 d->bge_len = segs[i].ds_len;
2778                 d->bge_flags = csum_flags;
2779
2780                 if (i == nsegs - 1)
2781                         break;
2782                 BNX_INC(idx, BGE_TX_RING_CNT);
2783         }
2784         /* Mark the last segment as end of packet... */
2785         d->bge_flags |= BGE_TXBDFLAG_END;
2786
2787         /* Set vlan tag to the first segment of the packet. */
2788         d = &sc->bnx_ldata.bnx_tx_ring[*txidx];
2789         if (m_head->m_flags & M_VLANTAG) {
2790                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2791                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2792         } else {
2793                 d->bge_vlan_tag = 0;
2794         }
2795
2796         /*
2797          * Insure that the map for this transmission is placed at
2798          * the array index of the last descriptor in this chain.
2799          */
2800         sc->bnx_cdata.bnx_tx_dmamap[*txidx] = sc->bnx_cdata.bnx_tx_dmamap[idx];
2801         sc->bnx_cdata.bnx_tx_dmamap[idx] = map;
2802         sc->bnx_cdata.bnx_tx_chain[idx] = m_head;
2803         sc->bnx_txcnt += nsegs;
2804
2805         BNX_INC(idx, BGE_TX_RING_CNT);
2806         *txidx = idx;
2807 back:
2808         if (error) {
2809                 m_freem(*m_head0);
2810                 *m_head0 = NULL;
2811         }
2812         return error;
2813 }
2814
2815 /*
2816  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2817  * to the mbuf data regions directly in the transmit descriptors.
2818  */
2819 static void
2820 bnx_start(struct ifnet *ifp)
2821 {
2822         struct bnx_softc *sc = ifp->if_softc;
2823         struct mbuf *m_head = NULL;
2824         uint32_t prodidx;
2825         int need_trans;
2826
2827         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2828                 return;
2829
2830         prodidx = sc->bnx_tx_prodidx;
2831
2832         need_trans = 0;
2833         while (sc->bnx_cdata.bnx_tx_chain[prodidx] == NULL) {
2834                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2835                 if (m_head == NULL)
2836                         break;
2837
2838                 /*
2839                  * XXX
2840                  * The code inside the if() block is never reached since we
2841                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2842                  * requests to checksum TCP/UDP in a fragmented packet.
2843                  *
2844                  * XXX
2845                  * safety overkill.  If this is a fragmented packet chain
2846                  * with delayed TCP/UDP checksums, then only encapsulate
2847                  * it if we have enough descriptors to handle the entire
2848                  * chain at once.
2849                  * (paranoia -- may not actually be needed)
2850                  */
2851                 if ((m_head->m_flags & M_FIRSTFRAG) &&
2852                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
2853                         if ((BGE_TX_RING_CNT - sc->bnx_txcnt) <
2854                             m_head->m_pkthdr.csum_data + BNX_NSEG_RSVD) {
2855                                 ifp->if_flags |= IFF_OACTIVE;
2856                                 ifq_prepend(&ifp->if_snd, m_head);
2857                                 break;
2858                         }
2859                 }
2860
2861                 /*
2862                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2863                  * descriptors of the end of the ring.  Also make
2864                  * sure there are BGE_NSEG_SPARE descriptors for
2865                  * jumbo buffers' defragmentation.
2866                  */
2867                 if ((BGE_TX_RING_CNT - sc->bnx_txcnt) <
2868                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
2869                         ifp->if_flags |= IFF_OACTIVE;
2870                         ifq_prepend(&ifp->if_snd, m_head);
2871                         break;
2872                 }
2873
2874                 /*
2875                  * Pack the data into the transmit ring. If we
2876                  * don't have room, set the OACTIVE flag and wait
2877                  * for the NIC to drain the ring.
2878                  */
2879                 if (bnx_encap(sc, &m_head, &prodidx)) {
2880                         ifp->if_flags |= IFF_OACTIVE;
2881                         ifp->if_oerrors++;
2882                         break;
2883                 }
2884                 need_trans = 1;
2885
2886                 ETHER_BPF_MTAP(ifp, m_head);
2887         }
2888
2889         if (!need_trans)
2890                 return;
2891
2892         /* Transmit */
2893         bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2894
2895         sc->bnx_tx_prodidx = prodidx;
2896
2897         /*
2898          * Set a timeout in case the chip goes out to lunch.
2899          */
2900         ifp->if_timer = 5;
2901 }
2902
2903 static void
2904 bnx_init(void *xsc)
2905 {
2906         struct bnx_softc *sc = xsc;
2907         struct ifnet *ifp = &sc->arpcom.ac_if;
2908         uint16_t *m;
2909         uint32_t mode;
2910
2911         ASSERT_SERIALIZED(ifp->if_serializer);
2912
2913         /* Cancel pending I/O and flush buffers. */
2914         bnx_stop(sc);
2915         bnx_reset(sc);
2916         bnx_chipinit(sc);
2917
2918         /*
2919          * Init the various state machines, ring
2920          * control blocks and firmware.
2921          */
2922         if (bnx_blockinit(sc)) {
2923                 if_printf(ifp, "initialization failure\n");
2924                 bnx_stop(sc);
2925                 return;
2926         }
2927
2928         /* Specify MTU. */
2929         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2930             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2931
2932         /* Load our MAC address. */
2933         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2934         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2935         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2936
2937         /* Enable or disable promiscuous mode as needed. */
2938         bnx_setpromisc(sc);
2939
2940         /* Program multicast filter. */
2941         bnx_setmulti(sc);
2942
2943         /* Init RX ring. */
2944         if (bnx_init_rx_ring_std(sc)) {
2945                 if_printf(ifp, "RX ring initialization failed\n");
2946                 bnx_stop(sc);
2947                 return;
2948         }
2949
2950         /* Init jumbo RX ring. */
2951         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
2952                 if (bnx_init_rx_ring_jumbo(sc)) {
2953                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
2954                         bnx_stop(sc);
2955                         return;
2956                 }
2957         }
2958
2959         /* Init our RX return ring index */
2960         sc->bnx_rx_saved_considx = 0;
2961
2962         /* Init TX ring. */
2963         bnx_init_tx_ring(sc);
2964
2965         /* Enable TX MAC state machine lockup fix. */
2966         mode = CSR_READ_4(sc, BGE_TX_MODE);
2967         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
2968         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2969                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
2970                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
2971                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
2972         }
2973         /* Turn on transmitter */
2974         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
2975
2976         /* Turn on receiver */
2977         BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2978
2979         /*
2980          * Set the number of good frames to receive after RX MBUF
2981          * Low Watermark has been reached.  After the RX MAC receives
2982          * this number of frames, it will drop subsequent incoming
2983          * frames until the MBUF High Watermark is reached.
2984          */
2985         if (sc->bnx_asicrev == BGE_ASICREV_BCM57765)
2986                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
2987         else
2988                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
2989
2990         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
2991                 if (bootverbose) {
2992                         if_printf(ifp, "MSI_MODE: %#x\n",
2993                             CSR_READ_4(sc, BGE_MSI_MODE));
2994                 }
2995         }
2996
2997         /* Tell firmware we're alive. */
2998         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2999
3000         /* Enable host interrupts if polling(4) is not enabled. */
3001         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3002 #ifdef DEVICE_POLLING
3003         if (ifp->if_flags & IFF_POLLING)
3004                 bnx_disable_intr(sc);
3005         else
3006 #endif
3007         bnx_enable_intr(sc);
3008
3009         bnx_ifmedia_upd(ifp);
3010
3011         ifp->if_flags |= IFF_RUNNING;
3012         ifp->if_flags &= ~IFF_OACTIVE;
3013
3014         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
3015 }
3016
3017 /*
3018  * Set media options.
3019  */
3020 static int
3021 bnx_ifmedia_upd(struct ifnet *ifp)
3022 {
3023         struct bnx_softc *sc = ifp->if_softc;
3024
3025         /* If this is a 1000baseX NIC, enable the TBI port. */
3026         if (sc->bnx_flags & BNX_FLAG_TBI) {
3027                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3028
3029                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3030                         return(EINVAL);
3031
3032                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3033                 case IFM_AUTO:
3034                         break;
3035
3036                 case IFM_1000_SX:
3037                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3038                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3039                                     BGE_MACMODE_HALF_DUPLEX);
3040                         } else {
3041                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3042                                     BGE_MACMODE_HALF_DUPLEX);
3043                         }
3044                         break;
3045                 default:
3046                         return(EINVAL);
3047                 }
3048         } else {
3049                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3050
3051                 sc->bnx_link_evt++;
3052                 sc->bnx_link = 0;
3053                 if (mii->mii_instance) {
3054                         struct mii_softc *miisc;
3055
3056                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3057                                 mii_phy_reset(miisc);
3058                 }
3059                 mii_mediachg(mii);
3060
3061                 /*
3062                  * Force an interrupt so that we will call bnx_link_upd
3063                  * if needed and clear any pending link state attention.
3064                  * Without this we are not getting any further interrupts
3065                  * for link state changes and thus will not UP the link and
3066                  * not be able to send in bnx_start.  The only way to get
3067                  * things working was to receive a packet and get an RX
3068                  * intr.
3069                  *
3070                  * bnx_tick should help for fiber cards and we might not
3071                  * need to do this here if BNX_FLAG_TBI is set but as
3072                  * we poll for fiber anyway it should not harm.
3073                  */
3074                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3075         }
3076         return(0);
3077 }
3078
3079 /*
3080  * Report current media status.
3081  */
3082 static void
3083 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3084 {
3085         struct bnx_softc *sc = ifp->if_softc;
3086
3087         if (sc->bnx_flags & BNX_FLAG_TBI) {
3088                 ifmr->ifm_status = IFM_AVALID;
3089                 ifmr->ifm_active = IFM_ETHER;
3090                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3091                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3092                         ifmr->ifm_status |= IFM_ACTIVE;
3093                 } else {
3094                         ifmr->ifm_active |= IFM_NONE;
3095                         return;
3096                 }
3097
3098                 ifmr->ifm_active |= IFM_1000_SX;
3099                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3100                         ifmr->ifm_active |= IFM_HDX;
3101                 else
3102                         ifmr->ifm_active |= IFM_FDX;
3103         } else {
3104                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3105
3106                 mii_pollstat(mii);
3107                 ifmr->ifm_active = mii->mii_media_active;
3108                 ifmr->ifm_status = mii->mii_media_status;
3109         }
3110 }
3111
3112 static int
3113 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3114 {
3115         struct bnx_softc *sc = ifp->if_softc;
3116         struct ifreq *ifr = (struct ifreq *)data;
3117         int mask, error = 0;
3118
3119         ASSERT_SERIALIZED(ifp->if_serializer);
3120
3121         switch (command) {
3122         case SIOCSIFMTU:
3123                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3124                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3125                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3126                         error = EINVAL;
3127                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3128                         ifp->if_mtu = ifr->ifr_mtu;
3129                         if (ifp->if_flags & IFF_RUNNING)
3130                                 bnx_init(sc);
3131                 }
3132                 break;
3133         case SIOCSIFFLAGS:
3134                 if (ifp->if_flags & IFF_UP) {
3135                         if (ifp->if_flags & IFF_RUNNING) {
3136                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3137
3138                                 /*
3139                                  * If only the state of the PROMISC flag
3140                                  * changed, then just use the 'set promisc
3141                                  * mode' command instead of reinitializing
3142                                  * the entire NIC. Doing a full re-init
3143                                  * means reloading the firmware and waiting
3144                                  * for it to start up, which may take a
3145                                  * second or two.  Similarly for ALLMULTI.
3146                                  */
3147                                 if (mask & IFF_PROMISC)
3148                                         bnx_setpromisc(sc);
3149                                 if (mask & IFF_ALLMULTI)
3150                                         bnx_setmulti(sc);
3151                         } else {
3152                                 bnx_init(sc);
3153                         }
3154                 } else if (ifp->if_flags & IFF_RUNNING) {
3155                         bnx_stop(sc);
3156                 }
3157                 sc->bnx_if_flags = ifp->if_flags;
3158                 break;
3159         case SIOCADDMULTI:
3160         case SIOCDELMULTI:
3161                 if (ifp->if_flags & IFF_RUNNING)
3162                         bnx_setmulti(sc);
3163                 break;
3164         case SIOCSIFMEDIA:
3165         case SIOCGIFMEDIA:
3166                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3167                         error = ifmedia_ioctl(ifp, ifr,
3168                             &sc->bnx_ifmedia, command);
3169                 } else {
3170                         struct mii_data *mii;
3171
3172                         mii = device_get_softc(sc->bnx_miibus);
3173                         error = ifmedia_ioctl(ifp, ifr,
3174                                               &mii->mii_media, command);
3175                 }
3176                 break;
3177         case SIOCSIFCAP:
3178                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3179                 if (mask & IFCAP_HWCSUM) {
3180                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3181                         if (IFCAP_HWCSUM & ifp->if_capenable)
3182                                 ifp->if_hwassist = BNX_CSUM_FEATURES;
3183                         else
3184                                 ifp->if_hwassist = 0;
3185                 }
3186                 break;
3187         default:
3188                 error = ether_ioctl(ifp, command, data);
3189                 break;
3190         }
3191         return error;
3192 }
3193
3194 static void
3195 bnx_watchdog(struct ifnet *ifp)
3196 {
3197         struct bnx_softc *sc = ifp->if_softc;
3198
3199         if_printf(ifp, "watchdog timeout -- resetting\n");
3200
3201         bnx_init(sc);
3202
3203         ifp->if_oerrors++;
3204
3205         if (!ifq_is_empty(&ifp->if_snd))
3206                 if_devstart(ifp);
3207 }
3208
3209 /*
3210  * Stop the adapter and free any mbufs allocated to the
3211  * RX and TX lists.
3212  */
3213 static void
3214 bnx_stop(struct bnx_softc *sc)
3215 {
3216         struct ifnet *ifp = &sc->arpcom.ac_if;
3217
3218         ASSERT_SERIALIZED(ifp->if_serializer);
3219
3220         callout_stop(&sc->bnx_stat_timer);
3221
3222         /*
3223          * Disable all of the receiver blocks
3224          */
3225         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3226         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3227         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3228         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3229         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3230         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3231
3232         /*
3233          * Disable all of the transmit blocks
3234          */
3235         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3236         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3237         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3238         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3239         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3240         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3241
3242         /*
3243          * Shut down all of the memory managers and related
3244          * state machines.
3245          */
3246         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3247         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3248         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3249         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3250
3251         /* Disable host interrupts. */
3252         bnx_disable_intr(sc);
3253
3254         /*
3255          * Tell firmware we're shutting down.
3256          */
3257         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3258
3259         /* Free the RX lists. */
3260         bnx_free_rx_ring_std(sc);
3261
3262         /* Free jumbo RX list. */
3263         if (BNX_IS_JUMBO_CAPABLE(sc))
3264                 bnx_free_rx_ring_jumbo(sc);
3265
3266         /* Free TX buffers. */
3267         bnx_free_tx_ring(sc);
3268
3269         sc->bnx_status_tag = 0;
3270         sc->bnx_link = 0;
3271         sc->bnx_coal_chg = 0;
3272
3273         sc->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
3274
3275         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3276         ifp->if_timer = 0;
3277 }
3278
3279 /*
3280  * Stop all chip I/O so that the kernel's probe routines don't
3281  * get confused by errant DMAs when rebooting.
3282  */
3283 static void
3284 bnx_shutdown(device_t dev)
3285 {
3286         struct bnx_softc *sc = device_get_softc(dev);
3287         struct ifnet *ifp = &sc->arpcom.ac_if;
3288
3289         lwkt_serialize_enter(ifp->if_serializer);
3290         bnx_stop(sc);
3291         bnx_reset(sc);
3292         lwkt_serialize_exit(ifp->if_serializer);
3293 }
3294
3295 static int
3296 bnx_suspend(device_t dev)
3297 {
3298         struct bnx_softc *sc = device_get_softc(dev);
3299         struct ifnet *ifp = &sc->arpcom.ac_if;
3300
3301         lwkt_serialize_enter(ifp->if_serializer);
3302         bnx_stop(sc);
3303         lwkt_serialize_exit(ifp->if_serializer);
3304
3305         return 0;
3306 }
3307
3308 static int
3309 bnx_resume(device_t dev)
3310 {
3311         struct bnx_softc *sc = device_get_softc(dev);
3312         struct ifnet *ifp = &sc->arpcom.ac_if;
3313
3314         lwkt_serialize_enter(ifp->if_serializer);
3315
3316         if (ifp->if_flags & IFF_UP) {
3317                 bnx_init(sc);
3318
3319                 if (!ifq_is_empty(&ifp->if_snd))
3320                         if_devstart(ifp);
3321         }
3322
3323         lwkt_serialize_exit(ifp->if_serializer);
3324
3325         return 0;
3326 }
3327
3328 static void
3329 bnx_setpromisc(struct bnx_softc *sc)
3330 {
3331         struct ifnet *ifp = &sc->arpcom.ac_if;
3332
3333         if (ifp->if_flags & IFF_PROMISC)
3334                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3335         else
3336                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3337 }
3338
3339 static void
3340 bnx_dma_free(struct bnx_softc *sc)
3341 {
3342         int i;
3343
3344         /* Destroy RX mbuf DMA stuffs. */
3345         if (sc->bnx_cdata.bnx_rx_mtag != NULL) {
3346                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3347                         bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3348                             sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3349                 }
3350                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3351                                    sc->bnx_cdata.bnx_rx_tmpmap);
3352                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3353         }
3354
3355         /* Destroy TX mbuf DMA stuffs. */
3356         if (sc->bnx_cdata.bnx_tx_mtag != NULL) {
3357                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3358                         bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3359                             sc->bnx_cdata.bnx_tx_dmamap[i]);
3360                 }
3361                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3362         }
3363
3364         /* Destroy standard RX ring */
3365         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_std_ring_tag,
3366                            sc->bnx_cdata.bnx_rx_std_ring_map,
3367                            sc->bnx_ldata.bnx_rx_std_ring);
3368
3369         if (BNX_IS_JUMBO_CAPABLE(sc))
3370                 bnx_free_jumbo_mem(sc);
3371
3372         /* Destroy RX return ring */
3373         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_return_ring_tag,
3374                            sc->bnx_cdata.bnx_rx_return_ring_map,
3375                            sc->bnx_ldata.bnx_rx_return_ring);
3376
3377         /* Destroy TX ring */
3378         bnx_dma_block_free(sc->bnx_cdata.bnx_tx_ring_tag,
3379                            sc->bnx_cdata.bnx_tx_ring_map,
3380                            sc->bnx_ldata.bnx_tx_ring);
3381
3382         /* Destroy status block */
3383         bnx_dma_block_free(sc->bnx_cdata.bnx_status_tag,
3384                            sc->bnx_cdata.bnx_status_map,
3385                            sc->bnx_ldata.bnx_status_block);
3386
3387         /* Destroy the parent tag */
3388         if (sc->bnx_cdata.bnx_parent_tag != NULL)
3389                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3390 }
3391
3392 static int
3393 bnx_dma_alloc(struct bnx_softc *sc)
3394 {
3395         struct ifnet *ifp = &sc->arpcom.ac_if;
3396         int i, error;
3397
3398         /*
3399          * Allocate the parent bus DMA tag appropriate for PCI.
3400          *
3401          * All of the NetExtreme/NetLink controllers have 4GB boundary
3402          * DMA bug.
3403          * Whenever an address crosses a multiple of the 4GB boundary
3404          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3405          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3406          * state machine will lockup and cause the device to hang.
3407          */
3408         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3409                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3410                                    NULL, NULL,
3411                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3412                                    BUS_SPACE_MAXSIZE_32BIT,
3413                                    0, &sc->bnx_cdata.bnx_parent_tag);
3414         if (error) {
3415                 if_printf(ifp, "could not allocate parent dma tag\n");
3416                 return error;
3417         }
3418
3419         /*
3420          * Create DMA tag and maps for RX mbufs.
3421          */
3422         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3423                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3424                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3425                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3426                                    &sc->bnx_cdata.bnx_rx_mtag);
3427         if (error) {
3428                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3429                 return error;
3430         }
3431
3432         error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3433                                   BUS_DMA_WAITOK, &sc->bnx_cdata.bnx_rx_tmpmap);
3434         if (error) {
3435                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3436                 sc->bnx_cdata.bnx_rx_mtag = NULL;
3437                 return error;
3438         }
3439
3440         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3441                 error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3442                                           BUS_DMA_WAITOK,
3443                                           &sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3444                 if (error) {
3445                         int j;
3446
3447                         for (j = 0; j < i; ++j) {
3448                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3449                                         sc->bnx_cdata.bnx_rx_std_dmamap[j]);
3450                         }
3451                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3452                         sc->bnx_cdata.bnx_rx_mtag = NULL;
3453
3454                         if_printf(ifp, "could not create DMA map for RX\n");
3455                         return error;
3456                 }
3457         }
3458
3459         /*
3460          * Create DMA tag and maps for TX mbufs.
3461          */
3462         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3463                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3464                                    NULL, NULL,
3465                                    BNX_JUMBO_FRAMELEN, BNX_NSEG_NEW, MCLBYTES,
3466                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3467                                    BUS_DMA_ONEBPAGE,
3468                                    &sc->bnx_cdata.bnx_tx_mtag);
3469         if (error) {
3470                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3471                 return error;
3472         }
3473
3474         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3475                 error = bus_dmamap_create(sc->bnx_cdata.bnx_tx_mtag,
3476                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3477                                           &sc->bnx_cdata.bnx_tx_dmamap[i]);
3478                 if (error) {
3479                         int j;
3480
3481                         for (j = 0; j < i; ++j) {
3482                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3483                                         sc->bnx_cdata.bnx_tx_dmamap[j]);
3484                         }
3485                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3486                         sc->bnx_cdata.bnx_tx_mtag = NULL;
3487
3488                         if_printf(ifp, "could not create DMA map for TX\n");
3489                         return error;
3490                 }
3491         }
3492
3493         /*
3494          * Create DMA stuffs for standard RX ring.
3495          */
3496         error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3497                                     &sc->bnx_cdata.bnx_rx_std_ring_tag,
3498                                     &sc->bnx_cdata.bnx_rx_std_ring_map,
3499                                     (void *)&sc->bnx_ldata.bnx_rx_std_ring,
3500                                     &sc->bnx_ldata.bnx_rx_std_ring_paddr);
3501         if (error) {
3502                 if_printf(ifp, "could not create std RX ring\n");
3503                 return error;
3504         }
3505
3506         /*
3507          * Create jumbo buffer pool.
3508          */
3509         if (BNX_IS_JUMBO_CAPABLE(sc)) {
3510                 error = bnx_alloc_jumbo_mem(sc);
3511                 if (error) {
3512                         if_printf(ifp, "could not create jumbo buffer pool\n");
3513                         return error;
3514                 }
3515         }
3516
3517         /*
3518          * Create DMA stuffs for RX return ring.
3519          */
3520         error = bnx_dma_block_alloc(sc,
3521             BGE_RX_RTN_RING_SZ(sc->bnx_return_ring_cnt),
3522             &sc->bnx_cdata.bnx_rx_return_ring_tag,
3523             &sc->bnx_cdata.bnx_rx_return_ring_map,
3524             (void *)&sc->bnx_ldata.bnx_rx_return_ring,
3525             &sc->bnx_ldata.bnx_rx_return_ring_paddr);
3526         if (error) {
3527                 if_printf(ifp, "could not create RX ret ring\n");
3528                 return error;
3529         }
3530
3531         /*
3532          * Create DMA stuffs for TX ring.
3533          */
3534         error = bnx_dma_block_alloc(sc, BGE_TX_RING_SZ,
3535                                     &sc->bnx_cdata.bnx_tx_ring_tag,
3536                                     &sc->bnx_cdata.bnx_tx_ring_map,
3537                                     (void *)&sc->bnx_ldata.bnx_tx_ring,
3538                                     &sc->bnx_ldata.bnx_tx_ring_paddr);
3539         if (error) {
3540                 if_printf(ifp, "could not create TX ring\n");
3541                 return error;
3542         }
3543
3544         /*
3545          * Create DMA stuffs for status block.
3546          */
3547         error = bnx_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3548                                     &sc->bnx_cdata.bnx_status_tag,
3549                                     &sc->bnx_cdata.bnx_status_map,
3550                                     (void *)&sc->bnx_ldata.bnx_status_block,
3551                                     &sc->bnx_ldata.bnx_status_block_paddr);
3552         if (error) {
3553                 if_printf(ifp, "could not create status block\n");
3554                 return error;
3555         }
3556
3557         return 0;
3558 }
3559
3560 static int
3561 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3562                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3563 {
3564         bus_dmamem_t dmem;
3565         int error;
3566
3567         error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
3568                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3569                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3570         if (error)
3571                 return error;
3572
3573         *tag = dmem.dmem_tag;
3574         *map = dmem.dmem_map;
3575         *addr = dmem.dmem_addr;
3576         *paddr = dmem.dmem_busaddr;
3577
3578         return 0;
3579 }
3580
3581 static void
3582 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3583 {
3584         if (tag != NULL) {
3585                 bus_dmamap_unload(tag, map);
3586                 bus_dmamem_free(tag, addr, map);
3587                 bus_dma_tag_destroy(tag);
3588         }
3589 }
3590
3591 static void
3592 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
3593 {
3594         struct ifnet *ifp = &sc->arpcom.ac_if;
3595
3596 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3597
3598         /*
3599          * Sometimes PCS encoding errors are detected in
3600          * TBI mode (on fiber NICs), and for some reason
3601          * the chip will signal them as link changes.
3602          * If we get a link change event, but the 'PCS
3603          * encoding error' bit in the MAC status register
3604          * is set, don't bother doing a link check.
3605          * This avoids spurious "gigabit link up" messages
3606          * that sometimes appear on fiber NICs during
3607          * periods of heavy traffic.
3608          */
3609         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3610                 if (!sc->bnx_link) {
3611                         sc->bnx_link++;
3612                         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
3613                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3614                                     BGE_MACMODE_TBI_SEND_CFGS);
3615                         }
3616                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3617
3618                         if (bootverbose)
3619                                 if_printf(ifp, "link UP\n");
3620
3621                         ifp->if_link_state = LINK_STATE_UP;
3622                         if_link_state_change(ifp);
3623                 }
3624         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3625                 if (sc->bnx_link) {
3626                         sc->bnx_link = 0;
3627
3628                         if (bootverbose)
3629                                 if_printf(ifp, "link DOWN\n");
3630
3631                         ifp->if_link_state = LINK_STATE_DOWN;
3632                         if_link_state_change(ifp);
3633                 }
3634         }
3635
3636 #undef PCS_ENCODE_ERR
3637
3638         /* Clear the attention. */
3639         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3640             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3641             BGE_MACSTAT_LINK_CHANGED);
3642 }
3643
3644 static void
3645 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3646 {
3647         struct ifnet *ifp = &sc->arpcom.ac_if;
3648         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3649
3650         mii_pollstat(mii);
3651         bnx_miibus_statchg(sc->bnx_dev);
3652
3653         if (bootverbose) {
3654                 if (sc->bnx_link)
3655                         if_printf(ifp, "link UP\n");
3656                 else
3657                         if_printf(ifp, "link DOWN\n");
3658         }
3659
3660         /* Clear the attention. */
3661         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3662             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3663             BGE_MACSTAT_LINK_CHANGED);
3664 }
3665
3666 static void
3667 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3668 {
3669         struct ifnet *ifp = &sc->arpcom.ac_if;
3670         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3671
3672         mii_pollstat(mii);
3673
3674         if (!sc->bnx_link &&
3675             (mii->mii_media_status & IFM_ACTIVE) &&
3676             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3677                 sc->bnx_link++;
3678                 if (bootverbose)
3679                         if_printf(ifp, "link UP\n");
3680         } else if (sc->bnx_link &&
3681             (!(mii->mii_media_status & IFM_ACTIVE) ||
3682             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3683                 sc->bnx_link = 0;
3684                 if (bootverbose)
3685                         if_printf(ifp, "link DOWN\n");
3686         }
3687
3688         /* Clear the attention. */
3689         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3690             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3691             BGE_MACSTAT_LINK_CHANGED);
3692 }
3693
3694 static int
3695 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3696 {
3697         struct bnx_softc *sc = arg1;
3698
3699         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3700             &sc->bnx_rx_coal_ticks,
3701             BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
3702             BNX_RX_COAL_TICKS_CHG);
3703 }
3704
3705 static int
3706 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3707 {
3708         struct bnx_softc *sc = arg1;
3709
3710         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3711             &sc->bnx_tx_coal_ticks,
3712             BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
3713             BNX_TX_COAL_TICKS_CHG);
3714 }
3715
3716 static int
3717 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
3718 {
3719         struct bnx_softc *sc = arg1;
3720
3721         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3722             &sc->bnx_rx_coal_bds,
3723             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3724             BNX_RX_COAL_BDS_CHG);
3725 }
3726
3727 static int
3728 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
3729 {
3730         struct bnx_softc *sc = arg1;
3731
3732         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3733             &sc->bnx_tx_coal_bds,
3734             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3735             BNX_TX_COAL_BDS_CHG);
3736 }
3737
3738 static int
3739 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3740 {
3741         struct bnx_softc *sc = arg1;
3742
3743         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3744             &sc->bnx_rx_coal_bds_int,
3745             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3746             BNX_RX_COAL_BDS_INT_CHG);
3747 }
3748
3749 static int
3750 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3751 {
3752         struct bnx_softc *sc = arg1;
3753
3754         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3755             &sc->bnx_tx_coal_bds_int,
3756             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3757             BNX_TX_COAL_BDS_INT_CHG);
3758 }
3759
3760 static int
3761 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3762     int coal_min, int coal_max, uint32_t coal_chg_mask)
3763 {
3764         struct bnx_softc *sc = arg1;
3765         struct ifnet *ifp = &sc->arpcom.ac_if;
3766         int error = 0, v;
3767
3768         lwkt_serialize_enter(ifp->if_serializer);
3769
3770         v = *coal;
3771         error = sysctl_handle_int(oidp, &v, 0, req);
3772         if (!error && req->newptr != NULL) {
3773                 if (v < coal_min || v > coal_max) {
3774                         error = EINVAL;
3775                 } else {
3776                         *coal = v;
3777                         sc->bnx_coal_chg |= coal_chg_mask;
3778                 }
3779         }
3780
3781         lwkt_serialize_exit(ifp->if_serializer);
3782         return error;
3783 }
3784
3785 static void
3786 bnx_coal_change(struct bnx_softc *sc)
3787 {
3788         struct ifnet *ifp = &sc->arpcom.ac_if;
3789         uint32_t val;
3790
3791         ASSERT_SERIALIZED(ifp->if_serializer);
3792
3793         if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
3794                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3795                             sc->bnx_rx_coal_ticks);
3796                 DELAY(10);
3797                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3798
3799                 if (bootverbose) {
3800                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3801                                   sc->bnx_rx_coal_ticks);
3802                 }
3803         }
3804
3805         if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
3806                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3807                             sc->bnx_tx_coal_ticks);
3808                 DELAY(10);
3809                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3810
3811                 if (bootverbose) {
3812                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3813                                   sc->bnx_tx_coal_ticks);
3814                 }
3815         }
3816
3817         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
3818                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3819                             sc->bnx_rx_coal_bds);
3820                 DELAY(10);
3821                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3822
3823                 if (bootverbose) {
3824                         if_printf(ifp, "rx_coal_bds -> %u\n",
3825                                   sc->bnx_rx_coal_bds);
3826                 }
3827         }
3828
3829         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
3830                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3831                             sc->bnx_tx_coal_bds);
3832                 DELAY(10);
3833                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3834
3835                 if (bootverbose) {
3836                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
3837                                   sc->bnx_tx_coal_bds);
3838                 }
3839         }
3840
3841         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
3842                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
3843                     sc->bnx_rx_coal_bds_int);
3844                 DELAY(10);
3845                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
3846
3847                 if (bootverbose) {
3848                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
3849                             sc->bnx_rx_coal_bds_int);
3850                 }
3851         }
3852
3853         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
3854                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
3855                     sc->bnx_tx_coal_bds_int);
3856                 DELAY(10);
3857                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
3858
3859                 if (bootverbose) {
3860                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
3861                             sc->bnx_tx_coal_bds_int);
3862                 }
3863         }
3864
3865         sc->bnx_coal_chg = 0;
3866 }
3867
3868 static void
3869 bnx_enable_intr(struct bnx_softc *sc)
3870 {
3871         struct ifnet *ifp = &sc->arpcom.ac_if;
3872
3873         lwkt_serialize_handler_enable(ifp->if_serializer);
3874
3875         /*
3876          * Enable interrupt.
3877          */
3878         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3879         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
3880                 /* XXX Linux driver */
3881                 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3882         }
3883
3884         /*
3885          * Unmask the interrupt when we stop polling.
3886          */
3887         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3888             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3889
3890         /*
3891          * Trigger another interrupt, since above writing
3892          * to interrupt mailbox0 may acknowledge pending
3893          * interrupt.
3894          */
3895         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3896 }
3897
3898 static void
3899 bnx_disable_intr(struct bnx_softc *sc)
3900 {
3901         struct ifnet *ifp = &sc->arpcom.ac_if;
3902
3903         /*
3904          * Mask the interrupt when we start polling.
3905          */
3906         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3907             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3908
3909         /*
3910          * Acknowledge possible asserted interrupt.
3911          */
3912         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3913
3914         lwkt_serialize_handler_disable(ifp->if_serializer);
3915 }
3916
3917 static int
3918 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
3919 {
3920         uint32_t mac_addr;
3921         int ret = 1;
3922
3923         mac_addr = bnx_readmem_ind(sc, 0x0c14);
3924         if ((mac_addr >> 16) == 0x484b) {
3925                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
3926                 ether_addr[1] = (uint8_t)mac_addr;
3927                 mac_addr = bnx_readmem_ind(sc, 0x0c18);
3928                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
3929                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
3930                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
3931                 ether_addr[5] = (uint8_t)mac_addr;
3932                 ret = 0;
3933         }
3934         return ret;
3935 }
3936
3937 static int
3938 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
3939 {
3940         int mac_offset = BGE_EE_MAC_OFFSET;
3941
3942         if (BNX_IS_5717_PLUS(sc)) {
3943                 int f;
3944
3945                 f = pci_get_function(sc->bnx_dev);
3946                 if (f & 1)
3947                         mac_offset = BGE_EE_MAC_OFFSET_5717;
3948                 if (f > 1)
3949                         mac_offset += BGE_EE_MAC_OFFSET_5717_OFF;
3950         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
3951                 mac_offset = BGE_EE_MAC_OFFSET_5906;
3952         }
3953
3954         return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
3955 }
3956
3957 static int
3958 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[])
3959 {
3960         if (sc->bnx_flags & BNX_FLAG_NO_EEPROM)
3961                 return 1;
3962
3963         return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
3964                                ETHER_ADDR_LEN);
3965 }
3966
3967 static int
3968 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[])
3969 {
3970         static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = {
3971                 /* NOTE: Order is critical */
3972                 bnx_get_eaddr_mem,
3973                 bnx_get_eaddr_nvram,
3974                 bnx_get_eaddr_eeprom,
3975                 NULL
3976         };
3977         const bnx_eaddr_fcn_t *func;
3978
3979         for (func = bnx_eaddr_funcs; *func != NULL; ++func) {
3980                 if ((*func)(sc, eaddr) == 0)
3981                         break;
3982         }
3983         return (*func == NULL ? ENXIO : 0);
3984 }
3985
3986 /*
3987  * NOTE: 'm' is not freed upon failure
3988  */
3989 struct mbuf *
3990 bnx_defrag_shortdma(struct mbuf *m)
3991 {
3992         struct mbuf *n;
3993         int found;
3994
3995         /*
3996          * If device receive two back-to-back send BDs with less than
3997          * or equal to 8 total bytes then the device may hang.  The two
3998          * back-to-back send BDs must in the same frame for this failure
3999          * to occur.  Scan mbuf chains and see whether two back-to-back
4000          * send BDs are there.  If this is the case, allocate new mbuf
4001          * and copy the frame to workaround the silicon bug.
4002          */
4003         for (n = m, found = 0; n != NULL; n = n->m_next) {
4004                 if (n->m_len < 8) {
4005                         found++;
4006                         if (found > 1)
4007                                 break;
4008                         continue;
4009                 }
4010                 found = 0;
4011         }
4012
4013         if (found > 1)
4014                 n = m_defrag(m, MB_DONTWAIT);
4015         else
4016                 n = m;
4017         return n;
4018 }
4019
4020 static void
4021 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)
4022 {
4023         int i;
4024
4025         BNX_CLRBIT(sc, reg, bit);
4026         for (i = 0; i < BNX_TIMEOUT; i++) {
4027                 if ((CSR_READ_4(sc, reg) & bit) == 0)
4028                         return;
4029                 DELAY(100);
4030         }
4031 }
4032
4033 static void
4034 bnx_link_poll(struct bnx_softc *sc)
4035 {
4036         uint32_t status;
4037
4038         status = CSR_READ_4(sc, BGE_MAC_STS);
4039         if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) {
4040                 sc->bnx_link_evt = 0;
4041                 sc->bnx_link_upd(sc, status);
4042         }
4043 }
4044
4045 static void
4046 bnx_enable_msi(struct bnx_softc *sc)
4047 {
4048         uint32_t msi_mode;
4049
4050         msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4051         msi_mode |= BGE_MSIMODE_ENABLE;
4052         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4053                 /*
4054                  * NOTE:
4055                  * 5718-PG105-R says that "one shot" mode
4056                  * does not work if MSI is used, however,
4057                  * it obviously works.
4058                  */
4059                 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4060         }
4061         CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4062 }
4063
4064 static uint32_t
4065 bnx_dma_swap_options(struct bnx_softc *sc)
4066 {
4067         uint32_t dma_options;
4068
4069         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
4070             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
4071 #if BYTE_ORDER == BIG_ENDIAN
4072         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
4073 #endif
4074         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
4075                 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
4076                     BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
4077                     BGE_MODECTL_HTX2B_ENABLE;
4078         }
4079         return dma_options;
4080 }