2 * Copyright 1996 Massachusetts Institute of Technology
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5 * its documentation for any purpose and without fee is hereby
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29 * $FreeBSD: src/sys/i386/i386/perfmon.c,v 1.21 1999/09/25 18:24:04 phk Exp $
30 * $DragonFly: src/sys/platform/pc32/i386/perfmon.c,v 1.11 2008/05/10 17:24:07 dillon Exp $
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/device.h>
38 #include <sys/fcntl.h>
42 #include <machine/cputypes.h>
44 #include <machine/clock.h>
45 #include <machine/perfmon.h>
47 static int perfmon_inuse;
48 static int perfmon_cpuok;
50 static int msr_ctl[NPMC];
52 static int msr_pmc[NPMC];
53 static unsigned int ctl_shadow[NPMC];
54 static quad_t pmc_shadow[NPMC]; /* used when ctr is stopped on P5 */
55 static int (*writectl)(int);
57 static int writectl5(int);
58 static int writectl6(int);
61 static d_close_t perfmon_close;
62 static d_open_t perfmon_open;
63 static d_ioctl_t perfmon_ioctl;
65 #define CDEV_MAJOR 2 /* We're really a minor of mem.c */
66 static struct dev_ops perfmon_ops = {
67 { "perfmon", CDEV_MAJOR, 0 },
68 .d_open = perfmon_open,
69 .d_close = perfmon_close,
70 .d_ioctl = perfmon_ioctl,
74 * Initialize the device ops for user access to the perfmon. This must
75 * be done late in the boot sequence.
77 * NOTE: The perfmon is really a minor of the mem major. Perfmon
81 perfmon_driver_init(void *unused __unused)
83 make_dev(&perfmon_ops, 32, UID_ROOT, GID_KMEM, 0640, "perfmon");
86 SYSINIT(perfmondrv, SI_SUB_DRIVERS, SI_ORDER_ANY, perfmon_driver_init, NULL)
89 * This is called in early boot, after cpu_class has been set up.
102 writectl = writectl5;
110 writectl = writectl6;
123 return perfmon_cpuok;
127 perfmon_setup(int pmc, unsigned int control)
129 if (pmc < 0 || pmc >= NPMC)
132 perfmon_inuse |= (1 << pmc);
133 control &= ~(PMCF_SYS_FLAGS << 16);
134 mpintr_lock(); /* doesn't have to be mpintr_lock YYY */
135 ctl_shadow[pmc] = control;
137 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
143 perfmon_get(int pmc, unsigned int *control)
145 if (pmc < 0 || pmc >= NPMC)
148 if (perfmon_inuse & (1 << pmc)) {
149 *control = ctl_shadow[pmc];
152 return EBUSY; /* XXX reversed sense */
156 perfmon_fini(int pmc)
158 if (pmc < 0 || pmc >= NPMC)
161 if (perfmon_inuse & (1 << pmc)) {
164 perfmon_inuse &= ~(1 << pmc);
167 return EBUSY; /* XXX reversed sense */
171 perfmon_start(int pmc)
173 if (pmc < 0 || pmc >= NPMC)
176 if (perfmon_inuse & (1 << pmc)) {
177 mpintr_lock(); /* doesn't have to be mpintr YYY */
178 ctl_shadow[pmc] |= (PMCF_EN << 16);
179 wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
188 perfmon_stop(int pmc)
190 if (pmc < 0 || pmc >= NPMC)
193 if (perfmon_inuse & (1 << pmc)) {
195 pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
196 ctl_shadow[pmc] &= ~(PMCF_EN << 16);
205 perfmon_read(int pmc, quad_t *val)
207 if (pmc < 0 || pmc >= NPMC)
210 if (perfmon_inuse & (1 << pmc)) {
211 if (ctl_shadow[pmc] & (PMCF_EN << 16))
212 *val = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
214 *val = pmc_shadow[pmc];
222 perfmon_reset(int pmc)
224 if (pmc < 0 || pmc >= NPMC)
227 if (perfmon_inuse & (1 << pmc)) {
228 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
236 * Unfortunately, the performance-monitoring registers are laid out
237 * differently in the P5 and P6. We keep everything in P6 format
238 * internally (except for the event code), and convert to P5
239 * format as needed on those CPUs. The writectl function pointer
240 * is set up to point to one of these functions by perfmon_init().
245 if (pmc > 0 && !(ctl_shadow[pmc] & (PMCF_EN << 16))) {
246 wrmsr(msr_ctl[pmc], 0);
248 wrmsr(msr_ctl[pmc], ctl_shadow[pmc]);
253 #define P5FLAG_P 0x200
254 #define P5FLAG_E 0x100
255 #define P5FLAG_USR 0x80
256 #define P5FLAG_OS 0x40
263 if (ctl_shadow[1] & (PMCF_EN << 16)) {
264 if (ctl_shadow[1] & (PMCF_USR << 16))
265 newval |= P5FLAG_USR << 16;
266 if (ctl_shadow[1] & (PMCF_OS << 16))
267 newval |= P5FLAG_OS << 16;
268 if (!(ctl_shadow[1] & (PMCF_E << 16)))
269 newval |= P5FLAG_E << 16;
270 newval |= (ctl_shadow[1] & 0x3f) << 16;
272 if (ctl_shadow[0] & (PMCF_EN << 16)) {
273 if (ctl_shadow[0] & (PMCF_USR << 16))
274 newval |= P5FLAG_USR;
275 if (ctl_shadow[0] & (PMCF_OS << 16))
277 if (!(ctl_shadow[0] & (PMCF_E << 16)))
279 newval |= ctl_shadow[0] & 0x3f;
282 wrmsr(msr_ctl[0], newval);
283 return 0; /* XXX should check for unimplemented bits */
288 * Now the user-mode interface, called from a subdevice of mem.c.
291 static int writerpmc;
294 perfmon_open(struct dev_open_args *ap)
299 if (ap->a_oflags & FWRITE) {
311 perfmon_close(struct dev_close_args *ap)
313 if (ap->a_fflag & FWRITE) {
316 for (i = 0; i < NPMC; i++) {
317 if (writerpmc & (1 << i))
326 perfmon_ioctl(struct dev_ioctl_args *ap)
328 caddr_t param = ap->a_data;
330 struct pmc_data *pmcd;
331 struct pmc_tstamp *pmct;
337 if (!(ap->a_fflag & FWRITE))
339 pmc = (struct pmc *)param;
341 rv = perfmon_setup(pmc->pmc_num, pmc->pmc_val);
343 writerpmc |= (1 << pmc->pmc_num);
348 pmc = (struct pmc *)param;
349 rv = perfmon_get(pmc->pmc_num, &pmc->pmc_val);
353 if (!(ap->a_fflag & FWRITE))
357 rv = perfmon_start(*ip);
361 if (!(ap->a_fflag & FWRITE))
365 rv = perfmon_stop(*ip);
369 if (!(ap->a_fflag & FWRITE))
373 rv = perfmon_reset(*ip);
377 pmcd = (struct pmc_data *)param;
378 rv = perfmon_read(pmcd->pmcd_num, &pmcd->pmcd_value);
382 if (tsc_frequency == 0) {
386 pmct = (struct pmc_tstamp *)param;
387 /* XXX interface loses precision. */
388 pmct->pmct_rate = (int)(tsc_frequency / 1000000);
389 pmct->pmct_value = rdtsc();