2 * Core routines and tables shareable across OS platforms.
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
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38 * POSSIBILITY OF SUCH DAMAGES.
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
42 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.111 2007/04/19 18:53:52 scottl Exp $
43 * $DragonFly: src/sys/dev/disk/aic7xxx/aic7xxx.c,v 1.29 2008/05/18 20:30:21 pavalos Exp $
46 #include "aic7xxx_osm.h"
47 #include "aic7xxx_inline.h"
48 #include "aicasm/aicasm_insformat.h"
50 /****************************** Softc Data ************************************/
51 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
53 /***************************** Lookup Tables **********************************/
54 char *ahc_chip_names[] =
71 static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names);
74 * Hardware error codes.
76 struct ahc_hard_error_entry {
81 static struct ahc_hard_error_entry ahc_hard_errors[] = {
82 { ILLHADDR, "Illegal Host Access" },
83 { ILLSADDR, "Illegal Sequencer Address referenced" },
84 { ILLOPCODE, "Illegal Opcode in sequencer program" },
85 { SQPARERR, "Sequencer Parity Error" },
86 { DPARERR, "Data-path Parity Error" },
87 { MPARERR, "Scratch or SCB Memory Parity Error" },
88 { PCIERRSTAT, "PCI Error detected" },
89 { CIOPARERR, "CIOBUS Parity Error" },
91 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
93 static struct ahc_phase_table_entry ahc_phase_table[] =
95 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
96 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
97 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
98 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
99 { P_COMMAND, MSG_NOOP, "in Command phase" },
100 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
101 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
102 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
103 { P_BUSFREE, MSG_NOOP, "while idle" },
104 { 0, MSG_NOOP, "in unknown phase" }
108 * In most cases we only wish to itterate over real phases, so
109 * exclude the last element from the count.
111 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
114 * Valid SCSIRATE values. (p. 3-17)
115 * Provides a mapping of tranfer periods in ns to the proper value to
116 * stick in the scsixfer reg.
118 static struct ahc_syncrate ahc_syncrates[] =
120 /* ultra2 fast/ultra period rate */
121 { 0x42, 0x000, 9, "80.0" },
122 { 0x03, 0x000, 10, "40.0" },
123 { 0x04, 0x000, 11, "33.0" },
124 { 0x05, 0x100, 12, "20.0" },
125 { 0x06, 0x110, 15, "16.0" },
126 { 0x07, 0x120, 18, "13.4" },
127 { 0x08, 0x000, 25, "10.0" },
128 { 0x19, 0x010, 31, "8.0" },
129 { 0x1a, 0x020, 37, "6.67" },
130 { 0x1b, 0x030, 43, "5.7" },
131 { 0x1c, 0x040, 50, "5.0" },
132 { 0x00, 0x050, 56, "4.4" },
133 { 0x00, 0x060, 62, "4.0" },
134 { 0x00, 0x070, 68, "3.6" },
135 { 0x00, 0x000, 0, NULL }
138 /* Our Sequencer Program */
139 #include "aic7xxx_seq.h"
141 /**************************** Function Declarations ***************************/
142 static void ahc_force_renegotiation(struct ahc_softc *ahc,
143 struct ahc_devinfo *devinfo);
144 static struct ahc_tmode_tstate*
145 ahc_alloc_tstate(struct ahc_softc *ahc,
146 u_int scsi_id, char channel);
147 #ifdef AHC_TARGET_MODE
148 static void ahc_free_tstate(struct ahc_softc *ahc,
149 u_int scsi_id, char channel, int force);
151 static struct ahc_syncrate*
152 ahc_devlimited_syncrate(struct ahc_softc *ahc,
153 struct ahc_initiator_tinfo *,
157 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
158 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
159 struct ahc_devinfo *devinfo);
160 static void ahc_scb_devinfo(struct ahc_softc *ahc,
161 struct ahc_devinfo *devinfo,
163 static void ahc_assert_atn(struct ahc_softc *ahc);
164 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
165 struct ahc_devinfo *devinfo,
167 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
168 struct ahc_devinfo *devinfo);
169 static void ahc_construct_sdtr(struct ahc_softc *ahc,
170 struct ahc_devinfo *devinfo,
171 u_int period, u_int offset);
172 static void ahc_construct_wdtr(struct ahc_softc *ahc,
173 struct ahc_devinfo *devinfo,
175 static void ahc_construct_ppr(struct ahc_softc *ahc,
176 struct ahc_devinfo *devinfo,
177 u_int period, u_int offset,
178 u_int bus_width, u_int ppr_options);
179 static void ahc_clear_msg_state(struct ahc_softc *ahc);
180 static void ahc_handle_proto_violation(struct ahc_softc *ahc);
181 static void ahc_handle_message_phase(struct ahc_softc *ahc);
187 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
188 u_int msgval, int full);
189 static int ahc_parse_msg(struct ahc_softc *ahc,
190 struct ahc_devinfo *devinfo);
191 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
192 struct ahc_devinfo *devinfo);
193 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
194 struct ahc_devinfo *devinfo);
195 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
196 static void ahc_handle_devreset(struct ahc_softc *ahc,
197 struct ahc_devinfo *devinfo,
198 cam_status status, char *message,
200 #ifdef AHC_TARGET_MODE
201 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
202 struct ahc_devinfo *devinfo,
206 static bus_dmamap_callback_t ahc_dmamap_cb;
207 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
208 static int ahc_init_scbdata(struct ahc_softc *ahc);
209 static void ahc_fini_scbdata(struct ahc_softc *ahc);
210 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
211 struct scb *prev_scb,
213 static int ahc_qinfifo_count(struct ahc_softc *ahc);
214 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
215 u_int prev, u_int scbptr);
216 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
217 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
218 u_int scbpos, u_int prev);
219 static void ahc_reset_current_bus(struct ahc_softc *ahc);
221 static void ahc_dumpseq(struct ahc_softc *ahc);
223 static int ahc_loadseq(struct ahc_softc *ahc);
224 static int ahc_check_patch(struct ahc_softc *ahc,
225 struct patch **start_patch,
226 u_int start_instr, u_int *skip_addr);
227 static void ahc_download_instr(struct ahc_softc *ahc,
228 u_int instrptr, uint8_t *dconsts);
229 static int ahc_other_scb_timeout(struct ahc_softc *ahc,
231 struct scb *other_scb);
232 #ifdef AHC_TARGET_MODE
233 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
234 struct ahc_tmode_lstate *lstate,
238 static void ahc_update_scsiid(struct ahc_softc *ahc,
240 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
241 struct target_cmd *cmd);
243 /************************* Sequencer Execution Control ************************/
245 * Restart the sequencer program from address zero
248 ahc_restart(struct ahc_softc *ahc)
253 /* No more pending messages. */
254 ahc_clear_msg_state(ahc);
256 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
257 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
258 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
259 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
260 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
261 ahc_outb(ahc, SAVED_LUN, 0xFF);
264 * Ensure that the sequencer's idea of TQINPOS
265 * matches our own. The sequencer increments TQINPOS
266 * only after it sees a DMA complete and a reset could
267 * occur before the increment leaving the kernel to believe
268 * the command arrived but the sequencer to not.
270 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
272 /* Always allow reselection */
273 ahc_outb(ahc, SCSISEQ,
274 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
275 if ((ahc->features & AHC_CMD_CHAN) != 0) {
276 /* Ensure that no DMA operations are in progress */
277 ahc_outb(ahc, CCSCBCNT, 0);
278 ahc_outb(ahc, CCSGCTL, 0);
279 ahc_outb(ahc, CCSCBCTL, 0);
282 * If we were in the process of DMA'ing SCB data into
283 * an SCB, replace that SCB on the free list. This prevents
286 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
287 ahc_add_curscb_to_free_list(ahc);
288 ahc_outb(ahc, SEQ_FLAGS2,
289 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
293 * Clear any pending sequencer interrupt. It is no
294 * longer relevant since we're resetting the Program
297 ahc_outb(ahc, CLRINT, CLRSEQINT);
299 ahc_outb(ahc, MWI_RESIDUAL, 0);
300 ahc_outb(ahc, SEQCTL, ahc->seqctl);
301 ahc_outb(ahc, SEQADDR0, 0);
302 ahc_outb(ahc, SEQADDR1, 0);
307 /************************* Input/Output Queues ********************************/
309 ahc_run_qoutfifo(struct ahc_softc *ahc)
314 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
315 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
317 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
318 if ((ahc->qoutfifonext & 0x03) == 0x03) {
322 * Clear 32bits of QOUTFIFO at a time
323 * so that we don't clobber an incoming
324 * byte DMA to the array on architectures
325 * that only support 32bit load and store
328 modnext = ahc->qoutfifonext & ~0x3;
329 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
330 aic_dmamap_sync(ahc, ahc->shared_data_dmat,
331 ahc->shared_data_dmamap,
332 /*offset*/modnext, /*len*/4,
333 BUS_DMASYNC_PREREAD);
337 scb = ahc_lookup_scb(ahc, scb_index);
339 kprintf("%s: WARNING no command for scb %d "
340 "(cmdcmplt)\nQOUTPOS = %d\n",
341 ahc_name(ahc), scb_index,
342 (ahc->qoutfifonext - 1) & 0xFF);
347 * Save off the residual
350 ahc_update_residual(ahc, scb);
356 ahc_run_untagged_queues(struct ahc_softc *ahc)
360 for (i = 0; i < 16; i++)
361 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
365 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
369 if (ahc->untagged_queue_lock != 0)
372 if ((scb = TAILQ_FIRST(queue)) != NULL
373 && (scb->flags & SCB_ACTIVE) == 0) {
374 scb->flags |= SCB_ACTIVE;
376 * Timers are disabled while recovery is in progress.
378 aic_scb_timer_start(scb);
379 ahc_queue_scb(ahc, scb);
383 /************************* Interrupt Handling *********************************/
385 ahc_handle_brkadrint(struct ahc_softc *ahc)
388 * We upset the sequencer :-(
389 * Lookup the error message
394 error = ahc_inb(ahc, ERROR);
395 for (i = 0; error != 1 && i < num_errors; i++)
397 kprintf("%s: brkadrint, %s at seqaddr = 0x%x\n",
398 ahc_name(ahc), ahc_hard_errors[i].errmesg,
399 ahc_inb(ahc, SEQADDR0) |
400 (ahc_inb(ahc, SEQADDR1) << 8));
402 ahc_dump_card_state(ahc);
404 /* Tell everyone that this HBA is no longer available */
405 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
406 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
409 /* Disable all interrupt sources by resetting the controller */
414 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
417 struct ahc_devinfo devinfo;
419 ahc_fetch_devinfo(ahc, &devinfo);
422 * Clear the upper byte that holds SEQINT status
423 * codes and clear the SEQINT bit. We will unpause
424 * the sequencer, if appropriate, after servicing
427 ahc_outb(ahc, CLRINT, CLRSEQINT);
428 switch (intstat & SEQINT_MASK) {
432 struct hardware_scb *hscb;
435 * Set the default return value to 0 (don't
436 * send sense). The sense code will change
439 ahc_outb(ahc, RETURN_1, 0);
442 * The sequencer will notify us when a command
443 * has an error that would be of interest to
444 * the kernel. This allows us to leave the sequencer
445 * running in the common case of command completes
446 * without error. The sequencer will already have
447 * dma'd the SCB back up to us, so we can reference
448 * the in kernel copy directly.
450 scb_index = ahc_inb(ahc, SCB_TAG);
451 scb = ahc_lookup_scb(ahc, scb_index);
453 ahc_print_devinfo(ahc, &devinfo);
454 kprintf("ahc_intr - referenced scb "
455 "not valid during seqint 0x%x scb(%d)\n",
457 ahc_dump_card_state(ahc);
464 /* Don't want to clobber the original sense code */
465 if ((scb->flags & SCB_SENSE) != 0) {
467 * Clear the SCB_SENSE Flag and have
468 * the sequencer do a normal command
471 scb->flags &= ~SCB_SENSE;
472 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
475 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
476 /* Freeze the queue until the client sees the error. */
477 ahc_freeze_devq(ahc, scb);
479 aic_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
480 switch (hscb->shared_data.status.scsi_status) {
482 kprintf("%s: Interrupted for staus of 0???\n",
485 case SCSI_STATUS_CMD_TERMINATED:
486 case SCSI_STATUS_CHECK_COND:
488 struct ahc_dma_seg *sg;
489 struct scsi_sense *sc;
490 struct ahc_initiator_tinfo *targ_info;
491 struct ahc_tmode_tstate *tstate;
492 struct ahc_transinfo *tinfo;
494 if (ahc_debug & AHC_SHOW_SENSE) {
495 ahc_print_path(ahc, scb);
496 kprintf("SCB %d: requests Check Status\n",
501 if (aic_perform_autosense(scb) == 0)
504 targ_info = ahc_fetch_transinfo(ahc,
509 tinfo = &targ_info->curr;
511 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
513 * Save off the residual if there is one.
515 ahc_update_residual(ahc, scb);
517 if (ahc_debug & AHC_SHOW_SENSE) {
518 ahc_print_path(ahc, scb);
519 kprintf("Sending Sense\n");
522 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
523 sg->len = aic_get_sense_bufsize(ahc, scb);
524 sg->len |= AHC_DMA_LAST_SEG;
526 /* Fixup byte order */
527 sg->addr = aic_htole32(sg->addr);
528 sg->len = aic_htole32(sg->len);
530 sc->opcode = REQUEST_SENSE;
532 if (tinfo->protocol_version <= SCSI_REV_2
533 && SCB_GET_LUN(scb) < 8)
534 sc->byte2 = SCB_GET_LUN(scb) << 5;
537 sc->length = sg->len;
541 * We can't allow the target to disconnect.
542 * This will be an untagged transaction and
543 * having the target disconnect will make this
544 * transaction indestinguishable from outstanding
545 * tagged transactions.
550 * This request sense could be because the
551 * the device lost power or in some other
552 * way has lost our transfer negotiations.
553 * Renegotiate if appropriate. Unit attention
554 * errors will be reported before any data
557 if (aic_get_residual(scb)
558 == aic_get_transfer_length(scb)) {
559 ahc_update_neg_request(ahc, &devinfo,
561 AHC_NEG_IF_NON_ASYNC);
563 if (tstate->auto_negotiate & devinfo.target_mask) {
564 hscb->control |= MK_MESSAGE;
565 scb->flags &= ~SCB_NEGOTIATE;
566 scb->flags |= SCB_AUTO_NEGOTIATE;
568 hscb->cdb_len = sizeof(*sc);
569 hscb->dataptr = sg->addr;
570 hscb->datacnt = sg->len;
571 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
572 hscb->sgptr = aic_htole32(hscb->sgptr);
574 scb->flags |= SCB_SENSE;
575 ahc_qinfifo_requeue_tail(ahc, scb);
576 ahc_outb(ahc, RETURN_1, SEND_SENSE);
578 * Ensure we have enough time to actually
579 * retrieve the sense, but only schedule
580 * the timer if we are not in recovery or
581 * this is a recovery SCB that is allowed
582 * to have an active timer.
584 if (ahc->scb_data->recovery_scbs == 0
585 || (scb->flags & SCB_RECOVERY_SCB) != 0)
586 aic_scb_timer_reset(scb, 5 * 1000);
596 /* Ensure we don't leave the selection hardware on */
597 ahc_outb(ahc, SCSISEQ,
598 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
600 kprintf("%s:%c:%d: no active SCB for reconnecting "
601 "target - issuing BUS DEVICE RESET\n",
602 ahc_name(ahc), devinfo.channel, devinfo.target);
603 kprintf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
604 "ARG_1 == 0x%x ACCUM = 0x%x\n",
605 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
606 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
607 kprintf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
609 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
610 ahc_index_busy_tcl(ahc,
611 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
612 ahc_inb(ahc, SAVED_LUN))),
613 ahc_inb(ahc, SINDEX));
614 kprintf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
615 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
616 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
617 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
618 ahc_inb(ahc, SCB_CONTROL));
619 kprintf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
620 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
621 kprintf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
622 kprintf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
623 ahc_dump_card_state(ahc);
624 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
626 ahc->msgout_index = 0;
627 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
628 ahc_outb(ahc, MSG_OUT, HOST_MSG);
634 u_int rejbyte = ahc_inb(ahc, ACCUM);
635 kprintf("%s:%c:%d: Warning - unknown message received from "
636 "target (0x%x). Rejecting\n",
637 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
640 case PROTO_VIOLATION:
642 ahc_handle_proto_violation(ahc);
646 ahc_handle_ign_wide_residue(ahc, &devinfo);
649 ahc_reinitialize_dataptrs(ahc);
655 lastphase = ahc_inb(ahc, LASTPHASE);
656 kprintf("%s:%c:%d: unknown scsi bus phase %x, "
657 "lastphase = 0x%x. Attempting to continue\n",
658 ahc_name(ahc), devinfo.channel, devinfo.target,
659 lastphase, ahc_inb(ahc, SCSISIGI));
666 lastphase = ahc_inb(ahc, LASTPHASE);
667 kprintf("%s:%c:%d: Missed busfree. "
668 "Lastphase = 0x%x, Curphase = 0x%x\n",
669 ahc_name(ahc), devinfo.channel, devinfo.target,
670 lastphase, ahc_inb(ahc, SCSISIGI));
677 * The sequencer has encountered a message phase
678 * that requires host assistance for completion.
679 * While handling the message phase(s), we will be
680 * notified by the sequencer after each byte is
681 * transfered so we can track bus phase changes.
683 * If this is the first time we've seen a HOST_MSG_LOOP
684 * interrupt, initialize the state of the host message
687 if (ahc->msg_type == MSG_TYPE_NONE) {
692 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
693 if (bus_phase != P_MESGIN
694 && bus_phase != P_MESGOUT) {
695 kprintf("ahc_intr: HOST_MSG_LOOP bad "
699 * Probably transitioned to bus free before
700 * we got here. Just punt the message.
702 ahc_clear_intstat(ahc);
707 scb_index = ahc_inb(ahc, SCB_TAG);
708 scb = ahc_lookup_scb(ahc, scb_index);
709 if (devinfo.role == ROLE_INITIATOR) {
711 panic("HOST_MSG_LOOP with "
712 "invalid SCB %x\n", scb_index);
714 if (bus_phase == P_MESGOUT)
715 ahc_setup_initiator_msgout(ahc,
720 MSG_TYPE_INITIATOR_MSGIN;
721 ahc->msgin_index = 0;
724 #ifdef AHC_TARGET_MODE
726 if (bus_phase == P_MESGOUT) {
728 MSG_TYPE_TARGET_MSGOUT;
729 ahc->msgin_index = 0;
732 ahc_setup_target_msgin(ahc,
739 ahc_handle_message_phase(ahc);
745 * If we've cleared the parity error interrupt
746 * but the sequencer still believes that SCSIPERR
747 * is true, it must be that the parity error is
748 * for the currently presented byte on the bus,
749 * and we are not in a phase (data-in) where we will
750 * eventually ack this byte. Ack the byte and
751 * throw it away in the hope that the target will
752 * take us to message out to deliver the appropriate
755 if ((intstat & SCSIINT) == 0
756 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
758 if ((ahc->features & AHC_DT) == 0) {
762 * The hardware will only let you ack bytes
763 * if the expected phase in SCSISIGO matches
764 * the current phase. Make sure this is
765 * currently the case.
767 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
768 ahc_outb(ahc, LASTPHASE, curphase);
769 ahc_outb(ahc, SCSISIGO, curphase);
771 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
775 * In a data phase. Faster to bitbucket
776 * the data than to individually ack each
777 * byte. This is also the only strategy
778 * that will work with AUTOACK enabled.
780 ahc_outb(ahc, SXFRCTL1,
781 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
783 while (--wait != 0) {
784 if ((ahc_inb(ahc, SCSISIGI)
789 ahc_outb(ahc, SXFRCTL1,
790 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
795 ahc_print_devinfo(ahc, &devinfo);
796 kprintf("Unable to clear parity error. "
798 scb_index = ahc_inb(ahc, SCB_TAG);
799 scb = ahc_lookup_scb(ahc, scb_index);
801 aic_set_transaction_status(scb,
803 ahc_reset_channel(ahc, devinfo.channel,
807 ahc_inb(ahc, SCSIDATL);
815 * When the sequencer detects an overrun, it
816 * places the controller in "BITBUCKET" mode
817 * and allows the target to complete its transfer.
818 * Unfortunately, none of the counters get updated
819 * when the controller is in this mode, so we have
820 * no way of knowing how large the overrun was.
822 u_int scbindex = ahc_inb(ahc, SCB_TAG);
823 u_int lastphase = ahc_inb(ahc, LASTPHASE);
826 scb = ahc_lookup_scb(ahc, scbindex);
827 for (i = 0; i < num_phases; i++) {
828 if (lastphase == ahc_phase_table[i].phase)
831 ahc_print_path(ahc, scb);
832 kprintf("data overrun detected %s."
834 ahc_phase_table[i].phasemsg,
836 ahc_print_path(ahc, scb);
837 kprintf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
838 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
839 aic_get_transfer_length(scb), scb->sg_count);
840 if (scb->sg_count > 0) {
841 for (i = 0; i < scb->sg_count; i++) {
843 kprintf("sg[%d] - Addr 0x%x%x : Length %d\n",
845 (aic_le32toh(scb->sg_list[i].len) >> 24
846 & SG_HIGH_ADDR_BITS),
847 aic_le32toh(scb->sg_list[i].addr),
848 aic_le32toh(scb->sg_list[i].len)
853 * Set this and it will take effect when the
854 * target does a command complete.
856 ahc_freeze_devq(ahc, scb);
857 if ((scb->flags & SCB_SENSE) == 0) {
858 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
860 scb->flags &= ~SCB_SENSE;
861 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
865 if ((ahc->features & AHC_ULTRA2) != 0) {
867 * Clear the channel in case we return
868 * to data phase later.
870 ahc_outb(ahc, SXFRCTL0,
871 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
872 ahc_outb(ahc, SXFRCTL0,
873 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
875 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
878 /* Ensure HHADDR is 0 for future DMA operations. */
879 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
880 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
881 ahc_outb(ahc, HADDR, 0);
882 ahc_outb(ahc, DSCOMMAND1, dscommand1);
890 kprintf("%s:%c:%d:%d: Attempt to issue message failed\n",
891 ahc_name(ahc), devinfo.channel, devinfo.target,
893 scbindex = ahc_inb(ahc, SCB_TAG);
894 scb = ahc_lookup_scb(ahc, scbindex);
896 && (scb->flags & SCB_RECOVERY_SCB) != 0)
898 * Ensure that we didn't put a second instance of this
899 * SCB into the QINFIFO.
901 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
902 SCB_GET_CHANNEL(ahc, scb),
903 SCB_GET_LUN(scb), scb->hscb->tag,
904 ROLE_INITIATOR, /*status*/0,
910 kprintf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
911 ahc_dump_card_state(ahc);
919 scbptr = ahc_inb(ahc, SCBPTR);
920 kprintf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
921 scbptr, ahc_inb(ahc, ARG_1),
922 ahc->scb_data->hscbs[scbptr].tag);
923 ahc_dump_card_state(ahc);
929 kprintf("%s: BTT calculation out of range\n", ahc_name(ahc));
930 kprintf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
931 "ARG_1 == 0x%x ACCUM = 0x%x\n",
932 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
933 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
934 kprintf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
935 "SINDEX == 0x%x\n, A == 0x%x\n",
936 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
937 ahc_index_busy_tcl(ahc,
938 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
939 ahc_inb(ahc, SAVED_LUN))),
940 ahc_inb(ahc, SINDEX),
941 ahc_inb(ahc, ACCUM));
942 kprintf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
943 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
944 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
945 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
946 ahc_inb(ahc, SCB_CONTROL));
947 kprintf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
948 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
949 ahc_dump_card_state(ahc);
954 kprintf("ahc_intr: seqint, "
955 "intstat == 0x%x, scsisigi = 0x%x\n",
956 intstat, ahc_inb(ahc, SCSISIGI));
961 * The sequencer is paused immediately on
962 * a SEQINT, so we should restart it when
969 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
978 if ((ahc->features & AHC_TWIN) != 0
979 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
983 intr_channel = cur_channel;
985 if ((ahc->features & AHC_ULTRA2) != 0)
986 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
989 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
990 if (status == 0 && status0 == 0) {
991 if ((ahc->features & AHC_TWIN) != 0) {
992 /* Try the other channel */
993 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
994 status = ahc_inb(ahc, SSTAT1)
995 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
996 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
999 kprintf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
1000 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1006 /* Make sure the sequencer is in a safe location. */
1007 ahc_clear_critical_section(ahc);
1009 scb_index = ahc_inb(ahc, SCB_TAG);
1010 scb = ahc_lookup_scb(ahc, scb_index);
1012 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1015 if ((ahc->features & AHC_ULTRA2) != 0
1016 && (status0 & IOERR) != 0) {
1019 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1020 kprintf("%s: Transceiver State Has Changed to %s mode\n",
1021 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1022 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1024 * When transitioning to SE mode, the reset line
1025 * glitches, triggering an arbitration bug in some
1026 * Ultra2 controllers. This bug is cleared when we
1027 * assert the reset line. Since a reset glitch has
1028 * already occurred with this transition and a
1029 * transceiver state change is handled just like
1030 * a bus reset anyway, asserting the reset line
1031 * ourselves is safe.
1033 ahc_reset_channel(ahc, intr_channel,
1034 /*Initiate Reset*/now_lvd == 0);
1035 } else if ((status & SCSIRSTI) != 0) {
1036 kprintf("%s: Someone reset channel %c\n",
1037 ahc_name(ahc), intr_channel);
1038 if (intr_channel != cur_channel)
1039 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1040 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1041 } else if ((status & SCSIPERR) != 0) {
1043 * Determine the bus phase and queue an appropriate message.
1044 * SCSIPERR is latched true as soon as a parity error
1045 * occurs. If the sequencer acked the transfer that
1046 * caused the parity error and the currently presented
1047 * transfer on the bus has correct parity, SCSIPERR will
1048 * be cleared by CLRSCSIPERR. Use this to determine if
1049 * we should look at the last phase the sequencer recorded,
1050 * or the current phase presented on the bus.
1052 struct ahc_devinfo devinfo;
1062 lastphase = ahc_inb(ahc, LASTPHASE);
1063 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1064 sstat2 = ahc_inb(ahc, SSTAT2);
1065 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1067 * For all phases save DATA, the sequencer won't
1068 * automatically ack a byte that has a parity error
1069 * in it. So the only way that the current phase
1070 * could be 'data-in' is if the parity error is for
1071 * an already acked byte in the data phase. During
1072 * synchronous data-in transfers, we may actually
1073 * ack bytes before latching the current phase in
1074 * LASTPHASE, leading to the discrepancy between
1075 * curphase and lastphase.
1077 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1078 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1079 errorphase = curphase;
1081 errorphase = lastphase;
1083 for (i = 0; i < num_phases; i++) {
1084 if (errorphase == ahc_phase_table[i].phase)
1087 mesg_out = ahc_phase_table[i].mesg_out;
1090 if (SCB_IS_SILENT(scb))
1093 ahc_print_path(ahc, scb);
1094 scb->flags |= SCB_TRANSMISSION_ERROR;
1096 kprintf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1097 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1098 scsirate = ahc_inb(ahc, SCSIRATE);
1099 if (silent == FALSE) {
1100 kprintf("parity error detected %s. "
1101 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1102 ahc_phase_table[i].phasemsg,
1103 ahc_inw(ahc, SEQADDR0),
1105 if ((ahc->features & AHC_DT) != 0) {
1106 if ((sstat2 & CRCVALERR) != 0)
1107 kprintf("\tCRC Value Mismatch\n");
1108 if ((sstat2 & CRCENDERR) != 0)
1109 kprintf("\tNo terminal CRC packet "
1111 if ((sstat2 & CRCREQERR) != 0)
1112 kprintf("\tIllegal CRC packet "
1114 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1115 kprintf("\tUnexpected %sDT Data Phase\n",
1116 (scsirate & SINGLE_EDGE)
1121 if ((ahc->features & AHC_DT) != 0
1122 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1124 * This error applies regardless of
1125 * data direction, so ignore the value
1126 * in the phase table.
1128 mesg_out = MSG_INITIATOR_DET_ERR;
1132 * We've set the hardware to assert ATN if we
1133 * get a parity error on "in" phases, so all we
1134 * need to do is stuff the message buffer with
1135 * the appropriate message. "In" phases have set
1136 * mesg_out to something other than MSG_NOP.
1138 if (mesg_out != MSG_NOOP) {
1139 if (ahc->msg_type != MSG_TYPE_NONE)
1140 ahc->send_msg_perror = TRUE;
1142 ahc_outb(ahc, MSG_OUT, mesg_out);
1145 * Force a renegotiation with this target just in
1146 * case we are out of sync for some external reason
1147 * unknown (or unreported) by the target.
1149 ahc_fetch_devinfo(ahc, &devinfo);
1150 ahc_force_renegotiation(ahc, &devinfo);
1152 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1154 } else if ((status & SELTO) != 0) {
1157 /* Stop the selection */
1158 ahc_outb(ahc, SCSISEQ, 0);
1160 /* No more pending messages */
1161 ahc_clear_msg_state(ahc);
1163 /* Clear interrupt state */
1164 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1165 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1168 * Although the driver does not care about the
1169 * 'Selection in Progress' status bit, the busy
1170 * LED does. SELINGO is only cleared by a successful
1171 * selection, so we must manually clear it to insure
1172 * the LED turns off just in case no future successful
1173 * selections occur (e.g. no devices on the bus).
1175 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1177 scbptr = ahc_inb(ahc, WAITING_SCBH);
1178 ahc_outb(ahc, SCBPTR, scbptr);
1179 scb_index = ahc_inb(ahc, SCB_TAG);
1181 scb = ahc_lookup_scb(ahc, scb_index);
1183 kprintf("%s: ahc_intr - referenced scb not "
1184 "valid during SELTO scb(%d, %d)\n",
1185 ahc_name(ahc), scbptr, scb_index);
1186 ahc_dump_card_state(ahc);
1188 struct ahc_devinfo devinfo;
1190 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1191 ahc_print_path(ahc, scb);
1192 kprintf("Saw Selection Timeout for SCB 0x%x\n",
1196 ahc_scb_devinfo(ahc, &devinfo, scb);
1197 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1198 ahc_freeze_devq(ahc, scb);
1201 * Cancel any pending transactions on the device
1202 * now that it seems to be missing. This will
1203 * also revert us to async/narrow transfers until
1204 * we can renegotiate with the device.
1206 ahc_handle_devreset(ahc, &devinfo,
1208 "Selection Timeout",
1209 /*verbose_level*/1);
1211 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1213 } else if ((status & BUSFREE) != 0
1214 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1215 struct ahc_devinfo devinfo;
1220 u_int initiator_role_id;
1225 * Clear our selection hardware as soon as possible.
1226 * We may have an entry in the waiting Q for this target,
1227 * that is affected by this busfree and we don't want to
1228 * go about selecting the target while we handle the event.
1230 ahc_outb(ahc, SCSISEQ,
1231 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1234 * Disable busfree interrupts and clear the busfree
1235 * interrupt status. We do this here so that several
1236 * bus transactions occur prior to clearing the SCSIINT
1237 * latch. It can take a bit for the clearing to take effect.
1239 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1240 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1243 * Look at what phase we were last in.
1244 * If its message out, chances are pretty good
1245 * that the busfree was in response to one of
1246 * our abort requests.
1248 lastphase = ahc_inb(ahc, LASTPHASE);
1249 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1250 saved_lun = ahc_inb(ahc, SAVED_LUN);
1251 target = SCSIID_TARGET(ahc, saved_scsiid);
1252 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1253 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1254 ahc_compile_devinfo(&devinfo, initiator_role_id,
1255 target, saved_lun, channel, ROLE_INITIATOR);
1258 if (lastphase == P_MESGOUT) {
1261 tag = SCB_LIST_NULL;
1262 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1263 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1264 if (ahc->msgout_buf[ahc->msgout_index - 1]
1266 tag = scb->hscb->tag;
1267 ahc_print_path(ahc, scb);
1268 kprintf("SCB %d - Abort%s Completed.\n",
1269 scb->hscb->tag, tag == SCB_LIST_NULL ?
1271 ahc_abort_scbs(ahc, target, channel,
1276 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1277 MSG_BUS_DEV_RESET, TRUE)) {
1278 #if defined(__DragonFly__) || defined(__FreeBSD__)
1280 * Don't mark the user's request for this BDR
1281 * as completing with CAM_BDR_SENT. CAM3
1282 * specifies CAM_REQ_CMP.
1285 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1286 && ahc_match_scb(ahc, scb, target, channel,
1290 aic_set_transaction_status(scb, CAM_REQ_CMP);
1293 ahc_compile_devinfo(&devinfo,
1299 ahc_handle_devreset(ahc, &devinfo,
1302 /*verbose_level*/0);
1304 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1305 MSG_EXT_PPR, FALSE)) {
1306 struct ahc_initiator_tinfo *tinfo;
1307 struct ahc_tmode_tstate *tstate;
1310 * PPR Rejected. Try non-ppr negotiation
1311 * and retry command.
1313 tinfo = ahc_fetch_transinfo(ahc,
1318 tinfo->curr.transport_version = 2;
1319 tinfo->goal.transport_version = 2;
1320 tinfo->goal.ppr_options = 0;
1321 ahc_qinfifo_requeue_tail(ahc, scb);
1323 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1324 MSG_EXT_WDTR, FALSE)) {
1326 * Negotiation Rejected. Go-narrow and
1329 ahc_set_width(ahc, &devinfo,
1330 MSG_EXT_WDTR_BUS_8_BIT,
1331 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1333 ahc_qinfifo_requeue_tail(ahc, scb);
1335 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1336 MSG_EXT_SDTR, FALSE)) {
1338 * Negotiation Rejected. Go-async and
1341 ahc_set_syncrate(ahc, &devinfo,
1343 /*period*/0, /*offset*/0,
1345 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1347 ahc_qinfifo_requeue_tail(ahc, scb);
1351 if (printerror != 0) {
1357 if ((scb->hscb->control & TAG_ENB) != 0)
1358 tag = scb->hscb->tag;
1360 tag = SCB_LIST_NULL;
1361 ahc_print_path(ahc, scb);
1362 ahc_abort_scbs(ahc, target, channel,
1363 SCB_GET_LUN(scb), tag,
1368 * We had not fully identified this connection,
1369 * so we cannot abort anything.
1371 kprintf("%s: ", ahc_name(ahc));
1373 for (i = 0; i < num_phases; i++) {
1374 if (lastphase == ahc_phase_table[i].phase)
1377 if (lastphase != P_BUSFREE) {
1379 * Renegotiate with this device at the
1380 * next oportunity just in case this busfree
1381 * is due to a negotiation mismatch with the
1384 ahc_force_renegotiation(ahc, &devinfo);
1386 kprintf("Unexpected busfree %s\n"
1387 "SEQADDR == 0x%x\n",
1388 ahc_phase_table[i].phasemsg,
1389 ahc_inb(ahc, SEQADDR0)
1390 | (ahc_inb(ahc, SEQADDR1) << 8));
1392 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1395 kprintf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1396 ahc_name(ahc), status);
1397 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1402 * Force renegotiation to occur the next time we initiate
1403 * a command to the current device.
1406 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1408 struct ahc_initiator_tinfo *targ_info;
1409 struct ahc_tmode_tstate *tstate;
1411 targ_info = ahc_fetch_transinfo(ahc,
1413 devinfo->our_scsiid,
1416 ahc_update_neg_request(ahc, devinfo, tstate,
1417 targ_info, AHC_NEG_IF_NON_ASYNC);
1420 #define AHC_MAX_STEPS 2000
1422 ahc_clear_critical_section(struct ahc_softc *ahc)
1429 if (ahc->num_critical_sections == 0)
1441 seqaddr = ahc_inb(ahc, SEQADDR0)
1442 | (ahc_inb(ahc, SEQADDR1) << 8);
1445 * Seqaddr represents the next instruction to execute,
1446 * so we are really executing the instruction just
1449 cs = ahc->critical_sections;
1450 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1452 if (cs->begin < seqaddr && cs->end >= seqaddr)
1456 if (i == ahc->num_critical_sections)
1459 if (steps > AHC_MAX_STEPS) {
1460 kprintf("%s: Infinite loop in critical section\n",
1462 ahc_dump_card_state(ahc);
1463 panic("critical section loop");
1467 if (stepping == FALSE) {
1470 * Disable all interrupt sources so that the
1471 * sequencer will not be stuck by a pausing
1472 * interrupt condition while we attempt to
1473 * leave a critical section.
1475 simode0 = ahc_inb(ahc, SIMODE0);
1476 ahc_outb(ahc, SIMODE0, 0);
1477 simode1 = ahc_inb(ahc, SIMODE1);
1478 if ((ahc->features & AHC_DT) != 0)
1480 * On DT class controllers, we
1481 * use the enhanced busfree logic.
1482 * Unfortunately we cannot re-enable
1483 * busfree detection within the
1484 * current connection, so we must
1485 * leave it on while single stepping.
1487 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1489 ahc_outb(ahc, SIMODE1, 0);
1490 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1491 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1494 if ((ahc->features & AHC_DT) != 0) {
1495 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1496 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1498 ahc_outb(ahc, HCNTRL, ahc->unpause);
1499 while (!ahc_is_paused(ahc))
1503 ahc_outb(ahc, SIMODE0, simode0);
1504 ahc_outb(ahc, SIMODE1, simode1);
1505 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1510 * Clear any pending interrupt status.
1513 ahc_clear_intstat(struct ahc_softc *ahc)
1515 /* Clear any interrupt conditions this may have caused */
1516 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1517 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1519 ahc_flush_device_writes(ahc);
1520 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1521 ahc_flush_device_writes(ahc);
1522 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1523 ahc_flush_device_writes(ahc);
1526 /**************************** Debugging Routines ******************************/
1528 uint32_t ahc_debug = AHC_DEBUG_OPTS;
1532 ahc_print_scb(struct scb *scb)
1536 struct hardware_scb *hscb = scb->hscb;
1538 kprintf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1544 kprintf("Shared Data: ");
1545 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1546 kprintf("%#02x", hscb->shared_data.cdb[i]);
1547 kprintf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1548 aic_le32toh(hscb->dataptr),
1549 aic_le32toh(hscb->datacnt),
1550 aic_le32toh(hscb->sgptr),
1552 if (scb->sg_count > 0) {
1553 for (i = 0; i < scb->sg_count; i++) {
1554 kprintf("sg[%d] - Addr 0x%x%x : Length %d\n",
1556 (aic_le32toh(scb->sg_list[i].len) >> 24
1557 & SG_HIGH_ADDR_BITS),
1558 aic_le32toh(scb->sg_list[i].addr),
1559 aic_le32toh(scb->sg_list[i].len));
1564 /************************* Transfer Negotiation *******************************/
1566 * Allocate per target mode instance (ID we respond to as a target)
1567 * transfer negotiation data structures.
1569 static struct ahc_tmode_tstate *
1570 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1572 struct ahc_tmode_tstate *master_tstate;
1573 struct ahc_tmode_tstate *tstate;
1576 master_tstate = ahc->enabled_targets[ahc->our_id];
1577 if (channel == 'B') {
1579 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1581 if (ahc->enabled_targets[scsi_id] != NULL
1582 && ahc->enabled_targets[scsi_id] != master_tstate)
1583 panic("%s: ahc_alloc_tstate - Target already allocated",
1585 tstate = kmalloc(sizeof(*tstate), M_DEVBUF, M_INTWAIT);
1588 * If we have allocated a master tstate, copy user settings from
1589 * the master tstate (taken from SRAM or the EEPROM) for this
1590 * channel, but reset our current and goal settings to async/narrow
1591 * until an initiator talks to us.
1593 if (master_tstate != NULL) {
1594 memcpy(tstate, master_tstate, sizeof(*tstate));
1595 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1596 tstate->ultraenb = 0;
1597 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1598 memset(&tstate->transinfo[i].curr, 0,
1599 sizeof(tstate->transinfo[i].curr));
1600 memset(&tstate->transinfo[i].goal, 0,
1601 sizeof(tstate->transinfo[i].goal));
1604 memset(tstate, 0, sizeof(*tstate));
1605 ahc->enabled_targets[scsi_id] = tstate;
1609 #ifdef AHC_TARGET_MODE
1611 * Free per target mode instance (ID we respond to as a target)
1612 * transfer negotiation data structures.
1615 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1617 struct ahc_tmode_tstate *tstate;
1620 * Don't clean up our "master" tstate.
1621 * It has our default user settings.
1623 if (((channel == 'B' && scsi_id == ahc->our_id_b)
1624 || (channel == 'A' && scsi_id == ahc->our_id))
1630 tstate = ahc->enabled_targets[scsi_id];
1632 kfree(tstate, M_DEVBUF);
1633 ahc->enabled_targets[scsi_id] = NULL;
1638 * Called when we have an active connection to a target on the bus,
1639 * this function finds the nearest syncrate to the input period limited
1640 * by the capabilities of the bus connectivity of and sync settings for
1643 struct ahc_syncrate *
1644 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1645 struct ahc_initiator_tinfo *tinfo,
1646 u_int *period, u_int *ppr_options, role_t role)
1648 struct ahc_transinfo *transinfo;
1651 if ((ahc->features & AHC_ULTRA2) != 0) {
1652 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1653 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1654 maxsync = AHC_SYNCRATE_DT;
1656 maxsync = AHC_SYNCRATE_ULTRA;
1657 /* Can't do DT on an SE bus */
1658 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1660 } else if ((ahc->features & AHC_ULTRA) != 0) {
1661 maxsync = AHC_SYNCRATE_ULTRA;
1663 maxsync = AHC_SYNCRATE_FAST;
1666 * Never allow a value higher than our current goal
1667 * period otherwise we may allow a target initiated
1668 * negotiation to go above the limit as set by the
1669 * user. In the case of an initiator initiated
1670 * sync negotiation, we limit based on the user
1671 * setting. This allows the system to still accept
1672 * incoming negotiations even if target initiated
1673 * negotiation is not performed.
1675 if (role == ROLE_TARGET)
1676 transinfo = &tinfo->user;
1678 transinfo = &tinfo->goal;
1679 *ppr_options &= transinfo->ppr_options;
1680 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1681 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
1682 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1684 if (transinfo->period == 0) {
1689 *period = MAX(*period, transinfo->period);
1690 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1694 * Look up the valid period to SCSIRATE conversion in our table.
1695 * Return the period and offset that should be sent to the target
1696 * if this was the beginning of an SDTR.
1698 struct ahc_syncrate *
1699 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1700 u_int *ppr_options, u_int maxsync)
1702 struct ahc_syncrate *syncrate;
1704 if ((ahc->features & AHC_DT) == 0)
1705 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1707 /* Skip all DT only entries if DT is not available */
1708 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1709 && maxsync < AHC_SYNCRATE_ULTRA2)
1710 maxsync = AHC_SYNCRATE_ULTRA2;
1712 for (syncrate = &ahc_syncrates[maxsync];
1713 syncrate->rate != NULL;
1717 * The Ultra2 table doesn't go as low
1718 * as for the Fast/Ultra cards.
1720 if ((ahc->features & AHC_ULTRA2) != 0
1721 && (syncrate->sxfr_u2 == 0))
1724 if (*period <= syncrate->period) {
1726 * When responding to a target that requests
1727 * sync, the requested rate may fall between
1728 * two rates that we can output, but still be
1729 * a rate that we can receive. Because of this,
1730 * we want to respond to the target with
1731 * the same rate that it sent to us even
1732 * if the period we use to send data to it
1733 * is lower. Only lower the response period
1736 if (syncrate == &ahc_syncrates[maxsync])
1737 *period = syncrate->period;
1740 * At some speeds, we only support
1743 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1744 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1750 || (syncrate->rate == NULL)
1751 || ((ahc->features & AHC_ULTRA2) != 0
1752 && (syncrate->sxfr_u2 == 0))) {
1753 /* Use asynchronous transfers. */
1756 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1762 * Convert from an entry in our syncrate table to the SCSI equivalent
1763 * sync "period" factor.
1766 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1768 struct ahc_syncrate *syncrate;
1770 if ((ahc->features & AHC_ULTRA2) != 0)
1771 scsirate &= SXFR_ULTRA2;
1775 syncrate = &ahc_syncrates[maxsync];
1776 while (syncrate->rate != NULL) {
1778 if ((ahc->features & AHC_ULTRA2) != 0) {
1779 if (syncrate->sxfr_u2 == 0)
1781 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1782 return (syncrate->period);
1783 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1784 return (syncrate->period);
1788 return (0); /* async */
1792 * Truncate the given synchronous offset to a value the
1793 * current adapter type and syncrate are capable of.
1796 ahc_validate_offset(struct ahc_softc *ahc,
1797 struct ahc_initiator_tinfo *tinfo,
1798 struct ahc_syncrate *syncrate,
1799 u_int *offset, int wide, role_t role)
1803 /* Limit offset to what we can do */
1804 if (syncrate == NULL) {
1806 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1807 maxoffset = MAX_OFFSET_ULTRA2;
1810 maxoffset = MAX_OFFSET_16BIT;
1812 maxoffset = MAX_OFFSET_8BIT;
1814 *offset = MIN(*offset, maxoffset);
1815 if (tinfo != NULL) {
1816 if (role == ROLE_TARGET)
1817 *offset = MIN(*offset, tinfo->user.offset);
1819 *offset = MIN(*offset, tinfo->goal.offset);
1824 * Truncate the given transfer width parameter to a value the
1825 * current adapter type is capable of.
1828 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1829 u_int *bus_width, role_t role)
1831 switch (*bus_width) {
1833 if (ahc->features & AHC_WIDE) {
1835 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1839 case MSG_EXT_WDTR_BUS_8_BIT:
1840 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1843 if (tinfo != NULL) {
1844 if (role == ROLE_TARGET)
1845 *bus_width = MIN(tinfo->user.width, *bus_width);
1847 *bus_width = MIN(tinfo->goal.width, *bus_width);
1852 * Update the bitmask of targets for which the controller should
1853 * negotiate with at the next convenient oportunity. This currently
1854 * means the next time we send the initial identify messages for
1855 * a new transaction.
1858 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1859 struct ahc_tmode_tstate *tstate,
1860 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1862 u_int auto_negotiate_orig;
1864 auto_negotiate_orig = tstate->auto_negotiate;
1865 if (neg_type == AHC_NEG_ALWAYS) {
1867 * Force our "current" settings to be
1868 * unknown so that unless a bus reset
1869 * occurs the need to renegotiate is
1870 * recorded persistently.
1872 if ((ahc->features & AHC_WIDE) != 0)
1873 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1874 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1875 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1877 if (tinfo->curr.period != tinfo->goal.period
1878 || tinfo->curr.width != tinfo->goal.width
1879 || tinfo->curr.offset != tinfo->goal.offset
1880 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1881 || (neg_type == AHC_NEG_IF_NON_ASYNC
1882 && (tinfo->goal.offset != 0
1883 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1884 || tinfo->goal.ppr_options != 0)))
1885 tstate->auto_negotiate |= devinfo->target_mask;
1887 tstate->auto_negotiate &= ~devinfo->target_mask;
1889 return (auto_negotiate_orig != tstate->auto_negotiate);
1893 * Update the user/goal/curr tables of synchronous negotiation
1894 * parameters as well as, in the case of a current or active update,
1895 * any data structures on the host controller. In the case of an
1896 * active update, the specified target is currently talking to us on
1897 * the bus, so the transfer parameter update must take effect
1901 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1902 struct ahc_syncrate *syncrate, u_int period,
1903 u_int offset, u_int ppr_options, u_int type, int paused)
1905 struct ahc_initiator_tinfo *tinfo;
1906 struct ahc_tmode_tstate *tstate;
1913 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1916 if (syncrate == NULL) {
1921 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1922 devinfo->target, &tstate);
1924 if ((type & AHC_TRANS_USER) != 0) {
1925 tinfo->user.period = period;
1926 tinfo->user.offset = offset;
1927 tinfo->user.ppr_options = ppr_options;
1930 if ((type & AHC_TRANS_GOAL) != 0) {
1931 tinfo->goal.period = period;
1932 tinfo->goal.offset = offset;
1933 tinfo->goal.ppr_options = ppr_options;
1936 old_period = tinfo->curr.period;
1937 old_offset = tinfo->curr.offset;
1938 old_ppr = tinfo->curr.ppr_options;
1940 if ((type & AHC_TRANS_CUR) != 0
1941 && (old_period != period
1942 || old_offset != offset
1943 || old_ppr != ppr_options)) {
1947 scsirate = tinfo->scsirate;
1948 if ((ahc->features & AHC_ULTRA2) != 0) {
1950 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1951 if (syncrate != NULL) {
1952 scsirate |= syncrate->sxfr_u2;
1953 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1954 scsirate |= ENABLE_CRC;
1956 scsirate |= SINGLE_EDGE;
1960 scsirate &= ~(SXFR|SOFS);
1962 * Ensure Ultra mode is set properly for
1965 tstate->ultraenb &= ~devinfo->target_mask;
1966 if (syncrate != NULL) {
1967 if (syncrate->sxfr & ULTRA_SXFR) {
1969 devinfo->target_mask;
1971 scsirate |= syncrate->sxfr & SXFR;
1972 scsirate |= offset & SOFS;
1977 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1978 sxfrctl0 &= ~FAST20;
1979 if (tstate->ultraenb & devinfo->target_mask)
1981 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1985 ahc_outb(ahc, SCSIRATE, scsirate);
1986 if ((ahc->features & AHC_ULTRA2) != 0)
1987 ahc_outb(ahc, SCSIOFFSET, offset);
1990 tinfo->scsirate = scsirate;
1991 tinfo->curr.period = period;
1992 tinfo->curr.offset = offset;
1993 tinfo->curr.ppr_options = ppr_options;
1995 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1996 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
1999 kprintf("%s: target %d synchronous at %sMHz%s, "
2000 "offset = 0x%x\n", ahc_name(ahc),
2001 devinfo->target, syncrate->rate,
2002 (ppr_options & MSG_EXT_PPR_DT_REQ)
2003 ? " DT" : "", offset);
2005 kprintf("%s: target %d using "
2006 "asynchronous transfers\n",
2007 ahc_name(ahc), devinfo->target);
2012 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2013 tinfo, AHC_NEG_TO_GOAL);
2016 ahc_update_pending_scbs(ahc);
2020 * Update the user/goal/curr tables of wide negotiation
2021 * parameters as well as, in the case of a current or active update,
2022 * any data structures on the host controller. In the case of an
2023 * active update, the specified target is currently talking to us on
2024 * the bus, so the transfer parameter update must take effect
2028 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2029 u_int width, u_int type, int paused)
2031 struct ahc_initiator_tinfo *tinfo;
2032 struct ahc_tmode_tstate *tstate;
2037 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2039 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2040 devinfo->target, &tstate);
2042 if ((type & AHC_TRANS_USER) != 0)
2043 tinfo->user.width = width;
2045 if ((type & AHC_TRANS_GOAL) != 0)
2046 tinfo->goal.width = width;
2048 oldwidth = tinfo->curr.width;
2049 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2053 scsirate = tinfo->scsirate;
2054 scsirate &= ~WIDEXFER;
2055 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2056 scsirate |= WIDEXFER;
2058 tinfo->scsirate = scsirate;
2061 ahc_outb(ahc, SCSIRATE, scsirate);
2063 tinfo->curr.width = width;
2065 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2066 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2068 kprintf("%s: target %d using %dbit transfers\n",
2069 ahc_name(ahc), devinfo->target,
2070 8 * (0x01 << width));
2074 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2075 tinfo, AHC_NEG_TO_GOAL);
2077 ahc_update_pending_scbs(ahc);
2081 * Update the current state of tagged queuing for a given target.
2084 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2087 ahc_platform_set_tags(ahc, devinfo, alg);
2088 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2089 devinfo->lun, AC_TRANSFER_NEG, &alg);
2093 * When the transfer settings for a connection change, update any
2094 * in-transit SCBs to contain the new data so the hardware will
2095 * be set correctly during future (re)selections.
2098 ahc_update_pending_scbs(struct ahc_softc *ahc)
2100 struct scb *pending_scb;
2101 int pending_scb_count;
2107 * Traverse the pending SCB list and ensure that all of the
2108 * SCBs there have the proper settings.
2110 pending_scb_count = 0;
2111 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2112 struct ahc_devinfo devinfo;
2113 struct hardware_scb *pending_hscb;
2114 struct ahc_initiator_tinfo *tinfo;
2115 struct ahc_tmode_tstate *tstate;
2117 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2118 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2120 devinfo.target, &tstate);
2121 pending_hscb = pending_scb->hscb;
2122 pending_hscb->control &= ~ULTRAENB;
2123 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2124 pending_hscb->control |= ULTRAENB;
2125 pending_hscb->scsirate = tinfo->scsirate;
2126 pending_hscb->scsioffset = tinfo->curr.offset;
2127 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2128 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2129 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2130 pending_hscb->control &= ~MK_MESSAGE;
2132 ahc_sync_scb(ahc, pending_scb,
2133 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2134 pending_scb_count++;
2137 if (pending_scb_count == 0)
2140 if (ahc_is_paused(ahc)) {
2147 saved_scbptr = ahc_inb(ahc, SCBPTR);
2148 /* Ensure that the hscbs down on the card match the new information */
2149 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2150 struct hardware_scb *pending_hscb;
2154 ahc_outb(ahc, SCBPTR, i);
2155 scb_tag = ahc_inb(ahc, SCB_TAG);
2156 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2157 if (pending_scb == NULL)
2160 pending_hscb = pending_scb->hscb;
2161 control = ahc_inb(ahc, SCB_CONTROL);
2162 control &= ~(ULTRAENB|MK_MESSAGE);
2163 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2164 ahc_outb(ahc, SCB_CONTROL, control);
2165 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2166 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2168 ahc_outb(ahc, SCBPTR, saved_scbptr);
2174 /**************************** Pathing Information *****************************/
2176 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2182 if (ahc_inb(ahc, SSTAT0) & TARGET)
2185 role = ROLE_INITIATOR;
2187 if (role == ROLE_TARGET
2188 && (ahc->features & AHC_MULTI_TID) != 0
2189 && (ahc_inb(ahc, SEQ_FLAGS)
2190 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2191 /* We were selected, so pull our id from TARGIDIN */
2192 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2193 } else if ((ahc->features & AHC_ULTRA2) != 0)
2194 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2196 our_id = ahc_inb(ahc, SCSIID) & OID;
2198 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2199 ahc_compile_devinfo(devinfo,
2201 SCSIID_TARGET(ahc, saved_scsiid),
2202 ahc_inb(ahc, SAVED_LUN),
2203 SCSIID_CHANNEL(ahc, saved_scsiid),
2207 struct ahc_phase_table_entry*
2208 ahc_lookup_phase_entry(int phase)
2210 struct ahc_phase_table_entry *entry;
2211 struct ahc_phase_table_entry *last_entry;
2214 * num_phases doesn't include the default entry which
2215 * will be returned if the phase doesn't match.
2217 last_entry = &ahc_phase_table[num_phases];
2218 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2219 if (phase == entry->phase)
2226 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2227 u_int lun, char channel, role_t role)
2229 devinfo->our_scsiid = our_id;
2230 devinfo->target = target;
2232 devinfo->target_offset = target;
2233 devinfo->channel = channel;
2234 devinfo->role = role;
2236 devinfo->target_offset += 8;
2237 devinfo->target_mask = (0x01 << devinfo->target_offset);
2241 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2243 kprintf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2244 devinfo->target, devinfo->lun);
2248 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2254 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2255 role = ROLE_INITIATOR;
2256 if ((scb->flags & SCB_TARGET_SCB) != 0)
2258 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2259 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2263 /************************ Message Phase Processing ****************************/
2265 ahc_assert_atn(struct ahc_softc *ahc)
2270 if ((ahc->features & AHC_DT) == 0)
2271 scsisigo |= ahc_inb(ahc, SCSISIGI);
2272 ahc_outb(ahc, SCSISIGO, scsisigo);
2276 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2277 * or enters the initial message out phase, we are interrupted. Fill our
2278 * outgoing message buffer with the appropriate message and beging handing
2279 * the message phase(s) manually.
2282 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2286 * To facilitate adding multiple messages together,
2287 * each routine should increment the index and len
2288 * variables instead of setting them explicitly.
2290 ahc->msgout_index = 0;
2291 ahc->msgout_len = 0;
2293 if ((scb->flags & SCB_DEVICE_RESET) == 0
2294 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2297 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2298 if ((scb->hscb->control & DISCENB) != 0)
2299 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2300 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2303 if ((scb->hscb->control & TAG_ENB) != 0) {
2304 ahc->msgout_buf[ahc->msgout_index++] =
2305 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2306 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2307 ahc->msgout_len += 2;
2311 if (scb->flags & SCB_DEVICE_RESET) {
2312 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2314 ahc_print_path(ahc, scb);
2315 kprintf("Bus Device Reset Message Sent\n");
2317 * Clear our selection hardware in advance of
2318 * the busfree. We may have an entry in the waiting
2319 * Q for this target, and we don't want to go about
2320 * selecting while we handle the busfree and blow it
2323 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2324 } else if ((scb->flags & SCB_ABORT) != 0) {
2325 if ((scb->hscb->control & TAG_ENB) != 0)
2326 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2328 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2330 ahc_print_path(ahc, scb);
2331 kprintf("Abort%s Message Sent\n",
2332 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2334 * Clear our selection hardware in advance of
2335 * the busfree. We may have an entry in the waiting
2336 * Q for this target, and we don't want to go about
2337 * selecting while we handle the busfree and blow it
2340 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2341 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2342 ahc_build_transfer_msg(ahc, devinfo);
2344 kprintf("ahc_intr: AWAITING_MSG for an SCB that "
2345 "does not have a waiting message\n");
2346 kprintf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2347 devinfo->target_mask);
2348 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2349 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2350 ahc_inb(ahc, MSG_OUT), scb->flags);
2354 * Clear the MK_MESSAGE flag from the SCB so we aren't
2355 * asked to send this message again.
2357 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2358 scb->hscb->control &= ~MK_MESSAGE;
2359 ahc->msgout_index = 0;
2360 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2364 * Build an appropriate transfer negotiation message for the
2365 * currently active target.
2368 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2371 * We need to initiate transfer negotiations.
2372 * If our current and goal settings are identical,
2373 * we want to renegotiate due to a check condition.
2375 struct ahc_initiator_tinfo *tinfo;
2376 struct ahc_tmode_tstate *tstate;
2377 struct ahc_syncrate *rate;
2385 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2386 devinfo->target, &tstate);
2388 * Filter our period based on the current connection.
2389 * If we can't perform DT transfers on this segment (not in LVD
2390 * mode for instance), then our decision to issue a PPR message
2393 period = tinfo->goal.period;
2394 offset = tinfo->goal.offset;
2395 ppr_options = tinfo->goal.ppr_options;
2396 /* Target initiated PPR is not allowed in the SCSI spec */
2397 if (devinfo->role == ROLE_TARGET)
2399 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2400 &ppr_options, devinfo->role);
2401 dowide = tinfo->curr.width != tinfo->goal.width;
2402 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2404 * Only use PPR if we have options that need it, even if the device
2405 * claims to support it. There might be an expander in the way
2408 doppr = ppr_options != 0;
2410 if (!dowide && !dosync && !doppr) {
2411 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2412 dosync = tinfo->goal.offset != 0;
2415 if (!dowide && !dosync && !doppr) {
2417 * Force async with a WDTR message if we have a wide bus,
2418 * or just issue an SDTR with a 0 offset.
2420 if ((ahc->features & AHC_WIDE) != 0)
2426 ahc_print_devinfo(ahc, devinfo);
2427 kprintf("Ensuring async\n");
2431 /* Target initiated PPR is not allowed in the SCSI spec */
2432 if (devinfo->role == ROLE_TARGET)
2436 * Both the PPR message and SDTR message require the
2437 * goal syncrate to be limited to what the target device
2438 * is capable of handling (based on whether an LVD->SE
2439 * expander is on the bus), so combine these two cases.
2440 * Regardless, guarantee that if we are using WDTR and SDTR
2441 * messages that WDTR comes first.
2443 if (doppr || (dosync && !dowide)) {
2445 offset = tinfo->goal.offset;
2446 ahc_validate_offset(ahc, tinfo, rate, &offset,
2447 doppr ? tinfo->goal.width
2448 : tinfo->curr.width,
2451 ahc_construct_ppr(ahc, devinfo, period, offset,
2452 tinfo->goal.width, ppr_options);
2454 ahc_construct_sdtr(ahc, devinfo, period, offset);
2457 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2462 * Build a synchronous negotiation message in our message
2463 * buffer based on the input parameters.
2466 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2467 u_int period, u_int offset)
2470 period = AHC_ASYNC_XFER_PERIOD;
2471 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2472 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2473 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2474 ahc->msgout_buf[ahc->msgout_index++] = period;
2475 ahc->msgout_buf[ahc->msgout_index++] = offset;
2476 ahc->msgout_len += 5;
2478 kprintf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2479 ahc_name(ahc), devinfo->channel, devinfo->target,
2480 devinfo->lun, period, offset);
2485 * Build a wide negotiation message in our message
2486 * buffer based on the input parameters.
2489 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2492 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2493 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2494 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2495 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2496 ahc->msgout_len += 4;
2498 kprintf("(%s:%c:%d:%d): Sending WDTR %x\n",
2499 ahc_name(ahc), devinfo->channel, devinfo->target,
2500 devinfo->lun, bus_width);
2505 * Build a parallel protocol request message in our message
2506 * buffer based on the input parameters.
2509 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2510 u_int period, u_int offset, u_int bus_width,
2514 period = AHC_ASYNC_XFER_PERIOD;
2515 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2516 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2517 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2518 ahc->msgout_buf[ahc->msgout_index++] = period;
2519 ahc->msgout_buf[ahc->msgout_index++] = 0;
2520 ahc->msgout_buf[ahc->msgout_index++] = offset;
2521 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2522 ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2523 ahc->msgout_len += 8;
2525 kprintf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2526 "offset %x, ppr_options %x\n", ahc_name(ahc),
2527 devinfo->channel, devinfo->target, devinfo->lun,
2528 bus_width, period, offset, ppr_options);
2533 * Clear any active message state.
2536 ahc_clear_msg_state(struct ahc_softc *ahc)
2538 ahc->msgout_len = 0;
2539 ahc->msgin_index = 0;
2540 ahc->msg_type = MSG_TYPE_NONE;
2541 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2543 * The target didn't care to respond to our
2544 * message request, so clear ATN.
2546 ahc_outb(ahc, CLRSINT1, CLRATNO);
2548 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2549 ahc_outb(ahc, SEQ_FLAGS2,
2550 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2554 ahc_handle_proto_violation(struct ahc_softc *ahc)
2556 struct ahc_devinfo devinfo;
2564 ahc_fetch_devinfo(ahc, &devinfo);
2565 scbid = ahc_inb(ahc, SCB_TAG);
2566 scb = ahc_lookup_scb(ahc, scbid);
2567 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2568 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2569 lastphase = ahc_inb(ahc, LASTPHASE);
2570 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2573 * The reconnecting target either did not send an
2574 * identify message, or did, but we didn't find an SCB
2577 ahc_print_devinfo(ahc, &devinfo);
2578 kprintf("Target did not send an IDENTIFY message. "
2579 "LASTPHASE = 0x%x.\n", lastphase);
2581 } else if (scb == NULL) {
2583 * We don't seem to have an SCB active for this
2584 * transaction. Print an error and reset the bus.
2586 ahc_print_devinfo(ahc, &devinfo);
2587 kprintf("No SCB found during protocol violation\n");
2588 goto proto_violation_reset;
2590 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2591 if ((seq_flags & NO_CDB_SENT) != 0) {
2592 ahc_print_path(ahc, scb);
2593 kprintf("No or incomplete CDB sent to device.\n");
2594 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2596 * The target never bothered to provide status to
2597 * us prior to completing the command. Since we don't
2598 * know the disposition of this command, we must attempt
2599 * to abort it. Assert ATN and prepare to send an abort
2602 ahc_print_path(ahc, scb);
2603 kprintf("Completed command without status.\n");
2605 ahc_print_path(ahc, scb);
2606 kprintf("Unknown protocol violation.\n");
2607 ahc_dump_card_state(ahc);
2610 if ((lastphase & ~P_DATAIN_DT) == 0
2611 || lastphase == P_COMMAND) {
2612 proto_violation_reset:
2614 * Target either went directly to data/command
2615 * phase or didn't respond to our ATN.
2616 * The only safe thing to do is to blow
2617 * it away with a bus reset.
2619 found = ahc_reset_channel(ahc, 'A', TRUE);
2620 kprintf("%s: Issued Channel %c Bus Reset. "
2621 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2624 * Leave the selection hardware off in case
2625 * this abort attempt will affect yet to
2628 ahc_outb(ahc, SCSISEQ,
2629 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2630 ahc_assert_atn(ahc);
2631 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2633 ahc_print_devinfo(ahc, &devinfo);
2634 ahc->msgout_buf[0] = MSG_ABORT_TASK;
2635 ahc->msgout_len = 1;
2636 ahc->msgout_index = 0;
2637 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2639 ahc_print_path(ahc, scb);
2640 scb->flags |= SCB_ABORT;
2642 kprintf("Protocol violation %s. Attempting to abort.\n",
2643 ahc_lookup_phase_entry(curphase)->phasemsg);
2648 * Manual message loop handler.
2651 ahc_handle_message_phase(struct ahc_softc *ahc)
2653 struct ahc_devinfo devinfo;
2657 ahc_fetch_devinfo(ahc, &devinfo);
2658 end_session = FALSE;
2659 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2662 switch (ahc->msg_type) {
2663 case MSG_TYPE_INITIATOR_MSGOUT:
2669 if (ahc->msgout_len == 0)
2670 panic("HOST_MSG_LOOP interrupt with no active message");
2673 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2674 ahc_print_devinfo(ahc, &devinfo);
2675 kprintf("INITIATOR_MSG_OUT");
2678 phasemis = bus_phase != P_MESGOUT;
2681 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2682 kprintf(" PHASEMIS %s\n",
2683 ahc_lookup_phase_entry(bus_phase)
2687 if (bus_phase == P_MESGIN) {
2689 * Change gears and see if
2690 * this messages is of interest to
2691 * us or should be passed back to
2694 ahc_outb(ahc, CLRSINT1, CLRATNO);
2695 ahc->send_msg_perror = FALSE;
2696 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2697 ahc->msgin_index = 0;
2704 if (ahc->send_msg_perror) {
2705 ahc_outb(ahc, CLRSINT1, CLRATNO);
2706 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2708 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2709 kprintf(" byte 0x%x\n", ahc->send_msg_perror);
2711 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2715 msgdone = ahc->msgout_index == ahc->msgout_len;
2718 * The target has requested a retry.
2719 * Re-assert ATN, reset our message index to
2722 ahc->msgout_index = 0;
2723 ahc_assert_atn(ahc);
2726 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2728 /* Last byte is signified by dropping ATN */
2729 ahc_outb(ahc, CLRSINT1, CLRATNO);
2733 * Clear our interrupt status and present
2734 * the next byte on the bus.
2736 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2738 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2739 kprintf(" byte 0x%x\n",
2740 ahc->msgout_buf[ahc->msgout_index]);
2742 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2745 case MSG_TYPE_INITIATOR_MSGIN:
2751 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2752 ahc_print_devinfo(ahc, &devinfo);
2753 kprintf("INITIATOR_MSG_IN");
2756 phasemis = bus_phase != P_MESGIN;
2759 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2760 kprintf(" PHASEMIS %s\n",
2761 ahc_lookup_phase_entry(bus_phase)
2765 ahc->msgin_index = 0;
2766 if (bus_phase == P_MESGOUT
2767 && (ahc->send_msg_perror == TRUE
2768 || (ahc->msgout_len != 0
2769 && ahc->msgout_index == 0))) {
2770 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2777 /* Pull the byte in without acking it */
2778 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2780 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2781 kprintf(" byte 0x%x\n",
2782 ahc->msgin_buf[ahc->msgin_index]);
2785 message_done = ahc_parse_msg(ahc, &devinfo);
2789 * Clear our incoming message buffer in case there
2790 * is another message following this one.
2792 ahc->msgin_index = 0;
2795 * If this message illicited a response,
2796 * assert ATN so the target takes us to the
2797 * message out phase.
2799 if (ahc->msgout_len != 0) {
2801 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2802 ahc_print_devinfo(ahc, &devinfo);
2803 kprintf("Asserting ATN for response\n");
2806 ahc_assert_atn(ahc);
2811 if (message_done == MSGLOOP_TERMINATED) {
2815 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2816 ahc_inb(ahc, SCSIDATL);
2820 case MSG_TYPE_TARGET_MSGIN:
2824 if (ahc->msgout_len == 0)
2825 panic("Target MSGIN with no active message");
2828 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2829 ahc_print_devinfo(ahc, &devinfo);
2830 kprintf("TARGET_MSG_IN");
2835 * If we interrupted a mesgout session, the initiator
2836 * will not know this until our first REQ. So, we
2837 * only honor mesgout requests after we've sent our
2840 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2841 && ahc->msgout_index > 0) {
2844 * Change gears and see if this messages is
2845 * of interest to us or should be passed back
2849 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2850 kprintf(" Honoring ATN Request.\n");
2852 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2855 * Disable SCSI Programmed I/O during the
2856 * phase change so as to avoid phantom REQs.
2858 ahc_outb(ahc, SXFRCTL0,
2859 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2862 * Since SPIORDY asserts when ACK is asserted
2863 * for P_MSGOUT, and SPIORDY's assertion triggered
2864 * our entry into this routine, wait for ACK to
2865 * *de-assert* before changing phases.
2867 while ((ahc_inb(ahc, SCSISIGI) & ACKI) != 0)
2870 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2873 * All phase line changes require a bus
2874 * settle delay before REQ is asserted.
2875 * [SCSI SPI4 10.7.1]
2877 ahc_flush_device_writes(ahc);
2878 aic_delay(AHC_BUSSETTLE_DELAY);
2880 ahc->msgin_index = 0;
2881 /* Enable SCSI Programmed I/O to REQ for first byte */
2882 ahc_outb(ahc, SXFRCTL0,
2883 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2887 msgdone = ahc->msgout_index == ahc->msgout_len;
2889 ahc_outb(ahc, SXFRCTL0,
2890 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2896 * Present the next byte on the bus.
2899 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2900 kprintf(" byte 0x%x\n",
2901 ahc->msgout_buf[ahc->msgout_index]);
2903 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2904 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2907 case MSG_TYPE_TARGET_MSGOUT:
2913 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2914 ahc_print_devinfo(ahc, &devinfo);
2915 kprintf("TARGET_MSG_OUT");
2919 * The initiator signals that this is
2920 * the last byte by dropping ATN.
2922 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2925 * Read the latched byte, but turn off SPIOEN first
2926 * so that we don't inadvertently cause a REQ for the
2929 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2930 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2933 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2934 kprintf(" byte 0x%x\n",
2935 ahc->msgin_buf[ahc->msgin_index]);
2938 msgdone = ahc_parse_msg(ahc, &devinfo);
2939 if (msgdone == MSGLOOP_TERMINATED) {
2941 * The message is *really* done in that it caused
2942 * us to go to bus free. The sequencer has already
2943 * been reset at this point, so pull the ejection
2952 * XXX Read spec about initiator dropping ATN too soon
2953 * and use msgdone to detect it.
2955 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2956 ahc->msgin_index = 0;
2959 * If this message illicited a response, transition
2960 * to the Message in phase and send it.
2962 if (ahc->msgout_len != 0) {
2964 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2965 ahc_print_devinfo(ahc, &devinfo);
2966 kprintf(" preparing response.\n");
2969 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2972 * All phase line changes require a bus
2973 * settle delay before REQ is asserted.
2974 * [SCSI SPI4 10.7.1] When transitioning
2975 * from an OUT to an IN phase, we must
2976 * also wait a data release delay to allow
2977 * the initiator time to release the data
2978 * lines. [SCSI SPI4 10.12]
2980 ahc_flush_device_writes(ahc);
2981 aic_delay(AHC_BUSSETTLE_DELAY
2982 + AHC_DATARELEASE_DELAY);
2985 * Enable SCSI Programmed I/O. This will
2986 * immediately cause SPIORDY to assert,
2987 * and the sequencer will call our message
2990 ahc_outb(ahc, SXFRCTL0,
2991 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2992 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
2993 ahc->msgin_index = 0;
3001 /* Ask for the next byte. */
3002 ahc_outb(ahc, SXFRCTL0,
3003 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3009 panic("Unknown REQINIT message type");
3013 ahc_clear_msg_state(ahc);
3014 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
3016 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
3020 * See if we sent a particular extended message to the target.
3021 * If "full" is true, return true only if the target saw the full
3022 * message. If "full" is false, return true if the target saw at
3023 * least the first byte of the message.
3026 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
3034 while (index < ahc->msgout_len) {
3035 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
3038 end_index = index + 1 + ahc->msgout_buf[index + 1];
3039 if (ahc->msgout_buf[index+2] == msgval
3040 && type == AHCMSG_EXT) {
3043 if (ahc->msgout_index > end_index)
3045 } else if (ahc->msgout_index > index)
3049 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
3050 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
3052 /* Skip tag type and tag id or residue param*/
3055 /* Single byte message */
3056 if (type == AHCMSG_1B
3057 && ahc->msgout_buf[index] == msgval
3058 && ahc->msgout_index > index)
3070 * Wait for a complete incoming message, parse it, and respond accordingly.
3073 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3075 struct ahc_initiator_tinfo *tinfo;
3076 struct ahc_tmode_tstate *tstate;
3080 u_int targ_scsirate;
3082 done = MSGLOOP_IN_PROG;
3085 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3086 devinfo->target, &tstate);
3087 targ_scsirate = tinfo->scsirate;
3090 * Parse as much of the message as is available,
3091 * rejecting it if we don't support it. When
3092 * the entire message is available and has been
3093 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3094 * that we have parsed an entire message.
3096 * In the case of extended messages, we accept the length
3097 * byte outright and perform more checking once we know the
3098 * extended message type.
3100 switch (ahc->msgin_buf[0]) {
3101 case MSG_DISCONNECT:
3102 case MSG_SAVEDATAPOINTER:
3103 case MSG_CMDCOMPLETE:
3104 case MSG_RESTOREPOINTERS:
3105 case MSG_IGN_WIDE_RESIDUE:
3107 * End our message loop as these are messages
3108 * the sequencer handles on its own.
3110 done = MSGLOOP_TERMINATED;
3112 case MSG_MESSAGE_REJECT:
3113 response = ahc_handle_msg_reject(ahc, devinfo);
3116 done = MSGLOOP_MSGCOMPLETE;
3120 /* Wait for enough of the message to begin validation */
3121 if (ahc->msgin_index < 2)
3123 switch (ahc->msgin_buf[2]) {
3126 struct ahc_syncrate *syncrate;
3132 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3138 * Wait until we have both args before validating
3139 * and acting on this message.
3141 * Add one to MSG_EXT_SDTR_LEN to account for
3142 * the extended message preamble.
3144 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3147 period = ahc->msgin_buf[3];
3149 saved_offset = offset = ahc->msgin_buf[4];
3150 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3153 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3154 targ_scsirate & WIDEXFER,
3157 kprintf("(%s:%c:%d:%d): Received "
3158 "SDTR period %x, offset %x\n\t"
3159 "Filtered to period %x, offset %x\n",
3160 ahc_name(ahc), devinfo->channel,
3161 devinfo->target, devinfo->lun,
3162 ahc->msgin_buf[3], saved_offset,
3165 ahc_set_syncrate(ahc, devinfo,
3167 offset, ppr_options,
3168 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3172 * See if we initiated Sync Negotiation
3173 * and didn't have to fall down to async
3176 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3178 if (saved_offset != offset) {
3179 /* Went too low - force async */
3184 * Send our own SDTR in reply
3187 && devinfo->role == ROLE_INITIATOR) {
3188 kprintf("(%s:%c:%d:%d): Target "
3190 ahc_name(ahc), devinfo->channel,
3191 devinfo->target, devinfo->lun);
3193 ahc->msgout_index = 0;
3194 ahc->msgout_len = 0;
3195 ahc_construct_sdtr(ahc, devinfo,
3197 ahc->msgout_index = 0;
3200 done = MSGLOOP_MSGCOMPLETE;
3207 u_int sending_reply;
3209 sending_reply = FALSE;
3210 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3216 * Wait until we have our arg before validating
3217 * and acting on this message.
3219 * Add one to MSG_EXT_WDTR_LEN to account for
3220 * the extended message preamble.
3222 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3225 bus_width = ahc->msgin_buf[3];
3226 saved_width = bus_width;
3227 ahc_validate_width(ahc, tinfo, &bus_width,
3230 kprintf("(%s:%c:%d:%d): Received WDTR "
3231 "%x filtered to %x\n",
3232 ahc_name(ahc), devinfo->channel,
3233 devinfo->target, devinfo->lun,
3234 saved_width, bus_width);
3237 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3239 * Don't send a WDTR back to the
3240 * target, since we asked first.
3241 * If the width went higher than our
3242 * request, reject it.
3244 if (saved_width > bus_width) {
3246 kprintf("(%s:%c:%d:%d): requested %dBit "
3247 "transfers. Rejecting...\n",
3248 ahc_name(ahc), devinfo->channel,
3249 devinfo->target, devinfo->lun,
3250 8 * (0x01 << bus_width));
3255 * Send our own WDTR in reply
3258 && devinfo->role == ROLE_INITIATOR) {
3259 kprintf("(%s:%c:%d:%d): Target "
3261 ahc_name(ahc), devinfo->channel,
3262 devinfo->target, devinfo->lun);
3264 ahc->msgout_index = 0;
3265 ahc->msgout_len = 0;
3266 ahc_construct_wdtr(ahc, devinfo, bus_width);
3267 ahc->msgout_index = 0;
3269 sending_reply = TRUE;
3272 * After a wide message, we are async, but
3273 * some devices don't seem to honor this portion
3274 * of the spec. Force a renegotiation of the
3275 * sync component of our transfer agreement even
3276 * if our goal is async. By updating our width
3277 * after forcing the negotiation, we avoid
3278 * renegotiating for width.
3280 ahc_update_neg_request(ahc, devinfo, tstate,
3281 tinfo, AHC_NEG_ALWAYS);
3282 ahc_set_width(ahc, devinfo, bus_width,
3283 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3285 if (sending_reply == FALSE && reject == FALSE) {
3288 * We will always have an SDTR to send.
3290 ahc->msgout_index = 0;
3291 ahc->msgout_len = 0;
3292 ahc_build_transfer_msg(ahc, devinfo);
3293 ahc->msgout_index = 0;
3296 done = MSGLOOP_MSGCOMPLETE;
3301 struct ahc_syncrate *syncrate;
3308 u_int saved_ppr_options;
3310 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3316 * Wait until we have all args before validating
3317 * and acting on this message.
3319 * Add one to MSG_EXT_PPR_LEN to account for
3320 * the extended message preamble.
3322 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3325 period = ahc->msgin_buf[3];
3326 offset = ahc->msgin_buf[5];
3327 bus_width = ahc->msgin_buf[6];
3328 saved_width = bus_width;
3329 ppr_options = ahc->msgin_buf[7];
3331 * According to the spec, a DT only
3332 * period factor with no DT option
3333 * set implies async.
3335 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3338 saved_ppr_options = ppr_options;
3339 saved_offset = offset;
3342 * Mask out any options we don't support
3343 * on any controller. Transfer options are
3344 * only available if we are negotiating wide.
3346 ppr_options &= MSG_EXT_PPR_DT_REQ;
3350 ahc_validate_width(ahc, tinfo, &bus_width,
3352 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3355 ahc_validate_offset(ahc, tinfo, syncrate,
3359 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3361 * If we are unable to do any of the
3362 * requested options (we went too low),
3363 * then we'll have to reject the message.
3365 if (saved_width > bus_width
3366 || saved_offset != offset
3367 || saved_ppr_options != ppr_options) {
3376 if (devinfo->role != ROLE_TARGET)
3377 kprintf("(%s:%c:%d:%d): Target "
3379 ahc_name(ahc), devinfo->channel,
3380 devinfo->target, devinfo->lun);
3382 kprintf("(%s:%c:%d:%d): Initiator "
3384 ahc_name(ahc), devinfo->channel,
3385 devinfo->target, devinfo->lun);
3386 ahc->msgout_index = 0;
3387 ahc->msgout_len = 0;
3388 ahc_construct_ppr(ahc, devinfo, period, offset,
3389 bus_width, ppr_options);
3390 ahc->msgout_index = 0;
3394 kprintf("(%s:%c:%d:%d): Received PPR width %x, "
3395 "period %x, offset %x,options %x\n"
3396 "\tFiltered to width %x, period %x, "
3397 "offset %x, options %x\n",
3398 ahc_name(ahc), devinfo->channel,
3399 devinfo->target, devinfo->lun,
3400 saved_width, ahc->msgin_buf[3],
3401 saved_offset, saved_ppr_options,
3402 bus_width, period, offset, ppr_options);
3404 ahc_set_width(ahc, devinfo, bus_width,
3405 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3407 ahc_set_syncrate(ahc, devinfo,
3409 offset, ppr_options,
3410 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3412 done = MSGLOOP_MSGCOMPLETE;
3416 /* Unknown extended message. Reject it. */
3422 #ifdef AHC_TARGET_MODE
3423 case MSG_BUS_DEV_RESET:
3424 ahc_handle_devreset(ahc, devinfo,
3426 "Bus Device Reset Received",
3427 /*verbose_level*/0);
3429 done = MSGLOOP_TERMINATED;
3433 case MSG_CLEAR_QUEUE:
3437 /* Target mode messages */
3438 if (devinfo->role != ROLE_TARGET) {
3442 tag = SCB_LIST_NULL;
3443 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3444 tag = ahc_inb(ahc, INITIATOR_TAG);
3445 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3446 devinfo->lun, tag, ROLE_TARGET,
3449 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3450 if (tstate != NULL) {
3451 struct ahc_tmode_lstate* lstate;
3453 lstate = tstate->enabled_luns[devinfo->lun];
3454 if (lstate != NULL) {
3455 ahc_queue_lstate_event(ahc, lstate,
3456 devinfo->our_scsiid,
3459 ahc_send_lstate_events(ahc, lstate);
3463 done = MSGLOOP_TERMINATED;
3467 case MSG_TERM_IO_PROC:
3475 * Setup to reject the message.
3477 ahc->msgout_index = 0;
3478 ahc->msgout_len = 1;
3479 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3480 done = MSGLOOP_MSGCOMPLETE;
3484 if (done != MSGLOOP_IN_PROG && !response)
3485 /* Clear the outgoing message buffer */
3486 ahc->msgout_len = 0;
3492 * Process a message reject message.
3495 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3498 * What we care about here is if we had an
3499 * outstanding SDTR or WDTR message for this
3500 * target. If we did, this is a signal that
3501 * the target is refusing negotiation.
3504 struct ahc_initiator_tinfo *tinfo;
3505 struct ahc_tmode_tstate *tstate;
3510 scb_index = ahc_inb(ahc, SCB_TAG);
3511 scb = ahc_lookup_scb(ahc, scb_index);
3512 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3513 devinfo->our_scsiid,
3514 devinfo->target, &tstate);
3515 /* Might be necessary */
3516 last_msg = ahc_inb(ahc, LAST_MSG);
3518 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3520 * Target does not support the PPR message.
3521 * Attempt to negotiate SPI-2 style.
3524 kprintf("(%s:%c:%d:%d): PPR Rejected. "
3525 "Trying WDTR/SDTR\n",
3526 ahc_name(ahc), devinfo->channel,
3527 devinfo->target, devinfo->lun);
3529 tinfo->goal.ppr_options = 0;
3530 tinfo->curr.transport_version = 2;
3531 tinfo->goal.transport_version = 2;
3532 ahc->msgout_index = 0;
3533 ahc->msgout_len = 0;
3534 ahc_build_transfer_msg(ahc, devinfo);
3535 ahc->msgout_index = 0;
3537 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3539 /* note 8bit xfers */
3540 kprintf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3541 "8bit transfers\n", ahc_name(ahc),
3542 devinfo->channel, devinfo->target, devinfo->lun);
3543 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3544 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3547 * No need to clear the sync rate. If the target
3548 * did not accept the command, our syncrate is
3549 * unaffected. If the target started the negotiation,
3550 * but rejected our response, we already cleared the
3551 * sync rate before sending our WDTR.
3553 if (tinfo->goal.offset != tinfo->curr.offset) {
3555 /* Start the sync negotiation */
3556 ahc->msgout_index = 0;
3557 ahc->msgout_len = 0;
3558 ahc_build_transfer_msg(ahc, devinfo);
3559 ahc->msgout_index = 0;
3562 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3563 /* note asynch xfers and clear flag */
3564 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3565 /*offset*/0, /*ppr_options*/0,
3566 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3568 kprintf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3569 "Using asynchronous transfers\n",
3570 ahc_name(ahc), devinfo->channel,
3571 devinfo->target, devinfo->lun);
3572 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3576 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3578 if (tag_type == MSG_SIMPLE_TASK) {
3579 kprintf("(%s:%c:%d:%d): refuses tagged commands. "
3580 "Performing non-tagged I/O\n", ahc_name(ahc),
3581 devinfo->channel, devinfo->target, devinfo->lun);
3582 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE);
3585 kprintf("(%s:%c:%d:%d): refuses %s tagged commands. "
3586 "Performing simple queue tagged I/O only\n",
3587 ahc_name(ahc), devinfo->channel, devinfo->target,
3588 devinfo->lun, tag_type == MSG_ORDERED_TASK
3589 ? "ordered" : "head of queue");
3590 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC);
3595 * Resend the identify for this CCB as the target
3596 * may believe that the selection is invalid otherwise.
3598 ahc_outb(ahc, SCB_CONTROL,
3599 ahc_inb(ahc, SCB_CONTROL) & mask);
3600 scb->hscb->control &= mask;
3601 aic_set_transaction_tag(scb, /*enabled*/FALSE,
3602 /*type*/MSG_SIMPLE_TASK);
3603 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3604 ahc_assert_atn(ahc);
3607 * This transaction is now at the head of
3608 * the untagged queue for this target.
3610 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3611 struct scb_tailq *untagged_q;
3614 &(ahc->untagged_queues[devinfo->target_offset]);
3615 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3616 scb->flags |= SCB_UNTAGGEDQ;
3618 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3622 * Requeue all tagged commands for this target
3623 * currently in our posession so they can be
3624 * converted to untagged commands.
3626 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3627 SCB_GET_CHANNEL(ahc, scb),
3628 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3629 ROLE_INITIATOR, CAM_REQUEUE_REQ,
3633 * Otherwise, we ignore it.
3635 kprintf("%s:%c:%d: Message reject for %x -- ignored\n",
3636 ahc_name(ahc), devinfo->channel, devinfo->target,
3643 * Process an ingnore wide residue message.
3646 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3651 scb_index = ahc_inb(ahc, SCB_TAG);
3652 scb = ahc_lookup_scb(ahc, scb_index);
3654 * XXX Actually check data direction in the sequencer?
3655 * Perhaps add datadir to some spare bits in the hscb?
3657 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3658 || aic_get_transfer_dir(scb) != CAM_DIR_IN) {
3660 * Ignore the message if we haven't
3661 * seen an appropriate data phase yet.
3665 * If the residual occurred on the last
3666 * transfer and the transfer request was
3667 * expected to end on an odd count, do
3668 * nothing. Otherwise, subtract a byte
3669 * and update the residual count accordingly.
3673 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3674 if ((sgptr & SG_LIST_NULL) != 0
3675 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
3677 * If the residual occurred on the last
3678 * transfer and the transfer request was
3679 * expected to end on an odd count, do
3683 struct ahc_dma_seg *sg;
3688 /* Pull in all of the sgptr */
3689 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
3690 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
3692 if ((sgptr & SG_LIST_NULL) != 0) {
3694 * The residual data count is not updated
3695 * for the command run to completion case.
3696 * Explicitly zero the count.
3698 data_cnt &= ~AHC_SG_LEN_MASK;
3701 data_addr = ahc_inl(ahc, SHADDR);
3705 sgptr &= SG_PTR_MASK;
3707 sg = ahc_sg_bus_to_virt(scb, sgptr);
3710 * The residual sg ptr points to the next S/G
3711 * to load so we must go back one.
3714 sglen = aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
3715 if (sg != scb->sg_list
3716 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3719 sglen = aic_le32toh(sg->len);
3721 * Preserve High Address and SG_LIST bits
3722 * while setting the count to 1.
3724 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3725 data_addr = aic_le32toh(sg->addr)
3726 + (sglen & AHC_SG_LEN_MASK) - 1;
3729 * Increment sg so it points to the
3733 sgptr = ahc_sg_virt_to_bus(scb, sg);
3735 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3736 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3738 * Toggle the "oddness" of the transfer length
3739 * to handle this mid-transfer ignore wide
3740 * residue. This ensures that the oddness is
3741 * correct for subsequent data transfers.
3743 ahc_outb(ahc, SCB_LUN,
3744 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
3751 * Reinitialize the data pointers for the active transfer
3752 * based on its current residual.
3755 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3758 struct ahc_dma_seg *sg;
3764 scb_index = ahc_inb(ahc, SCB_TAG);
3765 scb = ahc_lookup_scb(ahc, scb_index);
3766 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3767 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3768 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3769 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3771 sgptr &= SG_PTR_MASK;
3772 sg = ahc_sg_bus_to_virt(scb, sgptr);
3774 /* The residual sg_ptr always points to the next sg */
3777 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3778 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3779 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3781 dataptr = aic_le32toh(sg->addr)
3782 + (aic_le32toh(sg->len) & AHC_SG_LEN_MASK)
3784 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3787 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3788 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3789 ahc_outb(ahc, HADDR,
3790 (aic_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3791 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3793 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3794 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3795 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3796 ahc_outb(ahc, HADDR, dataptr);
3797 ahc_outb(ahc, HCNT + 2, resid >> 16);
3798 ahc_outb(ahc, HCNT + 1, resid >> 8);
3799 ahc_outb(ahc, HCNT, resid);
3800 if ((ahc->features & AHC_ULTRA2) == 0) {
3801 ahc_outb(ahc, STCNT + 2, resid >> 16);
3802 ahc_outb(ahc, STCNT + 1, resid >> 8);
3803 ahc_outb(ahc, STCNT, resid);
3808 * Handle the effects of issuing a bus device reset message.
3811 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3812 cam_status status, char *message, int verbose_level)
3814 #ifdef AHC_TARGET_MODE
3815 struct ahc_tmode_tstate* tstate;
3820 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3821 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3824 #ifdef AHC_TARGET_MODE
3826 * Send an immediate notify ccb to all target mord peripheral
3827 * drivers affected by this action.
3829 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3830 if (tstate != NULL) {
3831 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3832 struct ahc_tmode_lstate* lstate;
3834 lstate = tstate->enabled_luns[lun];
3838 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3839 MSG_BUS_DEV_RESET, /*arg*/0);
3840 ahc_send_lstate_events(ahc, lstate);
3846 * Go back to async/narrow transfers and renegotiate.
3848 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3849 AHC_TRANS_CUR, /*paused*/TRUE);
3850 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3851 /*period*/0, /*offset*/0, /*ppr_options*/0,
3852 AHC_TRANS_CUR, /*paused*/TRUE);
3854 if (status != CAM_SEL_TIMEOUT)
3855 ahc_send_async(ahc, devinfo->channel, devinfo->target,
3856 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
3859 && (verbose_level <= bootverbose))
3860 kprintf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3861 message, devinfo->channel, devinfo->target, found);
3864 #ifdef AHC_TARGET_MODE
3866 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3871 * To facilitate adding multiple messages together,
3872 * each routine should increment the index and len
3873 * variables instead of setting them explicitly.
3875 ahc->msgout_index = 0;
3876 ahc->msgout_len = 0;
3878 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3879 ahc_build_transfer_msg(ahc, devinfo);
3881 panic("ahc_intr: AWAITING target message with no message");
3883 ahc->msgout_index = 0;
3884 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3887 /**************************** Initialization **********************************/
3889 * Allocate a controller structure for a new device
3890 * and perform initial initializion.
3893 ahc_alloc(void *platform_arg, char *name)
3895 struct ahc_softc *ahc;
3898 #if !defined(__DragonFly__) && !defined(__FreeBSD__)
3899 ahc = kmalloc(sizeof(*ahc), M_DEVBUF, M_INTWAIT);
3901 ahc = device_get_softc((device_t)platform_arg);
3903 memset(ahc, 0, sizeof(*ahc));
3904 ahc->seep_config = kmalloc(sizeof(*ahc->seep_config),
3905 M_DEVBUF, M_INTWAIT);
3906 LIST_INIT(&ahc->pending_scbs);
3907 LIST_INIT(&ahc->timedout_scbs);
3908 /* We don't know our unit number until the OSM sets it */
3911 ahc->description = NULL;
3913 ahc->channel_b = 'B';
3914 ahc->chip = AHC_NONE;
3915 ahc->features = AHC_FENONE;
3916 ahc->bugs = AHC_BUGNONE;
3917 ahc->flags = AHC_FNONE;
3919 * Default to all error reporting enabled with the
3920 * sequencer operating at its fastest speed.
3921 * The bus attach code may modify this.
3923 ahc->seqctl = FASTMODE;
3925 for (i = 0; i < AHC_NUM_TARGETS; i++)
3926 TAILQ_INIT(&ahc->untagged_queues[i]);
3927 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3936 ahc_softc_init(struct ahc_softc *ahc)
3939 /* The IRQMS bit is only valid on VL and EISA chips */
3940 if ((ahc->chip & AHC_PCI) == 0)
3941 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
3944 ahc->pause = ahc->unpause | PAUSE;
3945 /* XXX The shared scb data stuff should be deprecated */
3946 if (ahc->scb_data == NULL) {
3947 ahc->scb_data = kmalloc(sizeof(*ahc->scb_data),
3948 M_DEVBUF, M_INTWAIT | M_ZERO);
3955 ahc_softc_insert(struct ahc_softc *ahc)
3957 struct ahc_softc *list_ahc;
3959 #if AIC_PCI_CONFIG > 0
3961 * Second Function PCI devices need to inherit some
3962 * settings from function 0.
3964 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI
3965 && (ahc->features & AHC_MULTI_FUNC) != 0) {
3966 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3967 aic_dev_softc_t list_pci;
3968 aic_dev_softc_t pci;
3970 list_pci = list_ahc->dev_softc;
3971 pci = ahc->dev_softc;
3972 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci)
3973 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) {
3974 struct ahc_softc *master;
3975 struct ahc_softc *slave;
3977 if (aic_get_pci_function(list_pci) == 0) {
3984 slave->flags &= ~AHC_BIOS_ENABLED;
3986 master->flags & AHC_BIOS_ENABLED;
3987 slave->flags &= ~AHC_PRIMARY_CHANNEL;
3989 master->flags & AHC_PRIMARY_CHANNEL;
3997 * Insertion sort into our list of softcs.
3999 list_ahc = TAILQ_FIRST(&ahc_tailq);
4000 while (list_ahc != NULL
4001 && ahc_softc_comp(ahc, list_ahc) <= 0)
4002 list_ahc = TAILQ_NEXT(list_ahc, links);
4003 if (list_ahc != NULL)
4004 TAILQ_INSERT_BEFORE(list_ahc, ahc, links);
4006 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links);
4011 ahc_set_unit(struct ahc_softc *ahc, int unit)
4017 ahc_set_name(struct ahc_softc *ahc, char *name)
4019 if (ahc->name != NULL)
4020 kfree(ahc->name, M_DEVBUF);
4025 ahc_free(struct ahc_softc *ahc)
4029 ahc_terminate_recovery_thread(ahc);
4030 switch (ahc->init_level) {
4036 aic_dmamap_unload(ahc, ahc->shared_data_dmat,
4037 ahc->shared_data_dmamap);
4040 aic_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
4041 ahc->shared_data_dmamap);
4042 aic_dmamap_destroy(ahc, ahc->shared_data_dmat,
4043 ahc->shared_data_dmamap);
4046 aic_dma_tag_destroy(ahc, ahc->shared_data_dmat);
4049 aic_dma_tag_destroy(ahc, ahc->buffer_dmat);
4057 aic_dma_tag_destroy(ahc, ahc->parent_dmat);
4059 ahc_platform_free(ahc);
4060 ahc_fini_scbdata(ahc);
4061 for (i = 0; i < AHC_NUM_TARGETS; i++) {
4062 struct ahc_tmode_tstate *tstate;
4064 tstate = ahc->enabled_targets[i];
4065 if (tstate != NULL) {
4066 #ifdef AHC_TARGET_MODE
4069 for (j = 0; j < AHC_NUM_LUNS; j++) {
4070 struct ahc_tmode_lstate *lstate;
4072 lstate = tstate->enabled_luns[j];
4073 if (lstate != NULL) {
4074 xpt_free_path(lstate->path);
4075 kfree(lstate, M_DEVBUF);
4079 kfree(tstate, M_DEVBUF);
4082 #ifdef AHC_TARGET_MODE
4083 if (ahc->black_hole != NULL) {
4084 xpt_free_path(ahc->black_hole->path);
4085 kfree(ahc->black_hole, M_DEVBUF);
4088 if (ahc->name != NULL)
4089 kfree(ahc->name, M_DEVBUF);
4090 if (ahc->seep_config != NULL)
4091 kfree(ahc->seep_config, M_DEVBUF);
4092 #if !defined(__DragonFly__) && !defined(__FreeBSD__)
4093 kfree(ahc, M_DEVBUF);
4099 ahc_shutdown(void *arg)
4101 struct ahc_softc *ahc;
4104 ahc = (struct ahc_softc *)arg;
4106 /* This will reset most registers to 0, but not all */
4107 ahc_reset(ahc, /*reinit*/FALSE);
4108 ahc_outb(ahc, SCSISEQ, 0);
4109 ahc_outb(ahc, SXFRCTL0, 0);
4110 ahc_outb(ahc, DSPCISTATUS, 0);
4112 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4113 ahc_outb(ahc, i, 0);
4117 * Reset the controller and record some information about it
4118 * that is only available just after a reset. If "reinit" is
4119 * non-zero, this reset occured after initial configuration
4120 * and the caller requests that the chip be fully reinitialized
4121 * to a runable state. Chip interrupts are *not* enabled after
4122 * a reinitialization. The caller must enable interrupts via
4123 * ahc_intr_enable().
4126 ahc_reset(struct ahc_softc *ahc, int reinit)
4129 u_int sxfrctl1_a, sxfrctl1_b;
4134 * Preserve the value of the SXFRCTL1 register for all channels.
4135 * It contains settings that affect termination and we don't want
4136 * to disturb the integrity of the bus.
4140 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4144 * Save channel B's settings in case this chip
4145 * is setup for TWIN channel operation.
4147 sblkctl = ahc_inb(ahc, SBLKCTL);
4148 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4149 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4150 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4152 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4154 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4157 * Ensure that the reset has finished. We delay 1000us
4158 * prior to reading the register to make sure the chip
4159 * has sufficiently completed its reset to handle register
4165 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4168 kprintf("%s: WARNING - Failed chip reset! "
4169 "Trying to initialize anyway.\n", ahc_name(ahc));
4171 ahc_outb(ahc, HCNTRL, ahc->pause);
4173 /* Determine channel configuration */
4174 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4175 /* No Twin Channel PCI cards */
4176 if ((ahc->chip & AHC_PCI) != 0)
4177 sblkctl &= ~SELBUSB;
4180 /* Single Narrow Channel */
4184 ahc->features |= AHC_WIDE;
4188 ahc->features |= AHC_TWIN;
4191 kprintf(" Unsupported adapter type. Ignoring\n");
4198 * We must always initialize STPWEN to 1 before we
4199 * restore the saved values. STPWEN is initialized
4200 * to a tri-state condition which can only be cleared
4203 if ((ahc->features & AHC_TWIN) != 0) {
4206 sblkctl = ahc_inb(ahc, SBLKCTL);
4207 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4208 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4209 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4211 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4216 * If a recovery action has forced a chip reset,
4217 * re-initialize the chip to our liking.
4219 error = ahc->bus_chip_init(ahc);
4229 * Determine the number of SCBs available on the controller
4232 ahc_probe_scbs(struct ahc_softc *ahc) {
4235 for (i = 0; i < AHC_SCB_MAX; i++) {
4237 ahc_outb(ahc, SCBPTR, i);
4238 ahc_outb(ahc, SCB_BASE, i);
4239 if (ahc_inb(ahc, SCB_BASE) != i)
4241 ahc_outb(ahc, SCBPTR, 0);
4242 if (ahc_inb(ahc, SCB_BASE) != 0)
4249 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4253 baddr = (bus_addr_t *)arg;
4254 *baddr = segs->ds_addr;
4258 ahc_build_free_scb_list(struct ahc_softc *ahc)
4264 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4267 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4270 ahc_outb(ahc, SCBPTR, i);
4273 * Touch all SCB bytes to avoid parity errors
4274 * should one of our debugging routines read
4275 * an otherwise uninitiatlized byte.
4277 for (j = 0; j < scbsize; j++)
4278 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4280 /* Clear the control byte. */
4281 ahc_outb(ahc, SCB_CONTROL, 0);
4283 /* Set the next pointer */
4284 if ((ahc->flags & AHC_PAGESCBS) != 0)
4285 ahc_outb(ahc, SCB_NEXT, i+1);
4287 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4289 /* Make the tag number, SCSIID, and lun invalid */
4290 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4291 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4292 ahc_outb(ahc, SCB_LUN, 0xFF);
4295 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4296 /* SCB 0 heads the free list. */
4297 ahc_outb(ahc, FREE_SCBH, 0);
4300 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4303 /* Make sure that the last SCB terminates the free list */
4304 ahc_outb(ahc, SCBPTR, i-1);
4305 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4309 ahc_init_scbdata(struct ahc_softc *ahc)
4311 struct scb_data *scb_data;
4313 scb_data = ahc->scb_data;
4314 SLIST_INIT(&scb_data->free_scbs);
4315 SLIST_INIT(&scb_data->sg_maps);
4317 /* Allocate SCB resources */
4318 scb_data->scbarray = kmalloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
4319 M_DEVBUF, M_INTWAIT | M_ZERO);
4321 /* Determine the number of hardware SCBs and initialize them */
4323 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4324 if (ahc->scb_data->maxhscbs == 0) {
4325 kprintf("%s: No SCB space found\n", ahc_name(ahc));
4330 * Create our DMA tags. These tags define the kinds of device
4331 * accessible memory allocations and memory mappings we will
4332 * need to perform during normal operation.
4334 * Unless we need to further restrict the allocation, we rely
4335 * on the restrictions of the parent dmat, hence the common
4336 * use of MAXADDR and MAXSIZE.
4339 /* DMA tag for our hardware scb structures */
4340 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4341 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4342 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4343 /*highaddr*/BUS_SPACE_MAXADDR,
4344 /*filter*/NULL, /*filterarg*/NULL,
4345 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4347 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4348 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4352 scb_data->init_level++;
4354 /* Allocation for our hscbs */
4355 if (aic_dmamem_alloc(ahc, scb_data->hscb_dmat,
4356 (void **)&scb_data->hscbs,
4357 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
4361 scb_data->init_level++;
4363 /* And permanently map them */
4364 aic_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4366 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4367 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4369 scb_data->init_level++;
4371 /* DMA tag for our sense buffers */
4372 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4373 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4374 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4375 /*highaddr*/BUS_SPACE_MAXADDR,
4376 /*filter*/NULL, /*filterarg*/NULL,
4377 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4379 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4380 /*flags*/0, &scb_data->sense_dmat) != 0) {
4384 scb_data->init_level++;
4387 if (aic_dmamem_alloc(ahc, scb_data->sense_dmat,
4388 (void **)&scb_data->sense,
4389 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4393 scb_data->init_level++;
4395 /* And permanently map them */
4396 aic_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4398 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4399 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4401 scb_data->init_level++;
4403 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4404 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4405 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4406 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4407 /*highaddr*/BUS_SPACE_MAXADDR,
4408 /*filter*/NULL, /*filterarg*/NULL,
4409 PAGE_SIZE, /*nsegments*/1,
4410 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4411 /*flags*/0, &scb_data->sg_dmat) != 0) {
4415 scb_data->init_level++;
4417 /* Perform initial CCB allocation */
4418 memset(scb_data->hscbs, 0,
4419 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4420 while (ahc_alloc_scbs(ahc) != 0)
4423 if (scb_data->numscbs == 0) {
4424 kprintf("%s: ahc_init_scbdata - "
4425 "Unable to allocate initial scbs\n",
4431 * Reserve the next queued SCB.
4433 ahc->next_queued_scb = ahc_get_scb(ahc);
4436 * Note that we were successful
4446 ahc_fini_scbdata(struct ahc_softc *ahc)
4448 struct scb_data *scb_data;
4450 scb_data = ahc->scb_data;
4451 if (scb_data == NULL)
4454 switch (scb_data->init_level) {
4458 struct sg_map_node *sg_map;
4460 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4461 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4462 aic_dmamap_unload(ahc, scb_data->sg_dmat,
4464 aic_dmamem_free(ahc, scb_data->sg_dmat,
4467 kfree(sg_map, M_DEVBUF);
4469 aic_dma_tag_destroy(ahc, scb_data->sg_dmat);
4472 aic_dmamap_unload(ahc, scb_data->sense_dmat,
4473 scb_data->sense_dmamap);
4475 aic_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4476 scb_data->sense_dmamap);
4477 aic_dmamap_destroy(ahc, scb_data->sense_dmat,
4478 scb_data->sense_dmamap);
4480 aic_dma_tag_destroy(ahc, scb_data->sense_dmat);
4482 aic_dmamap_unload(ahc, scb_data->hscb_dmat,
4483 scb_data->hscb_dmamap);
4485 aic_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4486 scb_data->hscb_dmamap);
4487 aic_dmamap_destroy(ahc, scb_data->hscb_dmat,
4488 scb_data->hscb_dmamap);
4490 aic_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4495 if (scb_data->scbarray != NULL)
4496 kfree(scb_data->scbarray, M_DEVBUF);
4500 ahc_alloc_scbs(struct ahc_softc *ahc)
4502 struct scb_data *scb_data;
4503 struct scb *next_scb;
4504 struct sg_map_node *sg_map;
4505 bus_addr_t physaddr;
4506 struct ahc_dma_seg *segs;
4510 scb_data = ahc->scb_data;
4511 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4512 /* Can't allocate any more */
4515 next_scb = &scb_data->scbarray[scb_data->numscbs];
4517 sg_map = kmalloc(sizeof(*sg_map), M_DEVBUF, M_INTWAIT);
4519 /* Allocate S/G space for the next batch of SCBS */
4520 if (aic_dmamem_alloc(ahc, scb_data->sg_dmat,
4521 (void **)&sg_map->sg_vaddr,
4522 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
4523 kfree(sg_map, M_DEVBUF);
4527 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4529 aic_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4530 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4531 &sg_map->sg_physaddr, /*flags*/0);
4533 segs = sg_map->sg_vaddr;
4534 physaddr = sg_map->sg_physaddr;
4536 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4537 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4538 for (i = 0; i < newcount; i++) {
4539 struct scb_platform_data *pdata;
4543 pdata = kmalloc(sizeof(*pdata), M_DEVBUF, M_INTWAIT);
4544 next_scb->platform_data = pdata;
4545 next_scb->sg_map = sg_map;
4546 next_scb->sg_list = segs;
4548 * The sequencer always starts with the second entry.
4549 * The first entry is embedded in the scb.
4551 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4552 next_scb->ahc_softc = ahc;
4553 next_scb->flags = SCB_FLAG_NONE;
4555 error = aic_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
4560 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4561 next_scb->hscb->tag = ahc->scb_data->numscbs;
4562 aic_timer_init(&next_scb->io_timer);
4563 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4564 next_scb, links.sle);
4566 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4568 ahc->scb_data->numscbs++;
4574 ahc_controller_info(struct ahc_softc *ahc, char *buf)
4578 len = ksprintf(buf, "%s: ",
4579 ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4581 if ((ahc->features & AHC_TWIN) != 0) {
4582 len = ksprintf(buf, "Twin Channel, A SCSI Id=%d, "
4583 "B SCSI Id=%d, primary %c, ",
4584 ahc->our_id, ahc->our_id_b,
4585 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4591 if ((ahc->features & AHC_ULTRA) != 0) {
4593 } else if ((ahc->features & AHC_DT) != 0) {
4594 speed = "Ultra160 ";
4595 } else if ((ahc->features & AHC_ULTRA2) != 0) {
4598 if ((ahc->features & AHC_WIDE) != 0) {
4603 len = ksprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
4604 speed, type, ahc->channel, ahc->our_id);
4608 if ((ahc->flags & AHC_PAGESCBS) != 0)
4609 ksprintf(buf, "%d/%d SCBs",
4610 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
4612 ksprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
4616 ahc_chip_init(struct ahc_softc *ahc)
4622 u_int scsiseq_template;
4625 ahc_outb(ahc, SEQ_FLAGS, 0);
4626 ahc_outb(ahc, SEQ_FLAGS2, 0);
4628 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4629 if (ahc->features & AHC_TWIN) {
4632 * Setup Channel B first.
4634 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4635 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4636 ahc_outb(ahc, SCSIID, ahc->our_id_b);
4637 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4638 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4639 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4640 if ((ahc->features & AHC_ULTRA2) != 0)
4641 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4642 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4643 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4645 /* Select Channel A */
4646 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4648 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4649 if ((ahc->features & AHC_ULTRA2) != 0)
4650 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4652 ahc_outb(ahc, SCSIID, ahc->our_id);
4653 scsi_conf = ahc_inb(ahc, SCSICONF);
4654 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4656 |ENSTIMER|ACTNEGEN);
4657 if ((ahc->features & AHC_ULTRA2) != 0)
4658 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4659 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4660 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4662 /* There are no untagged SCBs active yet. */
4663 for (i = 0; i < 16; i++) {
4664 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4665 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4669 * The SCB based BTT allows an entry per
4670 * target and lun pair.
4672 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4673 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4677 /* All of our queues are empty */
4678 for (i = 0; i < 256; i++)
4679 ahc->qoutfifo[i] = SCB_LIST_NULL;
4680 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4682 for (i = 0; i < 256; i++)
4683 ahc->qinfifo[i] = SCB_LIST_NULL;
4685 if ((ahc->features & AHC_MULTI_TID) != 0) {
4686 ahc_outb(ahc, TARGID, 0);
4687 ahc_outb(ahc, TARGID + 1, 0);
4691 * Tell the sequencer where it can find our arrays in memory.
4693 physaddr = ahc->scb_data->hscb_busaddr;
4694 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4695 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4696 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4697 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4699 physaddr = ahc->shared_data_busaddr;
4700 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4701 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4702 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4703 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4706 * Initialize the group code to command length table.
4707 * This overrides the values in TARG_SCSIRATE, so only
4708 * setup the table after we have processed that information.
4710 ahc_outb(ahc, CMDSIZE_TABLE, 5);
4711 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4712 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4713 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4714 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4715 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4716 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4717 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4719 if ((ahc->features & AHC_HS_MAILBOX) != 0)
4720 ahc_outb(ahc, HS_MAILBOX, 0);
4722 /* Tell the sequencer of our initial queue positions */
4723 if ((ahc->features & AHC_TARGETMODE) != 0) {
4724 ahc->tqinfifonext = 1;
4725 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4726 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4728 ahc->qinfifonext = 0;
4729 ahc->qoutfifonext = 0;
4730 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4731 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4732 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
4733 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
4734 ahc_outb(ahc, SDSCB_QOFF, 0);
4736 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4737 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
4738 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
4741 /* We don't have any waiting selections */
4742 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4744 /* Our disconnection list is empty too */
4745 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4747 /* Message out buffer starts empty */
4748 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4751 * Setup the allowed SCSI Sequences based on operational mode.
4752 * If we are a target, we'll enalbe select in operations once
4753 * we've had a lun enabled.
4755 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4756 if ((ahc->flags & AHC_INITIATORROLE) != 0)
4757 scsiseq_template |= ENRSELI;
4758 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4760 /* Initialize our list of free SCBs. */
4761 ahc_build_free_scb_list(ahc);
4764 * Tell the sequencer which SCB will be the next one it receives.
4766 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4769 * Load the Sequencer program and Enable the adapter
4773 kprintf("%s: Downloading Sequencer Program...",
4776 error = ahc_loadseq(ahc);
4780 if ((ahc->features & AHC_ULTRA2) != 0) {
4784 * Wait for up to 500ms for our transceivers
4785 * to settle. If the adapter does not have
4786 * a cable attached, the transceivers may
4787 * never settle, so don't complain if we
4791 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4800 * Start the board, ready for normal operation
4803 ahc_init(struct ahc_softc *ahc)
4812 size_t driver_data_size;
4815 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
4816 ahc->flags |= AHC_SEQUENCER_DEBUG;
4819 #ifdef AHC_PRINT_SRAM
4820 kprintf("Scratch Ram:");
4821 for (i = 0x20; i < 0x5f; i++) {
4822 if (((i % 8) == 0) && (i != 0)) {
4825 kprintf (" 0x%x", ahc_inb(ahc, i));
4827 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4828 for (i = 0x70; i < 0x7f; i++) {
4829 if (((i % 8) == 0) && (i != 0)) {
4832 kprintf (" 0x%x", ahc_inb(ahc, i));
4837 * Reading uninitialized scratch ram may
4838 * generate parity errors.
4840 ahc_outb(ahc, CLRINT, CLRPARERR);
4841 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
4846 * Assume we have a board at this stage and it has been reset.
4848 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4849 ahc->our_id = ahc->our_id_b = 7;
4852 * Default to allowing initiator operations.
4854 ahc->flags |= AHC_INITIATORROLE;
4857 * Only allow target mode features if this unit has them enabled.
4859 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4860 ahc->features &= ~AHC_TARGETMODE;
4863 /* DMA tag for mapping buffers into device visible space. */
4864 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4865 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4866 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
4867 ? (bus_addr_t)0x7FFFFFFFFFULL
4868 : BUS_SPACE_MAXADDR_32BIT,
4869 /*highaddr*/BUS_SPACE_MAXADDR,
4870 /*filter*/NULL, /*filterarg*/NULL,
4871 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
4872 /*nsegments*/AHC_NSEG,
4873 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4874 /*flags*/BUS_DMA_ALLOCNOW,
4875 &ahc->buffer_dmat) != 0) {
4883 * DMA tag for our command fifos and other data in system memory
4884 * the card's sequencer must be able to access. For initiator
4885 * roles, we need to allocate space for the qinfifo and qoutfifo.
4886 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4887 * When providing for the target mode role, we must additionally
4888 * provide space for the incoming target command fifo and an extra
4889 * byte to deal with a dma bug in some chip versions.
4891 driver_data_size = 2 * 256 * sizeof(uint8_t);
4892 if ((ahc->features & AHC_TARGETMODE) != 0)
4893 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4894 + /*DMA WideOdd Bug Buffer*/1;
4895 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4896 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4897 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4898 /*highaddr*/BUS_SPACE_MAXADDR,
4899 /*filter*/NULL, /*filterarg*/NULL,
4902 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4903 /*flags*/0, &ahc->shared_data_dmat) != 0) {
4909 /* Allocation of driver data */
4910 if (aic_dmamem_alloc(ahc, ahc->shared_data_dmat,
4911 (void **)&ahc->qoutfifo,
4912 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) {
4918 /* And permanently map it in */
4919 aic_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
4920 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
4921 &ahc->shared_data_busaddr, /*flags*/0);
4923 if ((ahc->features & AHC_TARGETMODE) != 0) {
4924 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4925 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4926 ahc->dma_bug_buf = ahc->shared_data_busaddr
4927 + driver_data_size - 1;
4928 /* All target command blocks start out invalid. */
4929 for (i = 0; i < AHC_TMODE_CMDS; i++)
4930 ahc->targetcmds[i].cmd_valid = 0;
4931 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4932 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4934 ahc->qinfifo = &ahc->qoutfifo[256];
4938 /* Allocate SCB data now that buffer_dmat is initialized */
4939 if (ahc->scb_data->maxhscbs == 0)
4940 if (ahc_init_scbdata(ahc) != 0)
4944 * Allocate a tstate to house information for our
4945 * initiator presence on the bus as well as the user
4946 * data for any target mode initiator.
4948 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4949 kprintf("%s: unable to allocate ahc_tmode_tstate. "
4950 "Failing attach\n", ahc_name(ahc));
4954 if ((ahc->features & AHC_TWIN) != 0) {
4955 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4956 kprintf("%s: unable to allocate ahc_tmode_tstate. "
4957 "Failing attach\n", ahc_name(ahc));
4963 * Fire up a recovery thread for this controller.
4965 error = ahc_spawn_recovery_thread(ahc);
4969 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
4970 ahc->flags |= AHC_PAGESCBS;
4972 ahc->flags &= ~AHC_PAGESCBS;
4976 if (ahc_debug & AHC_SHOW_MISC) {
4977 kprintf("%s: hardware scb %u bytes; kernel scb %u bytes; "
4978 "ahc_dma %u bytes\n",
4980 (u_int)sizeof(struct hardware_scb),
4981 (u_int)sizeof(struct scb),
4982 (u_int)sizeof(struct ahc_dma_seg));
4984 #endif /* AHC_DEBUG */
4987 * Look at the information that board initialization or
4988 * the board bios has left us.
4990 if (ahc->features & AHC_TWIN) {
4991 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4992 if ((scsi_conf & RESET_SCSI) != 0
4993 && (ahc->flags & AHC_INITIATORROLE) != 0)
4994 ahc->flags |= AHC_RESET_BUS_B;
4997 scsi_conf = ahc_inb(ahc, SCSICONF);
4998 if ((scsi_conf & RESET_SCSI) != 0
4999 && (ahc->flags & AHC_INITIATORROLE) != 0)
5000 ahc->flags |= AHC_RESET_BUS_A;
5003 tagenable = ALL_TARGETS_MASK;
5005 /* Grab the disconnection disable table and invert it for our needs */
5006 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
5007 kprintf("%s: Host Adapter Bios disabled. Using default SCSI "
5008 "device parameters\n", ahc_name(ahc));
5009 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
5010 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
5011 discenable = ALL_TARGETS_MASK;
5012 if ((ahc->features & AHC_ULTRA) != 0)
5013 ultraenb = ALL_TARGETS_MASK;
5015 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
5016 | ahc_inb(ahc, DISC_DSB));
5017 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
5018 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
5019 | ahc_inb(ahc, ULTRA_ENB);
5022 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
5025 for (i = 0; i <= max_targ; i++) {
5026 struct ahc_initiator_tinfo *tinfo;
5027 struct ahc_tmode_tstate *tstate;
5033 our_id = ahc->our_id;
5035 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
5037 our_id = ahc->our_id_b;
5040 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
5041 target_id, &tstate);
5042 /* Default to async narrow across the board */
5043 memset(tinfo, 0, sizeof(*tinfo));
5044 if (ahc->flags & AHC_USEDEFAULTS) {
5045 if ((ahc->features & AHC_WIDE) != 0)
5046 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5049 * These will be truncated when we determine the
5050 * connection type we have with the target.
5052 tinfo->user.period = ahc_syncrates->period;
5053 tinfo->user.offset = MAX_OFFSET;
5058 /* Take the settings leftover in scratch RAM. */
5059 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
5061 if ((ahc->features & AHC_ULTRA2) != 0) {
5065 if ((scsirate & SOFS) == 0x0F) {
5067 * Haven't negotiated yet,
5068 * so the format is different.
5070 scsirate = (scsirate & SXFR) >> 4
5073 | (scsirate & WIDEXFER);
5074 offset = MAX_OFFSET_ULTRA2;
5076 offset = ahc_inb(ahc, TARG_OFFSET + i);
5077 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
5078 /* Set to the lowest sync rate, 5MHz */
5080 maxsync = AHC_SYNCRATE_ULTRA2;
5081 if ((ahc->features & AHC_DT) != 0)
5082 maxsync = AHC_SYNCRATE_DT;
5083 tinfo->user.period =
5084 ahc_find_period(ahc, scsirate, maxsync);
5086 tinfo->user.period = 0;
5088 tinfo->user.offset = MAX_OFFSET;
5089 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
5090 && (ahc->features & AHC_DT) != 0)
5091 tinfo->user.ppr_options =
5093 } else if ((scsirate & SOFS) != 0) {
5094 if ((scsirate & SXFR) == 0x40
5095 && (ultraenb & mask) != 0) {
5096 /* Treat 10MHz as a non-ultra speed */
5100 tinfo->user.period =
5101 ahc_find_period(ahc, scsirate,
5103 ? AHC_SYNCRATE_ULTRA
5104 : AHC_SYNCRATE_FAST);
5105 if (tinfo->user.period != 0)
5106 tinfo->user.offset = MAX_OFFSET;
5108 if (tinfo->user.period == 0)
5109 tinfo->user.offset = 0;
5110 if ((scsirate & WIDEXFER) != 0
5111 && (ahc->features & AHC_WIDE) != 0)
5112 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5113 tinfo->user.protocol_version = 4;
5114 if ((ahc->features & AHC_DT) != 0)
5115 tinfo->user.transport_version = 3;
5117 tinfo->user.transport_version = 2;
5118 tinfo->goal.protocol_version = 2;
5119 tinfo->goal.transport_version = 2;
5120 tinfo->curr.protocol_version = 2;
5121 tinfo->curr.transport_version = 2;
5123 tstate->ultraenb = 0;
5125 ahc->user_discenable = discenable;
5126 ahc->user_tagenable = tagenable;
5128 return (ahc->bus_chip_init(ahc));
5132 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5136 hcntrl = ahc_inb(ahc, HCNTRL);
5138 ahc->pause &= ~INTEN;
5139 ahc->unpause &= ~INTEN;
5142 ahc->pause |= INTEN;
5143 ahc->unpause |= INTEN;
5145 ahc_outb(ahc, HCNTRL, hcntrl);
5149 * Ensure that the card is paused in a location
5150 * outside of all critical sections and that all
5151 * pending work is completed prior to returning.
5152 * This routine should only be called from outside
5153 * an interrupt context.
5156 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5163 ahc->flags |= AHC_ALL_INTERRUPTS;
5169 * Give the sequencer some time to service
5170 * any active selections.
5177 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5178 intstat = ahc_inb(ahc, INTSTAT);
5179 if ((intstat & INT_PEND) == 0) {
5180 ahc_clear_critical_section(ahc);
5181 intstat = ahc_inb(ahc, INTSTAT);
5184 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5185 && ((intstat & INT_PEND) != 0
5186 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5187 if (maxloops == 0) {
5188 kprintf("Infinite interrupt loop, INTSTAT = %x",
5189 ahc_inb(ahc, INTSTAT));
5191 ahc_platform_flushwork(ahc);
5192 ahc->flags &= ~AHC_ALL_INTERRUPTS;
5196 ahc_suspend(struct ahc_softc *ahc)
5199 ahc_pause_and_flushwork(ahc);
5201 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5206 #ifdef AHC_TARGET_MODE
5208 * XXX What about ATIOs that have not yet been serviced?
5209 * Perhaps we should just refuse to be suspended if we
5210 * are acting in a target role.
5212 if (ahc->pending_device != NULL) {
5222 ahc_resume(struct ahc_softc *ahc)
5225 ahc_reset(ahc, /*reinit*/TRUE);
5226 ahc_intr_enable(ahc, TRUE);
5231 /************************** Busy Target Table *********************************/
5233 * Return the untagged transaction id for a given target/channel lun.
5234 * Optionally, clear the entry.
5237 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5240 u_int target_offset;
5242 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5245 saved_scbptr = ahc_inb(ahc, SCBPTR);
5246 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5247 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5248 ahc_outb(ahc, SCBPTR, saved_scbptr);
5250 target_offset = TCL_TARGET_OFFSET(tcl);
5251 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5258 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5260 u_int target_offset;
5262 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5265 saved_scbptr = ahc_inb(ahc, SCBPTR);
5266 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5267 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5268 ahc_outb(ahc, SCBPTR, saved_scbptr);
5270 target_offset = TCL_TARGET_OFFSET(tcl);
5271 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5276 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5278 u_int target_offset;
5280 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5283 saved_scbptr = ahc_inb(ahc, SCBPTR);
5284 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5285 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5286 ahc_outb(ahc, SCBPTR, saved_scbptr);
5288 target_offset = TCL_TARGET_OFFSET(tcl);
5289 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5293 /************************** SCB and SCB queue management **********************/
5295 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5296 char channel, int lun, u_int tag, role_t role)
5298 int targ = SCB_GET_TARGET(ahc, scb);
5299 char chan = SCB_GET_CHANNEL(ahc, scb);
5300 int slun = SCB_GET_LUN(scb);
5303 match = ((chan == channel) || (channel == ALL_CHANNELS));
5305 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5307 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5309 #ifdef AHC_TARGET_MODE
5312 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5313 if (role == ROLE_INITIATOR) {
5314 match = (group != XPT_FC_GROUP_TMODE)
5315 && ((tag == scb->hscb->tag)
5316 || (tag == SCB_LIST_NULL));
5317 } else if (role == ROLE_TARGET) {
5318 match = (group == XPT_FC_GROUP_TMODE)
5319 && ((tag == scb->io_ctx->csio.tag_id)
5320 || (tag == SCB_LIST_NULL));
5322 #else /* !AHC_TARGET_MODE */
5323 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5324 #endif /* AHC_TARGET_MODE */
5331 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5337 target = SCB_GET_TARGET(ahc, scb);
5338 lun = SCB_GET_LUN(scb);
5339 channel = SCB_GET_CHANNEL(ahc, scb);
5341 ahc_search_qinfifo(ahc, target, channel, lun,
5342 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5343 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5345 ahc_platform_freeze_devq(ahc, scb);
5349 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5351 struct scb *prev_scb;
5354 if (ahc_qinfifo_count(ahc) != 0) {
5358 prev_pos = ahc->qinfifonext - 1;
5359 prev_tag = ahc->qinfifo[prev_pos];
5360 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5362 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5363 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5364 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5366 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5371 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5374 if (prev_scb == NULL) {
5375 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5377 prev_scb->hscb->next = scb->hscb->tag;
5378 ahc_sync_scb(ahc, prev_scb,
5379 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5381 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5382 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5383 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5387 ahc_qinfifo_count(struct ahc_softc *ahc)
5392 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5393 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5394 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5396 qinpos = ahc_inb(ahc, QINPOS);
5397 diff = ahc->qinfifonext - qinpos;
5402 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5403 int lun, u_int tag, role_t role, uint32_t status,
5404 ahc_search_action action)
5407 struct scb *prev_scb;
5417 qintail = ahc->qinfifonext;
5418 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5420 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5421 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5423 qinstart = ahc_inb(ahc, QINPOS);
5428 if (action == SEARCH_COMPLETE) {
5430 * Don't attempt to run any queued untagged transactions
5431 * until we are done with the abort process.
5433 ahc_freeze_untagged_queues(ahc);
5437 * Start with an empty queue. Entries that are not chosen
5438 * for removal will be re-added to the queue as we go.
5440 ahc->qinfifonext = qinpos;
5441 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5443 while (qinpos != qintail) {
5444 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5446 kprintf("qinpos = %d, SCB index = %d\n",
5447 qinpos, ahc->qinfifo[qinpos]);
5451 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5453 * We found an scb that needs to be acted on.
5457 case SEARCH_COMPLETE:
5462 ostat = aic_get_transaction_status(scb);
5463 if (ostat == CAM_REQ_INPROG)
5464 aic_set_transaction_status(scb, status);
5465 cstat = aic_get_transaction_status(scb);
5466 if (cstat != CAM_REQ_CMP)
5467 aic_freeze_scb(scb);
5468 if ((scb->flags & SCB_ACTIVE) == 0)
5469 kprintf("Inactive SCB in qinfifo\n");
5477 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5482 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5488 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5489 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5491 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5494 if (action != SEARCH_COUNT
5496 && (qinstart != ahc->qinfifonext)) {
5498 * The sequencer may be in the process of dmaing
5499 * down the SCB at the beginning of the queue.
5500 * This could be problematic if either the first,
5501 * or the second SCB is removed from the queue
5502 * (the first SCB includes a pointer to the "next"
5503 * SCB to dma). If we have removed any entries, swap
5504 * the first element in the queue with the next HSCB
5505 * so the sequencer will notice that NEXT_QUEUED_SCB
5506 * has changed during its dma attempt and will retry
5509 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5512 kprintf("found = %d, qinstart = %d, qinfifionext = %d\n",
5513 found, qinstart, ahc->qinfifonext);
5514 panic("First/Second Qinfifo fixup\n");
5517 * ahc_swap_with_next_hscb forces our next pointer to
5518 * point to the reserved SCB for future commands. Save
5519 * and restore our original next pointer to maintain
5522 next = scb->hscb->next;
5523 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5524 ahc_swap_with_next_hscb(ahc, scb);
5525 scb->hscb->next = next;
5526 ahc->qinfifo[qinstart] = scb->hscb->tag;
5528 /* Tell the card about the new head of the qinfifo. */
5529 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5531 /* Fixup the tail "next" pointer. */
5532 qintail = ahc->qinfifonext - 1;
5533 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5534 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5538 * Search waiting for selection list.
5540 curscbptr = ahc_inb(ahc, SCBPTR);
5541 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5542 prev = SCB_LIST_NULL;
5544 while (next != SCB_LIST_NULL) {
5547 ahc_outb(ahc, SCBPTR, next);
5548 scb_index = ahc_inb(ahc, SCB_TAG);
5549 if (scb_index >= ahc->scb_data->numscbs) {
5550 kprintf("Waiting List inconsistency. "
5551 "SCB index == %d, yet numscbs == %d.",
5552 scb_index, ahc->scb_data->numscbs);
5553 ahc_dump_card_state(ahc);
5554 panic("for safety");
5556 scb = ahc_lookup_scb(ahc, scb_index);
5558 kprintf("scb_index = %d, next = %d\n",
5560 panic("Waiting List traversal\n");
5562 if (ahc_match_scb(ahc, scb, target, channel,
5563 lun, SCB_LIST_NULL, role)) {
5565 * We found an scb that needs to be acted on.
5569 case SEARCH_COMPLETE:
5574 ostat = aic_get_transaction_status(scb);
5575 if (ostat == CAM_REQ_INPROG)
5576 aic_set_transaction_status(scb,
5578 cstat = aic_get_transaction_status(scb);
5579 if (cstat != CAM_REQ_CMP)
5580 aic_freeze_scb(scb);
5581 if ((scb->flags & SCB_ACTIVE) == 0)
5582 kprintf("Inactive SCB in Wait List\n");
5587 next = ahc_rem_wscb(ahc, next, prev);
5591 next = ahc_inb(ahc, SCB_NEXT);
5597 next = ahc_inb(ahc, SCB_NEXT);
5600 ahc_outb(ahc, SCBPTR, curscbptr);
5602 found += ahc_search_untagged_queues(ahc, /*aic_io_ctx_t*/NULL, target,
5603 channel, lun, status, action);
5605 if (action == SEARCH_COMPLETE)
5606 ahc_release_untagged_queues(ahc);
5611 ahc_search_untagged_queues(struct ahc_softc *ahc, aic_io_ctx_t ctx,
5612 int target, char channel, int lun, uint32_t status,
5613 ahc_search_action action)
5620 if (action == SEARCH_COMPLETE) {
5622 * Don't attempt to run any queued untagged transactions
5623 * until we are done with the abort process.
5625 ahc_freeze_untagged_queues(ahc);
5630 if ((ahc->flags & AHC_SCB_BTT) == 0) {
5633 if (target != CAM_TARGET_WILDCARD) {
5644 for (; i < maxtarget; i++) {
5645 struct scb_tailq *untagged_q;
5646 struct scb *next_scb;
5648 untagged_q = &(ahc->untagged_queues[i]);
5649 next_scb = TAILQ_FIRST(untagged_q);
5650 while (next_scb != NULL) {
5653 next_scb = TAILQ_NEXT(scb, links.tqe);
5656 * The head of the list may be the currently
5657 * active untagged command for a device.
5658 * We're only searching for commands that
5659 * have not been started. A transaction
5660 * marked active but still in the qinfifo
5661 * is removed by the qinfifo scanning code
5664 if ((scb->flags & SCB_ACTIVE) != 0)
5667 if (ahc_match_scb(ahc, scb, target, channel, lun,
5668 SCB_LIST_NULL, ROLE_INITIATOR) == 0
5669 || (ctx != NULL && ctx != scb->io_ctx))
5673 * We found an scb that needs to be acted on.
5677 case SEARCH_COMPLETE:
5682 ostat = aic_get_transaction_status(scb);
5683 if (ostat == CAM_REQ_INPROG)
5684 aic_set_transaction_status(scb, status);
5685 cstat = aic_get_transaction_status(scb);
5686 if (cstat != CAM_REQ_CMP)
5687 aic_freeze_scb(scb);
5692 scb->flags &= ~SCB_UNTAGGEDQ;
5693 TAILQ_REMOVE(untagged_q, scb, links.tqe);
5701 if (action == SEARCH_COMPLETE)
5702 ahc_release_untagged_queues(ahc);
5707 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5708 int lun, u_int tag, int stop_on_first, int remove,
5718 next = ahc_inb(ahc, DISCONNECTED_SCBH);
5719 prev = SCB_LIST_NULL;
5722 /* restore this when we're done */
5723 active_scb = ahc_inb(ahc, SCBPTR);
5725 /* Silence compiler */
5726 active_scb = SCB_LIST_NULL;
5728 while (next != SCB_LIST_NULL) {
5731 ahc_outb(ahc, SCBPTR, next);
5732 scb_index = ahc_inb(ahc, SCB_TAG);
5733 if (scb_index >= ahc->scb_data->numscbs) {
5734 kprintf("Disconnected List inconsistency. "
5735 "SCB index == %d, yet numscbs == %d.",
5736 scb_index, ahc->scb_data->numscbs);
5737 ahc_dump_card_state(ahc);
5738 panic("for safety");
5742 panic("Disconnected List Loop. "
5743 "cur SCBPTR == %x, prev SCBPTR == %x.",
5746 scbp = ahc_lookup_scb(ahc, scb_index);
5747 if (ahc_match_scb(ahc, scbp, target, channel, lun,
5748 tag, ROLE_INITIATOR)) {
5752 ahc_rem_scb_from_disc_list(ahc, prev, next);
5755 next = ahc_inb(ahc, SCB_NEXT);
5761 next = ahc_inb(ahc, SCB_NEXT);
5765 ahc_outb(ahc, SCBPTR, active_scb);
5770 * Remove an SCB from the on chip list of disconnected transactions.
5771 * This is empty/unused if we are not performing SCB paging.
5774 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5778 ahc_outb(ahc, SCBPTR, scbptr);
5779 next = ahc_inb(ahc, SCB_NEXT);
5781 ahc_outb(ahc, SCB_CONTROL, 0);
5783 ahc_add_curscb_to_free_list(ahc);
5785 if (prev != SCB_LIST_NULL) {
5786 ahc_outb(ahc, SCBPTR, prev);
5787 ahc_outb(ahc, SCB_NEXT, next);
5789 ahc_outb(ahc, DISCONNECTED_SCBH, next);
5795 * Add the SCB as selected by SCBPTR onto the on chip list of
5796 * free hardware SCBs. This list is empty/unused if we are not
5797 * performing SCB paging.
5800 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5803 * Invalidate the tag so that our abort
5804 * routines don't think it's active.
5806 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5808 if ((ahc->flags & AHC_PAGESCBS) != 0) {
5809 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5810 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5815 * Manipulate the waiting for selection list and return the
5816 * scb that follows the one that we remove.
5819 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5824 * Select the SCB we want to abort and
5825 * pull the next pointer out of it.
5827 curscb = ahc_inb(ahc, SCBPTR);
5828 ahc_outb(ahc, SCBPTR, scbpos);
5829 next = ahc_inb(ahc, SCB_NEXT);
5831 /* Clear the necessary fields */
5832 ahc_outb(ahc, SCB_CONTROL, 0);
5834 ahc_add_curscb_to_free_list(ahc);
5836 /* update the waiting list */
5837 if (prev == SCB_LIST_NULL) {
5838 /* First in the list */
5839 ahc_outb(ahc, WAITING_SCBH, next);
5842 * Ensure we aren't attempting to perform
5843 * selection for this entry.
5845 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5848 * Select the scb that pointed to us
5849 * and update its next pointer.
5851 ahc_outb(ahc, SCBPTR, prev);
5852 ahc_outb(ahc, SCB_NEXT, next);
5856 * Point us back at the original scb position.
5858 ahc_outb(ahc, SCBPTR, curscb);
5862 /******************************** Error Handling ******************************/
5864 * Abort all SCBs that match the given description (target/channel/lun/tag),
5865 * setting their status to the passed in status if the status has not already
5866 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5867 * is paused before it is called.
5870 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5871 int lun, u_int tag, role_t role, uint32_t status)
5874 struct scb *scbp_next;
5884 * Don't attempt to run any queued untagged transactions
5885 * until we are done with the abort process.
5887 ahc_freeze_untagged_queues(ahc);
5889 /* restore this when we're done */
5890 active_scb = ahc_inb(ahc, SCBPTR);
5892 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5893 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5896 * Clean out the busy target table for any untagged commands.
5900 if (target != CAM_TARGET_WILDCARD) {
5907 if (lun == CAM_LUN_WILDCARD) {
5910 * Unless we are using an SCB based
5911 * busy targets table, there is only
5912 * one table entry for all luns of
5917 if ((ahc->flags & AHC_SCB_BTT) != 0)
5918 maxlun = AHC_NUM_LUNS;
5924 if (role != ROLE_TARGET) {
5925 for (;i < maxtarget; i++) {
5926 for (j = minlun;j < maxlun; j++) {
5930 tcl = BUILD_TCL(i << 4, j);
5931 scbid = ahc_index_busy_tcl(ahc, tcl);
5932 scbp = ahc_lookup_scb(ahc, scbid);
5934 || ahc_match_scb(ahc, scbp, target, channel,
5935 lun, tag, role) == 0)
5937 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5942 * Go through the disconnected list and remove any entries we
5943 * have queued for completion, 0'ing their control byte too.
5944 * We save the active SCB and restore it ourselves, so there
5945 * is no reason for this search to restore it too.
5947 ahc_search_disc_list(ahc, target, channel, lun, tag,
5948 /*stop_on_first*/FALSE, /*remove*/TRUE,
5949 /*save_state*/FALSE);
5953 * Go through the hardware SCB array looking for commands that
5954 * were active but not on any list. In some cases, these remnants
5955 * might not still have mappings in the scbindex array (e.g. unexpected
5956 * bus free with the same scb queued for an abort). Don't hold this
5959 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5962 ahc_outb(ahc, SCBPTR, i);
5963 scbid = ahc_inb(ahc, SCB_TAG);
5964 scbp = ahc_lookup_scb(ahc, scbid);
5965 if ((scbp == NULL && scbid != SCB_LIST_NULL)
5967 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
5968 ahc_add_curscb_to_free_list(ahc);
5972 * Go through the pending CCB list and look for
5973 * commands for this target that are still active.
5974 * These are other tagged commands that were
5975 * disconnected when the reset occurred.
5977 scbp_next = LIST_FIRST(&ahc->pending_scbs);
5978 while (scbp_next != NULL) {
5980 scbp_next = LIST_NEXT(scbp, pending_links);
5981 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
5984 ostat = aic_get_transaction_status(scbp);
5985 if (ostat == CAM_REQ_INPROG)
5986 aic_set_transaction_status(scbp, status);
5987 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP)
5988 aic_freeze_scb(scbp);
5989 if ((scbp->flags & SCB_ACTIVE) == 0)
5990 kprintf("Inactive SCB on pending list\n");
5991 ahc_done(ahc, scbp);
5995 ahc_outb(ahc, SCBPTR, active_scb);
5996 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
5997 ahc_release_untagged_queues(ahc);
6002 ahc_reset_current_bus(struct ahc_softc *ahc)
6006 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
6007 scsiseq = ahc_inb(ahc, SCSISEQ);
6008 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
6009 ahc_flush_device_writes(ahc);
6010 aic_delay(AHC_BUSRESET_DELAY);
6011 /* Turn off the bus reset */
6012 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
6014 ahc_clear_intstat(ahc);
6016 /* Re-enable reset interrupts */
6017 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
6021 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
6023 struct ahc_devinfo devinfo;
6024 u_int initiator, target, max_scsiid;
6032 ahc->pending_device = NULL;
6034 ahc_compile_devinfo(&devinfo,
6035 CAM_TARGET_WILDCARD,
6036 CAM_TARGET_WILDCARD,
6038 channel, ROLE_UNKNOWN);
6041 /* Make sure the sequencer is in a safe location. */
6042 ahc_clear_critical_section(ahc);
6045 * Run our command complete fifos to ensure that we perform
6046 * completion processing on any commands that 'completed'
6047 * before the reset occurred.
6049 ahc_run_qoutfifo(ahc);
6050 #ifdef AHC_TARGET_MODE
6052 * XXX - In Twin mode, the tqinfifo may have commands
6053 * for an unaffected channel in it. However, if
6054 * we have run out of ATIO resources to drain that
6055 * queue, we may not get them all out here. Further,
6056 * the blocked transactions for the reset channel
6057 * should just be killed off, irrespecitve of whether
6058 * we are blocked on ATIO resources. Write a routine
6059 * to compact the tqinfifo appropriately.
6061 if ((ahc->flags & AHC_TARGETROLE) != 0) {
6062 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
6067 * Reset the bus if we are initiating this reset
6069 sblkctl = ahc_inb(ahc, SBLKCTL);
6071 if ((ahc->features & AHC_TWIN) != 0
6072 && ((sblkctl & SELBUSB) != 0))
6074 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6075 if (cur_channel != channel) {
6076 /* Case 1: Command for another bus is active
6077 * Stealthily reset the other bus without
6078 * upsetting the current bus.
6080 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
6081 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6082 #ifdef AHC_TARGET_MODE
6084 * Bus resets clear ENSELI, so we cannot
6085 * defer re-enabling bus reset interrupts
6086 * if we are in target mode.
6088 if ((ahc->flags & AHC_TARGETROLE) != 0)
6089 simode1 |= ENSCSIRST;
6091 ahc_outb(ahc, SIMODE1, simode1);
6093 ahc_reset_current_bus(ahc);
6094 ahc_clear_intstat(ahc);
6095 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6096 ahc_outb(ahc, SBLKCTL, sblkctl);
6097 restart_needed = FALSE;
6099 /* Case 2: A command from this bus is active or we're idle */
6100 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6101 #ifdef AHC_TARGET_MODE
6103 * Bus resets clear ENSELI, so we cannot
6104 * defer re-enabling bus reset interrupts
6105 * if we are in target mode.
6107 if ((ahc->flags & AHC_TARGETROLE) != 0)
6108 simode1 |= ENSCSIRST;
6110 ahc_outb(ahc, SIMODE1, simode1);
6112 ahc_reset_current_bus(ahc);
6113 ahc_clear_intstat(ahc);
6114 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6115 restart_needed = TRUE;
6119 * Clean up all the state information for the
6120 * pending transactions on this bus.
6122 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
6123 CAM_LUN_WILDCARD, SCB_LIST_NULL,
6124 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6126 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6128 #ifdef AHC_TARGET_MODE
6130 * Send an immediate notify ccb to all target more peripheral
6131 * drivers affected by this action.
6133 for (target = 0; target <= max_scsiid; target++) {
6134 struct ahc_tmode_tstate* tstate;
6137 tstate = ahc->enabled_targets[target];
6140 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6141 struct ahc_tmode_lstate* lstate;
6143 lstate = tstate->enabled_luns[lun];
6147 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6148 EVENT_TYPE_BUS_RESET, /*arg*/0);
6149 ahc_send_lstate_events(ahc, lstate);
6153 /* Notify the XPT that a bus reset occurred */
6154 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
6155 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
6158 * Revert to async/narrow transfers until we renegotiate.
6160 for (target = 0; target <= max_scsiid; target++) {
6162 if (ahc->enabled_targets[target] == NULL)
6164 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6165 struct ahc_devinfo devinfo;
6167 ahc_compile_devinfo(&devinfo, target, initiator,
6169 channel, ROLE_UNKNOWN);
6170 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6171 AHC_TRANS_CUR, /*paused*/TRUE);
6172 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6173 /*period*/0, /*offset*/0,
6174 /*ppr_options*/0, AHC_TRANS_CUR,
6187 /***************************** Residual Processing ****************************/
6189 * Calculate the residual for a just completed SCB.
6192 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6194 struct hardware_scb *hscb;
6195 struct status_pkt *spkt;
6197 uint32_t resid_sgptr;
6203 * SG_RESID_VALID clear in sgptr.
6204 * 2) Transferless command
6205 * 3) Never performed any transfers.
6206 * sgptr has SG_FULL_RESID set.
6207 * 4) No residual but target did not
6208 * save data pointers after the
6209 * last transfer, so sgptr was
6211 * 5) We have a partial residual.
6212 * Use residual_sgptr to determine
6217 sgptr = aic_le32toh(hscb->sgptr);
6218 if ((sgptr & SG_RESID_VALID) == 0)
6221 sgptr &= ~SG_RESID_VALID;
6223 if ((sgptr & SG_LIST_NULL) != 0)
6227 spkt = &hscb->shared_data.status;
6228 resid_sgptr = aic_le32toh(spkt->residual_sg_ptr);
6229 if ((sgptr & SG_FULL_RESID) != 0) {
6231 resid = aic_get_transfer_length(scb);
6232 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6235 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6236 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6240 struct ahc_dma_seg *sg;
6243 * Remainder of the SG where the transfer
6246 resid = aic_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6247 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6249 /* The residual sg_ptr always points to the next sg */
6253 * Add up the contents of all residual
6254 * SG segments that are after the SG where
6255 * the transfer stopped.
6257 while ((aic_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6259 resid += aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
6262 if ((scb->flags & SCB_SENSE) == 0)
6263 aic_set_residual(scb, resid);
6265 aic_set_sense_residual(scb, resid);
6268 if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6269 ahc_print_path(ahc, scb);
6270 kprintf("Handled %sResidual of %d bytes\n",
6271 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6276 /******************************* Target Mode **********************************/
6277 #ifdef AHC_TARGET_MODE
6279 * Add a target mode event to this lun's queue
6282 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6283 u_int initiator_id, u_int event_type, u_int event_arg)
6285 struct ahc_tmode_event *event;
6288 xpt_freeze_devq(lstate->path, /*count*/1);
6289 if (lstate->event_w_idx >= lstate->event_r_idx)
6290 pending = lstate->event_w_idx - lstate->event_r_idx;
6292 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6293 - (lstate->event_r_idx - lstate->event_w_idx);
6295 if (event_type == EVENT_TYPE_BUS_RESET
6296 || event_type == MSG_BUS_DEV_RESET) {
6298 * Any earlier events are irrelevant, so reset our buffer.
6299 * This has the effect of allowing us to deal with reset
6300 * floods (an external device holding down the reset line)
6301 * without losing the event that is really interesting.
6303 lstate->event_r_idx = 0;
6304 lstate->event_w_idx = 0;
6305 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6308 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6309 xpt_print_path(lstate->path);
6310 kprintf("immediate event %x:%x lost\n",
6311 lstate->event_buffer[lstate->event_r_idx].event_type,
6312 lstate->event_buffer[lstate->event_r_idx].event_arg);
6313 lstate->event_r_idx++;
6314 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6315 lstate->event_r_idx = 0;
6316 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6319 event = &lstate->event_buffer[lstate->event_w_idx];
6320 event->initiator_id = initiator_id;
6321 event->event_type = event_type;
6322 event->event_arg = event_arg;
6323 lstate->event_w_idx++;
6324 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6325 lstate->event_w_idx = 0;
6329 * Send any target mode events queued up waiting
6330 * for immediate notify resources.
6333 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6335 struct ccb_hdr *ccbh;
6336 struct ccb_immed_notify *inot;
6338 while (lstate->event_r_idx != lstate->event_w_idx
6339 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6340 struct ahc_tmode_event *event;
6342 event = &lstate->event_buffer[lstate->event_r_idx];
6343 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6344 inot = (struct ccb_immed_notify *)ccbh;
6345 switch (event->event_type) {
6346 case EVENT_TYPE_BUS_RESET:
6347 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6350 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6351 inot->message_args[0] = event->event_type;
6352 inot->message_args[1] = event->event_arg;
6355 inot->initiator_id = event->initiator_id;
6356 inot->sense_len = 0;
6357 xpt_done((union ccb *)inot);
6358 lstate->event_r_idx++;
6359 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6360 lstate->event_r_idx = 0;
6365 /******************** Sequencer Program Patching/Download *********************/
6369 ahc_dumpseq(struct ahc_softc* ahc)
6373 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6374 ahc_outb(ahc, SEQADDR0, 0);
6375 ahc_outb(ahc, SEQADDR1, 0);
6376 for (i = 0; i < ahc->instruction_ram_size; i++) {
6377 uint8_t ins_bytes[4];
6379 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6380 kprintf("0x%08x\n", ins_bytes[0] << 24
6381 | ins_bytes[1] << 16
6389 ahc_loadseq(struct ahc_softc *ahc)
6391 struct cs cs_table[num_critical_sections];
6392 u_int begin_set[num_critical_sections];
6393 u_int end_set[num_critical_sections];
6394 struct patch *cur_patch;
6399 u_int sg_prefetch_cnt;
6401 uint8_t download_consts[7];
6404 * Start out with 0 critical sections
6405 * that apply to this firmware load.
6409 memset(begin_set, 0, sizeof(begin_set));
6410 memset(end_set, 0, sizeof(end_set));
6412 /* Setup downloadable constant table */
6413 download_consts[QOUTFIFO_OFFSET] = 0;
6414 if (ahc->targetcmds != NULL)
6415 download_consts[QOUTFIFO_OFFSET] += 32;
6416 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6417 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6418 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6419 sg_prefetch_cnt = ahc->pci_cachesize;
6420 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6421 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6422 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6423 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6424 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6426 cur_patch = patches;
6429 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6430 ahc_outb(ahc, SEQADDR0, 0);
6431 ahc_outb(ahc, SEQADDR1, 0);
6433 for (i = 0; i < sizeof(seqprog)/4; i++) {
6434 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6436 * Don't download this instruction as it
6437 * is in a patch that was removed.
6442 if (downloaded == ahc->instruction_ram_size) {
6444 * We're about to exceed the instruction
6445 * storage capacity for this chip. Fail
6448 kprintf("\n%s: Program too large for instruction memory "
6449 "size of %d!\n", ahc_name(ahc),
6450 ahc->instruction_ram_size);
6455 * Move through the CS table until we find a CS
6456 * that might apply to this instruction.
6458 for (; cur_cs < num_critical_sections; cur_cs++) {
6459 if (critical_sections[cur_cs].end <= i) {
6460 if (begin_set[cs_count] == TRUE
6461 && end_set[cs_count] == FALSE) {
6462 cs_table[cs_count].end = downloaded;
6463 end_set[cs_count] = TRUE;
6468 if (critical_sections[cur_cs].begin <= i
6469 && begin_set[cs_count] == FALSE) {
6470 cs_table[cs_count].begin = downloaded;
6471 begin_set[cs_count] = TRUE;
6475 ahc_download_instr(ahc, i, download_consts);
6479 ahc->num_critical_sections = cs_count;
6480 if (cs_count != 0) {
6481 cs_count *= sizeof(struct cs);
6482 ahc->critical_sections = kmalloc(cs_count, M_DEVBUF, M_INTWAIT);
6483 memcpy(ahc->critical_sections, cs_table, cs_count);
6485 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6488 kprintf(" %d instructions downloaded\n", downloaded);
6489 kprintf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6490 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6496 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
6497 u_int start_instr, u_int *skip_addr)
6499 struct patch *cur_patch;
6500 struct patch *last_patch;
6503 num_patches = sizeof(patches)/sizeof(struct patch);
6504 last_patch = &patches[num_patches];
6505 cur_patch = *start_patch;
6507 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6509 if (cur_patch->patch_func(ahc) == 0) {
6511 /* Start rejecting code */
6512 *skip_addr = start_instr + cur_patch->skip_instr;
6513 cur_patch += cur_patch->skip_patch;
6515 /* Accepted this patch. Advance to the next
6516 * one and wait for our intruction pointer to
6523 *start_patch = cur_patch;
6524 if (start_instr < *skip_addr)
6525 /* Still skipping */
6532 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6534 union ins_formats instr;
6535 struct ins_format1 *fmt1_ins;
6536 struct ins_format3 *fmt3_ins;
6540 * The firmware is always compiled into a little endian format.
6542 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6544 fmt1_ins = &instr.format1;
6547 /* Pull the opcode */
6548 opcode = instr.format1.opcode;
6559 struct patch *cur_patch;
6565 fmt3_ins = &instr.format3;
6567 address = fmt3_ins->address;
6568 cur_patch = patches;
6571 for (i = 0; i < address;) {
6573 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6575 if (skip_addr > i) {
6578 end_addr = MIN(address, skip_addr);
6579 address_offset += end_addr - i;
6585 address -= address_offset;
6586 fmt3_ins->address = address;
6595 if (fmt1_ins->parity != 0) {
6596 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6598 fmt1_ins->parity = 0;
6599 if ((ahc->features & AHC_CMD_CHAN) == 0
6600 && opcode == AIC_OP_BMOV) {
6602 * Block move was added at the same time
6603 * as the command channel. Verify that
6604 * this is only a move of a single element
6605 * and convert the BMOV to a MOV
6606 * (AND with an immediate of FF).
6608 if (fmt1_ins->immediate != 1)
6609 panic("%s: BMOV not supported\n",
6611 fmt1_ins->opcode = AIC_OP_AND;
6612 fmt1_ins->immediate = 0xff;
6616 if ((ahc->features & AHC_ULTRA2) != 0) {
6619 /* Calculate odd parity for the instruction */
6620 for (i = 0, count = 0; i < 31; i++) {
6624 if ((instr.integer & mask) != 0)
6627 if ((count & 0x01) == 0)
6628 instr.format1.parity = 1;
6630 /* Compress the instruction for older sequencers */
6631 if (fmt3_ins != NULL) {
6634 | (fmt3_ins->source << 8)
6635 | (fmt3_ins->address << 16)
6636 | (fmt3_ins->opcode << 25);
6640 | (fmt1_ins->source << 8)
6641 | (fmt1_ins->destination << 16)
6642 | (fmt1_ins->ret << 24)
6643 | (fmt1_ins->opcode << 25);
6646 /* The sequencer is a little endian cpu */
6647 instr.integer = aic_htole32(instr.integer);
6648 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
6651 panic("Unknown opcode encountered in seq program");
6657 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries,
6658 const char *name, u_int address, u_int value,
6659 u_int *cur_column, u_int wrap_point)
6665 if (cur_column == NULL) {
6667 cur_column = &dummy_column;
6670 if (*cur_column >= wrap_point) {
6674 printed = kprintf("%s[0x%x]", name, value);
6675 if (table == NULL) {
6676 printed += kprintf(" ");
6677 *cur_column += printed;
6681 while (printed_mask != 0xFF) {
6684 for (entry = 0; entry < num_entries; entry++) {
6685 if (((value & table[entry].mask)
6686 != table[entry].value)
6687 || ((printed_mask & table[entry].mask)
6688 == table[entry].mask))
6691 printed += kprintf("%s%s",
6692 printed_mask == 0 ? ":(" : "|",
6694 printed_mask |= table[entry].mask;
6698 if (entry >= num_entries)
6701 if (printed_mask != 0)
6702 printed += kprintf(") ");
6704 printed += kprintf(" ");
6705 if (cur_column != NULL)
6706 *cur_column += printed;
6711 ahc_dump_card_state(struct ahc_softc *ahc)
6714 struct scb_tailq *untagged_q;
6725 uint8_t saved_scbptr;
6727 if (ahc_is_paused(ahc)) {
6734 saved_scbptr = ahc_inb(ahc, SCBPTR);
6735 last_phase = ahc_inb(ahc, LASTPHASE);
6736 kprintf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
6737 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6738 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
6739 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6741 kprintf("Card was paused\n");
6742 kprintf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6743 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
6744 ahc_inb(ahc, ARG_2));
6745 kprintf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
6746 ahc_inb(ahc, SCBPTR));
6748 if ((ahc->features & AHC_DT) != 0)
6749 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
6750 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
6751 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
6752 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
6753 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
6754 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
6755 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
6756 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
6757 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
6758 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
6759 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
6760 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
6761 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
6762 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
6763 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
6764 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
6765 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
6766 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
6767 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
6771 for (i = 0; i < STACK_SIZE; i++)
6772 kprintf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
6773 kprintf("\nSCB count = %d\n", ahc->scb_data->numscbs);
6774 kprintf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6775 kprintf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6777 kprintf("QINFIFO entries: ");
6778 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6779 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6780 ahc_outb(ahc, SNSCB_QOFF, qinpos);
6782 qinpos = ahc_inb(ahc, QINPOS);
6783 qintail = ahc->qinfifonext;
6784 while (qinpos != qintail) {
6785 kprintf("%d ", ahc->qinfifo[qinpos]);
6790 kprintf("Waiting Queue entries: ");
6791 scb_index = ahc_inb(ahc, WAITING_SCBH);
6793 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6794 ahc_outb(ahc, SCBPTR, scb_index);
6795 kprintf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6796 scb_index = ahc_inb(ahc, SCB_NEXT);
6800 kprintf("Disconnected Queue entries: ");
6801 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
6803 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6804 ahc_outb(ahc, SCBPTR, scb_index);
6805 kprintf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6806 scb_index = ahc_inb(ahc, SCB_NEXT);
6810 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6811 kprintf("QOUTFIFO entries: ");
6812 qoutpos = ahc->qoutfifonext;
6814 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6815 kprintf("%d ", ahc->qoutfifo[qoutpos]);
6820 kprintf("Sequencer Free SCB List: ");
6821 scb_index = ahc_inb(ahc, FREE_SCBH);
6823 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6824 ahc_outb(ahc, SCBPTR, scb_index);
6825 kprintf("%d ", scb_index);
6826 scb_index = ahc_inb(ahc, SCB_NEXT);
6830 kprintf("Sequencer SCB Info: ");
6831 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6832 ahc_outb(ahc, SCBPTR, i);
6833 cur_col = kprintf("\n%3d ", i);
6835 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
6836 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
6837 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
6838 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6842 kprintf("Pending list: ");
6844 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6847 cur_col = kprintf("\n%3d ", scb->hscb->tag);
6848 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
6849 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
6850 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
6851 if ((ahc->flags & AHC_PAGESCBS) == 0) {
6852 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
6854 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
6856 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6862 kprintf("Kernel Free SCB list: ");
6864 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
6867 kprintf("%d ", scb->hscb->tag);
6871 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
6872 for (target = 0; target <= maxtarget; target++) {
6873 untagged_q = &ahc->untagged_queues[target];
6874 if (TAILQ_FIRST(untagged_q) == NULL)
6876 kprintf("Untagged Q(%d): ", target);
6878 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
6881 kprintf("%d ", scb->hscb->tag);
6886 ahc_platform_dump_card_state(ahc);
6887 kprintf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
6888 ahc_outb(ahc, SCBPTR, saved_scbptr);
6893 /*************************** Timeout Handling *********************************/
6895 ahc_timeout(struct scb *scb)
6897 struct ahc_softc *ahc;
6899 ahc = scb->ahc_softc;
6900 if ((scb->flags & SCB_ACTIVE) != 0) {
6901 if ((scb->flags & SCB_TIMEDOUT) == 0) {
6902 LIST_INSERT_HEAD(&ahc->timedout_scbs, scb,
6904 scb->flags |= SCB_TIMEDOUT;
6906 ahc_wakeup_recovery_thread(ahc);
6911 * Re-schedule a timeout for the passed in SCB if we determine that some
6912 * other SCB is in the process of recovery or an SCB with a longer
6913 * timeout is still pending. Limit our search to just "other_scb"
6914 * if it is non-NULL.
6917 ahc_other_scb_timeout(struct ahc_softc *ahc, struct scb *scb,
6918 struct scb *other_scb)
6923 ahc_print_path(ahc, scb);
6924 kprintf("Other SCB Timeout%s",
6925 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0
6926 ? " again\n" : "\n");
6928 newtimeout = aic_get_timeout(scb);
6929 scb->flags |= SCB_OTHERTCL_TIMEOUT;
6931 if (other_scb != NULL) {
6932 if ((other_scb->flags
6933 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
6934 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
6936 newtimeout = MAX(aic_get_timeout(other_scb),
6940 LIST_FOREACH(other_scb, &ahc->pending_scbs, pending_links) {
6941 if ((other_scb->flags
6942 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
6943 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
6946 MAX(aic_get_timeout(other_scb),
6953 aic_scb_timer_reset(scb, newtimeout);
6955 ahc_print_path(ahc, scb);
6956 kprintf("No other SCB worth waiting for...\n");
6959 return (found != 0);
6963 * ahc_recover_commands determines if any of the commands that have currently
6964 * timedout are the root cause for this timeout. Innocent commands are given
6965 * a new timeout while we wait for the command executing on the bus to timeout.
6966 * This routine is invoked from a thread context so we are allowed to sleep.
6967 * Our lock is not held on entry.
6970 ahc_recover_commands(struct ahc_softc *ahc)
6978 * Pause the controller and manually flush any
6979 * commands that have just completed but that our
6980 * interrupt handler has yet to see.
6982 ahc_pause_and_flushwork(ahc);
6984 if (LIST_EMPTY(&ahc->timedout_scbs) != 0) {
6986 * The timedout commands have already
6987 * completed. This typically means
6988 * that either the timeout value was on
6989 * the hairy edge of what the device
6990 * requires or - more likely - interrupts
6991 * are not happening.
6993 kprintf("%s: Timedout SCBs already complete. "
6994 "Interrupts may not be functioning.\n", ahc_name(ahc));
7000 kprintf("%s: Recovery Initiated\n", ahc_name(ahc));
7001 ahc_dump_card_state(ahc);
7003 last_phase = ahc_inb(ahc, LASTPHASE);
7004 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) {
7005 u_int active_scb_index;
7012 target = SCB_GET_TARGET(ahc, scb);
7013 channel = SCB_GET_CHANNEL(ahc, scb);
7014 lun = SCB_GET_LUN(scb);
7016 ahc_print_path(ahc, scb);
7017 kprintf("SCB 0x%x - timed out\n", scb->hscb->tag);
7018 if (scb->sg_count > 0) {
7019 for (i = 0; i < scb->sg_count; i++) {
7020 kprintf("sg[%d] - Addr 0x%x : Length %d\n",
7022 scb->sg_list[i].addr,
7023 scb->sg_list[i].len & AHC_SG_LEN_MASK);
7026 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) {
7028 * Been down this road before.
7029 * Do a full bus reset.
7031 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT);
7033 found = ahc_reset_channel(ahc, channel,
7034 /*Initiate Reset*/TRUE);
7035 kprintf("%s: Issued Channel %c Bus Reset. "
7036 "%d SCBs aborted\n", ahc_name(ahc), channel,
7042 * Remove the command from the timedout list in
7043 * preparation for requeing it.
7045 LIST_REMOVE(scb, timedout_links);
7046 scb->flags &= ~SCB_TIMEDOUT;
7049 * If we are a target, transition to bus free and report
7052 * The target/initiator that is holding up the bus may not
7053 * be the same as the one that triggered this timeout
7054 * (different commands have different timeout lengths).
7055 * If the bus is idle and we are actiing as the initiator
7056 * for this request, queue a BDR message to the timed out
7057 * target. Otherwise, if the timed out transaction is
7059 * Initiator transaction:
7060 * Stuff the message buffer with a BDR message and assert
7061 * ATN in the hopes that the target will let go of the bus
7062 * and go to the mesgout phase. If this fails, we'll
7063 * get another timeout 2 seconds later which will attempt
7066 * Target transaction:
7067 * Transition to BUS FREE and report the error.
7068 * It's good to be the target!
7070 saved_scbptr = ahc_inb(ahc, SCBPTR);
7071 active_scb_index = ahc_inb(ahc, SCB_TAG);
7073 if ((ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) == 0
7074 && (active_scb_index < ahc->scb_data->numscbs)) {
7075 struct scb *active_scb;
7078 * If the active SCB is not us, assume that
7079 * the active SCB has a longer timeout than
7080 * the timedout SCB, and wait for the active
7083 active_scb = ahc_lookup_scb(ahc, active_scb_index);
7084 if (active_scb != scb) {
7085 if (ahc_other_scb_timeout(ahc, scb,
7092 if ((scb->flags & SCB_TARGET_SCB) != 0) {
7095 * Send back any queued up transactions
7096 * and properly record the error condition.
7098 ahc_abort_scbs(ahc, SCB_GET_TARGET(ahc, scb),
7099 SCB_GET_CHANNEL(ahc, scb),
7105 /* Will clear us from the bus */
7110 ahc_set_recoveryscb(ahc, active_scb);
7111 ahc_outb(ahc, MSG_OUT, HOST_MSG);
7112 ahc_outb(ahc, SCSISIGO, last_phase|ATNO);
7113 ahc_print_path(ahc, active_scb);
7114 kprintf("BDR message in message buffer\n");
7115 active_scb->flags |= SCB_DEVICE_RESET;
7116 aic_scb_timer_reset(scb, 2 * 1000);
7117 } else if (last_phase != P_BUSFREE
7118 && (ahc_inb(ahc, SSTAT1) & REQINIT) == 0) {
7120 * SCB is not identified, there
7121 * is no pending REQ, and the sequencer
7122 * has not seen a busfree. Looks like
7123 * a stuck connection waiting to
7124 * go busfree. Reset the bus.
7126 kprintf("%s: Connection stuck awaiting busfree or "
7127 "Identify Msg.\n", ahc_name(ahc));
7132 if (last_phase != P_BUSFREE
7133 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) {
7134 /* Hung target selection. Goto busfree */
7135 kprintf("%s: Hung target selection\n",
7141 /* XXX Shouldn't panic. Just punt instead? */
7142 if ((scb->flags & SCB_TARGET_SCB) != 0)
7143 panic("Timed-out target SCB but bus idle");
7145 if (ahc_search_qinfifo(ahc, target, channel, lun,
7146 scb->hscb->tag, ROLE_INITIATOR,
7147 /*status*/0, SEARCH_COUNT) > 0) {
7148 disconnected = FALSE;
7150 disconnected = TRUE;
7155 ahc_set_recoveryscb(ahc, scb);
7157 * Actually re-queue this SCB in an attempt
7158 * to select the device before it reconnects.
7159 * In either case (selection or reselection),
7160 * we will now issue a target reset to the
7163 * Set the MK_MESSAGE control bit indicating
7164 * that we desire to send a message. We
7165 * also set the disconnected flag since
7166 * in the paging case there is no guarantee
7167 * that our SCB control byte matches the
7168 * version on the card. We don't want the
7169 * sequencer to abort the command thinking
7170 * an unsolicited reselection occurred.
7172 scb->hscb->control |= MK_MESSAGE|DISCONNECTED;
7173 scb->flags |= SCB_DEVICE_RESET;
7176 * Remove any cached copy of this SCB in the
7177 * disconnected list in preparation for the
7178 * queuing of our abort SCB. We use the
7179 * same element in the SCB, SCB_NEXT, for
7180 * both the qinfifo and the disconnected list.
7182 ahc_search_disc_list(ahc, target, channel,
7183 lun, scb->hscb->tag,
7184 /*stop_on_first*/TRUE,
7186 /*save_state*/FALSE);
7189 * In the non-paging case, the sequencer will
7190 * never re-reference the in-core SCB.
7191 * To make sure we are notified during
7192 * reslection, set the MK_MESSAGE flag in
7193 * the card's copy of the SCB.
7195 if ((ahc->flags & AHC_PAGESCBS) == 0) {
7196 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
7197 ahc_outb(ahc, SCB_CONTROL,
7198 ahc_inb(ahc, SCB_CONTROL)
7203 * Clear out any entries in the QINFIFO first
7204 * so we are the next SCB for this target
7207 ahc_search_qinfifo(ahc,
7208 SCB_GET_TARGET(ahc, scb),
7209 channel, SCB_GET_LUN(scb),
7214 ahc_print_path(ahc, scb);
7215 kprintf("Queuing a BDR SCB\n");
7216 ahc_qinfifo_requeue_tail(ahc, scb);
7217 ahc_outb(ahc, SCBPTR, saved_scbptr);
7218 aic_scb_timer_reset(scb, 2 * 1000);
7220 /* Go "immediatly" to the bus reset */
7221 /* This shouldn't happen */
7222 ahc_set_recoveryscb(ahc, scb);
7223 ahc_print_path(ahc, scb);
7224 kprintf("SCB %d: Immediate reset. "
7225 "Flags = 0x%x\n", scb->hscb->tag,
7234 * Any remaining SCBs were not the "culprit", so remove
7235 * them from the timeout list. The timer for these commands
7236 * will be reset once the recovery SCB completes.
7238 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) {
7240 LIST_REMOVE(scb, timedout_links);
7241 scb->flags &= ~SCB_TIMEDOUT;
7250 /************************* Target Mode ****************************************/
7251 #ifdef AHC_TARGET_MODE
7253 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
7254 struct ahc_tmode_tstate **tstate,
7255 struct ahc_tmode_lstate **lstate,
7256 int notfound_failure)
7259 if ((ahc->features & AHC_TARGETMODE) == 0)
7260 return (CAM_REQ_INVALID);
7263 * Handle the 'black hole' device that sucks up
7264 * requests to unattached luns on enabled targets.
7266 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
7267 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
7269 *lstate = ahc->black_hole;
7273 max_id = (ahc->features & AHC_WIDE) ? 15 : 7;
7274 if (ccb->ccb_h.target_id > max_id)
7275 return (CAM_TID_INVALID);
7277 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
7278 return (CAM_LUN_INVALID);
7280 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
7282 if (*tstate != NULL)
7284 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
7287 if (notfound_failure != 0 && *lstate == NULL)
7288 return (CAM_PATH_INVALID);
7290 return (CAM_REQ_CMP);
7294 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
7296 struct ahc_tmode_tstate *tstate;
7297 struct ahc_tmode_lstate *lstate;
7298 struct ccb_en_lun *cel;
7307 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
7308 /*notfound_failure*/FALSE);
7310 if (status != CAM_REQ_CMP) {
7311 ccb->ccb_h.status = status;
7315 if (cam_sim_bus(sim) == 0)
7316 our_id = ahc->our_id;
7318 our_id = ahc->our_id_b;
7320 if (ccb->ccb_h.target_id != our_id) {
7322 * our_id represents our initiator ID, or
7323 * the ID of the first target to have an
7324 * enabled lun in target mode. There are
7325 * two cases that may preclude enabling a
7326 * target id other than our_id.
7328 * o our_id is for an active initiator role.
7329 * Since the hardware does not support
7330 * reselections to the initiator role at
7331 * anything other than our_id, and our_id
7332 * is used by the hardware to indicate the
7333 * ID to use for both select-out and
7334 * reselect-out operations, the only target
7335 * ID we can support in this mode is our_id.
7337 * o The MULTARGID feature is not available and
7338 * a previous target mode ID has been enabled.
7340 if ((ahc->features & AHC_MULTIROLE) != 0) {
7342 if ((ahc->features & AHC_MULTI_TID) != 0
7343 && (ahc->flags & AHC_INITIATORROLE) != 0) {
7345 * Only allow additional targets if
7346 * the initiator role is disabled.
7347 * The hardware cannot handle a re-select-in
7348 * on the initiator id during a re-select-out
7349 * on a different target id.
7351 status = CAM_TID_INVALID;
7352 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
7353 || ahc->enabled_luns > 0) {
7355 * Only allow our target id to change
7356 * if the initiator role is not configured
7357 * and there are no enabled luns which
7358 * are attached to the currently registered
7361 status = CAM_TID_INVALID;
7363 } else if ((ahc->features & AHC_MULTI_TID) == 0
7364 && ahc->enabled_luns > 0) {
7366 status = CAM_TID_INVALID;
7370 if (status != CAM_REQ_CMP) {
7371 ccb->ccb_h.status = status;
7376 * We now have an id that is valid.
7377 * If we aren't in target mode, switch modes.
7379 if ((ahc->flags & AHC_TARGETROLE) == 0
7380 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7381 ahc_flag saved_flags;
7383 kprintf("Configuring Target Mode\n");
7384 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
7385 ccb->ccb_h.status = CAM_BUSY;
7388 saved_flags = ahc->flags;
7389 ahc->flags |= AHC_TARGETROLE;
7390 if ((ahc->features & AHC_MULTIROLE) == 0)
7391 ahc->flags &= ~AHC_INITIATORROLE;
7393 error = ahc_loadseq(ahc);
7396 * Restore original configuration and notify
7397 * the caller that we cannot support target mode.
7398 * Since the adapter started out in this
7399 * configuration, the firmware load will succeed,
7400 * so there is no point in checking ahc_loadseq's
7403 ahc->flags = saved_flags;
7404 (void)ahc_loadseq(ahc);
7406 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
7412 target = ccb->ccb_h.target_id;
7413 lun = ccb->ccb_h.target_lun;
7414 channel = SIM_CHANNEL(ahc, sim);
7415 target_mask = 0x01 << target;
7419 if (cel->enable != 0) {
7422 /* Are we already enabled?? */
7423 if (lstate != NULL) {
7424 xpt_print_path(ccb->ccb_h.path);
7425 kprintf("Lun already enabled\n");
7426 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
7430 if (cel->grp6_len != 0
7431 || cel->grp7_len != 0) {
7433 * Don't (yet?) support vendor
7434 * specific commands.
7436 ccb->ccb_h.status = CAM_REQ_INVALID;
7437 kprintf("Non-zero Group Codes\n");
7443 * Setup our data structures.
7445 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
7446 tstate = ahc_alloc_tstate(ahc, target, channel);
7447 if (tstate == NULL) {
7448 xpt_print_path(ccb->ccb_h.path);
7449 kprintf("Couldn't allocate tstate\n");
7450 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7454 lstate = kmalloc(sizeof(*lstate), M_DEVBUF, M_INTWAIT | M_ZERO);
7455 status = xpt_create_path(&lstate->path, /*periph*/NULL,
7456 xpt_path_path_id(ccb->ccb_h.path),
7457 xpt_path_target_id(ccb->ccb_h.path),
7458 xpt_path_lun_id(ccb->ccb_h.path));
7459 if (status != CAM_REQ_CMP) {
7460 kfree(lstate, M_DEVBUF);
7461 xpt_print_path(ccb->ccb_h.path);
7462 kprintf("Couldn't allocate path\n");
7463 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7466 SLIST_INIT(&lstate->accept_tios);
7467 SLIST_INIT(&lstate->immed_notifies);
7469 if (target != CAM_TARGET_WILDCARD) {
7470 tstate->enabled_luns[lun] = lstate;
7471 ahc->enabled_luns++;
7473 if ((ahc->features & AHC_MULTI_TID) != 0) {
7476 targid_mask = ahc_inb(ahc, TARGID)
7477 | (ahc_inb(ahc, TARGID + 1) << 8);
7479 targid_mask |= target_mask;
7480 ahc_outb(ahc, TARGID, targid_mask);
7481 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7483 ahc_update_scsiid(ahc, targid_mask);
7488 channel = SIM_CHANNEL(ahc, sim);
7489 our_id = SIM_SCSI_ID(ahc, sim);
7492 * This can only happen if selections
7495 if (target != our_id) {
7500 sblkctl = ahc_inb(ahc, SBLKCTL);
7501 cur_channel = (sblkctl & SELBUSB)
7503 if ((ahc->features & AHC_TWIN) == 0)
7505 swap = cur_channel != channel;
7507 ahc->our_id = target;
7509 ahc->our_id_b = target;
7512 ahc_outb(ahc, SBLKCTL,
7515 ahc_outb(ahc, SCSIID, target);
7518 ahc_outb(ahc, SBLKCTL, sblkctl);
7522 ahc->black_hole = lstate;
7523 /* Allow select-in operations */
7524 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7525 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7527 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7528 scsiseq = ahc_inb(ahc, SCSISEQ);
7530 ahc_outb(ahc, SCSISEQ, scsiseq);
7533 ccb->ccb_h.status = CAM_REQ_CMP;
7534 xpt_print_path(ccb->ccb_h.path);
7535 kprintf("Lun now enabled for target mode\n");
7540 if (lstate == NULL) {
7541 ccb->ccb_h.status = CAM_LUN_INVALID;
7545 ccb->ccb_h.status = CAM_REQ_CMP;
7546 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7547 struct ccb_hdr *ccbh;
7549 ccbh = &scb->io_ctx->ccb_h;
7550 if (ccbh->func_code == XPT_CONT_TARGET_IO
7551 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7552 kprintf("CTIO pending\n");
7553 ccb->ccb_h.status = CAM_REQ_INVALID;
7558 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7559 kprintf("ATIOs pending\n");
7560 ccb->ccb_h.status = CAM_REQ_INVALID;
7563 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7564 kprintf("INOTs pending\n");
7565 ccb->ccb_h.status = CAM_REQ_INVALID;
7568 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7572 xpt_print_path(ccb->ccb_h.path);
7573 kprintf("Target mode disabled\n");
7574 xpt_free_path(lstate->path);
7575 kfree(lstate, M_DEVBUF);
7578 /* Can we clean up the target too? */
7579 if (target != CAM_TARGET_WILDCARD) {
7580 tstate->enabled_luns[lun] = NULL;
7581 ahc->enabled_luns--;
7582 for (empty = 1, i = 0; i < 8; i++)
7583 if (tstate->enabled_luns[i] != NULL) {
7589 ahc_free_tstate(ahc, target, channel,
7591 if (ahc->features & AHC_MULTI_TID) {
7594 targid_mask = ahc_inb(ahc, TARGID)
7595 | (ahc_inb(ahc, TARGID + 1)
7598 targid_mask &= ~target_mask;
7599 ahc_outb(ahc, TARGID, targid_mask);
7600 ahc_outb(ahc, TARGID+1,
7601 (targid_mask >> 8));
7602 ahc_update_scsiid(ahc, targid_mask);
7607 ahc->black_hole = NULL;
7610 * We can't allow selections without
7611 * our black hole device.
7615 if (ahc->enabled_luns == 0) {
7616 /* Disallow select-in */
7619 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7621 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7622 scsiseq = ahc_inb(ahc, SCSISEQ);
7624 ahc_outb(ahc, SCSISEQ, scsiseq);
7626 if ((ahc->features & AHC_MULTIROLE) == 0) {
7627 kprintf("Configuring Initiator Mode\n");
7628 ahc->flags &= ~AHC_TARGETROLE;
7629 ahc->flags |= AHC_INITIATORROLE;
7631 * Returning to a configuration that
7632 * fit previously will always succeed.
7634 (void)ahc_loadseq(ahc);
7637 * Unpaused. The extra unpause
7638 * that follows is harmless.
7647 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7652 if ((ahc->features & AHC_MULTI_TID) == 0)
7653 panic("ahc_update_scsiid called on non-multitid unit\n");
7656 * Since we will rely on the TARGID mask
7657 * for selection enables, ensure that OID
7658 * in SCSIID is not set to some other ID
7659 * that we don't want to allow selections on.
7661 if ((ahc->features & AHC_ULTRA2) != 0)
7662 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7664 scsiid = ahc_inb(ahc, SCSIID);
7665 scsiid_mask = 0x1 << (scsiid & OID);
7666 if ((targid_mask & scsiid_mask) == 0) {
7669 /* ffs counts from 1 */
7670 our_id = ffs(targid_mask);
7672 our_id = ahc->our_id;
7678 if ((ahc->features & AHC_ULTRA2) != 0)
7679 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7681 ahc_outb(ahc, SCSIID, scsiid);
7685 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7687 struct target_cmd *cmd;
7690 * If the card supports auto-access pause,
7691 * we can access the card directly regardless
7692 * of whether it is paused or not.
7694 if ((ahc->features & AHC_AUTOPAUSE) != 0)
7697 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7698 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7701 * Only advance through the queue if we
7702 * have the resources to process the command.
7704 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7708 aic_dmamap_sync(ahc, ahc->shared_data_dmat,
7709 ahc->shared_data_dmamap,
7710 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7711 sizeof(struct target_cmd),
7712 BUS_DMASYNC_PREREAD);
7713 ahc->tqinfifonext++;
7716 * Lazily update our position in the target mode incoming
7717 * command queue as seen by the sequencer.
7719 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7720 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7723 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7724 hs_mailbox &= ~HOST_TQINPOS;
7725 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7726 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7730 ahc_outb(ahc, KERNEL_TQINPOS,
7731 ahc->tqinfifonext & HOST_TQINPOS);
7740 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7742 struct ahc_tmode_tstate *tstate;
7743 struct ahc_tmode_lstate *lstate;
7744 struct ccb_accept_tio *atio;
7750 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7751 target = SCSIID_OUR_ID(cmd->scsiid);
7752 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7755 tstate = ahc->enabled_targets[target];
7758 lstate = tstate->enabled_luns[lun];
7761 * Commands for disabled luns go to the black hole driver.
7764 lstate = ahc->black_hole;
7766 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7768 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7770 * Wait for more ATIOs from the peripheral driver for this lun.
7773 kprintf("%s: ATIOs exhausted\n", ahc_name(ahc));
7776 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7778 if (ahc_debug & AHC_SHOW_TQIN) {
7779 kprintf("Incoming command from %d for %d:%d%s\n",
7780 initiator, target, lun,
7781 lstate == ahc->black_hole ? "(Black Holed)" : "");
7784 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7786 if (lstate == ahc->black_hole) {
7787 /* Fill in the wildcards */
7788 atio->ccb_h.target_id = target;
7789 atio->ccb_h.target_lun = lun;
7793 * Package it up and send it off to
7794 * whomever has this lun enabled.
7796 atio->sense_len = 0;
7797 atio->init_id = initiator;
7798 if (byte[0] != 0xFF) {
7799 /* Tag was included */
7800 atio->tag_action = *byte++;
7801 atio->tag_id = *byte++;
7802 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
7804 atio->ccb_h.flags = 0;
7808 /* Okay. Now determine the cdb size based on the command code */
7809 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7825 /* Only copy the opcode. */
7827 kprintf("Reserved or VU command code type encountered\n");
7831 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7833 atio->ccb_h.status |= CAM_CDB_RECVD;
7835 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7837 * We weren't allowed to disconnect.
7838 * We're hanging on the bus until a
7839 * continue target I/O comes in response
7840 * to this accept tio.
7843 if (ahc_debug & AHC_SHOW_TQIN) {
7844 kprintf("Received Immediate Command %d:%d:%d - %p\n",
7845 initiator, target, lun, ahc->pending_device);
7848 ahc->pending_device = lstate;
7849 aic_freeze_ccb((union ccb *)atio);
7850 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7852 xpt_done((union ccb*)atio);