1 /* $OpenBSD: rgephy.c,v 1.12 2006/06/27 05:36:58 brad Exp $ */
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/dev/mii/rgephy.c,v 1.7 2005/09/30 19:39:27 imp Exp $
35 * $DragonFly: src/sys/dev/netif/mii_layer/rgephy.c,v 1.2 2006/08/06 10:32:23 sephe Exp $
39 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/socket.h>
49 #include <machine/bus.h>
50 #include <machine/clock.h>
53 #include <net/if_arp.h>
54 #include <net/if_media.h>
56 #include <dev/netif/mii_layer/mii.h>
57 #include <dev/netif/mii_layer/miivar.h>
58 #include <dev/netif/mii_layer/miidevs.h>
60 #include <dev/netif/re/if_rereg.h>
61 #include <dev/netif/mii_layer/rgephyreg.h>
63 #include "miibus_if.h"
65 #include <machine/bus.h>
67 static int rgephy_probe(device_t);
68 static int rgephy_attach(device_t);
70 static device_method_t rgephy_methods[] = {
71 /* device interface */
72 DEVMETHOD(device_probe, rgephy_probe),
73 DEVMETHOD(device_attach, rgephy_attach),
74 DEVMETHOD(device_detach, ukphy_detach),
75 DEVMETHOD(device_shutdown, bus_generic_shutdown),
79 static const struct mii_phydesc rgephys[] = {
80 MII_PHYDESC(REALTEK2, RTL8169S),
81 MII_PHYDESC(xxREALTEK, RTL8169S),
85 static devclass_t rgephy_devclass;
87 static driver_t rgephy_driver = {
90 sizeof(struct mii_softc)
93 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
95 static int rgephy_service(struct mii_softc *, struct mii_data *, int);
96 static void rgephy_status(struct mii_softc *);
97 static int rgephy_mii_phy_auto(struct mii_softc *);
98 static void rgephy_reset(struct mii_softc *);
99 static void rgephy_loop(struct mii_softc *);
100 static void rgephy_load_dspcode(struct mii_softc *);
103 rgephy_probe(device_t dev)
105 struct mii_attach_args *ma = device_get_ivars(dev);
106 const struct mii_phydesc *mpd;
108 mpd = mii_phy_match(ma, rgephys);
110 device_set_desc(dev, mpd->mpd_name);
117 rgephy_attach(device_t dev)
119 struct mii_softc *sc;
120 struct mii_attach_args *ma;
121 struct mii_data *mii;
123 sc = device_get_softc(dev);
124 ma = device_get_ivars(dev);
125 mii_softc_init(sc, ma);
126 sc->mii_dev = device_get_parent(dev);
128 mii = device_get_softc(sc->mii_dev);
129 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
131 sc->mii_inst = mii->mii_instance;
132 sc->mii_service = rgephy_service;
133 sc->mii_reset = rgephy_reset;
136 sc->mii_flags |= MIIF_NOISOLATE;
141 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
142 if (sc->mii_capabilities & BMSR_EXTSTAT)
143 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
145 device_printf(dev, " ");
146 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
147 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0)
148 printf("no media present");
150 mii_phy_add_media(sc);
153 MIIBUS_MEDIAINIT(sc->mii_dev);
158 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
160 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
166 * If we're not polling our PHY instance, just return.
168 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
174 * If the media indicates a different PHY instance,
177 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
178 reg = PHY_READ(sc, MII_BMCR);
179 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
184 * If the interface is not up, don't do anything.
186 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
189 rgephy_reset(sc); /* XXX hardware bug work-around */
191 switch (IFM_SUBTYPE(ife->ifm_media)) {
195 * If we're already in auto mode, just return.
197 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
200 rgephy_mii_phy_auto(sc);
203 speed = RGEPHY_S1000;
212 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
213 speed |= RGEPHY_BMCR_FDX;
214 gig = RGEPHY_1000CTL_AFD;
216 gig = RGEPHY_1000CTL_AHD;
219 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
220 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
221 PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE);
223 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
226 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
227 PHY_WRITE(sc, RGEPHY_MII_BMCR,
228 speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG);
231 * When settning the link manually, one side must
232 * be the master and the other the slave. However
233 * ifmedia doesn't give us a good way to specify
234 * this, so we fake it by using one of the LINK
235 * flags. If LINK0 is set, we program the PHY to
236 * be a master, otherwise it's a slave.
238 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
239 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
240 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
242 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
243 gig|RGEPHY_1000CTL_MSE);
248 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
259 * If we're not currently selected, just return.
261 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
265 * Is the interface even up?
267 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
271 * Only used for autonegotiation.
273 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
277 * Check to see if we have link. If we do, we don't
278 * need to restart the autonegotiation process.
280 * XXX Read the BMSR twice in case it's latched?
282 reg = PHY_READ(sc, RE_GMEDIASTAT);
283 if (reg & RE_GMEDIASTAT_LINK)
287 * Only retry autonegotiation every mii_anegticks seconds.
289 if (++sc->mii_ticks <= sc->mii_anegticks)
295 * Although rgephy_mii_phy_auto() always returns EJUSTRETURN,
296 * we should not rely on that.
298 if (rgephy_mii_phy_auto(sc) == EJUSTRETURN)
303 /* Update the media status. */
307 * Callback if something changed. Note that we need to poke
308 * the DSP on the RealTek PHYs if the media changes.
310 if (sc->mii_media_active != mii->mii_media_active ||
311 sc->mii_media_status != mii->mii_media_status ||
313 rgephy_load_dspcode(sc);
314 mii_phy_update(sc, cmd);
319 rgephy_status(struct mii_softc *sc)
321 struct mii_data *mii = sc->mii_pdata;
324 mii->mii_media_status = IFM_AVALID;
325 mii->mii_media_active = IFM_ETHER;
327 bmsr = PHY_READ(sc, RE_GMEDIASTAT);
329 if (bmsr & RE_GMEDIASTAT_LINK)
330 mii->mii_media_status |= IFM_ACTIVE;
331 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
333 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
335 if (bmcr & RGEPHY_BMCR_LOOP)
336 mii->mii_media_active |= IFM_LOOP;
338 if (bmcr & RGEPHY_BMCR_AUTOEN) {
339 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
340 /* Erg, still trying, I guess... */
341 mii->mii_media_active |= IFM_NONE;
346 bmsr = PHY_READ(sc, RE_GMEDIASTAT);
348 if (bmsr & RE_GMEDIASTAT_1000MBPS) {
349 mii->mii_media_active |= IFM_1000_T;
350 } else if (bmsr & RE_GMEDIASTAT_100MBPS) {
351 mii->mii_media_active |= IFM_100_TX;
352 } else if (bmsr & RE_GMEDIASTAT_10MBPS) {
353 mii->mii_media_active |= IFM_10_T;
355 mii->mii_media_active |= IFM_NONE;
359 if (bmsr & RE_GMEDIASTAT_FDX)
360 mii->mii_media_active |= IFM_FDX;
364 rgephy_mii_phy_auto(struct mii_softc *sc)
369 PHY_WRITE(sc, RGEPHY_MII_ANAR,
370 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
372 PHY_WRITE(sc, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AFD);
374 PHY_WRITE(sc, RGEPHY_MII_BMCR,
375 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
378 return (EJUSTRETURN);
382 rgephy_loop(struct mii_softc *sc)
387 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
390 for (i = 0; i < 15000; i++) {
391 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
392 if (!(bmsr & RGEPHY_BMSR_LINK)) {
394 device_printf(sc->mii_dev, "looped %d\n", i);
402 #define PHY_SETBIT(x, y, z) \
403 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
404 #define PHY_CLRBIT(x, y, z) \
405 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
408 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
409 * existing revisions of the 8169S/8110S chips need to be tuned in
410 * order to reliably negotiate a 1000Mbps link. Later revs of the
411 * chips may not require this software tuning.
414 rgephy_load_dspcode(struct mii_softc *sc)
418 PHY_WRITE(sc, 31, 0x0001);
419 PHY_WRITE(sc, 21, 0x1000);
420 PHY_WRITE(sc, 24, 0x65C7);
421 PHY_CLRBIT(sc, 4, 0x0800);
422 val = PHY_READ(sc, 4) & 0xFFF;
423 PHY_WRITE(sc, 4, val);
424 PHY_WRITE(sc, 3, 0x00A1);
425 PHY_WRITE(sc, 2, 0x0008);
426 PHY_WRITE(sc, 1, 0x1020);
427 PHY_WRITE(sc, 0, 0x1000);
428 PHY_SETBIT(sc, 4, 0x0800);
429 PHY_CLRBIT(sc, 4, 0x0800);
430 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
431 PHY_WRITE(sc, 4, val);
432 PHY_WRITE(sc, 3, 0xFF41);
433 PHY_WRITE(sc, 2, 0xDE60);
434 PHY_WRITE(sc, 1, 0x0140);
435 PHY_WRITE(sc, 0, 0x0077);
436 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
437 PHY_WRITE(sc, 4, val);
438 PHY_WRITE(sc, 3, 0xDF01);
439 PHY_WRITE(sc, 2, 0xDF20);
440 PHY_WRITE(sc, 1, 0xFF95);
441 PHY_WRITE(sc, 0, 0xFA00);
442 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
443 PHY_WRITE(sc, 4, val);
444 PHY_WRITE(sc, 3, 0xFF41);
445 PHY_WRITE(sc, 2, 0xDE20);
446 PHY_WRITE(sc, 1, 0x0140);
447 PHY_WRITE(sc, 0, 0x00BB);
448 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
449 PHY_WRITE(sc, 4, val);
450 PHY_WRITE(sc, 3, 0xDF01);
451 PHY_WRITE(sc, 2, 0xDF20);
452 PHY_WRITE(sc, 1, 0xFF95);
453 PHY_WRITE(sc, 0, 0xBF00);
454 PHY_SETBIT(sc, 4, 0x0800);
455 PHY_CLRBIT(sc, 4, 0x0800);
456 PHY_WRITE(sc, 31, 0x0000);
462 rgephy_reset(struct mii_softc *sc)
466 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_AUTOEN);
468 rgephy_load_dspcode(sc);