1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx *reg_equiv_invariant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx *reg_equiv_address;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx *reg_equiv_alt_mem_list;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
162 call-saved. This is only meaningful for members of reg_reloaded_valid. */
163 static HARD_REG_SET reg_reloaded_call_part_clobbered;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs[FIRST_PSEUDO_REGISTER];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET *pseudo_previous_regs;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET *pseudo_forbidden_regs;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos;
261 /* Record which pseudos changed their allocation in finish_spills. */
262 static regset_head changed_allocation_pseudos;
264 /* Used for communication between order_regs_for_reload and count_pseudo.
265 Used to avoid counting one pseudo twice. */
266 static regset_head pseudos_counted;
268 /* First uid used by insns created by reload in this function.
269 Used in find_equiv_reg. */
270 int reload_first_uid;
272 /* Flag set by local-alloc or global-alloc if anything is live in
273 a call-clobbered reg across calls. */
274 int caller_save_needed;
276 /* Set to 1 while reload_as_needed is operating.
277 Required by some machines to handle any generated moves differently. */
278 int reload_in_progress = 0;
280 /* These arrays record the insn_code of insns that may be needed to
281 perform input and output reloads of special objects. They provide a
282 place to pass a scratch register. */
283 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
284 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
286 /* This obstack is used for allocation of rtl during register elimination.
287 The allocated storage can be freed once find_reloads has processed the
289 static struct obstack reload_obstack;
291 /* Points to the beginning of the reload_obstack. All insn_chain structures
292 are allocated first. */
293 static char *reload_startobj;
295 /* The point after all insn_chain structures. Used to quickly deallocate
296 memory allocated in copy_reloads during calculate_needs_all_insns. */
297 static char *reload_firstobj;
299 /* This points before all local rtl generated by register elimination.
300 Used to quickly free all memory after processing one insn. */
301 static char *reload_insn_firstobj;
303 /* List of insn_chain instructions, one for every insn that reload needs to
305 struct insn_chain *reload_insn_chain;
307 /* List of all insns needing reloads. */
308 static struct insn_chain *insns_need_reload;
310 /* This structure is used to record information about register eliminations.
311 Each array entry describes one possible way of eliminating a register
312 in favor of another. If there is more than one way of eliminating a
313 particular register, the most preferred should be specified first. */
317 int from; /* Register number to be eliminated. */
318 int to; /* Register number used as replacement. */
319 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
320 int can_eliminate; /* Nonzero if this elimination can be done. */
321 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
322 insns made by reload. */
323 HOST_WIDE_INT offset; /* Current offset between the two regs. */
324 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
325 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
326 rtx from_rtx; /* REG rtx for the register to be eliminated.
327 We cannot simply compare the number since
328 we might then spuriously replace a hard
329 register corresponding to a pseudo
330 assigned to the reg to be eliminated. */
331 rtx to_rtx; /* REG rtx for the replacement. */
334 static struct elim_table *reg_eliminate = 0;
336 /* This is an intermediate structure to initialize the table. It has
337 exactly the members provided by ELIMINABLE_REGS. */
338 static const struct elim_table_1
342 } reg_eliminate_1[] =
344 /* If a set of eliminable registers was specified, define the table from it.
345 Otherwise, default to the normal case of the frame pointer being
346 replaced by the stack pointer. */
348 #ifdef ELIMINABLE_REGS
351 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
354 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
356 /* Record the number of pending eliminations that have an offset not equal
357 to their initial offset. If nonzero, we use a new copy of each
358 replacement result in any insns encountered. */
359 int num_not_at_initial_offset;
361 /* Count the number of registers that we may be able to eliminate. */
362 static int num_eliminable;
363 /* And the number of registers that are equivalent to a constant that
364 can be eliminated to frame_pointer / arg_pointer + constant. */
365 static int num_eliminable_invariants;
367 /* For each label, we record the offset of each elimination. If we reach
368 a label by more than one path and an offset differs, we cannot do the
369 elimination. This information is indexed by the difference of the
370 number of the label and the first label number. We can't offset the
371 pointer itself as this can cause problems on machines with segmented
372 memory. The first table is an array of flags that records whether we
373 have yet encountered a label and the second table is an array of arrays,
374 one entry in the latter array for each elimination. */
376 static int first_label_num;
377 static char *offsets_known_at;
378 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
380 /* Number of labels in the current function. */
382 static int num_labels;
384 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
385 static void maybe_fix_stack_asms (void);
386 static void copy_reloads (struct insn_chain *);
387 static void calculate_needs_all_insns (int);
388 static int find_reg (struct insn_chain *, int);
389 static void find_reload_regs (struct insn_chain *);
390 static void select_reload_regs (void);
391 static void delete_caller_save_insns (void);
393 static void spill_failure (rtx, enum reg_class);
394 static void count_spilled_pseudo (int, int, int);
395 static void delete_dead_insn (rtx);
396 static void alter_reg (int, int, bool);
397 static void set_label_offsets (rtx, rtx, int);
398 static void check_eliminable_occurrences (rtx);
399 static void elimination_effects (rtx, enum machine_mode);
400 static int eliminate_regs_in_insn (rtx, int);
401 static void update_eliminable_offsets (void);
402 static void mark_not_eliminable (rtx, const_rtx, void *);
403 static void set_initial_elim_offsets (void);
404 static bool verify_initial_elim_offsets (void);
405 static void set_initial_label_offsets (void);
406 static void set_offsets_for_label (rtx);
407 static void init_elim_table (void);
408 static void update_eliminables (HARD_REG_SET *);
409 static void spill_hard_reg (unsigned int, int);
410 static int finish_spills (int);
411 static void scan_paradoxical_subregs (rtx);
412 static void count_pseudo (int);
413 static void order_regs_for_reload (struct insn_chain *);
414 static void reload_as_needed (int);
415 static void forget_old_reloads_1 (rtx, const_rtx, void *);
416 static void forget_marked_reloads (regset);
417 static int reload_reg_class_lower (const void *, const void *);
418 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
420 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
422 static int reload_reg_free_p (unsigned int, int, enum reload_type);
423 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
425 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
427 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
428 static int allocate_reload_reg (struct insn_chain *, int, int);
429 static int conflicts_with_override (rtx);
430 static void failed_reload (rtx, int);
431 static int set_reload_reg (int, int);
432 static void choose_reload_regs_init (struct insn_chain *, rtx *);
433 static void choose_reload_regs (struct insn_chain *);
434 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
436 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
438 static void do_input_reload (struct insn_chain *, struct reload *, int);
439 static void do_output_reload (struct insn_chain *, struct reload *, int);
440 static void emit_reload_insns (struct insn_chain *);
441 static void delete_output_reload (rtx, int, int, rtx);
442 static void delete_address_reloads (rtx, rtx);
443 static void delete_address_reloads_1 (rtx, rtx, rtx);
444 static rtx inc_for_reload (rtx, rtx, rtx, int);
446 static void add_auto_inc_notes (rtx, rtx);
448 static void copy_eh_notes (rtx, rtx);
449 static void substitute (rtx *, const_rtx, rtx);
450 static bool gen_reload_chain_without_interm_reg_p (int, int);
451 static int reloads_conflict (int, int);
452 static rtx gen_reload (rtx, rtx, int, enum reload_type);
453 static rtx emit_insn_if_valid_for_reload (rtx);
455 /* Initialize the reload pass. This is called at the beginning of compilation
456 and may be called again if the target is reinitialized. */
463 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
464 Set spill_indirect_levels to the number of levels such addressing is
465 permitted, zero if it is not permitted at all. */
468 = gen_rtx_MEM (Pmode,
471 LAST_VIRTUAL_REGISTER + 1),
473 spill_indirect_levels = 0;
475 while (memory_address_p (QImode, tem))
477 spill_indirect_levels++;
478 tem = gen_rtx_MEM (Pmode, tem);
481 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
483 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
484 indirect_symref_ok = memory_address_p (QImode, tem);
486 /* See if reg+reg is a valid (and offsettable) address. */
488 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
490 tem = gen_rtx_PLUS (Pmode,
491 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
492 gen_rtx_REG (Pmode, i));
494 /* This way, we make sure that reg+reg is an offsettable address. */
495 tem = plus_constant (tem, 4);
497 if (memory_address_p (QImode, tem))
499 double_reg_address_ok = 1;
504 /* Initialize obstack for our rtl allocation. */
505 gcc_obstack_init (&reload_obstack);
506 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
508 INIT_REG_SET (&spilled_pseudos);
509 INIT_REG_SET (&changed_allocation_pseudos);
510 INIT_REG_SET (&pseudos_counted);
513 /* List of insn chains that are currently unused. */
514 static struct insn_chain *unused_insn_chains = 0;
516 /* Allocate an empty insn_chain structure. */
518 new_insn_chain (void)
520 struct insn_chain *c;
522 if (unused_insn_chains == 0)
524 c = XOBNEW (&reload_obstack, struct insn_chain);
525 INIT_REG_SET (&c->live_throughout);
526 INIT_REG_SET (&c->dead_or_set);
530 c = unused_insn_chains;
531 unused_insn_chains = c->next;
533 c->is_caller_save_insn = 0;
534 c->need_operand_change = 0;
540 /* Small utility function to set all regs in hard reg set TO which are
541 allocated to pseudos in regset FROM. */
544 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
547 reg_set_iterator rsi;
549 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
551 int r = reg_renumber[regno];
555 /* reload_combine uses the information from DF_LIVE_IN,
556 which might still contain registers that have not
557 actually been allocated since they have an
559 gcc_assert (ira_conflicts_p || reload_completed);
562 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
566 /* Replace all pseudos found in LOC with their corresponding
570 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
583 unsigned int regno = REGNO (x);
585 if (regno < FIRST_PSEUDO_REGISTER)
588 x = eliminate_regs (x, mem_mode, usage);
592 replace_pseudos_in (loc, mem_mode, usage);
596 if (reg_equiv_constant[regno])
597 *loc = reg_equiv_constant[regno];
598 else if (reg_equiv_mem[regno])
599 *loc = reg_equiv_mem[regno];
600 else if (reg_equiv_address[regno])
601 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
604 gcc_assert (!REG_P (regno_reg_rtx[regno])
605 || REGNO (regno_reg_rtx[regno]) != regno);
606 *loc = regno_reg_rtx[regno];
611 else if (code == MEM)
613 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
617 /* Process each of our operands recursively. */
618 fmt = GET_RTX_FORMAT (code);
619 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
621 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
622 else if (*fmt == 'E')
623 for (j = 0; j < XVECLEN (x, i); j++)
624 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
627 /* Determine if the current function has an exception receiver block
628 that reaches the exit block via non-exceptional edges */
631 has_nonexceptional_receiver (void)
635 basic_block *tos, *worklist, bb;
637 /* If we're not optimizing, then just err on the safe side. */
641 /* First determine which blocks can reach exit via normal paths. */
642 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
645 bb->flags &= ~BB_REACHABLE;
647 /* Place the exit block on our worklist. */
648 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
649 *tos++ = EXIT_BLOCK_PTR;
651 /* Iterate: find everything reachable from what we've already seen. */
652 while (tos != worklist)
656 FOR_EACH_EDGE (e, ei, bb->preds)
657 if (!(e->flags & EDGE_ABNORMAL))
659 basic_block src = e->src;
661 if (!(src->flags & BB_REACHABLE))
663 src->flags |= BB_REACHABLE;
670 /* Now see if there's a reachable block with an exceptional incoming
673 if (bb->flags & BB_REACHABLE)
674 FOR_EACH_EDGE (e, ei, bb->preds)
675 if (e->flags & EDGE_ABNORMAL)
678 /* No exceptional block reached exit unexceptionally. */
683 /* Global variables used by reload and its subroutines. */
685 /* Set during calculate_needs if an insn needs register elimination. */
686 static int something_needs_elimination;
687 /* Set during calculate_needs if an insn needs an operand changed. */
688 static int something_needs_operands_changed;
690 /* Nonzero means we couldn't get enough spill regs. */
693 /* Temporary array of pseudo-register number. */
694 static int *temp_pseudo_reg_arr;
696 /* Main entry point for the reload pass.
698 FIRST is the first insn of the function being compiled.
700 GLOBAL nonzero means we were called from global_alloc
701 and should attempt to reallocate any pseudoregs that we
702 displace from hard regs we will use for reloads.
703 If GLOBAL is zero, we do not have enough information to do that,
704 so any pseudo reg that is spilled must go to the stack.
706 Return value is nonzero if reload failed
707 and we must not do any more for this function. */
710 reload (rtx first, int global)
714 struct elim_table *ep;
717 /* Make sure even insns with volatile mem refs are recognizable. */
722 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
724 /* Make sure that the last insn in the chain
725 is not something that needs reloading. */
726 emit_note (NOTE_INSN_DELETED);
728 /* Enable find_equiv_reg to distinguish insns made by reload. */
729 reload_first_uid = get_max_uid ();
731 #ifdef SECONDARY_MEMORY_NEEDED
732 /* Initialize the secondary memory table. */
733 clear_secondary_mem ();
736 /* We don't have a stack slot for any spill reg yet. */
737 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
738 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
740 /* Initialize the save area information for caller-save, in case some
744 /* Compute which hard registers are now in use
745 as homes for pseudo registers.
746 This is done here rather than (eg) in global_alloc
747 because this point is reached even if not optimizing. */
748 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
751 /* A function that has a nonlocal label that can reach the exit
752 block via non-exceptional paths must save all call-saved
754 if (cfun->has_nonlocal_label
755 && has_nonexceptional_receiver ())
756 crtl->saves_all_registers = 1;
758 if (crtl->saves_all_registers)
759 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
760 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
761 df_set_regs_ever_live (i, true);
763 /* Find all the pseudo registers that didn't get hard regs
764 but do have known equivalent constants or memory slots.
765 These include parameters (known equivalent to parameter slots)
766 and cse'd or loop-moved constant memory addresses.
768 Record constant equivalents in reg_equiv_constant
769 so they will be substituted by find_reloads.
770 Record memory equivalents in reg_mem_equiv so they can
771 be substituted eventually by altering the REG-rtx's. */
773 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
774 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
775 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
776 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
777 reg_equiv_address = XCNEWVEC (rtx, max_regno);
778 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
779 reg_old_renumber = XCNEWVEC (short, max_regno);
780 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
781 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
782 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
784 CLEAR_HARD_REG_SET (bad_spill_regs_global);
786 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
787 to. Also find all paradoxical subregs and find largest such for
790 num_eliminable_invariants = 0;
791 for (insn = first; insn; insn = NEXT_INSN (insn))
793 rtx set = single_set (insn);
795 /* We may introduce USEs that we want to remove at the end, so
796 we'll mark them with QImode. Make sure there are no
797 previously-marked insns left by say regmove. */
798 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
799 && GET_MODE (insn) != VOIDmode)
800 PUT_MODE (insn, VOIDmode);
803 scan_paradoxical_subregs (PATTERN (insn));
805 if (set != 0 && REG_P (SET_DEST (set)))
807 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
813 i = REGNO (SET_DEST (set));
816 if (i <= LAST_VIRTUAL_REGISTER)
819 if (! function_invariant_p (x)
821 /* A function invariant is often CONSTANT_P but may
822 include a register. We promise to only pass
823 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
825 && LEGITIMATE_PIC_OPERAND_P (x)))
827 /* It can happen that a REG_EQUIV note contains a MEM
828 that is not a legitimate memory operand. As later
829 stages of reload assume that all addresses found
830 in the reg_equiv_* arrays were originally legitimate,
831 we ignore such REG_EQUIV notes. */
832 if (memory_operand (x, VOIDmode))
834 /* Always unshare the equivalence, so we can
835 substitute into this insn without touching the
837 reg_equiv_memory_loc[i] = copy_rtx (x);
839 else if (function_invariant_p (x))
841 if (GET_CODE (x) == PLUS)
843 /* This is PLUS of frame pointer and a constant,
844 and might be shared. Unshare it. */
845 reg_equiv_invariant[i] = copy_rtx (x);
846 num_eliminable_invariants++;
848 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
850 reg_equiv_invariant[i] = x;
851 num_eliminable_invariants++;
853 else if (LEGITIMATE_CONSTANT_P (x))
854 reg_equiv_constant[i] = x;
857 reg_equiv_memory_loc[i]
858 = force_const_mem (GET_MODE (SET_DEST (set)), x);
859 if (! reg_equiv_memory_loc[i])
860 reg_equiv_init[i] = NULL_RTX;
865 reg_equiv_init[i] = NULL_RTX;
870 reg_equiv_init[i] = NULL_RTX;
875 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
876 if (reg_equiv_init[i])
878 fprintf (dump_file, "init_insns for %u: ", i);
879 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
880 fprintf (dump_file, "\n");
885 first_label_num = get_first_label_num ();
886 num_labels = max_label_num () - first_label_num;
888 /* Allocate the tables used to store offset information at labels. */
889 /* We used to use alloca here, but the size of what it would try to
890 allocate would occasionally cause it to exceed the stack limit and
891 cause a core dump. */
892 offsets_known_at = XNEWVEC (char, num_labels);
893 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
895 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
896 stack slots to the pseudos that lack hard regs or equivalents.
897 Do not touch virtual registers. */
899 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
900 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
901 temp_pseudo_reg_arr[n++] = i;
904 /* Ask IRA to order pseudo-registers for better stack slot
906 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
908 for (i = 0; i < n; i++)
909 alter_reg (temp_pseudo_reg_arr[i], -1, false);
911 /* If we have some registers we think can be eliminated, scan all insns to
912 see if there is an insn that sets one of these registers to something
913 other than itself plus a constant. If so, the register cannot be
914 eliminated. Doing this scan here eliminates an extra pass through the
915 main reload loop in the most common case where register elimination
917 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
919 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
921 maybe_fix_stack_asms ();
923 insns_need_reload = 0;
924 something_needs_elimination = 0;
926 /* Initialize to -1, which means take the first spill register. */
929 /* Spill any hard regs that we know we can't eliminate. */
930 CLEAR_HARD_REG_SET (used_spill_regs);
931 /* There can be multiple ways to eliminate a register;
932 they should be listed adjacently.
933 Elimination for any register fails only if all possible ways fail. */
934 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
937 int can_eliminate = 0;
940 can_eliminate |= ep->can_eliminate;
943 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
945 spill_hard_reg (from, 1);
948 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
949 if (frame_pointer_needed)
950 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
952 finish_spills (global);
954 /* From now on, we may need to generate moves differently. We may also
955 allow modifications of insns which cause them to not be recognized.
956 Any such modifications will be cleaned up during reload itself. */
957 reload_in_progress = 1;
959 /* This loop scans the entire function each go-round
960 and repeats until one repetition spills no additional hard regs. */
963 int something_changed;
965 HOST_WIDE_INT starting_frame_size;
967 starting_frame_size = get_frame_size ();
969 set_initial_elim_offsets ();
970 set_initial_label_offsets ();
972 /* For each pseudo register that has an equivalent location defined,
973 try to eliminate any eliminable registers (such as the frame pointer)
974 assuming initial offsets for the replacement register, which
977 If the resulting location is directly addressable, substitute
978 the MEM we just got directly for the old REG.
980 If it is not addressable but is a constant or the sum of a hard reg
981 and constant, it is probably not addressable because the constant is
982 out of range, in that case record the address; we will generate
983 hairy code to compute the address in a register each time it is
984 needed. Similarly if it is a hard register, but one that is not
985 valid as an address register.
987 If the location is not addressable, but does not have one of the
988 above forms, assign a stack slot. We have to do this to avoid the
989 potential of producing lots of reloads if, e.g., a location involves
990 a pseudo that didn't get a hard register and has an equivalent memory
991 location that also involves a pseudo that didn't get a hard register.
993 Perhaps at some point we will improve reload_when_needed handling
994 so this problem goes away. But that's very hairy. */
996 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
997 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
999 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
1001 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
1003 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
1004 else if (CONSTANT_P (XEXP (x, 0))
1005 || (REG_P (XEXP (x, 0))
1006 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
1007 || (GET_CODE (XEXP (x, 0)) == PLUS
1008 && REG_P (XEXP (XEXP (x, 0), 0))
1009 && (REGNO (XEXP (XEXP (x, 0), 0))
1010 < FIRST_PSEUDO_REGISTER)
1011 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
1012 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
1015 /* Make a new stack slot. Then indicate that something
1016 changed so we go back and recompute offsets for
1017 eliminable registers because the allocation of memory
1018 below might change some offset. reg_equiv_{mem,address}
1019 will be set up for this pseudo on the next pass around
1021 reg_equiv_memory_loc[i] = 0;
1022 reg_equiv_init[i] = 0;
1023 alter_reg (i, -1, true);
1027 if (caller_save_needed)
1028 setup_save_areas ();
1030 /* If we allocated another stack slot, redo elimination bookkeeping. */
1031 if (starting_frame_size != get_frame_size ())
1033 if (starting_frame_size && crtl->stack_alignment_needed)
1035 /* If we have a stack frame, we must align it now. The
1036 stack size may be a part of the offset computation for
1037 register elimination. So if this changes the stack size,
1038 then repeat the elimination bookkeeping. We don't
1039 realign when there is no stack, as that will cause a
1040 stack frame when none is needed should
1041 STARTING_FRAME_OFFSET not be already aligned to
1043 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1044 if (starting_frame_size != get_frame_size ())
1048 if (caller_save_needed)
1050 save_call_clobbered_regs ();
1051 /* That might have allocated new insn_chain structures. */
1052 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1055 calculate_needs_all_insns (global);
1057 if (! ira_conflicts_p)
1058 /* Don't do it for IRA. We need this info because we don't
1059 change live_throughout and dead_or_set for chains when IRA
1061 CLEAR_REG_SET (&spilled_pseudos);
1065 something_changed = 0;
1067 /* If we allocated any new memory locations, make another pass
1068 since it might have changed elimination offsets. */
1069 if (starting_frame_size != get_frame_size ())
1070 something_changed = 1;
1072 /* Even if the frame size remained the same, we might still have
1073 changed elimination offsets, e.g. if find_reloads called
1074 force_const_mem requiring the back end to allocate a constant
1075 pool base register that needs to be saved on the stack. */
1076 else if (!verify_initial_elim_offsets ())
1077 something_changed = 1;
1080 HARD_REG_SET to_spill;
1081 CLEAR_HARD_REG_SET (to_spill);
1082 update_eliminables (&to_spill);
1083 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1085 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1086 if (TEST_HARD_REG_BIT (to_spill, i))
1088 spill_hard_reg (i, 1);
1091 /* Regardless of the state of spills, if we previously had
1092 a register that we thought we could eliminate, but now can
1093 not eliminate, we must run another pass.
1095 Consider pseudos which have an entry in reg_equiv_* which
1096 reference an eliminable register. We must make another pass
1097 to update reg_equiv_* so that we do not substitute in the
1098 old value from when we thought the elimination could be
1100 something_changed = 1;
1104 select_reload_regs ();
1108 if (insns_need_reload != 0 || did_spill)
1109 something_changed |= finish_spills (global);
1111 if (! something_changed)
1114 if (caller_save_needed)
1115 delete_caller_save_insns ();
1117 obstack_free (&reload_obstack, reload_firstobj);
1120 /* If global-alloc was run, notify it of any register eliminations we have
1123 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1124 if (ep->can_eliminate)
1125 mark_elimination (ep->from, ep->to);
1127 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1128 If that insn didn't set the register (i.e., it copied the register to
1129 memory), just delete that insn instead of the equivalencing insn plus
1130 anything now dead. If we call delete_dead_insn on that insn, we may
1131 delete the insn that actually sets the register if the register dies
1132 there and that is incorrect. */
1134 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1136 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1139 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1141 rtx equiv_insn = XEXP (list, 0);
1143 /* If we already deleted the insn or if it may trap, we can't
1144 delete it. The latter case shouldn't happen, but can
1145 if an insn has a variable address, gets a REG_EH_REGION
1146 note added to it, and then gets converted into a load
1147 from a constant address. */
1148 if (NOTE_P (equiv_insn)
1149 || can_throw_internal (equiv_insn))
1151 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1152 delete_dead_insn (equiv_insn);
1154 SET_INSN_DELETED (equiv_insn);
1159 /* Use the reload registers where necessary
1160 by generating move instructions to move the must-be-register
1161 values into or out of the reload registers. */
1163 if (insns_need_reload != 0 || something_needs_elimination
1164 || something_needs_operands_changed)
1166 HOST_WIDE_INT old_frame_size = get_frame_size ();
1168 reload_as_needed (global);
1170 gcc_assert (old_frame_size == get_frame_size ());
1172 gcc_assert (verify_initial_elim_offsets ());
1175 /* If we were able to eliminate the frame pointer, show that it is no
1176 longer live at the start of any basic block. If it ls live by
1177 virtue of being in a pseudo, that pseudo will be marked live
1178 and hence the frame pointer will be known to be live via that
1181 if (! frame_pointer_needed)
1183 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1185 /* Come here (with failure set nonzero) if we can't get enough spill
1189 CLEAR_REG_SET (&changed_allocation_pseudos);
1190 CLEAR_REG_SET (&spilled_pseudos);
1191 reload_in_progress = 0;
1193 /* Now eliminate all pseudo regs by modifying them into
1194 their equivalent memory references.
1195 The REG-rtx's for the pseudos are modified in place,
1196 so all insns that used to refer to them now refer to memory.
1198 For a reg that has a reg_equiv_address, all those insns
1199 were changed by reloading so that no insns refer to it any longer;
1200 but the DECL_RTL of a variable decl may refer to it,
1201 and if so this causes the debugging info to mention the variable. */
1203 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1207 if (reg_equiv_mem[i])
1208 addr = XEXP (reg_equiv_mem[i], 0);
1210 if (reg_equiv_address[i])
1211 addr = reg_equiv_address[i];
1215 if (reg_renumber[i] < 0)
1217 rtx reg = regno_reg_rtx[i];
1219 REG_USERVAR_P (reg) = 0;
1220 PUT_CODE (reg, MEM);
1221 XEXP (reg, 0) = addr;
1222 if (reg_equiv_memory_loc[i])
1223 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1226 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1227 MEM_ATTRS (reg) = 0;
1229 MEM_NOTRAP_P (reg) = 1;
1231 else if (reg_equiv_mem[i])
1232 XEXP (reg_equiv_mem[i], 0) = addr;
1236 /* We must set reload_completed now since the cleanup_subreg_operands call
1237 below will re-recognize each insn and reload may have generated insns
1238 which are only valid during and after reload. */
1239 reload_completed = 1;
1241 /* Make a pass over all the insns and delete all USEs which we inserted
1242 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1243 notes. Delete all CLOBBER insns, except those that refer to the return
1244 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1245 from misarranging variable-array code, and simplify (subreg (reg))
1246 operands. Strip and regenerate REG_INC notes that may have been moved
1249 for (insn = first; insn; insn = NEXT_INSN (insn))
1255 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1256 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1258 if ((GET_CODE (PATTERN (insn)) == USE
1259 /* We mark with QImode USEs introduced by reload itself. */
1260 && (GET_MODE (insn) == QImode
1261 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1262 || (GET_CODE (PATTERN (insn)) == CLOBBER
1263 && (!MEM_P (XEXP (PATTERN (insn), 0))
1264 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1265 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1266 && XEXP (XEXP (PATTERN (insn), 0), 0)
1267 != stack_pointer_rtx))
1268 && (!REG_P (XEXP (PATTERN (insn), 0))
1269 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1275 /* Some CLOBBERs may survive until here and still reference unassigned
1276 pseudos with const equivalent, which may in turn cause ICE in later
1277 passes if the reference remains in place. */
1278 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1279 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1280 VOIDmode, PATTERN (insn));
1282 /* Discard obvious no-ops, even without -O. This optimization
1283 is fast and doesn't interfere with debugging. */
1284 if (NONJUMP_INSN_P (insn)
1285 && GET_CODE (PATTERN (insn)) == SET
1286 && REG_P (SET_SRC (PATTERN (insn)))
1287 && REG_P (SET_DEST (PATTERN (insn)))
1288 && (REGNO (SET_SRC (PATTERN (insn)))
1289 == REGNO (SET_DEST (PATTERN (insn)))))
1295 pnote = ®_NOTES (insn);
1298 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1299 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1300 || REG_NOTE_KIND (*pnote) == REG_INC)
1301 *pnote = XEXP (*pnote, 1);
1303 pnote = &XEXP (*pnote, 1);
1307 add_auto_inc_notes (insn, PATTERN (insn));
1310 /* Simplify (subreg (reg)) if it appears as an operand. */
1311 cleanup_subreg_operands (insn);
1313 /* Clean up invalid ASMs so that they don't confuse later passes.
1315 if (asm_noperands (PATTERN (insn)) >= 0)
1317 extract_insn (insn);
1318 if (!constrain_operands (1))
1320 error_for_asm (insn,
1321 "%<asm%> operand has impossible constraints");
1328 /* If we are doing generic stack checking, give a warning if this
1329 function's frame size is larger than we expect. */
1330 if (flag_stack_check == GENERIC_STACK_CHECK)
1332 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1333 static int verbose_warned = 0;
1335 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1336 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1337 size += UNITS_PER_WORD;
1339 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1341 warning (0, "frame size too large for reliable stack checking");
1342 if (! verbose_warned)
1344 warning (0, "try reducing the number of local variables");
1350 /* Indicate that we no longer have known memory locations or constants. */
1351 if (reg_equiv_constant)
1352 free (reg_equiv_constant);
1353 if (reg_equiv_invariant)
1354 free (reg_equiv_invariant);
1355 reg_equiv_constant = 0;
1356 reg_equiv_invariant = 0;
1357 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1358 reg_equiv_memory_loc = 0;
1360 free (temp_pseudo_reg_arr);
1362 if (offsets_known_at)
1363 free (offsets_known_at);
1367 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1368 if (reg_equiv_alt_mem_list[i])
1369 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1370 free (reg_equiv_alt_mem_list);
1372 free (reg_equiv_mem);
1374 free (reg_equiv_address);
1375 free (reg_max_ref_width);
1376 free (reg_old_renumber);
1377 free (pseudo_previous_regs);
1378 free (pseudo_forbidden_regs);
1380 CLEAR_HARD_REG_SET (used_spill_regs);
1381 for (i = 0; i < n_spills; i++)
1382 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1384 /* Free all the insn_chain structures at once. */
1385 obstack_free (&reload_obstack, reload_startobj);
1386 unused_insn_chains = 0;
1387 fixup_abnormal_edges ();
1389 /* Replacing pseudos with their memory equivalents might have
1390 created shared rtx. Subsequent passes would get confused
1391 by this, so unshare everything here. */
1392 unshare_all_rtl_again (first);
1394 #ifdef STACK_BOUNDARY
1395 /* init_emit has set the alignment of the hard frame pointer
1396 to STACK_BOUNDARY. It is very likely no longer valid if
1397 the hard frame pointer was used for register allocation. */
1398 if (!frame_pointer_needed)
1399 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1405 /* Yet another special case. Unfortunately, reg-stack forces people to
1406 write incorrect clobbers in asm statements. These clobbers must not
1407 cause the register to appear in bad_spill_regs, otherwise we'll call
1408 fatal_insn later. We clear the corresponding regnos in the live
1409 register sets to avoid this.
1410 The whole thing is rather sick, I'm afraid. */
1413 maybe_fix_stack_asms (void)
1416 const char *constraints[MAX_RECOG_OPERANDS];
1417 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1418 struct insn_chain *chain;
1420 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1423 HARD_REG_SET clobbered, allowed;
1426 if (! INSN_P (chain->insn)
1427 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1429 pat = PATTERN (chain->insn);
1430 if (GET_CODE (pat) != PARALLEL)
1433 CLEAR_HARD_REG_SET (clobbered);
1434 CLEAR_HARD_REG_SET (allowed);
1436 /* First, make a mask of all stack regs that are clobbered. */
1437 for (i = 0; i < XVECLEN (pat, 0); i++)
1439 rtx t = XVECEXP (pat, 0, i);
1440 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1441 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1444 /* Get the operand values and constraints out of the insn. */
1445 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1446 constraints, operand_mode, NULL);
1448 /* For every operand, see what registers are allowed. */
1449 for (i = 0; i < noperands; i++)
1451 const char *p = constraints[i];
1452 /* For every alternative, we compute the class of registers allowed
1453 for reloading in CLS, and merge its contents into the reg set
1455 int cls = (int) NO_REGS;
1461 if (c == '\0' || c == ',' || c == '#')
1463 /* End of one alternative - mark the regs in the current
1464 class, and reset the class. */
1465 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1471 } while (c != '\0' && c != ',');
1479 case '=': case '+': case '*': case '%': case '?': case '!':
1480 case '0': case '1': case '2': case '3': case '4': case '<':
1481 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1482 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1483 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1484 case TARGET_MEM_CONSTRAINT:
1488 cls = (int) reg_class_subunion[cls]
1489 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1494 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1498 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1499 cls = (int) reg_class_subunion[cls]
1500 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1502 cls = (int) reg_class_subunion[cls]
1503 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1505 p += CONSTRAINT_LEN (c, p);
1508 /* Those of the registers which are clobbered, but allowed by the
1509 constraints, must be usable as reload registers. So clear them
1510 out of the life information. */
1511 AND_HARD_REG_SET (allowed, clobbered);
1512 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1513 if (TEST_HARD_REG_BIT (allowed, i))
1515 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1516 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1523 /* Copy the global variables n_reloads and rld into the corresponding elts
1526 copy_reloads (struct insn_chain *chain)
1528 chain->n_reloads = n_reloads;
1529 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1530 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1531 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1534 /* Walk the chain of insns, and determine for each whether it needs reloads
1535 and/or eliminations. Build the corresponding insns_need_reload list, and
1536 set something_needs_elimination as appropriate. */
1538 calculate_needs_all_insns (int global)
1540 struct insn_chain **pprev_reload = &insns_need_reload;
1541 struct insn_chain *chain, *next = 0;
1543 something_needs_elimination = 0;
1545 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1546 for (chain = reload_insn_chain; chain != 0; chain = next)
1548 rtx insn = chain->insn;
1552 /* Clear out the shortcuts. */
1553 chain->n_reloads = 0;
1554 chain->need_elim = 0;
1555 chain->need_reload = 0;
1556 chain->need_operand_change = 0;
1558 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1559 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1560 what effects this has on the known offsets at labels. */
1562 if (LABEL_P (insn) || JUMP_P (insn)
1563 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1564 set_label_offsets (insn, insn, 0);
1568 rtx old_body = PATTERN (insn);
1569 int old_code = INSN_CODE (insn);
1570 rtx old_notes = REG_NOTES (insn);
1571 int did_elimination = 0;
1572 int operands_changed = 0;
1573 rtx set = single_set (insn);
1575 /* Skip insns that only set an equivalence. */
1576 if (set && REG_P (SET_DEST (set))
1577 && reg_renumber[REGNO (SET_DEST (set))] < 0
1578 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1579 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1580 && reg_equiv_init[REGNO (SET_DEST (set))])
1583 /* If needed, eliminate any eliminable registers. */
1584 if (num_eliminable || num_eliminable_invariants)
1585 did_elimination = eliminate_regs_in_insn (insn, 0);
1587 /* Analyze the instruction. */
1588 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1589 global, spill_reg_order);
1591 /* If a no-op set needs more than one reload, this is likely
1592 to be something that needs input address reloads. We
1593 can't get rid of this cleanly later, and it is of no use
1594 anyway, so discard it now.
1595 We only do this when expensive_optimizations is enabled,
1596 since this complements reload inheritance / output
1597 reload deletion, and it can make debugging harder. */
1598 if (flag_expensive_optimizations && n_reloads > 1)
1600 rtx set = single_set (insn);
1603 ((SET_SRC (set) == SET_DEST (set)
1604 && REG_P (SET_SRC (set))
1605 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1606 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1607 && reg_renumber[REGNO (SET_SRC (set))] < 0
1608 && reg_renumber[REGNO (SET_DEST (set))] < 0
1609 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1610 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1611 && rtx_equal_p (reg_equiv_memory_loc
1612 [REGNO (SET_SRC (set))],
1613 reg_equiv_memory_loc
1614 [REGNO (SET_DEST (set))]))))
1616 if (ira_conflicts_p)
1617 /* Inform IRA about the insn deletion. */
1618 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1619 REGNO (SET_SRC (set)));
1621 /* Delete it from the reload chain. */
1623 chain->prev->next = next;
1625 reload_insn_chain = next;
1627 next->prev = chain->prev;
1628 chain->next = unused_insn_chains;
1629 unused_insn_chains = chain;
1634 update_eliminable_offsets ();
1636 /* Remember for later shortcuts which insns had any reloads or
1637 register eliminations. */
1638 chain->need_elim = did_elimination;
1639 chain->need_reload = n_reloads > 0;
1640 chain->need_operand_change = operands_changed;
1642 /* Discard any register replacements done. */
1643 if (did_elimination)
1645 obstack_free (&reload_obstack, reload_insn_firstobj);
1646 PATTERN (insn) = old_body;
1647 INSN_CODE (insn) = old_code;
1648 REG_NOTES (insn) = old_notes;
1649 something_needs_elimination = 1;
1652 something_needs_operands_changed |= operands_changed;
1656 copy_reloads (chain);
1657 *pprev_reload = chain;
1658 pprev_reload = &chain->next_need_reload;
1665 /* Comparison function for qsort to decide which of two reloads
1666 should be handled first. *P1 and *P2 are the reload numbers. */
1669 reload_reg_class_lower (const void *r1p, const void *r2p)
1671 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1674 /* Consider required reloads before optional ones. */
1675 t = rld[r1].optional - rld[r2].optional;
1679 /* Count all solitary classes before non-solitary ones. */
1680 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1681 - (reg_class_size[(int) rld[r1].rclass] == 1));
1685 /* Aside from solitaires, consider all multi-reg groups first. */
1686 t = rld[r2].nregs - rld[r1].nregs;
1690 /* Consider reloads in order of increasing reg-class number. */
1691 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1695 /* If reloads are equally urgent, sort by reload number,
1696 so that the results of qsort leave nothing to chance. */
1700 /* The cost of spilling each hard reg. */
1701 static int spill_cost[FIRST_PSEUDO_REGISTER];
1703 /* When spilling multiple hard registers, we use SPILL_COST for the first
1704 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1705 only the first hard reg for a multi-reg pseudo. */
1706 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1708 /* Map of hard regno to pseudo regno currently occupying the hard
1710 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1712 /* Update the spill cost arrays, considering that pseudo REG is live. */
1715 count_pseudo (int reg)
1717 int freq = REG_FREQ (reg);
1718 int r = reg_renumber[reg];
1721 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1722 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1723 /* Ignore spilled pseudo-registers which can be here only if IRA
1725 || (ira_conflicts_p && r < 0))
1728 SET_REGNO_REG_SET (&pseudos_counted, reg);
1730 gcc_assert (r >= 0);
1732 spill_add_cost[r] += freq;
1733 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1736 hard_regno_to_pseudo_regno[r + nregs] = reg;
1737 spill_cost[r + nregs] += freq;
1741 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1742 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1745 order_regs_for_reload (struct insn_chain *chain)
1748 HARD_REG_SET used_by_pseudos;
1749 HARD_REG_SET used_by_pseudos2;
1750 reg_set_iterator rsi;
1752 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1754 memset (spill_cost, 0, sizeof spill_cost);
1755 memset (spill_add_cost, 0, sizeof spill_add_cost);
1756 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1757 hard_regno_to_pseudo_regno[i] = -1;
1759 /* Count number of uses of each hard reg by pseudo regs allocated to it
1760 and then order them by decreasing use. First exclude hard registers
1761 that are live in or across this insn. */
1763 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1764 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1765 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1766 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1768 /* Now find out which pseudos are allocated to it, and update
1770 CLEAR_REG_SET (&pseudos_counted);
1772 EXECUTE_IF_SET_IN_REG_SET
1773 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1777 EXECUTE_IF_SET_IN_REG_SET
1778 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1782 CLEAR_REG_SET (&pseudos_counted);
1785 /* Vector of reload-numbers showing the order in which the reloads should
1787 static short reload_order[MAX_RELOADS];
1789 /* This is used to keep track of the spill regs used in one insn. */
1790 static HARD_REG_SET used_spill_regs_local;
1792 /* We decided to spill hard register SPILLED, which has a size of
1793 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1794 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1795 update SPILL_COST/SPILL_ADD_COST. */
1798 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1800 int freq = REG_FREQ (reg);
1801 int r = reg_renumber[reg];
1802 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1804 /* Ignore spilled pseudo-registers which can be here only if IRA is
1806 if ((ira_conflicts_p && r < 0)
1807 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1808 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1811 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1813 spill_add_cost[r] -= freq;
1816 hard_regno_to_pseudo_regno[r + nregs] = -1;
1817 spill_cost[r + nregs] -= freq;
1821 /* Find reload register to use for reload number ORDER. */
1824 find_reg (struct insn_chain *chain, int order)
1826 int rnum = reload_order[order];
1827 struct reload *rl = rld + rnum;
1828 int best_cost = INT_MAX;
1830 unsigned int i, j, n;
1832 HARD_REG_SET not_usable;
1833 HARD_REG_SET used_by_other_reload;
1834 reg_set_iterator rsi;
1835 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1836 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1838 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1839 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1840 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1842 CLEAR_HARD_REG_SET (used_by_other_reload);
1843 for (k = 0; k < order; k++)
1845 int other = reload_order[k];
1847 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1848 for (j = 0; j < rld[other].nregs; j++)
1849 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1852 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1854 #ifdef REG_ALLOC_ORDER
1855 unsigned int regno = reg_alloc_order[i];
1857 unsigned int regno = i;
1860 if (! TEST_HARD_REG_BIT (not_usable, regno)
1861 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1862 && HARD_REGNO_MODE_OK (regno, rl->mode))
1864 int this_cost = spill_cost[regno];
1866 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1868 for (j = 1; j < this_nregs; j++)
1870 this_cost += spill_add_cost[regno + j];
1871 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1872 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1878 if (ira_conflicts_p)
1880 /* Ask IRA to find a better pseudo-register for
1882 for (n = j = 0; j < this_nregs; j++)
1884 int r = hard_regno_to_pseudo_regno[regno + j];
1888 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1889 regno_pseudo_regs[n++] = r;
1891 regno_pseudo_regs[n++] = -1;
1893 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1894 best_regno_pseudo_regs,
1901 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1902 if (regno_pseudo_regs[j] < 0)
1909 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1911 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1913 if (this_cost < best_cost
1914 /* Among registers with equal cost, prefer caller-saved ones, or
1915 use REG_ALLOC_ORDER if it is defined. */
1916 || (this_cost == best_cost
1917 #ifdef REG_ALLOC_ORDER
1918 && (inv_reg_alloc_order[regno]
1919 < inv_reg_alloc_order[best_reg])
1921 && call_used_regs[regno]
1922 && ! call_used_regs[best_reg]
1927 best_cost = this_cost;
1935 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1937 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1938 rl->regno = best_reg;
1940 EXECUTE_IF_SET_IN_REG_SET
1941 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1943 count_spilled_pseudo (best_reg, rl->nregs, j);
1946 EXECUTE_IF_SET_IN_REG_SET
1947 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1949 count_spilled_pseudo (best_reg, rl->nregs, j);
1952 for (i = 0; i < rl->nregs; i++)
1954 gcc_assert (spill_cost[best_reg + i] == 0);
1955 gcc_assert (spill_add_cost[best_reg + i] == 0);
1956 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1957 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1962 /* Find more reload regs to satisfy the remaining need of an insn, which
1964 Do it by ascending class number, since otherwise a reg
1965 might be spilled for a big class and might fail to count
1966 for a smaller class even though it belongs to that class. */
1969 find_reload_regs (struct insn_chain *chain)
1973 /* In order to be certain of getting the registers we need,
1974 we must sort the reloads into order of increasing register class.
1975 Then our grabbing of reload registers will parallel the process
1976 that provided the reload registers. */
1977 for (i = 0; i < chain->n_reloads; i++)
1979 /* Show whether this reload already has a hard reg. */
1980 if (chain->rld[i].reg_rtx)
1982 int regno = REGNO (chain->rld[i].reg_rtx);
1983 chain->rld[i].regno = regno;
1985 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1988 chain->rld[i].regno = -1;
1989 reload_order[i] = i;
1992 n_reloads = chain->n_reloads;
1993 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1995 CLEAR_HARD_REG_SET (used_spill_regs_local);
1998 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2000 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2002 /* Compute the order of preference for hard registers to spill. */
2004 order_regs_for_reload (chain);
2006 for (i = 0; i < n_reloads; i++)
2008 int r = reload_order[i];
2010 /* Ignore reloads that got marked inoperative. */
2011 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2012 && ! rld[r].optional
2013 && rld[r].regno == -1)
2014 if (! find_reg (chain, i))
2017 fprintf (dump_file, "reload failure for reload %d\n", r);
2018 spill_failure (chain->insn, rld[r].rclass);
2024 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2025 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2027 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2031 select_reload_regs (void)
2033 struct insn_chain *chain;
2035 /* Try to satisfy the needs for each insn. */
2036 for (chain = insns_need_reload; chain != 0;
2037 chain = chain->next_need_reload)
2038 find_reload_regs (chain);
2041 /* Delete all insns that were inserted by emit_caller_save_insns during
2044 delete_caller_save_insns (void)
2046 struct insn_chain *c = reload_insn_chain;
2050 while (c != 0 && c->is_caller_save_insn)
2052 struct insn_chain *next = c->next;
2055 if (c == reload_insn_chain)
2056 reload_insn_chain = next;
2060 next->prev = c->prev;
2062 c->prev->next = next;
2063 c->next = unused_insn_chains;
2064 unused_insn_chains = c;
2072 /* Handle the failure to find a register to spill.
2073 INSN should be one of the insns which needed this particular spill reg. */
2076 spill_failure (rtx insn, enum reg_class rclass)
2078 if (asm_noperands (PATTERN (insn)) >= 0)
2079 error_for_asm (insn, "can't find a register in class %qs while "
2080 "reloading %<asm%>",
2081 reg_class_names[rclass]);
2084 error ("unable to find a register to spill in class %qs",
2085 reg_class_names[rclass]);
2089 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2090 debug_reload_to_stream (dump_file);
2092 fatal_insn ("this is the insn:", insn);
2096 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2097 data that is dead in INSN. */
2100 delete_dead_insn (rtx insn)
2102 rtx prev = prev_real_insn (insn);
2105 /* If the previous insn sets a register that dies in our insn, delete it
2107 if (prev && GET_CODE (PATTERN (prev)) == SET
2108 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2109 && reg_mentioned_p (prev_dest, PATTERN (insn))
2110 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2111 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2112 delete_dead_insn (prev);
2114 SET_INSN_DELETED (insn);
2117 /* Modify the home of pseudo-reg I.
2118 The new home is present in reg_renumber[I].
2120 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2121 or it may be -1, meaning there is none or it is not relevant.
2122 This is used so that all pseudos spilled from a given hard reg
2123 can share one stack slot. */
2126 alter_reg (int i, int from_reg, bool dont_share_p)
2128 /* When outputting an inline function, this can happen
2129 for a reg that isn't actually used. */
2130 if (regno_reg_rtx[i] == 0)
2133 /* If the reg got changed to a MEM at rtl-generation time,
2135 if (!REG_P (regno_reg_rtx[i]))
2138 /* Modify the reg-rtx to contain the new hard reg
2139 number or else to contain its pseudo reg number. */
2140 SET_REGNO (regno_reg_rtx[i],
2141 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2143 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2144 allocate a stack slot for it. */
2146 if (reg_renumber[i] < 0
2147 && REG_N_REFS (i) > 0
2148 && reg_equiv_constant[i] == 0
2149 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2150 && reg_equiv_memory_loc[i] == 0)
2153 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2154 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2155 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2156 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2157 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2160 if (ira_conflicts_p)
2162 /* Mark the spill for IRA. */
2163 SET_REGNO_REG_SET (&spilled_pseudos, i);
2165 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2171 /* Each pseudo reg has an inherent size which comes from its own mode,
2172 and a total size which provides room for paradoxical subregs
2173 which refer to the pseudo reg in wider modes.
2175 We can use a slot already allocated if it provides both
2176 enough inherent space and enough total space.
2177 Otherwise, we allocate a new slot, making sure that it has no less
2178 inherent space, and no less total space, then the previous slot. */
2179 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2183 /* No known place to spill from => no slot to reuse. */
2184 x = assign_stack_local (mode, total_size,
2185 min_align > inherent_align
2186 || total_size > inherent_size ? -1 : 0);
2190 /* Cancel the big-endian correction done in assign_stack_local.
2191 Get the address of the beginning of the slot. This is so we
2192 can do a big-endian correction unconditionally below. */
2193 if (BYTES_BIG_ENDIAN)
2195 adjust = inherent_size - total_size;
2198 = adjust_address_nv (x, mode_for_size (total_size
2204 if (! dont_share_p && ira_conflicts_p)
2205 /* Inform IRA about allocation a new stack slot. */
2206 ira_mark_new_stack_slot (stack_slot, i, total_size);
2209 /* Reuse a stack slot if possible. */
2210 else if (spill_stack_slot[from_reg] != 0
2211 && spill_stack_slot_width[from_reg] >= total_size
2212 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2214 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2215 x = spill_stack_slot[from_reg];
2217 /* Allocate a bigger slot. */
2220 /* Compute maximum size needed, both for inherent size
2221 and for total size. */
2224 if (spill_stack_slot[from_reg])
2226 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2228 mode = GET_MODE (spill_stack_slot[from_reg]);
2229 if (spill_stack_slot_width[from_reg] > total_size)
2230 total_size = spill_stack_slot_width[from_reg];
2231 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2232 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2235 /* Make a slot with that size. */
2236 x = assign_stack_local (mode, total_size,
2237 min_align > inherent_align
2238 || total_size > inherent_size ? -1 : 0);
2241 /* Cancel the big-endian correction done in assign_stack_local.
2242 Get the address of the beginning of the slot. This is so we
2243 can do a big-endian correction unconditionally below. */
2244 if (BYTES_BIG_ENDIAN)
2246 adjust = GET_MODE_SIZE (mode) - total_size;
2249 = adjust_address_nv (x, mode_for_size (total_size
2255 spill_stack_slot[from_reg] = stack_slot;
2256 spill_stack_slot_width[from_reg] = total_size;
2259 /* On a big endian machine, the "address" of the slot
2260 is the address of the low part that fits its inherent mode. */
2261 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2262 adjust += (total_size - inherent_size);
2264 /* If we have any adjustment to make, or if the stack slot is the
2265 wrong mode, make a new stack slot. */
2266 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2268 /* Set all of the memory attributes as appropriate for a spill. */
2269 set_mem_attrs_for_spill (x);
2271 /* Save the stack slot for later. */
2272 reg_equiv_memory_loc[i] = x;
2276 /* Mark the slots in regs_ever_live for the hard regs used by
2277 pseudo-reg number REGNO, accessed in MODE. */
2280 mark_home_live_1 (int regno, enum machine_mode mode)
2284 i = reg_renumber[regno];
2287 lim = end_hard_regno (mode, i);
2289 df_set_regs_ever_live(i++, true);
2292 /* Mark the slots in regs_ever_live for the hard regs
2293 used by pseudo-reg number REGNO. */
2296 mark_home_live (int regno)
2298 if (reg_renumber[regno] >= 0)
2299 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2302 /* This function handles the tracking of elimination offsets around branches.
2304 X is a piece of RTL being scanned.
2306 INSN is the insn that it came from, if any.
2308 INITIAL_P is nonzero if we are to set the offset to be the initial
2309 offset and zero if we are setting the offset of the label to be the
2313 set_label_offsets (rtx x, rtx insn, int initial_p)
2315 enum rtx_code code = GET_CODE (x);
2318 struct elim_table *p;
2323 if (LABEL_REF_NONLOCAL_P (x))
2328 /* ... fall through ... */
2331 /* If we know nothing about this label, set the desired offsets. Note
2332 that this sets the offset at a label to be the offset before a label
2333 if we don't know anything about the label. This is not correct for
2334 the label after a BARRIER, but is the best guess we can make. If
2335 we guessed wrong, we will suppress an elimination that might have
2336 been possible had we been able to guess correctly. */
2338 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2340 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2341 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2342 = (initial_p ? reg_eliminate[i].initial_offset
2343 : reg_eliminate[i].offset);
2344 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2347 /* Otherwise, if this is the definition of a label and it is
2348 preceded by a BARRIER, set our offsets to the known offset of
2352 && (tem = prev_nonnote_insn (insn)) != 0
2354 set_offsets_for_label (insn);
2356 /* If neither of the above cases is true, compare each offset
2357 with those previously recorded and suppress any eliminations
2358 where the offsets disagree. */
2360 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2361 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2362 != (initial_p ? reg_eliminate[i].initial_offset
2363 : reg_eliminate[i].offset))
2364 reg_eliminate[i].can_eliminate = 0;
2369 set_label_offsets (PATTERN (insn), insn, initial_p);
2371 /* ... fall through ... */
2375 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2376 to indirectly and hence must have all eliminations at their
2378 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2379 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2380 set_label_offsets (XEXP (tem, 0), insn, 1);
2386 /* Each of the labels in the parallel or address vector must be
2387 at their initial offsets. We want the first field for PARALLEL
2388 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2390 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2391 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2396 /* We only care about setting PC. If the source is not RETURN,
2397 IF_THEN_ELSE, or a label, disable any eliminations not at
2398 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2399 isn't one of those possibilities. For branches to a label,
2400 call ourselves recursively.
2402 Note that this can disable elimination unnecessarily when we have
2403 a non-local goto since it will look like a non-constant jump to
2404 someplace in the current function. This isn't a significant
2405 problem since such jumps will normally be when all elimination
2406 pairs are back to their initial offsets. */
2408 if (SET_DEST (x) != pc_rtx)
2411 switch (GET_CODE (SET_SRC (x)))
2418 set_label_offsets (SET_SRC (x), insn, initial_p);
2422 tem = XEXP (SET_SRC (x), 1);
2423 if (GET_CODE (tem) == LABEL_REF)
2424 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2425 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2428 tem = XEXP (SET_SRC (x), 2);
2429 if (GET_CODE (tem) == LABEL_REF)
2430 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2431 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2439 /* If we reach here, all eliminations must be at their initial
2440 offset because we are doing a jump to a variable address. */
2441 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2442 if (p->offset != p->initial_offset)
2443 p->can_eliminate = 0;
2451 /* Scan X and replace any eliminable registers (such as fp) with a
2452 replacement (such as sp), plus an offset.
2454 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2455 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2456 MEM, we are allowed to replace a sum of a register and the constant zero
2457 with the register, which we cannot do outside a MEM. In addition, we need
2458 to record the fact that a register is referenced outside a MEM.
2460 If INSN is an insn, it is the insn containing X. If we replace a REG
2461 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2462 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2463 the REG is being modified.
2465 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2466 That's used when we eliminate in expressions stored in notes.
2467 This means, do not set ref_outside_mem even if the reference
2470 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2471 replacements done assuming all offsets are at their initial values. If
2472 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2473 encounter, return the actual location so that find_reloads will do
2474 the proper thing. */
2477 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2478 bool may_use_invariant)
2480 enum rtx_code code = GET_CODE (x);
2481 struct elim_table *ep;
2488 if (! current_function_decl)
2511 /* First handle the case where we encounter a bare register that
2512 is eliminable. Replace it with a PLUS. */
2513 if (regno < FIRST_PSEUDO_REGISTER)
2515 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2517 if (ep->from_rtx == x && ep->can_eliminate)
2518 return plus_constant (ep->to_rtx, ep->previous_offset);
2521 else if (reg_renumber && reg_renumber[regno] < 0
2522 && reg_equiv_invariant && reg_equiv_invariant[regno])
2524 if (may_use_invariant)
2525 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2526 mem_mode, insn, true);
2527 /* There exists at least one use of REGNO that cannot be
2528 eliminated. Prevent the defining insn from being deleted. */
2529 reg_equiv_init[regno] = NULL_RTX;
2530 alter_reg (regno, -1, true);
2534 /* You might think handling MINUS in a manner similar to PLUS is a
2535 good idea. It is not. It has been tried multiple times and every
2536 time the change has had to have been reverted.
2538 Other parts of reload know a PLUS is special (gen_reload for example)
2539 and require special code to handle code a reloaded PLUS operand.
2541 Also consider backends where the flags register is clobbered by a
2542 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2543 lea instruction comes to mind). If we try to reload a MINUS, we
2544 may kill the flags register that was holding a useful value.
2546 So, please before trying to handle MINUS, consider reload as a
2547 whole instead of this little section as well as the backend issues. */
2549 /* If this is the sum of an eliminable register and a constant, rework
2551 if (REG_P (XEXP (x, 0))
2552 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2553 && CONSTANT_P (XEXP (x, 1)))
2555 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2557 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2559 /* The only time we want to replace a PLUS with a REG (this
2560 occurs when the constant operand of the PLUS is the negative
2561 of the offset) is when we are inside a MEM. We won't want
2562 to do so at other times because that would change the
2563 structure of the insn in a way that reload can't handle.
2564 We special-case the commonest situation in
2565 eliminate_regs_in_insn, so just replace a PLUS with a
2566 PLUS here, unless inside a MEM. */
2567 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2568 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2571 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2572 plus_constant (XEXP (x, 1),
2573 ep->previous_offset));
2576 /* If the register is not eliminable, we are done since the other
2577 operand is a constant. */
2581 /* If this is part of an address, we want to bring any constant to the
2582 outermost PLUS. We will do this by doing register replacement in
2583 our operands and seeing if a constant shows up in one of them.
2585 Note that there is no risk of modifying the structure of the insn,
2586 since we only get called for its operands, thus we are either
2587 modifying the address inside a MEM, or something like an address
2588 operand of a load-address insn. */
2591 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2592 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2594 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2596 /* If one side is a PLUS and the other side is a pseudo that
2597 didn't get a hard register but has a reg_equiv_constant,
2598 we must replace the constant here since it may no longer
2599 be in the position of any operand. */
2600 if (GET_CODE (new0) == PLUS && REG_P (new1)
2601 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2602 && reg_renumber[REGNO (new1)] < 0
2603 && reg_equiv_constant != 0
2604 && reg_equiv_constant[REGNO (new1)] != 0)
2605 new1 = reg_equiv_constant[REGNO (new1)];
2606 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2607 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2608 && reg_renumber[REGNO (new0)] < 0
2609 && reg_equiv_constant[REGNO (new0)] != 0)
2610 new0 = reg_equiv_constant[REGNO (new0)];
2612 new_rtx = form_sum (new0, new1);
2614 /* As above, if we are not inside a MEM we do not want to
2615 turn a PLUS into something else. We might try to do so here
2616 for an addition of 0 if we aren't optimizing. */
2617 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2618 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2626 /* If this is the product of an eliminable register and a
2627 constant, apply the distribute law and move the constant out
2628 so that we have (plus (mult ..) ..). This is needed in order
2629 to keep load-address insns valid. This case is pathological.
2630 We ignore the possibility of overflow here. */
2631 if (REG_P (XEXP (x, 0))
2632 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2633 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2634 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2636 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2639 /* Refs inside notes don't count for this purpose. */
2640 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2641 || GET_CODE (insn) == INSN_LIST)))
2642 ep->ref_outside_mem = 1;
2645 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2646 ep->previous_offset * INTVAL (XEXP (x, 1)));
2649 /* ... fall through ... */
2653 /* See comments before PLUS about handling MINUS. */
2655 case DIV: case UDIV:
2656 case MOD: case UMOD:
2657 case AND: case IOR: case XOR:
2658 case ROTATERT: case ROTATE:
2659 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2661 case GE: case GT: case GEU: case GTU:
2662 case LE: case LT: case LEU: case LTU:
2664 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2665 rtx new1 = XEXP (x, 1)
2666 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2668 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2669 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2674 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2677 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2678 if (new_rtx != XEXP (x, 0))
2680 /* If this is a REG_DEAD note, it is not valid anymore.
2681 Using the eliminated version could result in creating a
2682 REG_DEAD note for the stack or frame pointer. */
2683 if (REG_NOTE_KIND (x) == REG_DEAD)
2685 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2688 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2692 /* ... fall through ... */
2695 /* Now do eliminations in the rest of the chain. If this was
2696 an EXPR_LIST, this might result in allocating more memory than is
2697 strictly needed, but it simplifies the code. */
2700 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2701 if (new_rtx != XEXP (x, 1))
2703 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2711 /* We do not support elimination of a register that is modified.
2712 elimination_effects has already make sure that this does not
2718 /* We do not support elimination of a register that is modified.
2719 elimination_effects has already make sure that this does not
2720 happen. The only remaining case we need to consider here is
2721 that the increment value may be an eliminable register. */
2722 if (GET_CODE (XEXP (x, 1)) == PLUS
2723 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2725 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2728 if (new_rtx != XEXP (XEXP (x, 1), 1))
2729 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2730 gen_rtx_PLUS (GET_MODE (x),
2731 XEXP (x, 0), new_rtx));
2735 case STRICT_LOW_PART:
2737 case SIGN_EXTEND: case ZERO_EXTEND:
2738 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2739 case FLOAT: case FIX:
2740 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2749 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2750 if (new_rtx != XEXP (x, 0))
2751 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2755 /* Similar to above processing, but preserve SUBREG_BYTE.
2756 Convert (subreg (mem)) to (mem) if not paradoxical.
2757 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2758 pseudo didn't get a hard reg, we must replace this with the
2759 eliminated version of the memory location because push_reload
2760 may do the replacement in certain circumstances. */
2761 if (REG_P (SUBREG_REG (x))
2762 && (GET_MODE_SIZE (GET_MODE (x))
2763 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2764 && reg_equiv_memory_loc != 0
2765 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2767 new_rtx = SUBREG_REG (x);
2770 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2772 if (new_rtx != SUBREG_REG (x))
2774 int x_size = GET_MODE_SIZE (GET_MODE (x));
2775 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2778 && ((x_size < new_size
2779 #ifdef WORD_REGISTER_OPERATIONS
2780 /* On these machines, combine can create rtl of the form
2781 (set (subreg:m1 (reg:m2 R) 0) ...)
2782 where m1 < m2, and expects something interesting to
2783 happen to the entire word. Moreover, it will use the
2784 (reg:m2 R) later, expecting all bits to be preserved.
2785 So if the number of words is the same, preserve the
2786 subreg so that push_reload can see it. */
2787 && ! ((x_size - 1) / UNITS_PER_WORD
2788 == (new_size -1 ) / UNITS_PER_WORD)
2791 || x_size == new_size)
2793 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2795 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2801 /* Our only special processing is to pass the mode of the MEM to our
2802 recursive call and copy the flags. While we are here, handle this
2803 case more efficiently. */
2805 replace_equiv_address_nv (x,
2806 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2810 /* Handle insn_list USE that a call to a pure function may generate. */
2811 new_rtx = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2812 if (new_rtx != XEXP (x, 0))
2813 return gen_rtx_USE (GET_MODE (x), new_rtx);
2825 /* Process each of our operands recursively. If any have changed, make a
2827 fmt = GET_RTX_FORMAT (code);
2828 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2832 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2833 if (new_rtx != XEXP (x, i) && ! copied)
2835 x = shallow_copy_rtx (x);
2838 XEXP (x, i) = new_rtx;
2840 else if (*fmt == 'E')
2843 for (j = 0; j < XVECLEN (x, i); j++)
2845 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2846 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2848 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2852 x = shallow_copy_rtx (x);
2855 XVEC (x, i) = new_v;
2858 XVECEXP (x, i, j) = new_rtx;
2867 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2869 return eliminate_regs_1 (x, mem_mode, insn, false);
2872 /* Scan rtx X for modifications of elimination target registers. Update
2873 the table of eliminables to reflect the changed state. MEM_MODE is
2874 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2877 elimination_effects (rtx x, enum machine_mode mem_mode)
2879 enum rtx_code code = GET_CODE (x);
2880 struct elim_table *ep;
2905 /* First handle the case where we encounter a bare register that
2906 is eliminable. Replace it with a PLUS. */
2907 if (regno < FIRST_PSEUDO_REGISTER)
2909 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2911 if (ep->from_rtx == x && ep->can_eliminate)
2914 ep->ref_outside_mem = 1;
2919 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2920 && reg_equiv_constant[regno]
2921 && ! function_invariant_p (reg_equiv_constant[regno]))
2922 elimination_effects (reg_equiv_constant[regno], mem_mode);
2931 /* If we modify the source of an elimination rule, disable it. */
2932 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2933 if (ep->from_rtx == XEXP (x, 0))
2934 ep->can_eliminate = 0;
2936 /* If we modify the target of an elimination rule by adding a constant,
2937 update its offset. If we modify the target in any other way, we'll
2938 have to disable the rule as well. */
2939 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2940 if (ep->to_rtx == XEXP (x, 0))
2942 int size = GET_MODE_SIZE (mem_mode);
2944 /* If more bytes than MEM_MODE are pushed, account for them. */
2945 #ifdef PUSH_ROUNDING
2946 if (ep->to_rtx == stack_pointer_rtx)
2947 size = PUSH_ROUNDING (size);
2949 if (code == PRE_DEC || code == POST_DEC)
2951 else if (code == PRE_INC || code == POST_INC)
2953 else if (code == PRE_MODIFY || code == POST_MODIFY)
2955 if (GET_CODE (XEXP (x, 1)) == PLUS
2956 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2957 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2958 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2960 ep->can_eliminate = 0;
2964 /* These two aren't unary operators. */
2965 if (code == POST_MODIFY || code == PRE_MODIFY)
2968 /* Fall through to generic unary operation case. */
2969 case STRICT_LOW_PART:
2971 case SIGN_EXTEND: case ZERO_EXTEND:
2972 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2973 case FLOAT: case FIX:
2974 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2983 elimination_effects (XEXP (x, 0), mem_mode);
2987 if (REG_P (SUBREG_REG (x))
2988 && (GET_MODE_SIZE (GET_MODE (x))
2989 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2990 && reg_equiv_memory_loc != 0
2991 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2994 elimination_effects (SUBREG_REG (x), mem_mode);
2998 /* If using a register that is the source of an eliminate we still
2999 think can be performed, note it cannot be performed since we don't
3000 know how this register is used. */
3001 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3002 if (ep->from_rtx == XEXP (x, 0))
3003 ep->can_eliminate = 0;
3005 elimination_effects (XEXP (x, 0), mem_mode);
3009 /* If clobbering a register that is the replacement register for an
3010 elimination we still think can be performed, note that it cannot
3011 be performed. Otherwise, we need not be concerned about it. */
3012 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3013 if (ep->to_rtx == XEXP (x, 0))
3014 ep->can_eliminate = 0;
3016 elimination_effects (XEXP (x, 0), mem_mode);
3020 /* Check for setting a register that we know about. */
3021 if (REG_P (SET_DEST (x)))
3023 /* See if this is setting the replacement register for an
3026 If DEST is the hard frame pointer, we do nothing because we
3027 assume that all assignments to the frame pointer are for
3028 non-local gotos and are being done at a time when they are valid
3029 and do not disturb anything else. Some machines want to
3030 eliminate a fake argument pointer (or even a fake frame pointer)
3031 with either the real frame or the stack pointer. Assignments to
3032 the hard frame pointer must not prevent this elimination. */
3034 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3036 if (ep->to_rtx == SET_DEST (x)
3037 && SET_DEST (x) != hard_frame_pointer_rtx)
3039 /* If it is being incremented, adjust the offset. Otherwise,
3040 this elimination can't be done. */
3041 rtx src = SET_SRC (x);
3043 if (GET_CODE (src) == PLUS
3044 && XEXP (src, 0) == SET_DEST (x)
3045 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3046 ep->offset -= INTVAL (XEXP (src, 1));
3048 ep->can_eliminate = 0;
3052 elimination_effects (SET_DEST (x), 0);
3053 elimination_effects (SET_SRC (x), 0);
3057 /* Our only special processing is to pass the mode of the MEM to our
3059 elimination_effects (XEXP (x, 0), GET_MODE (x));
3066 fmt = GET_RTX_FORMAT (code);
3067 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3070 elimination_effects (XEXP (x, i), mem_mode);
3071 else if (*fmt == 'E')
3072 for (j = 0; j < XVECLEN (x, i); j++)
3073 elimination_effects (XVECEXP (x, i, j), mem_mode);
3077 /* Descend through rtx X and verify that no references to eliminable registers
3078 remain. If any do remain, mark the involved register as not
3082 check_eliminable_occurrences (rtx x)
3091 code = GET_CODE (x);
3093 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3095 struct elim_table *ep;
3097 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3098 if (ep->from_rtx == x)
3099 ep->can_eliminate = 0;
3103 fmt = GET_RTX_FORMAT (code);
3104 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3107 check_eliminable_occurrences (XEXP (x, i));
3108 else if (*fmt == 'E')
3111 for (j = 0; j < XVECLEN (x, i); j++)
3112 check_eliminable_occurrences (XVECEXP (x, i, j));
3117 /* Scan INSN and eliminate all eliminable registers in it.
3119 If REPLACE is nonzero, do the replacement destructively. Also
3120 delete the insn as dead it if it is setting an eliminable register.
3122 If REPLACE is zero, do all our allocations in reload_obstack.
3124 If no eliminations were done and this insn doesn't require any elimination
3125 processing (these are not identical conditions: it might be updating sp,
3126 but not referencing fp; this needs to be seen during reload_as_needed so
3127 that the offset between fp and sp can be taken into consideration), zero
3128 is returned. Otherwise, 1 is returned. */
3131 eliminate_regs_in_insn (rtx insn, int replace)
3133 int icode = recog_memoized (insn);
3134 rtx old_body = PATTERN (insn);
3135 int insn_is_asm = asm_noperands (old_body) >= 0;
3136 rtx old_set = single_set (insn);
3140 rtx substed_operand[MAX_RECOG_OPERANDS];
3141 rtx orig_operand[MAX_RECOG_OPERANDS];
3142 struct elim_table *ep;
3143 rtx plus_src, plus_cst_src;
3145 if (! insn_is_asm && icode < 0)
3147 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3148 || GET_CODE (PATTERN (insn)) == CLOBBER
3149 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3150 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3151 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3155 if (old_set != 0 && REG_P (SET_DEST (old_set))
3156 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3158 /* Check for setting an eliminable register. */
3159 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3160 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3162 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3163 /* If this is setting the frame pointer register to the
3164 hardware frame pointer register and this is an elimination
3165 that will be done (tested above), this insn is really
3166 adjusting the frame pointer downward to compensate for
3167 the adjustment done before a nonlocal goto. */
3168 if (ep->from == FRAME_POINTER_REGNUM
3169 && ep->to == HARD_FRAME_POINTER_REGNUM)
3171 rtx base = SET_SRC (old_set);
3172 rtx base_insn = insn;
3173 HOST_WIDE_INT offset = 0;
3175 while (base != ep->to_rtx)
3177 rtx prev_insn, prev_set;
3179 if (GET_CODE (base) == PLUS
3180 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3182 offset += INTVAL (XEXP (base, 1));
3183 base = XEXP (base, 0);
3185 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3186 && (prev_set = single_set (prev_insn)) != 0
3187 && rtx_equal_p (SET_DEST (prev_set), base))
3189 base = SET_SRC (prev_set);
3190 base_insn = prev_insn;
3196 if (base == ep->to_rtx)
3199 = plus_constant (ep->to_rtx, offset - ep->offset);
3201 new_body = old_body;
3204 new_body = copy_insn (old_body);
3205 if (REG_NOTES (insn))
3206 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3208 PATTERN (insn) = new_body;
3209 old_set = single_set (insn);
3211 /* First see if this insn remains valid when we
3212 make the change. If not, keep the INSN_CODE
3213 the same and let reload fit it up. */
3214 validate_change (insn, &SET_SRC (old_set), src, 1);
3215 validate_change (insn, &SET_DEST (old_set),
3217 if (! apply_change_group ())
3219 SET_SRC (old_set) = src;
3220 SET_DEST (old_set) = ep->to_rtx;
3229 /* In this case this insn isn't serving a useful purpose. We
3230 will delete it in reload_as_needed once we know that this
3231 elimination is, in fact, being done.
3233 If REPLACE isn't set, we can't delete this insn, but needn't
3234 process it since it won't be used unless something changes. */
3237 delete_dead_insn (insn);
3245 /* We allow one special case which happens to work on all machines we
3246 currently support: a single set with the source or a REG_EQUAL
3247 note being a PLUS of an eliminable register and a constant. */
3248 plus_src = plus_cst_src = 0;
3249 if (old_set && REG_P (SET_DEST (old_set)))
3251 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3252 plus_src = SET_SRC (old_set);
3253 /* First see if the source is of the form (plus (...) CST). */
3255 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3256 plus_cst_src = plus_src;
3257 else if (REG_P (SET_SRC (old_set))
3260 /* Otherwise, see if we have a REG_EQUAL note of the form
3261 (plus (...) CST). */
3263 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3265 if ((REG_NOTE_KIND (links) == REG_EQUAL
3266 || REG_NOTE_KIND (links) == REG_EQUIV)
3267 && GET_CODE (XEXP (links, 0)) == PLUS
3268 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3270 plus_cst_src = XEXP (links, 0);
3276 /* Check that the first operand of the PLUS is a hard reg or
3277 the lowpart subreg of one. */
3280 rtx reg = XEXP (plus_cst_src, 0);
3281 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3282 reg = SUBREG_REG (reg);
3284 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3290 rtx reg = XEXP (plus_cst_src, 0);
3291 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3293 if (GET_CODE (reg) == SUBREG)
3294 reg = SUBREG_REG (reg);
3296 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3297 if (ep->from_rtx == reg && ep->can_eliminate)
3299 rtx to_rtx = ep->to_rtx;
3300 offset += ep->offset;
3301 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3303 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3304 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3306 /* If we have a nonzero offset, and the source is already
3307 a simple REG, the following transformation would
3308 increase the cost of the insn by replacing a simple REG
3309 with (plus (reg sp) CST). So try only when we already
3310 had a PLUS before. */
3311 if (offset == 0 || plus_src)
3313 rtx new_src = plus_constant (to_rtx, offset);
3315 new_body = old_body;
3318 new_body = copy_insn (old_body);
3319 if (REG_NOTES (insn))
3320 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3322 PATTERN (insn) = new_body;
3323 old_set = single_set (insn);
3325 /* First see if this insn remains valid when we make the
3326 change. If not, try to replace the whole pattern with
3327 a simple set (this may help if the original insn was a
3328 PARALLEL that was only recognized as single_set due to
3329 REG_UNUSED notes). If this isn't valid either, keep
3330 the INSN_CODE the same and let reload fix it up. */
3331 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3333 rtx new_pat = gen_rtx_SET (VOIDmode,
3334 SET_DEST (old_set), new_src);
3336 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3337 SET_SRC (old_set) = new_src;
3344 /* This can't have an effect on elimination offsets, so skip right
3350 /* Determine the effects of this insn on elimination offsets. */
3351 elimination_effects (old_body, 0);
3353 /* Eliminate all eliminable registers occurring in operands that
3354 can be handled by reload. */
3355 extract_insn (insn);
3356 for (i = 0; i < recog_data.n_operands; i++)
3358 orig_operand[i] = recog_data.operand[i];
3359 substed_operand[i] = recog_data.operand[i];
3361 /* For an asm statement, every operand is eliminable. */
3362 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3364 bool is_set_src, in_plus;
3366 /* Check for setting a register that we know about. */
3367 if (recog_data.operand_type[i] != OP_IN
3368 && REG_P (orig_operand[i]))
3370 /* If we are assigning to a register that can be eliminated, it
3371 must be as part of a PARALLEL, since the code above handles
3372 single SETs. We must indicate that we can no longer
3373 eliminate this reg. */
3374 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3376 if (ep->from_rtx == orig_operand[i])
3377 ep->can_eliminate = 0;
3380 /* Companion to the above plus substitution, we can allow
3381 invariants as the source of a plain move. */
3383 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3387 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3388 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3392 = eliminate_regs_1 (recog_data.operand[i], 0,
3393 replace ? insn : NULL_RTX,
3394 is_set_src || in_plus);
3395 if (substed_operand[i] != orig_operand[i])
3397 /* Terminate the search in check_eliminable_occurrences at
3399 *recog_data.operand_loc[i] = 0;
3401 /* If an output operand changed from a REG to a MEM and INSN is an
3402 insn, write a CLOBBER insn. */
3403 if (recog_data.operand_type[i] != OP_IN
3404 && REG_P (orig_operand[i])
3405 && MEM_P (substed_operand[i])
3407 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3411 for (i = 0; i < recog_data.n_dups; i++)
3412 *recog_data.dup_loc[i]
3413 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3415 /* If any eliminable remain, they aren't eliminable anymore. */
3416 check_eliminable_occurrences (old_body);
3418 /* Substitute the operands; the new values are in the substed_operand
3420 for (i = 0; i < recog_data.n_operands; i++)
3421 *recog_data.operand_loc[i] = substed_operand[i];
3422 for (i = 0; i < recog_data.n_dups; i++)
3423 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3425 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3426 re-recognize the insn. We do this in case we had a simple addition
3427 but now can do this as a load-address. This saves an insn in this
3429 If re-recognition fails, the old insn code number will still be used,
3430 and some register operands may have changed into PLUS expressions.
3431 These will be handled by find_reloads by loading them into a register
3436 /* If we aren't replacing things permanently and we changed something,
3437 make another copy to ensure that all the RTL is new. Otherwise
3438 things can go wrong if find_reload swaps commutative operands
3439 and one is inside RTL that has been copied while the other is not. */
3440 new_body = old_body;
3443 new_body = copy_insn (old_body);
3444 if (REG_NOTES (insn))
3445 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3447 PATTERN (insn) = new_body;
3449 /* If we had a move insn but now we don't, rerecognize it. This will
3450 cause spurious re-recognition if the old move had a PARALLEL since
3451 the new one still will, but we can't call single_set without
3452 having put NEW_BODY into the insn and the re-recognition won't
3453 hurt in this rare case. */
3454 /* ??? Why this huge if statement - why don't we just rerecognize the
3458 && ((REG_P (SET_SRC (old_set))
3459 && (GET_CODE (new_body) != SET
3460 || !REG_P (SET_SRC (new_body))))
3461 /* If this was a load from or store to memory, compare
3462 the MEM in recog_data.operand to the one in the insn.
3463 If they are not equal, then rerecognize the insn. */
3465 && ((MEM_P (SET_SRC (old_set))
3466 && SET_SRC (old_set) != recog_data.operand[1])
3467 || (MEM_P (SET_DEST (old_set))
3468 && SET_DEST (old_set) != recog_data.operand[0])))
3469 /* If this was an add insn before, rerecognize. */
3470 || GET_CODE (SET_SRC (old_set)) == PLUS))
3472 int new_icode = recog (PATTERN (insn), insn, 0);
3474 INSN_CODE (insn) = new_icode;
3478 /* Restore the old body. If there were any changes to it, we made a copy
3479 of it while the changes were still in place, so we'll correctly return
3480 a modified insn below. */
3483 /* Restore the old body. */
3484 for (i = 0; i < recog_data.n_operands; i++)
3485 *recog_data.operand_loc[i] = orig_operand[i];
3486 for (i = 0; i < recog_data.n_dups; i++)
3487 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3490 /* Update all elimination pairs to reflect the status after the current
3491 insn. The changes we make were determined by the earlier call to
3492 elimination_effects.
3494 We also detect cases where register elimination cannot be done,
3495 namely, if a register would be both changed and referenced outside a MEM
3496 in the resulting insn since such an insn is often undefined and, even if
3497 not, we cannot know what meaning will be given to it. Note that it is
3498 valid to have a register used in an address in an insn that changes it
3499 (presumably with a pre- or post-increment or decrement).
3501 If anything changes, return nonzero. */
3503 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3505 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3506 ep->can_eliminate = 0;
3508 ep->ref_outside_mem = 0;
3510 if (ep->previous_offset != ep->offset)
3515 /* If we changed something, perform elimination in REG_NOTES. This is
3516 needed even when REPLACE is zero because a REG_DEAD note might refer
3517 to a register that we eliminate and could cause a different number
3518 of spill registers to be needed in the final reload pass than in
3520 if (val && REG_NOTES (insn) != 0)
3522 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3527 /* Loop through all elimination pairs.
3528 Recalculate the number not at initial offset.
3530 Compute the maximum offset (minimum offset if the stack does not
3531 grow downward) for each elimination pair. */
3534 update_eliminable_offsets (void)
3536 struct elim_table *ep;
3538 num_not_at_initial_offset = 0;
3539 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3541 ep->previous_offset = ep->offset;
3542 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3543 num_not_at_initial_offset++;
3547 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3548 replacement we currently believe is valid, mark it as not eliminable if X
3549 modifies DEST in any way other than by adding a constant integer to it.
3551 If DEST is the frame pointer, we do nothing because we assume that
3552 all assignments to the hard frame pointer are nonlocal gotos and are being
3553 done at a time when they are valid and do not disturb anything else.
3554 Some machines want to eliminate a fake argument pointer with either the
3555 frame or stack pointer. Assignments to the hard frame pointer must not
3556 prevent this elimination.
3558 Called via note_stores from reload before starting its passes to scan
3559 the insns of the function. */
3562 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3566 /* A SUBREG of a hard register here is just changing its mode. We should
3567 not see a SUBREG of an eliminable hard register, but check just in
3569 if (GET_CODE (dest) == SUBREG)
3570 dest = SUBREG_REG (dest);
3572 if (dest == hard_frame_pointer_rtx)
3575 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3576 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3577 && (GET_CODE (x) != SET
3578 || GET_CODE (SET_SRC (x)) != PLUS
3579 || XEXP (SET_SRC (x), 0) != dest
3580 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3582 reg_eliminate[i].can_eliminate_previous
3583 = reg_eliminate[i].can_eliminate = 0;
3588 /* Verify that the initial elimination offsets did not change since the
3589 last call to set_initial_elim_offsets. This is used to catch cases
3590 where something illegal happened during reload_as_needed that could
3591 cause incorrect code to be generated if we did not check for it. */
3594 verify_initial_elim_offsets (void)
3598 if (!num_eliminable)
3601 #ifdef ELIMINABLE_REGS
3603 struct elim_table *ep;
3605 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3607 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3608 if (t != ep->initial_offset)
3613 INITIAL_FRAME_POINTER_OFFSET (t);
3614 if (t != reg_eliminate[0].initial_offset)
3621 /* Reset all offsets on eliminable registers to their initial values. */
3624 set_initial_elim_offsets (void)
3626 struct elim_table *ep = reg_eliminate;
3628 #ifdef ELIMINABLE_REGS
3629 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3631 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3632 ep->previous_offset = ep->offset = ep->initial_offset;
3635 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3636 ep->previous_offset = ep->offset = ep->initial_offset;
3639 num_not_at_initial_offset = 0;
3642 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3645 set_initial_eh_label_offset (rtx label)
3647 set_label_offsets (label, NULL_RTX, 1);
3650 /* Initialize the known label offsets.
3651 Set a known offset for each forced label to be at the initial offset
3652 of each elimination. We do this because we assume that all
3653 computed jumps occur from a location where each elimination is
3654 at its initial offset.
3655 For all other labels, show that we don't know the offsets. */
3658 set_initial_label_offsets (void)
3661 memset (offsets_known_at, 0, num_labels);
3663 for (x = forced_labels; x; x = XEXP (x, 1))
3665 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3667 for_each_eh_label (set_initial_eh_label_offset);
3670 /* Set all elimination offsets to the known values for the code label given
3674 set_offsets_for_label (rtx insn)
3677 int label_nr = CODE_LABEL_NUMBER (insn);
3678 struct elim_table *ep;
3680 num_not_at_initial_offset = 0;
3681 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3683 ep->offset = ep->previous_offset
3684 = offsets_at[label_nr - first_label_num][i];
3685 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3686 num_not_at_initial_offset++;
3690 /* See if anything that happened changes which eliminations are valid.
3691 For example, on the SPARC, whether or not the frame pointer can
3692 be eliminated can depend on what registers have been used. We need
3693 not check some conditions again (such as flag_omit_frame_pointer)
3694 since they can't have changed. */
3697 update_eliminables (HARD_REG_SET *pset)
3699 int previous_frame_pointer_needed = frame_pointer_needed;
3700 struct elim_table *ep;
3702 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3703 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3704 #ifdef ELIMINABLE_REGS
3705 || ! CAN_ELIMINATE (ep->from, ep->to)
3708 ep->can_eliminate = 0;
3710 /* Look for the case where we have discovered that we can't replace
3711 register A with register B and that means that we will now be
3712 trying to replace register A with register C. This means we can
3713 no longer replace register C with register B and we need to disable
3714 such an elimination, if it exists. This occurs often with A == ap,
3715 B == sp, and C == fp. */
3717 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3719 struct elim_table *op;
3722 if (! ep->can_eliminate && ep->can_eliminate_previous)
3724 /* Find the current elimination for ep->from, if there is a
3726 for (op = reg_eliminate;
3727 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3728 if (op->from == ep->from && op->can_eliminate)
3734 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3736 for (op = reg_eliminate;
3737 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3738 if (op->from == new_to && op->to == ep->to)
3739 op->can_eliminate = 0;
3743 /* See if any registers that we thought we could eliminate the previous
3744 time are no longer eliminable. If so, something has changed and we
3745 must spill the register. Also, recompute the number of eliminable
3746 registers and see if the frame pointer is needed; it is if there is
3747 no elimination of the frame pointer that we can perform. */
3749 frame_pointer_needed = 1;
3750 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3752 if (ep->can_eliminate
3753 && ep->from == FRAME_POINTER_REGNUM
3754 && ep->to != HARD_FRAME_POINTER_REGNUM
3755 && (! SUPPORTS_STACK_ALIGNMENT
3756 || ! crtl->stack_realign_needed))
3757 frame_pointer_needed = 0;
3759 if (! ep->can_eliminate && ep->can_eliminate_previous)
3761 ep->can_eliminate_previous = 0;
3762 SET_HARD_REG_BIT (*pset, ep->from);
3767 /* If we didn't need a frame pointer last time, but we do now, spill
3768 the hard frame pointer. */
3769 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3770 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3773 /* Return true if X is used as the target register of an elimination. */
3776 elimination_target_reg_p (rtx x)
3778 struct elim_table *ep;
3780 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3781 if (ep->to_rtx == x && ep->can_eliminate)
3787 /* Initialize the table of registers to eliminate.
3788 Pre-condition: global flag frame_pointer_needed has been set before
3789 calling this function. */
3792 init_elim_table (void)
3794 struct elim_table *ep;
3795 #ifdef ELIMINABLE_REGS
3796 const struct elim_table_1 *ep1;
3800 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3804 #ifdef ELIMINABLE_REGS
3805 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3806 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3808 ep->from = ep1->from;
3810 ep->can_eliminate = ep->can_eliminate_previous
3811 = (CAN_ELIMINATE (ep->from, ep->to)
3812 && ! (ep->to == STACK_POINTER_REGNUM
3813 && frame_pointer_needed
3814 && (! SUPPORTS_STACK_ALIGNMENT
3815 || ! stack_realign_fp)));
3818 reg_eliminate[0].from = reg_eliminate_1[0].from;
3819 reg_eliminate[0].to = reg_eliminate_1[0].to;
3820 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3821 = ! frame_pointer_needed;
3824 /* Count the number of eliminable registers and build the FROM and TO
3825 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3826 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3827 We depend on this. */
3828 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3830 num_eliminable += ep->can_eliminate;
3831 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3832 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3836 /* Kick all pseudos out of hard register REGNO.
3838 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3839 because we found we can't eliminate some register. In the case, no pseudos
3840 are allowed to be in the register, even if they are only in a block that
3841 doesn't require spill registers, unlike the case when we are spilling this
3842 hard reg to produce another spill register.
3844 Return nonzero if any pseudos needed to be kicked out. */
3847 spill_hard_reg (unsigned int regno, int cant_eliminate)
3853 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3854 df_set_regs_ever_live (regno, true);
3857 /* Spill every pseudo reg that was allocated to this reg
3858 or to something that overlaps this reg. */
3860 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3861 if (reg_renumber[i] >= 0
3862 && (unsigned int) reg_renumber[i] <= regno
3863 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3864 SET_REGNO_REG_SET (&spilled_pseudos, i);
3867 /* After find_reload_regs has been run for all insn that need reloads,
3868 and/or spill_hard_regs was called, this function is used to actually
3869 spill pseudo registers and try to reallocate them. It also sets up the
3870 spill_regs array for use by choose_reload_regs. */
3873 finish_spills (int global)
3875 struct insn_chain *chain;
3876 int something_changed = 0;
3878 reg_set_iterator rsi;
3880 /* Build the spill_regs array for the function. */
3881 /* If there are some registers still to eliminate and one of the spill regs
3882 wasn't ever used before, additional stack space may have to be
3883 allocated to store this register. Thus, we may have changed the offset
3884 between the stack and frame pointers, so mark that something has changed.
3886 One might think that we need only set VAL to 1 if this is a call-used
3887 register. However, the set of registers that must be saved by the
3888 prologue is not identical to the call-used set. For example, the
3889 register used by the call insn for the return PC is a call-used register,
3890 but must be saved by the prologue. */
3893 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3894 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3896 spill_reg_order[i] = n_spills;
3897 spill_regs[n_spills++] = i;
3898 if (num_eliminable && ! df_regs_ever_live_p (i))
3899 something_changed = 1;
3900 df_set_regs_ever_live (i, true);
3903 spill_reg_order[i] = -1;
3905 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3906 if (! ira_conflicts_p || reg_renumber[i] >= 0)
3908 /* Record the current hard register the pseudo is allocated to
3909 in pseudo_previous_regs so we avoid reallocating it to the
3910 same hard reg in a later pass. */
3911 gcc_assert (reg_renumber[i] >= 0);
3913 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3914 /* Mark it as no longer having a hard register home. */
3915 reg_renumber[i] = -1;
3916 if (ira_conflicts_p)
3917 /* Inform IRA about the change. */
3918 ira_mark_allocation_change (i);
3919 /* We will need to scan everything again. */
3920 something_changed = 1;
3923 /* Retry global register allocation if possible. */
3924 if (global && ira_conflicts_p)
3928 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3929 /* For every insn that needs reloads, set the registers used as spill
3930 regs in pseudo_forbidden_regs for every pseudo live across the
3932 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3934 EXECUTE_IF_SET_IN_REG_SET
3935 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3937 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3938 chain->used_spill_regs);
3940 EXECUTE_IF_SET_IN_REG_SET
3941 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3943 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3944 chain->used_spill_regs);
3948 /* Retry allocating the pseudos spilled in IRA and the
3949 reload. For each reg, merge the various reg sets that
3950 indicate which hard regs can't be used, and call
3951 ira_reassign_pseudos. */
3952 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
3953 if (reg_old_renumber[i] != reg_renumber[i])
3955 if (reg_renumber[i] < 0)
3956 temp_pseudo_reg_arr[n++] = i;
3958 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3960 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
3961 bad_spill_regs_global,
3962 pseudo_forbidden_regs, pseudo_previous_regs,
3964 something_changed = 1;
3966 /* Fix up the register information in the insn chain.
3967 This involves deleting those of the spilled pseudos which did not get
3968 a new hard register home from the live_{before,after} sets. */
3969 for (chain = reload_insn_chain; chain; chain = chain->next)
3971 HARD_REG_SET used_by_pseudos;
3972 HARD_REG_SET used_by_pseudos2;
3974 if (! ira_conflicts_p)
3976 /* Don't do it for IRA because IRA and the reload still can
3977 assign hard registers to the spilled pseudos on next
3978 reload iterations. */
3979 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3980 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3982 /* Mark any unallocated hard regs as available for spills. That
3983 makes inheritance work somewhat better. */
3984 if (chain->need_reload)
3986 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3987 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3988 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3990 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3991 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3992 /* Value of chain->used_spill_regs from previous iteration
3993 may be not included in the value calculated here because
3994 of possible removing caller-saves insns (see function
3995 delete_caller_save_insns. */
3996 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3997 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4001 CLEAR_REG_SET (&changed_allocation_pseudos);
4002 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4003 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4005 int regno = reg_renumber[i];
4006 if (reg_old_renumber[i] == regno)
4009 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4011 alter_reg (i, reg_old_renumber[i], false);
4012 reg_old_renumber[i] = regno;
4016 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4018 fprintf (dump_file, " Register %d now in %d.\n\n",
4019 i, reg_renumber[i]);
4023 return something_changed;
4026 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4029 scan_paradoxical_subregs (rtx x)
4033 enum rtx_code code = GET_CODE (x);
4044 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4052 if (REG_P (SUBREG_REG (x))
4053 && (GET_MODE_SIZE (GET_MODE (x))
4054 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4056 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4057 = GET_MODE_SIZE (GET_MODE (x));
4058 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4066 fmt = GET_RTX_FORMAT (code);
4067 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4070 scan_paradoxical_subregs (XEXP (x, i));
4071 else if (fmt[i] == 'E')
4074 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4075 scan_paradoxical_subregs (XVECEXP (x, i, j));
4080 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4081 examine all of the reload insns between PREV and NEXT exclusive, and
4082 annotate all that may trap. */
4085 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4087 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4088 unsigned int trap_count;
4094 if (may_trap_p (PATTERN (insn)))
4098 remove_note (insn, note);
4102 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
4103 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4106 add_reg_note (i, REG_EH_REGION, XEXP (note, 0));
4110 /* Reload pseudo-registers into hard regs around each insn as needed.
4111 Additional register load insns are output before the insn that needs it
4112 and perhaps store insns after insns that modify the reloaded pseudo reg.
4114 reg_last_reload_reg and reg_reloaded_contents keep track of
4115 which registers are already available in reload registers.
4116 We update these for the reloads that we perform,
4117 as the insns are scanned. */
4120 reload_as_needed (int live_known)
4122 struct insn_chain *chain;
4123 #if defined (AUTO_INC_DEC)
4128 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4129 memset (spill_reg_store, 0, sizeof spill_reg_store);
4130 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4131 INIT_REG_SET (®_has_output_reload);
4132 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4133 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4135 set_initial_elim_offsets ();
4137 for (chain = reload_insn_chain; chain; chain = chain->next)
4140 rtx insn = chain->insn;
4141 rtx old_next = NEXT_INSN (insn);
4143 rtx old_prev = PREV_INSN (insn);
4146 /* If we pass a label, copy the offsets from the label information
4147 into the current offsets of each elimination. */
4149 set_offsets_for_label (insn);
4151 else if (INSN_P (insn))
4153 regset_head regs_to_forget;
4154 INIT_REG_SET (®s_to_forget);
4155 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4157 /* If this is a USE and CLOBBER of a MEM, ensure that any
4158 references to eliminable registers have been removed. */
4160 if ((GET_CODE (PATTERN (insn)) == USE
4161 || GET_CODE (PATTERN (insn)) == CLOBBER)
4162 && MEM_P (XEXP (PATTERN (insn), 0)))
4163 XEXP (XEXP (PATTERN (insn), 0), 0)
4164 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4165 GET_MODE (XEXP (PATTERN (insn), 0)),
4168 /* If we need to do register elimination processing, do so.
4169 This might delete the insn, in which case we are done. */
4170 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4172 eliminate_regs_in_insn (insn, 1);
4175 update_eliminable_offsets ();
4176 CLEAR_REG_SET (®s_to_forget);
4181 /* If need_elim is nonzero but need_reload is zero, one might think
4182 that we could simply set n_reloads to 0. However, find_reloads
4183 could have done some manipulation of the insn (such as swapping
4184 commutative operands), and these manipulations are lost during
4185 the first pass for every insn that needs register elimination.
4186 So the actions of find_reloads must be redone here. */
4188 if (! chain->need_elim && ! chain->need_reload
4189 && ! chain->need_operand_change)
4191 /* First find the pseudo regs that must be reloaded for this insn.
4192 This info is returned in the tables reload_... (see reload.h).
4193 Also modify the body of INSN by substituting RELOAD
4194 rtx's for those pseudo regs. */
4197 CLEAR_REG_SET (®_has_output_reload);
4198 CLEAR_HARD_REG_SET (reg_is_output_reload);
4200 find_reloads (insn, 1, spill_indirect_levels, live_known,
4206 rtx next = NEXT_INSN (insn);
4209 prev = PREV_INSN (insn);
4211 /* Now compute which reload regs to reload them into. Perhaps
4212 reusing reload regs from previous insns, or else output
4213 load insns to reload them. Maybe output store insns too.
4214 Record the choices of reload reg in reload_reg_rtx. */
4215 choose_reload_regs (chain);
4217 /* Generate the insns to reload operands into or out of
4218 their reload regs. */
4219 emit_reload_insns (chain);
4221 /* Substitute the chosen reload regs from reload_reg_rtx
4222 into the insn's body (or perhaps into the bodies of other
4223 load and store insn that we just made for reloading
4224 and that we moved the structure into). */
4225 subst_reloads (insn);
4227 /* Adjust the exception region notes for loads and stores. */
4228 if (flag_non_call_exceptions && !CALL_P (insn))
4229 fixup_eh_region_note (insn, prev, next);
4231 /* If this was an ASM, make sure that all the reload insns
4232 we have generated are valid. If not, give an error
4234 if (asm_noperands (PATTERN (insn)) >= 0)
4235 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4236 if (p != insn && INSN_P (p)
4237 && GET_CODE (PATTERN (p)) != USE
4238 && (recog_memoized (p) < 0
4239 || (extract_insn (p), ! constrain_operands (1))))
4241 error_for_asm (insn,
4242 "%<asm%> operand requires "
4243 "impossible reload");
4248 if (num_eliminable && chain->need_elim)
4249 update_eliminable_offsets ();
4251 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4252 is no longer validly lying around to save a future reload.
4253 Note that this does not detect pseudos that were reloaded
4254 for this insn in order to be stored in
4255 (obeying register constraints). That is correct; such reload
4256 registers ARE still valid. */
4257 forget_marked_reloads (®s_to_forget);
4258 CLEAR_REG_SET (®s_to_forget);
4260 /* There may have been CLOBBER insns placed after INSN. So scan
4261 between INSN and NEXT and use them to forget old reloads. */
4262 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4263 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4264 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4267 /* Likewise for regs altered by auto-increment in this insn.
4268 REG_INC notes have been changed by reloading:
4269 find_reloads_address_1 records substitutions for them,
4270 which have been performed by subst_reloads above. */
4271 for (i = n_reloads - 1; i >= 0; i--)
4273 rtx in_reg = rld[i].in_reg;
4276 enum rtx_code code = GET_CODE (in_reg);
4277 /* PRE_INC / PRE_DEC will have the reload register ending up
4278 with the same value as the stack slot, but that doesn't
4279 hold true for POST_INC / POST_DEC. Either we have to
4280 convert the memory access to a true POST_INC / POST_DEC,
4281 or we can't use the reload register for inheritance. */
4282 if ((code == POST_INC || code == POST_DEC)
4283 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4284 REGNO (rld[i].reg_rtx))
4285 /* Make sure it is the inc/dec pseudo, and not
4286 some other (e.g. output operand) pseudo. */
4287 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4288 == REGNO (XEXP (in_reg, 0))))
4291 rtx reload_reg = rld[i].reg_rtx;
4292 enum machine_mode mode = GET_MODE (reload_reg);
4296 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4298 /* We really want to ignore REG_INC notes here, so
4299 use PATTERN (p) as argument to reg_set_p . */
4300 if (reg_set_p (reload_reg, PATTERN (p)))
4302 n = count_occurrences (PATTERN (p), reload_reg, 0);
4307 n = validate_replace_rtx (reload_reg,
4308 gen_rtx_fmt_e (code,
4313 /* We must also verify that the constraints
4314 are met after the replacement. */
4317 n = constrain_operands (1);
4321 /* If the constraints were not met, then
4322 undo the replacement. */
4325 validate_replace_rtx (gen_rtx_fmt_e (code,
4337 add_reg_note (p, REG_INC, reload_reg);
4338 /* Mark this as having an output reload so that the
4339 REG_INC processing code below won't invalidate
4340 the reload for inheritance. */
4341 SET_HARD_REG_BIT (reg_is_output_reload,
4342 REGNO (reload_reg));
4343 SET_REGNO_REG_SET (®_has_output_reload,
4344 REGNO (XEXP (in_reg, 0)));
4347 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4350 else if ((code == PRE_INC || code == PRE_DEC)
4351 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4352 REGNO (rld[i].reg_rtx))
4353 /* Make sure it is the inc/dec pseudo, and not
4354 some other (e.g. output operand) pseudo. */
4355 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4356 == REGNO (XEXP (in_reg, 0))))
4358 SET_HARD_REG_BIT (reg_is_output_reload,
4359 REGNO (rld[i].reg_rtx));
4360 SET_REGNO_REG_SET (®_has_output_reload,
4361 REGNO (XEXP (in_reg, 0)));
4363 else if (code == PRE_INC || code == PRE_DEC
4364 || code == POST_INC || code == POST_DEC)
4366 int in_regno = REGNO (XEXP (in_reg, 0));
4368 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4371 bool forget_p = true;
4373 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4374 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4377 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4380 if (x == reg_reloaded_insn[in_hard_regno])
4386 /* If for some reasons, we didn't set up
4387 reg_last_reload_reg in this insn,
4388 invalidate inheritance from previous
4389 insns for the incremented/decremented
4390 register. Such registers will be not in
4391 reg_has_output_reload. Invalidate it
4392 also if the corresponding element in
4393 reg_reloaded_insn is also
4396 forget_old_reloads_1 (XEXP (in_reg, 0),
4402 /* If a pseudo that got a hard register is auto-incremented,
4403 we must purge records of copying it into pseudos without
4405 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4406 if (REG_NOTE_KIND (x) == REG_INC)
4408 /* See if this pseudo reg was reloaded in this insn.
4409 If so, its last-reload info is still valid
4410 because it is based on this insn's reload. */
4411 for (i = 0; i < n_reloads; i++)
4412 if (rld[i].out == XEXP (x, 0))
4416 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4420 /* A reload reg's contents are unknown after a label. */
4422 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4424 /* Don't assume a reload reg is still good after a call insn
4425 if it is a call-used reg, or if it contains a value that will
4426 be partially clobbered by the call. */
4427 else if (CALL_P (insn))
4429 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4430 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4432 /* If this is a call to a setjmp-type function, we must not
4433 reuse any reload reg contents across the call; that will
4434 just be clobbered by other uses of the register in later
4435 code, before the longjmp. */
4436 if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4437 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4442 free (reg_last_reload_reg);
4443 CLEAR_REG_SET (®_has_output_reload);
4446 /* Discard all record of any value reloaded from X,
4447 or reloaded in X from someplace else;
4448 unless X is an output reload reg of the current insn.
4450 X may be a hard reg (the reload reg)
4451 or it may be a pseudo reg that was reloaded from.
4453 When DATA is non-NULL just mark the registers in regset
4454 to be forgotten later. */
4457 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4462 regset regs = (regset) data;
4464 /* note_stores does give us subregs of hard regs,
4465 subreg_regno_offset requires a hard reg. */
4466 while (GET_CODE (x) == SUBREG)
4468 /* We ignore the subreg offset when calculating the regno,
4469 because we are using the entire underlying hard register
4479 if (regno >= FIRST_PSEUDO_REGISTER)
4485 nr = hard_regno_nregs[regno][GET_MODE (x)];
4486 /* Storing into a spilled-reg invalidates its contents.
4487 This can happen if a block-local pseudo is allocated to that reg
4488 and it wasn't spilled because this block's total need is 0.
4489 Then some insn might have an optional reload and use this reg. */
4491 for (i = 0; i < nr; i++)
4492 /* But don't do this if the reg actually serves as an output
4493 reload reg in the current instruction. */
4495 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4497 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4498 spill_reg_store[regno + i] = 0;
4504 SET_REGNO_REG_SET (regs, regno + nr);
4507 /* Since value of X has changed,
4508 forget any value previously copied from it. */
4511 /* But don't forget a copy if this is the output reload
4512 that establishes the copy's validity. */
4514 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4515 reg_last_reload_reg[regno + nr] = 0;
4519 /* Forget the reloads marked in regset by previous function. */
4521 forget_marked_reloads (regset regs)
4524 reg_set_iterator rsi;
4525 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4527 if (reg < FIRST_PSEUDO_REGISTER
4528 /* But don't do this if the reg actually serves as an output
4529 reload reg in the current instruction. */
4531 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4533 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4534 spill_reg_store[reg] = 0;
4537 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4538 reg_last_reload_reg[reg] = 0;
4542 /* The following HARD_REG_SETs indicate when each hard register is
4543 used for a reload of various parts of the current insn. */
4545 /* If reg is unavailable for all reloads. */
4546 static HARD_REG_SET reload_reg_unavailable;
4547 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4548 static HARD_REG_SET reload_reg_used;
4549 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4550 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4551 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4552 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4553 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4554 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4555 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4556 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4557 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4558 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4559 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4560 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4561 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4562 static HARD_REG_SET reload_reg_used_in_op_addr;
4563 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4564 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4565 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4566 static HARD_REG_SET reload_reg_used_in_insn;
4567 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4568 static HARD_REG_SET reload_reg_used_in_other_addr;
4570 /* If reg is in use as a reload reg for any sort of reload. */
4571 static HARD_REG_SET reload_reg_used_at_all;
4573 /* If reg is use as an inherited reload. We just mark the first register
4575 static HARD_REG_SET reload_reg_used_for_inherit;
4577 /* Records which hard regs are used in any way, either as explicit use or
4578 by being allocated to a pseudo during any point of the current insn. */
4579 static HARD_REG_SET reg_used_in_insn;
4581 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4582 TYPE. MODE is used to indicate how many consecutive regs are
4586 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4587 enum machine_mode mode)
4589 unsigned int nregs = hard_regno_nregs[regno][mode];
4592 for (i = regno; i < nregs + regno; i++)
4597 SET_HARD_REG_BIT (reload_reg_used, i);
4600 case RELOAD_FOR_INPUT_ADDRESS:
4601 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4604 case RELOAD_FOR_INPADDR_ADDRESS:
4605 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4608 case RELOAD_FOR_OUTPUT_ADDRESS:
4609 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4612 case RELOAD_FOR_OUTADDR_ADDRESS:
4613 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4616 case RELOAD_FOR_OPERAND_ADDRESS:
4617 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4620 case RELOAD_FOR_OPADDR_ADDR:
4621 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4624 case RELOAD_FOR_OTHER_ADDRESS:
4625 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4628 case RELOAD_FOR_INPUT:
4629 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4632 case RELOAD_FOR_OUTPUT:
4633 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4636 case RELOAD_FOR_INSN:
4637 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4641 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4645 /* Similarly, but show REGNO is no longer in use for a reload. */
4648 clear_reload_reg_in_use (unsigned int regno, int opnum,
4649 enum reload_type type, enum machine_mode mode)
4651 unsigned int nregs = hard_regno_nregs[regno][mode];
4652 unsigned int start_regno, end_regno, r;
4654 /* A complication is that for some reload types, inheritance might
4655 allow multiple reloads of the same types to share a reload register.
4656 We set check_opnum if we have to check only reloads with the same
4657 operand number, and check_any if we have to check all reloads. */
4658 int check_opnum = 0;
4660 HARD_REG_SET *used_in_set;
4665 used_in_set = &reload_reg_used;
4668 case RELOAD_FOR_INPUT_ADDRESS:
4669 used_in_set = &reload_reg_used_in_input_addr[opnum];
4672 case RELOAD_FOR_INPADDR_ADDRESS:
4674 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4677 case RELOAD_FOR_OUTPUT_ADDRESS:
4678 used_in_set = &reload_reg_used_in_output_addr[opnum];
4681 case RELOAD_FOR_OUTADDR_ADDRESS:
4683 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4686 case RELOAD_FOR_OPERAND_ADDRESS:
4687 used_in_set = &reload_reg_used_in_op_addr;
4690 case RELOAD_FOR_OPADDR_ADDR:
4692 used_in_set = &reload_reg_used_in_op_addr_reload;
4695 case RELOAD_FOR_OTHER_ADDRESS:
4696 used_in_set = &reload_reg_used_in_other_addr;
4700 case RELOAD_FOR_INPUT:
4701 used_in_set = &reload_reg_used_in_input[opnum];
4704 case RELOAD_FOR_OUTPUT:
4705 used_in_set = &reload_reg_used_in_output[opnum];
4708 case RELOAD_FOR_INSN:
4709 used_in_set = &reload_reg_used_in_insn;
4714 /* We resolve conflicts with remaining reloads of the same type by
4715 excluding the intervals of reload registers by them from the
4716 interval of freed reload registers. Since we only keep track of
4717 one set of interval bounds, we might have to exclude somewhat
4718 more than what would be necessary if we used a HARD_REG_SET here.
4719 But this should only happen very infrequently, so there should
4720 be no reason to worry about it. */
4722 start_regno = regno;
4723 end_regno = regno + nregs;
4724 if (check_opnum || check_any)
4726 for (i = n_reloads - 1; i >= 0; i--)
4728 if (rld[i].when_needed == type
4729 && (check_any || rld[i].opnum == opnum)
4732 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4733 unsigned int conflict_end
4734 = end_hard_regno (rld[i].mode, conflict_start);
4736 /* If there is an overlap with the first to-be-freed register,
4737 adjust the interval start. */
4738 if (conflict_start <= start_regno && conflict_end > start_regno)
4739 start_regno = conflict_end;
4740 /* Otherwise, if there is a conflict with one of the other
4741 to-be-freed registers, adjust the interval end. */
4742 if (conflict_start > start_regno && conflict_start < end_regno)
4743 end_regno = conflict_start;
4748 for (r = start_regno; r < end_regno; r++)
4749 CLEAR_HARD_REG_BIT (*used_in_set, r);
4752 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4753 specified by OPNUM and TYPE. */
4756 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4760 /* In use for a RELOAD_OTHER means it's not available for anything. */
4761 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4762 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4768 /* In use for anything means we can't use it for RELOAD_OTHER. */
4769 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4770 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4771 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4772 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4775 for (i = 0; i < reload_n_operands; i++)
4776 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4777 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4778 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4779 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4780 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4781 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4786 case RELOAD_FOR_INPUT:
4787 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4788 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4791 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4794 /* If it is used for some other input, can't use it. */
4795 for (i = 0; i < reload_n_operands; i++)
4796 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4799 /* If it is used in a later operand's address, can't use it. */
4800 for (i = opnum + 1; i < reload_n_operands; i++)
4801 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4802 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4807 case RELOAD_FOR_INPUT_ADDRESS:
4808 /* Can't use a register if it is used for an input address for this
4809 operand or used as an input in an earlier one. */
4810 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4811 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4814 for (i = 0; i < opnum; i++)
4815 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4820 case RELOAD_FOR_INPADDR_ADDRESS:
4821 /* Can't use a register if it is used for an input address
4822 for this operand or used as an input in an earlier
4824 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4827 for (i = 0; i < opnum; i++)
4828 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4833 case RELOAD_FOR_OUTPUT_ADDRESS:
4834 /* Can't use a register if it is used for an output address for this
4835 operand or used as an output in this or a later operand. Note
4836 that multiple output operands are emitted in reverse order, so
4837 the conflicting ones are those with lower indices. */
4838 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4841 for (i = 0; i <= opnum; i++)
4842 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4847 case RELOAD_FOR_OUTADDR_ADDRESS:
4848 /* Can't use a register if it is used for an output address
4849 for this operand or used as an output in this or a
4850 later operand. Note that multiple output operands are
4851 emitted in reverse order, so the conflicting ones are
4852 those with lower indices. */
4853 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4856 for (i = 0; i <= opnum; i++)
4857 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4862 case RELOAD_FOR_OPERAND_ADDRESS:
4863 for (i = 0; i < reload_n_operands; i++)
4864 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4867 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4868 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4870 case RELOAD_FOR_OPADDR_ADDR:
4871 for (i = 0; i < reload_n_operands; i++)
4872 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4875 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4877 case RELOAD_FOR_OUTPUT:
4878 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4879 outputs, or an operand address for this or an earlier output.
4880 Note that multiple output operands are emitted in reverse order,
4881 so the conflicting ones are those with higher indices. */
4882 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4885 for (i = 0; i < reload_n_operands; i++)
4886 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4889 for (i = opnum; i < reload_n_operands; i++)
4890 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4891 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4896 case RELOAD_FOR_INSN:
4897 for (i = 0; i < reload_n_operands; i++)
4898 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4899 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4902 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4903 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4905 case RELOAD_FOR_OTHER_ADDRESS:
4906 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4913 /* Return 1 if the value in reload reg REGNO, as used by a reload
4914 needed for the part of the insn specified by OPNUM and TYPE,
4915 is still available in REGNO at the end of the insn.
4917 We can assume that the reload reg was already tested for availability
4918 at the time it is needed, and we should not check this again,
4919 in case the reg has already been marked in use. */
4922 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4929 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4930 its value must reach the end. */
4933 /* If this use is for part of the insn,
4934 its value reaches if no subsequent part uses the same register.
4935 Just like the above function, don't try to do this with lots
4938 case RELOAD_FOR_OTHER_ADDRESS:
4939 /* Here we check for everything else, since these don't conflict
4940 with anything else and everything comes later. */
4942 for (i = 0; i < reload_n_operands; i++)
4943 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4944 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4945 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4946 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4947 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4948 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4951 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4952 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4953 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4954 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4956 case RELOAD_FOR_INPUT_ADDRESS:
4957 case RELOAD_FOR_INPADDR_ADDRESS:
4958 /* Similar, except that we check only for this and subsequent inputs
4959 and the address of only subsequent inputs and we do not need
4960 to check for RELOAD_OTHER objects since they are known not to
4963 for (i = opnum; i < reload_n_operands; i++)
4964 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4967 for (i = opnum + 1; i < reload_n_operands; i++)
4968 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4969 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4972 for (i = 0; i < reload_n_operands; i++)
4973 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4974 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4975 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4978 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4981 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4982 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4983 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4985 case RELOAD_FOR_INPUT:
4986 /* Similar to input address, except we start at the next operand for
4987 both input and input address and we do not check for
4988 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4991 for (i = opnum + 1; i < reload_n_operands; i++)
4992 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4993 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4994 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4997 /* ... fall through ... */
4999 case RELOAD_FOR_OPERAND_ADDRESS:
5000 /* Check outputs and their addresses. */
5002 for (i = 0; i < reload_n_operands; i++)
5003 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5004 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5005 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5008 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5010 case RELOAD_FOR_OPADDR_ADDR:
5011 for (i = 0; i < reload_n_operands; i++)
5012 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5013 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5014 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5017 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5018 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5019 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5021 case RELOAD_FOR_INSN:
5022 /* These conflict with other outputs with RELOAD_OTHER. So
5023 we need only check for output addresses. */
5025 opnum = reload_n_operands;
5027 /* ... fall through ... */
5029 case RELOAD_FOR_OUTPUT:
5030 case RELOAD_FOR_OUTPUT_ADDRESS:
5031 case RELOAD_FOR_OUTADDR_ADDRESS:
5032 /* We already know these can't conflict with a later output. So the
5033 only thing to check are later output addresses.
5034 Note that multiple output operands are emitted in reverse order,
5035 so the conflicting ones are those with lower indices. */
5036 for (i = 0; i < opnum; i++)
5037 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5038 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5048 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5049 every register in the range [REGNO, REGNO + NREGS). */
5052 reload_regs_reach_end_p (unsigned int regno, int nregs,
5053 int opnum, enum reload_type type)
5057 for (i = 0; i < nregs; i++)
5058 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5064 /* Returns whether R1 and R2 are uniquely chained: the value of one
5065 is used by the other, and that value is not used by any other
5066 reload for this insn. This is used to partially undo the decision
5067 made in find_reloads when in the case of multiple
5068 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5069 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5070 reloads. This code tries to avoid the conflict created by that
5071 change. It might be cleaner to explicitly keep track of which
5072 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5073 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5074 this after the fact. */
5076 reloads_unique_chain_p (int r1, int r2)
5080 /* We only check input reloads. */
5081 if (! rld[r1].in || ! rld[r2].in)
5084 /* Avoid anything with output reloads. */
5085 if (rld[r1].out || rld[r2].out)
5088 /* "chained" means one reload is a component of the other reload,
5089 not the same as the other reload. */
5090 if (rld[r1].opnum != rld[r2].opnum
5091 || rtx_equal_p (rld[r1].in, rld[r2].in)
5092 || rld[r1].optional || rld[r2].optional
5093 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5094 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5097 for (i = 0; i < n_reloads; i ++)
5098 /* Look for input reloads that aren't our two */
5099 if (i != r1 && i != r2 && rld[i].in)
5101 /* If our reload is mentioned at all, it isn't a simple chain. */
5102 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5109 /* The recursive function change all occurrences of WHAT in *WHERE
5112 substitute (rtx *where, const_rtx what, rtx repl)
5121 if (*where == what || rtx_equal_p (*where, what))
5127 code = GET_CODE (*where);
5128 fmt = GET_RTX_FORMAT (code);
5129 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5135 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5136 substitute (&XVECEXP (*where, i, j), what, repl);
5138 else if (fmt[i] == 'e')
5139 substitute (&XEXP (*where, i), what, repl);
5143 /* The function returns TRUE if chain of reload R1 and R2 (in any
5144 order) can be evaluated without usage of intermediate register for
5145 the reload containing another reload. It is important to see
5146 gen_reload to understand what the function is trying to do. As an
5147 example, let us have reload chain
5150 r1: <something> + const
5152 and reload R2 got reload reg HR. The function returns true if
5153 there is a correct insn HR = HR + <something>. Otherwise,
5154 gen_reload will use intermediate register (and this is the reload
5155 reg for R1) to reload <something>.
5157 We need this function to find a conflict for chain reloads. In our
5158 example, if HR = HR + <something> is incorrect insn, then we cannot
5159 use HR as a reload register for R2. If we do use it then we get a
5168 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5172 rtx out, in, tem, insn;
5173 rtx last = get_last_insn ();
5175 /* Make r2 a component of r1. */
5176 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5182 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5183 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5184 gcc_assert (regno >= 0);
5185 out = gen_rtx_REG (rld[r1].mode, regno);
5186 in = copy_rtx (rld[r1].in);
5187 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5189 /* If IN is a paradoxical SUBREG, remove it and try to put the
5190 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5191 if (GET_CODE (in) == SUBREG
5192 && (GET_MODE_SIZE (GET_MODE (in))
5193 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5194 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5195 in = SUBREG_REG (in), out = tem;
5197 if (GET_CODE (in) == PLUS
5198 && (REG_P (XEXP (in, 0))
5199 || GET_CODE (XEXP (in, 0)) == SUBREG
5200 || MEM_P (XEXP (in, 0)))
5201 && (REG_P (XEXP (in, 1))
5202 || GET_CODE (XEXP (in, 1)) == SUBREG
5203 || CONSTANT_P (XEXP (in, 1))
5204 || MEM_P (XEXP (in, 1))))
5206 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5207 code = recog_memoized (insn);
5212 extract_insn (insn);
5213 /* We want constrain operands to treat this insn strictly in
5214 its validity determination, i.e., the way it would after
5215 reload has completed. */
5216 result = constrain_operands (1);
5219 delete_insns_since (last);
5223 /* It looks like other cases in gen_reload are not possible for
5224 chain reloads or do need an intermediate hard registers. */
5228 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5231 This function uses the same algorithm as reload_reg_free_p above. */
5234 reloads_conflict (int r1, int r2)
5236 enum reload_type r1_type = rld[r1].when_needed;
5237 enum reload_type r2_type = rld[r2].when_needed;
5238 int r1_opnum = rld[r1].opnum;
5239 int r2_opnum = rld[r2].opnum;
5241 /* RELOAD_OTHER conflicts with everything. */
5242 if (r2_type == RELOAD_OTHER)
5245 /* Otherwise, check conflicts differently for each type. */
5249 case RELOAD_FOR_INPUT:
5250 return (r2_type == RELOAD_FOR_INSN
5251 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5252 || r2_type == RELOAD_FOR_OPADDR_ADDR
5253 || r2_type == RELOAD_FOR_INPUT
5254 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5255 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5256 && r2_opnum > r1_opnum));
5258 case RELOAD_FOR_INPUT_ADDRESS:
5259 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5260 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5262 case RELOAD_FOR_INPADDR_ADDRESS:
5263 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5264 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5266 case RELOAD_FOR_OUTPUT_ADDRESS:
5267 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5268 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5270 case RELOAD_FOR_OUTADDR_ADDRESS:
5271 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5272 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5274 case RELOAD_FOR_OPERAND_ADDRESS:
5275 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5276 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5277 && (!reloads_unique_chain_p (r1, r2)
5278 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5280 case RELOAD_FOR_OPADDR_ADDR:
5281 return (r2_type == RELOAD_FOR_INPUT
5282 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5284 case RELOAD_FOR_OUTPUT:
5285 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5286 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5287 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5288 && r2_opnum >= r1_opnum));
5290 case RELOAD_FOR_INSN:
5291 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5292 || r2_type == RELOAD_FOR_INSN
5293 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5295 case RELOAD_FOR_OTHER_ADDRESS:
5296 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5306 /* Indexed by reload number, 1 if incoming value
5307 inherited from previous insns. */
5308 static char reload_inherited[MAX_RELOADS];
5310 /* For an inherited reload, this is the insn the reload was inherited from,
5311 if we know it. Otherwise, this is 0. */
5312 static rtx reload_inheritance_insn[MAX_RELOADS];
5314 /* If nonzero, this is a place to get the value of the reload,
5315 rather than using reload_in. */
5316 static rtx reload_override_in[MAX_RELOADS];
5318 /* For each reload, the hard register number of the register used,
5319 or -1 if we did not need a register for this reload. */
5320 static int reload_spill_index[MAX_RELOADS];
5322 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5323 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5325 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5326 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5328 /* Subroutine of free_for_value_p, used to check a single register.
5329 START_REGNO is the starting regno of the full reload register
5330 (possibly comprising multiple hard registers) that we are considering. */
5333 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5334 enum reload_type type, rtx value, rtx out,
5335 int reloadnum, int ignore_address_reloads)
5338 /* Set if we see an input reload that must not share its reload register
5339 with any new earlyclobber, but might otherwise share the reload
5340 register with an output or input-output reload. */
5341 int check_earlyclobber = 0;
5345 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5348 if (out == const0_rtx)
5354 /* We use some pseudo 'time' value to check if the lifetimes of the
5355 new register use would overlap with the one of a previous reload
5356 that is not read-only or uses a different value.
5357 The 'time' used doesn't have to be linear in any shape or form, just
5359 Some reload types use different 'buckets' for each operand.
5360 So there are MAX_RECOG_OPERANDS different time values for each
5362 We compute TIME1 as the time when the register for the prospective
5363 new reload ceases to be live, and TIME2 for each existing
5364 reload as the time when that the reload register of that reload
5366 Where there is little to be gained by exact lifetime calculations,
5367 we just make conservative assumptions, i.e. a longer lifetime;
5368 this is done in the 'default:' cases. */
5371 case RELOAD_FOR_OTHER_ADDRESS:
5372 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5373 time1 = copy ? 0 : 1;
5376 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5378 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5379 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5380 respectively, to the time values for these, we get distinct time
5381 values. To get distinct time values for each operand, we have to
5382 multiply opnum by at least three. We round that up to four because
5383 multiply by four is often cheaper. */
5384 case RELOAD_FOR_INPADDR_ADDRESS:
5385 time1 = opnum * 4 + 2;
5387 case RELOAD_FOR_INPUT_ADDRESS:
5388 time1 = opnum * 4 + 3;
5390 case RELOAD_FOR_INPUT:
5391 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5392 executes (inclusive). */
5393 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5395 case RELOAD_FOR_OPADDR_ADDR:
5397 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5398 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5400 case RELOAD_FOR_OPERAND_ADDRESS:
5401 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5403 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5405 case RELOAD_FOR_OUTADDR_ADDRESS:
5406 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5408 case RELOAD_FOR_OUTPUT_ADDRESS:
5409 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5412 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5415 for (i = 0; i < n_reloads; i++)
5417 rtx reg = rld[i].reg_rtx;
5418 if (reg && REG_P (reg)
5419 && ((unsigned) regno - true_regnum (reg)
5420 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5423 rtx other_input = rld[i].in;
5425 /* If the other reload loads the same input value, that
5426 will not cause a conflict only if it's loading it into
5427 the same register. */
5428 if (true_regnum (reg) != start_regno)
5429 other_input = NULL_RTX;
5430 if (! other_input || ! rtx_equal_p (other_input, value)
5431 || rld[i].out || out)
5434 switch (rld[i].when_needed)
5436 case RELOAD_FOR_OTHER_ADDRESS:
5439 case RELOAD_FOR_INPADDR_ADDRESS:
5440 /* find_reloads makes sure that a
5441 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5442 by at most one - the first -
5443 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5444 address reload is inherited, the address address reload
5445 goes away, so we can ignore this conflict. */
5446 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5447 && ignore_address_reloads
5448 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5449 Then the address address is still needed to store
5450 back the new address. */
5451 && ! rld[reloadnum].out)
5453 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5454 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5456 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5457 && ignore_address_reloads
5458 /* Unless we are reloading an auto_inc expression. */
5459 && ! rld[reloadnum].out)
5461 time2 = rld[i].opnum * 4 + 2;
5463 case RELOAD_FOR_INPUT_ADDRESS:
5464 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5465 && ignore_address_reloads
5466 && ! rld[reloadnum].out)
5468 time2 = rld[i].opnum * 4 + 3;
5470 case RELOAD_FOR_INPUT:
5471 time2 = rld[i].opnum * 4 + 4;
5472 check_earlyclobber = 1;
5474 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5475 == MAX_RECOG_OPERAND * 4 */
5476 case RELOAD_FOR_OPADDR_ADDR:
5477 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5478 && ignore_address_reloads
5479 && ! rld[reloadnum].out)
5481 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5483 case RELOAD_FOR_OPERAND_ADDRESS:
5484 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5485 check_earlyclobber = 1;
5487 case RELOAD_FOR_INSN:
5488 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5490 case RELOAD_FOR_OUTPUT:
5491 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5492 instruction is executed. */
5493 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5495 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5496 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5498 case RELOAD_FOR_OUTADDR_ADDRESS:
5499 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5500 && ignore_address_reloads
5501 && ! rld[reloadnum].out)
5503 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5505 case RELOAD_FOR_OUTPUT_ADDRESS:
5506 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5509 /* If there is no conflict in the input part, handle this
5510 like an output reload. */
5511 if (! rld[i].in || rtx_equal_p (other_input, value))
5513 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5514 /* Earlyclobbered outputs must conflict with inputs. */
5515 if (earlyclobber_operand_p (rld[i].out))
5516 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5521 /* RELOAD_OTHER might be live beyond instruction execution,
5522 but this is not obvious when we set time2 = 1. So check
5523 here if there might be a problem with the new reload
5524 clobbering the register used by the RELOAD_OTHER. */
5532 && (! rld[i].in || rld[i].out
5533 || ! rtx_equal_p (other_input, value)))
5534 || (out && rld[reloadnum].out_reg
5535 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5541 /* Earlyclobbered outputs must conflict with inputs. */
5542 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5548 /* Return 1 if the value in reload reg REGNO, as used by a reload
5549 needed for the part of the insn specified by OPNUM and TYPE,
5550 may be used to load VALUE into it.
5552 MODE is the mode in which the register is used, this is needed to
5553 determine how many hard regs to test.
5555 Other read-only reloads with the same value do not conflict
5556 unless OUT is nonzero and these other reloads have to live while
5557 output reloads live.
5558 If OUT is CONST0_RTX, this is a special case: it means that the
5559 test should not be for using register REGNO as reload register, but
5560 for copying from register REGNO into the reload register.
5562 RELOADNUM is the number of the reload we want to load this value for;
5563 a reload does not conflict with itself.
5565 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5566 reloads that load an address for the very reload we are considering.
5568 The caller has to make sure that there is no conflict with the return
5572 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5573 enum reload_type type, rtx value, rtx out, int reloadnum,
5574 int ignore_address_reloads)
5576 int nregs = hard_regno_nregs[regno][mode];
5578 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5579 value, out, reloadnum,
5580 ignore_address_reloads))
5585 /* Return nonzero if the rtx X is invariant over the current function. */
5586 /* ??? Actually, the places where we use this expect exactly what is
5587 tested here, and not everything that is function invariant. In
5588 particular, the frame pointer and arg pointer are special cased;
5589 pic_offset_table_rtx is not, and we must not spill these things to
5593 function_invariant_p (const_rtx x)
5597 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5599 if (GET_CODE (x) == PLUS
5600 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5601 && CONSTANT_P (XEXP (x, 1)))
5606 /* Determine whether the reload reg X overlaps any rtx'es used for
5607 overriding inheritance. Return nonzero if so. */
5610 conflicts_with_override (rtx x)
5613 for (i = 0; i < n_reloads; i++)
5614 if (reload_override_in[i]
5615 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5620 /* Give an error message saying we failed to find a reload for INSN,
5621 and clear out reload R. */
5623 failed_reload (rtx insn, int r)
5625 if (asm_noperands (PATTERN (insn)) < 0)
5626 /* It's the compiler's fault. */
5627 fatal_insn ("could not find a spill register", insn);
5629 /* It's the user's fault; the operand's mode and constraint
5630 don't match. Disable this reload so we don't crash in final. */
5631 error_for_asm (insn,
5632 "%<asm%> operand constraint incompatible with operand size");
5636 rld[r].optional = 1;
5637 rld[r].secondary_p = 1;
5640 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5641 for reload R. If it's valid, get an rtx for it. Return nonzero if
5644 set_reload_reg (int i, int r)
5647 rtx reg = spill_reg_rtx[i];
5649 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5650 spill_reg_rtx[i] = reg
5651 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5653 regno = true_regnum (reg);
5655 /* Detect when the reload reg can't hold the reload mode.
5656 This used to be one `if', but Sequent compiler can't handle that. */
5657 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5659 enum machine_mode test_mode = VOIDmode;
5661 test_mode = GET_MODE (rld[r].in);
5662 /* If rld[r].in has VOIDmode, it means we will load it
5663 in whatever mode the reload reg has: to wit, rld[r].mode.
5664 We have already tested that for validity. */
5665 /* Aside from that, we need to test that the expressions
5666 to reload from or into have modes which are valid for this
5667 reload register. Otherwise the reload insns would be invalid. */
5668 if (! (rld[r].in != 0 && test_mode != VOIDmode
5669 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5670 if (! (rld[r].out != 0
5671 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5673 /* The reg is OK. */
5676 /* Mark as in use for this insn the reload regs we use
5678 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5679 rld[r].when_needed, rld[r].mode);
5681 rld[r].reg_rtx = reg;
5682 reload_spill_index[r] = spill_regs[i];
5689 /* Find a spill register to use as a reload register for reload R.
5690 LAST_RELOAD is nonzero if this is the last reload for the insn being
5693 Set rld[R].reg_rtx to the register allocated.
5695 We return 1 if successful, or 0 if we couldn't find a spill reg and
5696 we didn't change anything. */
5699 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5704 /* If we put this reload ahead, thinking it is a group,
5705 then insist on finding a group. Otherwise we can grab a
5706 reg that some other reload needs.
5707 (That can happen when we have a 68000 DATA_OR_FP_REG
5708 which is a group of data regs or one fp reg.)
5709 We need not be so restrictive if there are no more reloads
5712 ??? Really it would be nicer to have smarter handling
5713 for that kind of reg class, where a problem like this is normal.
5714 Perhaps those classes should be avoided for reloading
5715 by use of more alternatives. */
5717 int force_group = rld[r].nregs > 1 && ! last_reload;
5719 /* If we want a single register and haven't yet found one,
5720 take any reg in the right class and not in use.
5721 If we want a consecutive group, here is where we look for it.
5723 We use two passes so we can first look for reload regs to
5724 reuse, which are already in use for other reloads in this insn,
5725 and only then use additional registers.
5726 I think that maximizing reuse is needed to make sure we don't
5727 run out of reload regs. Suppose we have three reloads, and
5728 reloads A and B can share regs. These need two regs.
5729 Suppose A and B are given different regs.
5730 That leaves none for C. */
5731 for (pass = 0; pass < 2; pass++)
5733 /* I is the index in spill_regs.
5734 We advance it round-robin between insns to use all spill regs
5735 equally, so that inherited reloads have a chance
5736 of leapfrogging each other. */
5740 for (count = 0; count < n_spills; count++)
5742 int rclass = (int) rld[r].rclass;
5748 regnum = spill_regs[i];
5750 if ((reload_reg_free_p (regnum, rld[r].opnum,
5753 /* We check reload_reg_used to make sure we
5754 don't clobber the return register. */
5755 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5756 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5757 rld[r].when_needed, rld[r].in,
5759 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
5760 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5761 /* Look first for regs to share, then for unshared. But
5762 don't share regs used for inherited reloads; they are
5763 the ones we want to preserve. */
5765 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5767 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5770 int nr = hard_regno_nregs[regnum][rld[r].mode];
5771 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5772 (on 68000) got us two FP regs. If NR is 1,
5773 we would reject both of them. */
5776 /* If we need only one reg, we have already won. */
5779 /* But reject a single reg if we demand a group. */
5784 /* Otherwise check that as many consecutive regs as we need
5785 are available here. */
5788 int regno = regnum + nr - 1;
5789 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
5790 && spill_reg_order[regno] >= 0
5791 && reload_reg_free_p (regno, rld[r].opnum,
5792 rld[r].when_needed)))
5801 /* If we found something on pass 1, omit pass 2. */
5802 if (count < n_spills)
5806 /* We should have found a spill register by now. */
5807 if (count >= n_spills)
5810 /* I is the index in SPILL_REG_RTX of the reload register we are to
5811 allocate. Get an rtx for it and find its register number. */
5813 return set_reload_reg (i, r);
5816 /* Initialize all the tables needed to allocate reload registers.
5817 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5818 is the array we use to restore the reg_rtx field for every reload. */
5821 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5825 for (i = 0; i < n_reloads; i++)
5826 rld[i].reg_rtx = save_reload_reg_rtx[i];
5828 memset (reload_inherited, 0, MAX_RELOADS);
5829 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5830 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5832 CLEAR_HARD_REG_SET (reload_reg_used);
5833 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5834 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5835 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5836 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5837 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5839 CLEAR_HARD_REG_SET (reg_used_in_insn);
5842 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5843 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5844 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5845 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5846 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5847 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5850 for (i = 0; i < reload_n_operands; i++)
5852 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5853 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5854 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5855 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5856 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5857 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5860 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5862 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5864 for (i = 0; i < n_reloads; i++)
5865 /* If we have already decided to use a certain register,
5866 don't use it in another way. */
5868 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5869 rld[i].when_needed, rld[i].mode);
5872 /* Assign hard reg targets for the pseudo-registers we must reload
5873 into hard regs for this insn.
5874 Also output the instructions to copy them in and out of the hard regs.
5876 For machines with register classes, we are responsible for
5877 finding a reload reg in the proper class. */
5880 choose_reload_regs (struct insn_chain *chain)
5882 rtx insn = chain->insn;
5884 unsigned int max_group_size = 1;
5885 enum reg_class group_class = NO_REGS;
5886 int pass, win, inheritance;
5888 rtx save_reload_reg_rtx[MAX_RELOADS];
5890 /* In order to be certain of getting the registers we need,
5891 we must sort the reloads into order of increasing register class.
5892 Then our grabbing of reload registers will parallel the process
5893 that provided the reload registers.
5895 Also note whether any of the reloads wants a consecutive group of regs.
5896 If so, record the maximum size of the group desired and what
5897 register class contains all the groups needed by this insn. */
5899 for (j = 0; j < n_reloads; j++)
5901 reload_order[j] = j;
5902 if (rld[j].reg_rtx != NULL_RTX)
5904 gcc_assert (REG_P (rld[j].reg_rtx)
5905 && HARD_REGISTER_P (rld[j].reg_rtx));
5906 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5909 reload_spill_index[j] = -1;
5911 if (rld[j].nregs > 1)
5913 max_group_size = MAX (rld[j].nregs, max_group_size);
5915 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
5918 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5922 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5924 /* If -O, try first with inheritance, then turning it off.
5925 If not -O, don't do inheritance.
5926 Using inheritance when not optimizing leads to paradoxes
5927 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5928 because one side of the comparison might be inherited. */
5930 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5932 choose_reload_regs_init (chain, save_reload_reg_rtx);
5934 /* Process the reloads in order of preference just found.
5935 Beyond this point, subregs can be found in reload_reg_rtx.
5937 This used to look for an existing reloaded home for all of the
5938 reloads, and only then perform any new reloads. But that could lose
5939 if the reloads were done out of reg-class order because a later
5940 reload with a looser constraint might have an old home in a register
5941 needed by an earlier reload with a tighter constraint.
5943 To solve this, we make two passes over the reloads, in the order
5944 described above. In the first pass we try to inherit a reload
5945 from a previous insn. If there is a later reload that needs a
5946 class that is a proper subset of the class being processed, we must
5947 also allocate a spill register during the first pass.
5949 Then make a second pass over the reloads to allocate any reloads
5950 that haven't been given registers yet. */
5952 for (j = 0; j < n_reloads; j++)
5954 int r = reload_order[j];
5955 rtx search_equiv = NULL_RTX;
5957 /* Ignore reloads that got marked inoperative. */
5958 if (rld[r].out == 0 && rld[r].in == 0
5959 && ! rld[r].secondary_p)
5962 /* If find_reloads chose to use reload_in or reload_out as a reload
5963 register, we don't need to chose one. Otherwise, try even if it
5964 found one since we might save an insn if we find the value lying
5966 Try also when reload_in is a pseudo without a hard reg. */
5967 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5968 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5969 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5970 && !MEM_P (rld[r].in)
5971 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5974 #if 0 /* No longer needed for correct operation.
5975 It might give better code, or might not; worth an experiment? */
5976 /* If this is an optional reload, we can't inherit from earlier insns
5977 until we are sure that any non-optional reloads have been allocated.
5978 The following code takes advantage of the fact that optional reloads
5979 are at the end of reload_order. */
5980 if (rld[r].optional != 0)
5981 for (i = 0; i < j; i++)
5982 if ((rld[reload_order[i]].out != 0
5983 || rld[reload_order[i]].in != 0
5984 || rld[reload_order[i]].secondary_p)
5985 && ! rld[reload_order[i]].optional
5986 && rld[reload_order[i]].reg_rtx == 0)
5987 allocate_reload_reg (chain, reload_order[i], 0);
5990 /* First see if this pseudo is already available as reloaded
5991 for a previous insn. We cannot try to inherit for reloads
5992 that are smaller than the maximum number of registers needed
5993 for groups unless the register we would allocate cannot be used
5996 We could check here to see if this is a secondary reload for
5997 an object that is already in a register of the desired class.
5998 This would avoid the need for the secondary reload register.
5999 But this is complex because we can't easily determine what
6000 objects might want to be loaded via this reload. So let a
6001 register be allocated here. In `emit_reload_insns' we suppress
6002 one of the loads in the case described above. */
6008 enum machine_mode mode = VOIDmode;
6012 else if (REG_P (rld[r].in))
6014 regno = REGNO (rld[r].in);
6015 mode = GET_MODE (rld[r].in);
6017 else if (REG_P (rld[r].in_reg))
6019 regno = REGNO (rld[r].in_reg);
6020 mode = GET_MODE (rld[r].in_reg);
6022 else if (GET_CODE (rld[r].in_reg) == SUBREG
6023 && REG_P (SUBREG_REG (rld[r].in_reg)))
6025 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6026 if (regno < FIRST_PSEUDO_REGISTER)
6027 regno = subreg_regno (rld[r].in_reg);
6029 byte = SUBREG_BYTE (rld[r].in_reg);
6030 mode = GET_MODE (rld[r].in_reg);
6033 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6034 && REG_P (XEXP (rld[r].in_reg, 0)))
6036 regno = REGNO (XEXP (rld[r].in_reg, 0));
6037 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6038 rld[r].out = rld[r].in;
6042 /* This won't work, since REGNO can be a pseudo reg number.
6043 Also, it takes much more hair to keep track of all the things
6044 that can invalidate an inherited reload of part of a pseudoreg. */
6045 else if (GET_CODE (rld[r].in) == SUBREG
6046 && REG_P (SUBREG_REG (rld[r].in)))
6047 regno = subreg_regno (rld[r].in);
6051 && reg_last_reload_reg[regno] != 0
6052 #ifdef CANNOT_CHANGE_MODE_CLASS
6053 /* Verify that the register it's in can be used in
6055 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6056 GET_MODE (reg_last_reload_reg[regno]),
6061 enum reg_class rclass = rld[r].rclass, last_class;
6062 rtx last_reg = reg_last_reload_reg[regno];
6063 enum machine_mode need_mode;
6065 i = REGNO (last_reg);
6066 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6067 last_class = REGNO_REG_CLASS (i);
6073 = smallest_mode_for_size
6074 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6075 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6076 ? MODE_INT : GET_MODE_CLASS (mode));
6078 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6079 >= GET_MODE_SIZE (need_mode))
6080 && reg_reloaded_contents[i] == regno
6081 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6082 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6083 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6084 /* Even if we can't use this register as a reload
6085 register, we might use it for reload_override_in,
6086 if copying it to the desired class is cheap
6088 || ((REGISTER_MOVE_COST (mode, last_class, rclass)
6089 < MEMORY_MOVE_COST (mode, rclass, 1))
6090 && (secondary_reload_class (1, rclass, mode,
6093 #ifdef SECONDARY_MEMORY_NEEDED
6094 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6099 && (rld[r].nregs == max_group_size
6100 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6102 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6103 rld[r].when_needed, rld[r].in,
6106 /* If a group is needed, verify that all the subsequent
6107 registers still have their values intact. */
6108 int nr = hard_regno_nregs[i][rld[r].mode];
6111 for (k = 1; k < nr; k++)
6112 if (reg_reloaded_contents[i + k] != regno
6113 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6121 last_reg = (GET_MODE (last_reg) == mode
6122 ? last_reg : gen_rtx_REG (mode, i));
6125 for (k = 0; k < nr; k++)
6126 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6129 /* We found a register that contains the
6130 value we need. If this register is the
6131 same as an `earlyclobber' operand of the
6132 current insn, just mark it as a place to
6133 reload from since we can't use it as the
6134 reload register itself. */
6136 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6137 if (reg_overlap_mentioned_for_reload_p
6138 (reg_last_reload_reg[regno],
6139 reload_earlyclobbers[i1]))
6142 if (i1 != n_earlyclobbers
6143 || ! (free_for_value_p (i, rld[r].mode,
6145 rld[r].when_needed, rld[r].in,
6147 /* Don't use it if we'd clobber a pseudo reg. */
6148 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6150 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6151 /* Don't clobber the frame pointer. */
6152 || (i == HARD_FRAME_POINTER_REGNUM
6153 && frame_pointer_needed
6155 /* Don't really use the inherited spill reg
6156 if we need it wider than we've got it. */
6157 || (GET_MODE_SIZE (rld[r].mode)
6158 > GET_MODE_SIZE (mode))
6161 /* If find_reloads chose reload_out as reload
6162 register, stay with it - that leaves the
6163 inherited register for subsequent reloads. */
6164 || (rld[r].out && rld[r].reg_rtx
6165 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6167 if (! rld[r].optional)
6169 reload_override_in[r] = last_reg;
6170 reload_inheritance_insn[r]
6171 = reg_reloaded_insn[i];
6177 /* We can use this as a reload reg. */
6178 /* Mark the register as in use for this part of
6180 mark_reload_reg_in_use (i,
6184 rld[r].reg_rtx = last_reg;
6185 reload_inherited[r] = 1;
6186 reload_inheritance_insn[r]
6187 = reg_reloaded_insn[i];
6188 reload_spill_index[r] = i;
6189 for (k = 0; k < nr; k++)
6190 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6198 /* Here's another way to see if the value is already lying around. */
6201 && ! reload_inherited[r]
6203 && (CONSTANT_P (rld[r].in)
6204 || GET_CODE (rld[r].in) == PLUS
6205 || REG_P (rld[r].in)
6206 || MEM_P (rld[r].in))
6207 && (rld[r].nregs == max_group_size
6208 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6209 search_equiv = rld[r].in;
6214 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6215 -1, NULL, 0, rld[r].mode);
6221 regno = REGNO (equiv);
6224 /* This must be a SUBREG of a hard register.
6225 Make a new REG since this might be used in an
6226 address and not all machines support SUBREGs
6228 gcc_assert (GET_CODE (equiv) == SUBREG);
6229 regno = subreg_regno (equiv);
6230 equiv = gen_rtx_REG (rld[r].mode, regno);
6231 /* If we choose EQUIV as the reload register, but the
6232 loop below decides to cancel the inheritance, we'll
6233 end up reloading EQUIV in rld[r].mode, not the mode
6234 it had originally. That isn't safe when EQUIV isn't
6235 available as a spill register since its value might
6236 still be live at this point. */
6237 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6238 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6243 /* If we found a spill reg, reject it unless it is free
6244 and of the desired class. */
6248 int bad_for_class = 0;
6249 int max_regno = regno + rld[r].nregs;
6251 for (i = regno; i < max_regno; i++)
6253 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6255 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6260 && ! free_for_value_p (regno, rld[r].mode,
6261 rld[r].opnum, rld[r].when_needed,
6262 rld[r].in, rld[r].out, r, 1))
6267 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6270 /* We found a register that contains the value we need.
6271 If this register is the same as an `earlyclobber' operand
6272 of the current insn, just mark it as a place to reload from
6273 since we can't use it as the reload register itself. */
6276 for (i = 0; i < n_earlyclobbers; i++)
6277 if (reg_overlap_mentioned_for_reload_p (equiv,
6278 reload_earlyclobbers[i]))
6280 if (! rld[r].optional)
6281 reload_override_in[r] = equiv;
6286 /* If the equiv register we have found is explicitly clobbered
6287 in the current insn, it depends on the reload type if we
6288 can use it, use it for reload_override_in, or not at all.
6289 In particular, we then can't use EQUIV for a
6290 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6294 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6295 switch (rld[r].when_needed)
6297 case RELOAD_FOR_OTHER_ADDRESS:
6298 case RELOAD_FOR_INPADDR_ADDRESS:
6299 case RELOAD_FOR_INPUT_ADDRESS:
6300 case RELOAD_FOR_OPADDR_ADDR:
6303 case RELOAD_FOR_INPUT:
6304 case RELOAD_FOR_OPERAND_ADDRESS:
6305 if (! rld[r].optional)
6306 reload_override_in[r] = equiv;
6312 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6313 switch (rld[r].when_needed)
6315 case RELOAD_FOR_OTHER_ADDRESS:
6316 case RELOAD_FOR_INPADDR_ADDRESS:
6317 case RELOAD_FOR_INPUT_ADDRESS:
6318 case RELOAD_FOR_OPADDR_ADDR:
6319 case RELOAD_FOR_OPERAND_ADDRESS:
6320 case RELOAD_FOR_INPUT:
6323 if (! rld[r].optional)
6324 reload_override_in[r] = equiv;
6332 /* If we found an equivalent reg, say no code need be generated
6333 to load it, and use it as our reload reg. */
6335 && (regno != HARD_FRAME_POINTER_REGNUM
6336 || !frame_pointer_needed))
6338 int nr = hard_regno_nregs[regno][rld[r].mode];
6340 rld[r].reg_rtx = equiv;
6341 reload_spill_index[r] = regno;
6342 reload_inherited[r] = 1;
6344 /* If reg_reloaded_valid is not set for this register,
6345 there might be a stale spill_reg_store lying around.
6346 We must clear it, since otherwise emit_reload_insns
6347 might delete the store. */
6348 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6349 spill_reg_store[regno] = NULL_RTX;
6350 /* If any of the hard registers in EQUIV are spill
6351 registers, mark them as in use for this insn. */
6352 for (k = 0; k < nr; k++)
6354 i = spill_reg_order[regno + k];
6357 mark_reload_reg_in_use (regno, rld[r].opnum,
6360 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6367 /* If we found a register to use already, or if this is an optional
6368 reload, we are done. */
6369 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6373 /* No longer needed for correct operation. Might or might
6374 not give better code on the average. Want to experiment? */
6376 /* See if there is a later reload that has a class different from our
6377 class that intersects our class or that requires less register
6378 than our reload. If so, we must allocate a register to this
6379 reload now, since that reload might inherit a previous reload
6380 and take the only available register in our class. Don't do this
6381 for optional reloads since they will force all previous reloads
6382 to be allocated. Also don't do this for reloads that have been
6385 for (i = j + 1; i < n_reloads; i++)
6387 int s = reload_order[i];
6389 if ((rld[s].in == 0 && rld[s].out == 0
6390 && ! rld[s].secondary_p)
6394 if ((rld[s].rclass != rld[r].rclass
6395 && reg_classes_intersect_p (rld[r].rclass,
6397 || rld[s].nregs < rld[r].nregs)
6404 allocate_reload_reg (chain, r, j == n_reloads - 1);
6408 /* Now allocate reload registers for anything non-optional that
6409 didn't get one yet. */
6410 for (j = 0; j < n_reloads; j++)
6412 int r = reload_order[j];
6414 /* Ignore reloads that got marked inoperative. */
6415 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6418 /* Skip reloads that already have a register allocated or are
6420 if (rld[r].reg_rtx != 0 || rld[r].optional)
6423 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6427 /* If that loop got all the way, we have won. */
6434 /* Loop around and try without any inheritance. */
6439 /* First undo everything done by the failed attempt
6440 to allocate with inheritance. */
6441 choose_reload_regs_init (chain, save_reload_reg_rtx);
6443 /* Some sanity tests to verify that the reloads found in the first
6444 pass are identical to the ones we have now. */
6445 gcc_assert (chain->n_reloads == n_reloads);
6447 for (i = 0; i < n_reloads; i++)
6449 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6451 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6452 for (j = 0; j < n_spills; j++)
6453 if (spill_regs[j] == chain->rld[i].regno)
6454 if (! set_reload_reg (j, i))
6455 failed_reload (chain->insn, i);
6459 /* If we thought we could inherit a reload, because it seemed that
6460 nothing else wanted the same reload register earlier in the insn,
6461 verify that assumption, now that all reloads have been assigned.
6462 Likewise for reloads where reload_override_in has been set. */
6464 /* If doing expensive optimizations, do one preliminary pass that doesn't
6465 cancel any inheritance, but removes reloads that have been needed only
6466 for reloads that we know can be inherited. */
6467 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6469 for (j = 0; j < n_reloads; j++)
6471 int r = reload_order[j];
6473 if (reload_inherited[r] && rld[r].reg_rtx)
6474 check_reg = rld[r].reg_rtx;
6475 else if (reload_override_in[r]
6476 && (REG_P (reload_override_in[r])
6477 || GET_CODE (reload_override_in[r]) == SUBREG))
6478 check_reg = reload_override_in[r];
6481 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6482 rld[r].opnum, rld[r].when_needed, rld[r].in,
6483 (reload_inherited[r]
6484 ? rld[r].out : const0_rtx),
6489 reload_inherited[r] = 0;
6490 reload_override_in[r] = 0;
6492 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6493 reload_override_in, then we do not need its related
6494 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6495 likewise for other reload types.
6496 We handle this by removing a reload when its only replacement
6497 is mentioned in reload_in of the reload we are going to inherit.
6498 A special case are auto_inc expressions; even if the input is
6499 inherited, we still need the address for the output. We can
6500 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6501 If we succeeded removing some reload and we are doing a preliminary
6502 pass just to remove such reloads, make another pass, since the
6503 removal of one reload might allow us to inherit another one. */
6505 && rld[r].out != rld[r].in
6506 && remove_address_replacements (rld[r].in) && pass)
6511 /* Now that reload_override_in is known valid,
6512 actually override reload_in. */
6513 for (j = 0; j < n_reloads; j++)
6514 if (reload_override_in[j])
6515 rld[j].in = reload_override_in[j];
6517 /* If this reload won't be done because it has been canceled or is
6518 optional and not inherited, clear reload_reg_rtx so other
6519 routines (such as subst_reloads) don't get confused. */
6520 for (j = 0; j < n_reloads; j++)
6521 if (rld[j].reg_rtx != 0
6522 && ((rld[j].optional && ! reload_inherited[j])
6523 || (rld[j].in == 0 && rld[j].out == 0
6524 && ! rld[j].secondary_p)))
6526 int regno = true_regnum (rld[j].reg_rtx);
6528 if (spill_reg_order[regno] >= 0)
6529 clear_reload_reg_in_use (regno, rld[j].opnum,
6530 rld[j].when_needed, rld[j].mode);
6532 reload_spill_index[j] = -1;
6535 /* Record which pseudos and which spill regs have output reloads. */
6536 for (j = 0; j < n_reloads; j++)
6538 int r = reload_order[j];
6540 i = reload_spill_index[r];
6542 /* I is nonneg if this reload uses a register.
6543 If rld[r].reg_rtx is 0, this is an optional reload
6544 that we opted to ignore. */
6545 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6546 && rld[r].reg_rtx != 0)
6548 int nregno = REGNO (rld[r].out_reg);
6551 if (nregno < FIRST_PSEUDO_REGISTER)
6552 nr = hard_regno_nregs[nregno][rld[r].mode];
6555 SET_REGNO_REG_SET (®_has_output_reload,
6560 nr = hard_regno_nregs[i][rld[r].mode];
6562 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6565 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6566 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6567 || rld[r].when_needed == RELOAD_FOR_INSN);
6572 /* Deallocate the reload register for reload R. This is called from
6573 remove_address_replacements. */
6576 deallocate_reload_reg (int r)
6580 if (! rld[r].reg_rtx)
6582 regno = true_regnum (rld[r].reg_rtx);
6584 if (spill_reg_order[regno] >= 0)
6585 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6587 reload_spill_index[r] = -1;
6590 /* These arrays are filled by emit_reload_insns and its subroutines. */
6591 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6592 static rtx other_input_address_reload_insns = 0;
6593 static rtx other_input_reload_insns = 0;
6594 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6595 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6596 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6597 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6598 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6599 static rtx operand_reload_insns = 0;
6600 static rtx other_operand_reload_insns = 0;
6601 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6603 /* Values to be put in spill_reg_store are put here first. */
6604 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6605 static HARD_REG_SET reg_reloaded_died;
6607 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6608 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6609 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6610 adjusted register, and return true. Otherwise, return false. */
6612 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6613 enum reg_class new_class,
6614 enum machine_mode new_mode)
6619 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6621 unsigned regno = REGNO (reg);
6623 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6625 if (GET_MODE (reg) != new_mode)
6627 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6629 if (hard_regno_nregs[regno][new_mode]
6630 > hard_regno_nregs[regno][GET_MODE (reg)])
6632 reg = reload_adjust_reg_for_mode (reg, new_mode);
6640 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6641 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6642 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6643 adjusted register, and return true. Otherwise, return false. */
6645 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6646 enum insn_code icode)
6649 enum reg_class new_class = scratch_reload_class (icode);
6650 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6652 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6653 new_class, new_mode);
6656 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6657 has the number J. OLD contains the value to be used as input. */
6660 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6663 rtx insn = chain->insn;
6665 rtx oldequiv_reg = 0;
6668 enum machine_mode mode;
6671 /* delete_output_reload is only invoked properly if old contains
6672 the original pseudo register. Since this is replaced with a
6673 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6674 find the pseudo in RELOAD_IN_REG. */
6675 if (reload_override_in[j]
6676 && REG_P (rl->in_reg))
6683 else if (REG_P (oldequiv))
6684 oldequiv_reg = oldequiv;
6685 else if (GET_CODE (oldequiv) == SUBREG)
6686 oldequiv_reg = SUBREG_REG (oldequiv);
6688 reloadreg = reload_reg_rtx_for_input[j];
6689 mode = GET_MODE (reloadreg);
6691 /* If we are reloading from a register that was recently stored in
6692 with an output-reload, see if we can prove there was
6693 actually no need to store the old value in it. */
6695 if (optimize && REG_P (oldequiv)
6696 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6697 && spill_reg_store[REGNO (oldequiv)]
6699 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6700 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6702 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6704 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6707 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6708 oldequiv = SUBREG_REG (oldequiv);
6709 if (GET_MODE (oldequiv) != VOIDmode
6710 && mode != GET_MODE (oldequiv))
6711 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6713 /* Switch to the right place to emit the reload insns. */
6714 switch (rl->when_needed)
6717 where = &other_input_reload_insns;
6719 case RELOAD_FOR_INPUT:
6720 where = &input_reload_insns[rl->opnum];
6722 case RELOAD_FOR_INPUT_ADDRESS:
6723 where = &input_address_reload_insns[rl->opnum];
6725 case RELOAD_FOR_INPADDR_ADDRESS:
6726 where = &inpaddr_address_reload_insns[rl->opnum];
6728 case RELOAD_FOR_OUTPUT_ADDRESS:
6729 where = &output_address_reload_insns[rl->opnum];
6731 case RELOAD_FOR_OUTADDR_ADDRESS:
6732 where = &outaddr_address_reload_insns[rl->opnum];
6734 case RELOAD_FOR_OPERAND_ADDRESS:
6735 where = &operand_reload_insns;
6737 case RELOAD_FOR_OPADDR_ADDR:
6738 where = &other_operand_reload_insns;
6740 case RELOAD_FOR_OTHER_ADDRESS:
6741 where = &other_input_address_reload_insns;
6747 push_to_sequence (*where);
6749 /* Auto-increment addresses must be reloaded in a special way. */
6750 if (rl->out && ! rl->out_reg)
6752 /* We are not going to bother supporting the case where a
6753 incremented register can't be copied directly from
6754 OLDEQUIV since this seems highly unlikely. */
6755 gcc_assert (rl->secondary_in_reload < 0);
6757 if (reload_inherited[j])
6758 oldequiv = reloadreg;
6760 old = XEXP (rl->in_reg, 0);
6762 if (optimize && REG_P (oldequiv)
6763 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6764 && spill_reg_store[REGNO (oldequiv)]
6766 && (dead_or_set_p (insn,
6767 spill_reg_stored_to[REGNO (oldequiv)])
6768 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6770 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6772 /* Prevent normal processing of this reload. */
6774 /* Output a special code sequence for this case. */
6775 new_spill_reg_store[REGNO (reloadreg)]
6776 = inc_for_reload (reloadreg, oldequiv, rl->out,
6780 /* If we are reloading a pseudo-register that was set by the previous
6781 insn, see if we can get rid of that pseudo-register entirely
6782 by redirecting the previous insn into our reload register. */
6784 else if (optimize && REG_P (old)
6785 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6786 && dead_or_set_p (insn, old)
6787 /* This is unsafe if some other reload
6788 uses the same reg first. */
6789 && ! conflicts_with_override (reloadreg)
6790 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6791 rl->when_needed, old, rl->out, j, 0))
6793 rtx temp = PREV_INSN (insn);
6794 while (temp && NOTE_P (temp))
6795 temp = PREV_INSN (temp);
6797 && NONJUMP_INSN_P (temp)
6798 && GET_CODE (PATTERN (temp)) == SET
6799 && SET_DEST (PATTERN (temp)) == old
6800 /* Make sure we can access insn_operand_constraint. */
6801 && asm_noperands (PATTERN (temp)) < 0
6802 /* This is unsafe if operand occurs more than once in current
6803 insn. Perhaps some occurrences aren't reloaded. */
6804 && count_occurrences (PATTERN (insn), old, 0) == 1)
6806 rtx old = SET_DEST (PATTERN (temp));
6807 /* Store into the reload register instead of the pseudo. */
6808 SET_DEST (PATTERN (temp)) = reloadreg;
6810 /* Verify that resulting insn is valid. */
6811 extract_insn (temp);
6812 if (constrain_operands (1))
6814 /* If the previous insn is an output reload, the source is
6815 a reload register, and its spill_reg_store entry will
6816 contain the previous destination. This is now
6818 if (REG_P (SET_SRC (PATTERN (temp)))
6819 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6821 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6822 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6825 /* If these are the only uses of the pseudo reg,
6826 pretend for GDB it lives in the reload reg we used. */
6827 if (REG_N_DEATHS (REGNO (old)) == 1
6828 && REG_N_SETS (REGNO (old)) == 1)
6830 reg_renumber[REGNO (old)] = REGNO (reloadreg);
6831 if (ira_conflicts_p)
6832 /* Inform IRA about the change. */
6833 ira_mark_allocation_change (REGNO (old));
6834 alter_reg (REGNO (old), -1, false);
6840 SET_DEST (PATTERN (temp)) = old;
6845 /* We can't do that, so output an insn to load RELOADREG. */
6847 /* If we have a secondary reload, pick up the secondary register
6848 and icode, if any. If OLDEQUIV and OLD are different or
6849 if this is an in-out reload, recompute whether or not we
6850 still need a secondary register and what the icode should
6851 be. If we still need a secondary register and the class or
6852 icode is different, go back to reloading from OLD if using
6853 OLDEQUIV means that we got the wrong type of register. We
6854 cannot have different class or icode due to an in-out reload
6855 because we don't make such reloads when both the input and
6856 output need secondary reload registers. */
6858 if (! special && rl->secondary_in_reload >= 0)
6860 rtx second_reload_reg = 0;
6861 rtx third_reload_reg = 0;
6862 int secondary_reload = rl->secondary_in_reload;
6863 rtx real_oldequiv = oldequiv;
6866 enum insn_code icode;
6867 enum insn_code tertiary_icode = CODE_FOR_nothing;
6869 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6870 and similarly for OLD.
6871 See comments in get_secondary_reload in reload.c. */
6872 /* If it is a pseudo that cannot be replaced with its
6873 equivalent MEM, we must fall back to reload_in, which
6874 will have all the necessary substitutions registered.
6875 Likewise for a pseudo that can't be replaced with its
6876 equivalent constant.
6878 Take extra care for subregs of such pseudos. Note that
6879 we cannot use reg_equiv_mem in this case because it is
6880 not in the right mode. */
6883 if (GET_CODE (tmp) == SUBREG)
6884 tmp = SUBREG_REG (tmp);
6886 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6887 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6888 || reg_equiv_constant[REGNO (tmp)] != 0))
6890 if (! reg_equiv_mem[REGNO (tmp)]
6891 || num_not_at_initial_offset
6892 || GET_CODE (oldequiv) == SUBREG)
6893 real_oldequiv = rl->in;
6895 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6899 if (GET_CODE (tmp) == SUBREG)
6900 tmp = SUBREG_REG (tmp);
6902 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6903 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6904 || reg_equiv_constant[REGNO (tmp)] != 0))
6906 if (! reg_equiv_mem[REGNO (tmp)]
6907 || num_not_at_initial_offset
6908 || GET_CODE (old) == SUBREG)
6911 real_old = reg_equiv_mem[REGNO (tmp)];
6914 second_reload_reg = rld[secondary_reload].reg_rtx;
6915 if (rld[secondary_reload].secondary_in_reload >= 0)
6917 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6919 third_reload_reg = rld[tertiary_reload].reg_rtx;
6920 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6921 /* We'd have to add more code for quartary reloads. */
6922 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6924 icode = rl->secondary_in_icode;
6926 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6927 || (rl->in != 0 && rl->out != 0))
6929 secondary_reload_info sri, sri2;
6930 enum reg_class new_class, new_t_class;
6932 sri.icode = CODE_FOR_nothing;
6933 sri.prev_sri = NULL;
6934 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
6937 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6938 second_reload_reg = 0;
6939 else if (new_class == NO_REGS)
6941 if (reload_adjust_reg_for_icode (&second_reload_reg,
6942 third_reload_reg, sri.icode))
6943 icode = sri.icode, third_reload_reg = 0;
6945 oldequiv = old, real_oldequiv = real_old;
6947 else if (sri.icode != CODE_FOR_nothing)
6948 /* We currently lack a way to express this in reloads. */
6952 sri2.icode = CODE_FOR_nothing;
6953 sri2.prev_sri = &sri;
6954 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6955 new_class, mode, &sri);
6956 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6958 if (reload_adjust_reg_for_temp (&second_reload_reg,
6961 third_reload_reg = 0, tertiary_icode = sri2.icode;
6963 oldequiv = old, real_oldequiv = real_old;
6965 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6967 rtx intermediate = second_reload_reg;
6969 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6971 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6974 second_reload_reg = intermediate;
6975 tertiary_icode = sri2.icode;
6978 oldequiv = old, real_oldequiv = real_old;
6980 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6982 rtx intermediate = second_reload_reg;
6984 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6986 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6989 second_reload_reg = intermediate;
6990 tertiary_icode = sri2.icode;
6993 oldequiv = old, real_oldequiv = real_old;
6996 /* This could be handled more intelligently too. */
6997 oldequiv = old, real_oldequiv = real_old;
7001 /* If we still need a secondary reload register, check
7002 to see if it is being used as a scratch or intermediate
7003 register and generate code appropriately. If we need
7004 a scratch register, use REAL_OLDEQUIV since the form of
7005 the insn may depend on the actual address if it is
7008 if (second_reload_reg)
7010 if (icode != CODE_FOR_nothing)
7012 /* We'd have to add extra code to handle this case. */
7013 gcc_assert (!third_reload_reg);
7015 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7016 second_reload_reg));
7021 /* See if we need a scratch register to load the
7022 intermediate register (a tertiary reload). */
7023 if (tertiary_icode != CODE_FOR_nothing)
7025 emit_insn ((GEN_FCN (tertiary_icode)
7026 (second_reload_reg, real_oldequiv,
7027 third_reload_reg)));
7029 else if (third_reload_reg)
7031 gen_reload (third_reload_reg, real_oldequiv,
7034 gen_reload (second_reload_reg, third_reload_reg,
7039 gen_reload (second_reload_reg, real_oldequiv,
7043 oldequiv = second_reload_reg;
7048 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7050 rtx real_oldequiv = oldequiv;
7052 if ((REG_P (oldequiv)
7053 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7054 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7055 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7056 || (GET_CODE (oldequiv) == SUBREG
7057 && REG_P (SUBREG_REG (oldequiv))
7058 && (REGNO (SUBREG_REG (oldequiv))
7059 >= FIRST_PSEUDO_REGISTER)
7060 && ((reg_equiv_memory_loc
7061 [REGNO (SUBREG_REG (oldequiv))] != 0)
7062 || (reg_equiv_constant
7063 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7064 || (CONSTANT_P (oldequiv)
7065 && (PREFERRED_RELOAD_CLASS (oldequiv,
7066 REGNO_REG_CLASS (REGNO (reloadreg)))
7068 real_oldequiv = rl->in;
7069 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7073 if (flag_non_call_exceptions)
7074 copy_eh_notes (insn, get_insns ());
7076 /* End this sequence. */
7077 *where = get_insns ();
7080 /* Update reload_override_in so that delete_address_reloads_1
7081 can see the actual register usage. */
7083 reload_override_in[j] = oldequiv;
7086 /* Generate insns to for the output reload RL, which is for the insn described
7087 by CHAIN and has the number J. */
7089 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7093 rtx insn = chain->insn;
7096 enum machine_mode mode;
7100 if (rl->when_needed == RELOAD_OTHER)
7103 push_to_sequence (output_reload_insns[rl->opnum]);
7105 rl_reg_rtx = reload_reg_rtx_for_output[j];
7106 mode = GET_MODE (rl_reg_rtx);
7108 reloadreg = rl_reg_rtx;
7110 /* If we need two reload regs, set RELOADREG to the intermediate
7111 one, since it will be stored into OLD. We might need a secondary
7112 register only for an input reload, so check again here. */
7114 if (rl->secondary_out_reload >= 0)
7117 int secondary_reload = rl->secondary_out_reload;
7118 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7120 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7121 && reg_equiv_mem[REGNO (old)] != 0)
7122 real_old = reg_equiv_mem[REGNO (old)];
7124 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7126 rtx second_reloadreg = reloadreg;
7127 reloadreg = rld[secondary_reload].reg_rtx;
7129 /* See if RELOADREG is to be used as a scratch register
7130 or as an intermediate register. */
7131 if (rl->secondary_out_icode != CODE_FOR_nothing)
7133 /* We'd have to add extra code to handle this case. */
7134 gcc_assert (tertiary_reload < 0);
7136 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7137 (real_old, second_reloadreg, reloadreg)));
7142 /* See if we need both a scratch and intermediate reload
7145 enum insn_code tertiary_icode
7146 = rld[secondary_reload].secondary_out_icode;
7148 /* We'd have to add more code for quartary reloads. */
7149 gcc_assert (tertiary_reload < 0
7150 || rld[tertiary_reload].secondary_out_reload < 0);
7152 if (GET_MODE (reloadreg) != mode)
7153 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7155 if (tertiary_icode != CODE_FOR_nothing)
7157 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7160 /* Copy primary reload reg to secondary reload reg.
7161 (Note that these have been swapped above, then
7162 secondary reload reg to OLD using our insn.) */
7164 /* If REAL_OLD is a paradoxical SUBREG, remove it
7165 and try to put the opposite SUBREG on
7167 if (GET_CODE (real_old) == SUBREG
7168 && (GET_MODE_SIZE (GET_MODE (real_old))
7169 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7170 && 0 != (tem = gen_lowpart_common
7171 (GET_MODE (SUBREG_REG (real_old)),
7173 real_old = SUBREG_REG (real_old), reloadreg = tem;
7175 gen_reload (reloadreg, second_reloadreg,
7176 rl->opnum, rl->when_needed);
7177 emit_insn ((GEN_FCN (tertiary_icode)
7178 (real_old, reloadreg, third_reloadreg)));
7184 /* Copy between the reload regs here and then to
7187 gen_reload (reloadreg, second_reloadreg,
7188 rl->opnum, rl->when_needed);
7189 if (tertiary_reload >= 0)
7191 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7193 gen_reload (third_reloadreg, reloadreg,
7194 rl->opnum, rl->when_needed);
7195 reloadreg = third_reloadreg;
7202 /* Output the last reload insn. */
7207 /* Don't output the last reload if OLD is not the dest of
7208 INSN and is in the src and is clobbered by INSN. */
7209 if (! flag_expensive_optimizations
7211 || !(set = single_set (insn))
7212 || rtx_equal_p (old, SET_DEST (set))
7213 || !reg_mentioned_p (old, SET_SRC (set))
7214 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7215 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7216 gen_reload (old, reloadreg, rl->opnum,
7220 /* Look at all insns we emitted, just to be safe. */
7221 for (p = get_insns (); p; p = NEXT_INSN (p))
7224 rtx pat = PATTERN (p);
7226 /* If this output reload doesn't come from a spill reg,
7227 clear any memory of reloaded copies of the pseudo reg.
7228 If this output reload comes from a spill reg,
7229 reg_has_output_reload will make this do nothing. */
7230 note_stores (pat, forget_old_reloads_1, NULL);
7232 if (reg_mentioned_p (rl_reg_rtx, pat))
7234 rtx set = single_set (insn);
7235 if (reload_spill_index[j] < 0
7237 && SET_SRC (set) == rl_reg_rtx)
7239 int src = REGNO (SET_SRC (set));
7241 reload_spill_index[j] = src;
7242 SET_HARD_REG_BIT (reg_is_output_reload, src);
7243 if (find_regno_note (insn, REG_DEAD, src))
7244 SET_HARD_REG_BIT (reg_reloaded_died, src);
7246 if (HARD_REGISTER_P (rl_reg_rtx))
7248 int s = rl->secondary_out_reload;
7249 set = single_set (p);
7250 /* If this reload copies only to the secondary reload
7251 register, the secondary reload does the actual
7253 if (s >= 0 && set == NULL_RTX)
7254 /* We can't tell what function the secondary reload
7255 has and where the actual store to the pseudo is
7256 made; leave new_spill_reg_store alone. */
7259 && SET_SRC (set) == rl_reg_rtx
7260 && SET_DEST (set) == rld[s].reg_rtx)
7262 /* Usually the next instruction will be the
7263 secondary reload insn; if we can confirm
7264 that it is, setting new_spill_reg_store to
7265 that insn will allow an extra optimization. */
7266 rtx s_reg = rld[s].reg_rtx;
7267 rtx next = NEXT_INSN (p);
7268 rld[s].out = rl->out;
7269 rld[s].out_reg = rl->out_reg;
7270 set = single_set (next);
7271 if (set && SET_SRC (set) == s_reg
7272 && ! new_spill_reg_store[REGNO (s_reg)])
7274 SET_HARD_REG_BIT (reg_is_output_reload,
7276 new_spill_reg_store[REGNO (s_reg)] = next;
7280 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7285 if (rl->when_needed == RELOAD_OTHER)
7287 emit_insn (other_output_reload_insns[rl->opnum]);
7288 other_output_reload_insns[rl->opnum] = get_insns ();
7291 output_reload_insns[rl->opnum] = get_insns ();
7293 if (flag_non_call_exceptions)
7294 copy_eh_notes (insn, get_insns ());
7299 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7300 and has the number J. */
7302 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7304 rtx insn = chain->insn;
7305 rtx old = (rl->in && MEM_P (rl->in)
7306 ? rl->in_reg : rl->in);
7307 rtx reg_rtx = rl->reg_rtx;
7311 enum machine_mode mode;
7313 /* Determine the mode to reload in.
7314 This is very tricky because we have three to choose from.
7315 There is the mode the insn operand wants (rl->inmode).
7316 There is the mode of the reload register RELOADREG.
7317 There is the intrinsic mode of the operand, which we could find
7318 by stripping some SUBREGs.
7319 It turns out that RELOADREG's mode is irrelevant:
7320 we can change that arbitrarily.
7322 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7323 then the reload reg may not support QImode moves, so use SImode.
7324 If foo is in memory due to spilling a pseudo reg, this is safe,
7325 because the QImode value is in the least significant part of a
7326 slot big enough for a SImode. If foo is some other sort of
7327 memory reference, then it is impossible to reload this case,
7328 so previous passes had better make sure this never happens.
7330 Then consider a one-word union which has SImode and one of its
7331 members is a float, being fetched as (SUBREG:SF union:SI).
7332 We must fetch that as SFmode because we could be loading into
7333 a float-only register. In this case OLD's mode is correct.
7335 Consider an immediate integer: it has VOIDmode. Here we need
7336 to get a mode from something else.
7338 In some cases, there is a fourth mode, the operand's
7339 containing mode. If the insn specifies a containing mode for
7340 this operand, it overrides all others.
7342 I am not sure whether the algorithm here is always right,
7343 but it does the right things in those cases. */
7345 mode = GET_MODE (old);
7346 if (mode == VOIDmode)
7349 /* We cannot use gen_lowpart_common since it can do the wrong thing
7350 when REG_RTX has a multi-word mode. Note that REG_RTX must
7351 always be a REG here. */
7352 if (GET_MODE (reg_rtx) != mode)
7353 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7355 reload_reg_rtx_for_input[j] = reg_rtx;
7358 /* AUTO_INC reloads need to be handled even if inherited. We got an
7359 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7360 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7361 && ! rtx_equal_p (reg_rtx, old)
7363 emit_input_reload_insns (chain, rld + j, old, j);
7365 /* When inheriting a wider reload, we have a MEM in rl->in,
7366 e.g. inheriting a SImode output reload for
7367 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7368 if (optimize && reload_inherited[j] && rl->in
7370 && MEM_P (rl->in_reg)
7371 && reload_spill_index[j] >= 0
7372 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7373 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7375 /* If we are reloading a register that was recently stored in with an
7376 output-reload, see if we can prove there was
7377 actually no need to store the old value in it. */
7380 && (reload_inherited[j] || reload_override_in[j])
7383 && spill_reg_store[REGNO (reg_rtx)] != 0
7385 /* There doesn't seem to be any reason to restrict this to pseudos
7386 and doing so loses in the case where we are copying from a
7387 register of the wrong class. */
7388 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7390 /* The insn might have already some references to stackslots
7391 replaced by MEMs, while reload_out_reg still names the
7393 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7394 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7395 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7398 /* Do output reloading for reload RL, which is for the insn described by
7399 CHAIN and has the number J.
7400 ??? At some point we need to support handling output reloads of
7401 JUMP_INSNs or insns that set cc0. */
7403 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7406 rtx insn = chain->insn;
7407 /* If this is an output reload that stores something that is
7408 not loaded in this same reload, see if we can eliminate a previous
7410 rtx pseudo = rl->out_reg;
7411 rtx reg_rtx = rl->reg_rtx;
7413 if (rl->out && reg_rtx)
7415 enum machine_mode mode;
7417 /* Determine the mode to reload in.
7418 See comments above (for input reloading). */
7419 mode = GET_MODE (rl->out);
7420 if (mode == VOIDmode)
7422 /* VOIDmode should never happen for an output. */
7423 if (asm_noperands (PATTERN (insn)) < 0)
7424 /* It's the compiler's fault. */
7425 fatal_insn ("VOIDmode on an output", insn);
7426 error_for_asm (insn, "output operand is constant in %<asm%>");
7427 /* Prevent crash--use something we know is valid. */
7429 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7431 if (GET_MODE (reg_rtx) != mode)
7432 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7434 reload_reg_rtx_for_output[j] = reg_rtx;
7439 && ! rtx_equal_p (rl->in_reg, pseudo)
7440 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7441 && reg_last_reload_reg[REGNO (pseudo)])
7443 int pseudo_no = REGNO (pseudo);
7444 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7446 /* We don't need to test full validity of last_regno for
7447 inherit here; we only want to know if the store actually
7448 matches the pseudo. */
7449 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7450 && reg_reloaded_contents[last_regno] == pseudo_no
7451 && spill_reg_store[last_regno]
7452 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7453 delete_output_reload (insn, j, last_regno, reg_rtx);
7459 || rtx_equal_p (old, reg_rtx))
7462 /* An output operand that dies right away does need a reload,
7463 but need not be copied from it. Show the new location in the
7465 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7466 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7468 XEXP (note, 0) = reg_rtx;
7471 /* Likewise for a SUBREG of an operand that dies. */
7472 else if (GET_CODE (old) == SUBREG
7473 && REG_P (SUBREG_REG (old))
7474 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7477 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7480 else if (GET_CODE (old) == SCRATCH)
7481 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7482 but we don't want to make an output reload. */
7485 /* If is a JUMP_INSN, we can't support output reloads yet. */
7486 gcc_assert (NONJUMP_INSN_P (insn));
7488 emit_output_reload_insns (chain, rld + j, j);
7491 /* A reload copies values of MODE from register SRC to register DEST.
7492 Return true if it can be treated for inheritance purposes like a
7493 group of reloads, each one reloading a single hard register. The
7494 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7495 occupy the same number of hard registers. */
7498 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7499 int src ATTRIBUTE_UNUSED,
7500 enum machine_mode mode ATTRIBUTE_UNUSED)
7502 #ifdef CANNOT_CHANGE_MODE_CLASS
7503 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7504 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7510 /* Output insns to reload values in and out of the chosen reload regs. */
7513 emit_reload_insns (struct insn_chain *chain)
7515 rtx insn = chain->insn;
7519 CLEAR_HARD_REG_SET (reg_reloaded_died);
7521 for (j = 0; j < reload_n_operands; j++)
7522 input_reload_insns[j] = input_address_reload_insns[j]
7523 = inpaddr_address_reload_insns[j]
7524 = output_reload_insns[j] = output_address_reload_insns[j]
7525 = outaddr_address_reload_insns[j]
7526 = other_output_reload_insns[j] = 0;
7527 other_input_address_reload_insns = 0;
7528 other_input_reload_insns = 0;
7529 operand_reload_insns = 0;
7530 other_operand_reload_insns = 0;
7532 /* Dump reloads into the dump file. */
7535 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7536 debug_reload_to_stream (dump_file);
7539 /* Now output the instructions to copy the data into and out of the
7540 reload registers. Do these in the order that the reloads were reported,
7541 since reloads of base and index registers precede reloads of operands
7542 and the operands may need the base and index registers reloaded. */
7544 for (j = 0; j < n_reloads; j++)
7546 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7550 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7551 new_spill_reg_store[i] = 0;
7554 do_input_reload (chain, rld + j, j);
7555 do_output_reload (chain, rld + j, j);
7558 /* Now write all the insns we made for reloads in the order expected by
7559 the allocation functions. Prior to the insn being reloaded, we write
7560 the following reloads:
7562 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7564 RELOAD_OTHER reloads.
7566 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7567 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7568 RELOAD_FOR_INPUT reload for the operand.
7570 RELOAD_FOR_OPADDR_ADDRS reloads.
7572 RELOAD_FOR_OPERAND_ADDRESS reloads.
7574 After the insn being reloaded, we write the following:
7576 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7577 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7578 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7579 reloads for the operand. The RELOAD_OTHER output reloads are
7580 output in descending order by reload number. */
7582 emit_insn_before (other_input_address_reload_insns, insn);
7583 emit_insn_before (other_input_reload_insns, insn);
7585 for (j = 0; j < reload_n_operands; j++)
7587 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7588 emit_insn_before (input_address_reload_insns[j], insn);
7589 emit_insn_before (input_reload_insns[j], insn);
7592 emit_insn_before (other_operand_reload_insns, insn);
7593 emit_insn_before (operand_reload_insns, insn);
7595 for (j = 0; j < reload_n_operands; j++)
7597 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7598 x = emit_insn_after (output_address_reload_insns[j], x);
7599 x = emit_insn_after (output_reload_insns[j], x);
7600 emit_insn_after (other_output_reload_insns[j], x);
7603 /* For all the spill regs newly reloaded in this instruction,
7604 record what they were reloaded from, so subsequent instructions
7605 can inherit the reloads.
7607 Update spill_reg_store for the reloads of this insn.
7608 Copy the elements that were updated in the loop above. */
7610 for (j = 0; j < n_reloads; j++)
7612 int r = reload_order[j];
7613 int i = reload_spill_index[r];
7615 /* If this is a non-inherited input reload from a pseudo, we must
7616 clear any memory of a previous store to the same pseudo. Only do
7617 something if there will not be an output reload for the pseudo
7619 if (rld[r].in_reg != 0
7620 && ! (reload_inherited[r] || reload_override_in[r]))
7622 rtx reg = rld[r].in_reg;
7624 if (GET_CODE (reg) == SUBREG)
7625 reg = SUBREG_REG (reg);
7628 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7629 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7631 int nregno = REGNO (reg);
7633 if (reg_last_reload_reg[nregno])
7635 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7637 if (reg_reloaded_contents[last_regno] == nregno)
7638 spill_reg_store[last_regno] = 0;
7643 /* I is nonneg if this reload used a register.
7644 If rld[r].reg_rtx is 0, this is an optional reload
7645 that we opted to ignore. */
7647 if (i >= 0 && rld[r].reg_rtx != 0)
7649 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7652 /* For a multi register reload, we need to check if all or part
7653 of the value lives to the end. */
7654 for (k = 0; k < nr; k++)
7655 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7656 rld[r].when_needed))
7657 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7659 /* Maybe the spill reg contains a copy of reload_out. */
7661 && (REG_P (rld[r].out)
7665 || REG_P (rld[r].out_reg)))
7668 enum machine_mode mode;
7671 reg = reload_reg_rtx_for_output[r];
7672 mode = GET_MODE (reg);
7673 regno = REGNO (reg);
7674 nregs = hard_regno_nregs[regno][mode];
7675 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7676 rld[r].when_needed))
7678 rtx out = (REG_P (rld[r].out)
7682 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7683 int out_regno = REGNO (out);
7684 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7685 : hard_regno_nregs[out_regno][mode]);
7688 spill_reg_store[regno] = new_spill_reg_store[regno];
7689 spill_reg_stored_to[regno] = out;
7690 reg_last_reload_reg[out_regno] = reg;
7692 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7693 && nregs == out_nregs
7694 && inherit_piecemeal_p (out_regno, regno, mode));
7696 /* If OUT_REGNO is a hard register, it may occupy more than
7697 one register. If it does, say what is in the
7698 rest of the registers assuming that both registers
7699 agree on how many words the object takes. If not,
7700 invalidate the subsequent registers. */
7702 if (HARD_REGISTER_NUM_P (out_regno))
7703 for (k = 1; k < out_nregs; k++)
7704 reg_last_reload_reg[out_regno + k]
7705 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7707 /* Now do the inverse operation. */
7708 for (k = 0; k < nregs; k++)
7710 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7711 reg_reloaded_contents[regno + k]
7712 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7715 reg_reloaded_insn[regno + k] = insn;
7716 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7717 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7718 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7721 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7726 /* Maybe the spill reg contains a copy of reload_in. Only do
7727 something if there will not be an output reload for
7728 the register being reloaded. */
7729 else if (rld[r].out_reg == 0
7731 && ((REG_P (rld[r].in)
7732 && !HARD_REGISTER_P (rld[r].in)
7733 && !REGNO_REG_SET_P (®_has_output_reload,
7735 || (REG_P (rld[r].in_reg)
7736 && !REGNO_REG_SET_P (®_has_output_reload,
7737 REGNO (rld[r].in_reg))))
7738 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7741 enum machine_mode mode;
7744 reg = reload_reg_rtx_for_input[r];
7745 mode = GET_MODE (reg);
7746 regno = REGNO (reg);
7747 nregs = hard_regno_nregs[regno][mode];
7748 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7749 rld[r].when_needed))
7756 if (REG_P (rld[r].in)
7757 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7759 else if (REG_P (rld[r].in_reg))
7762 in = XEXP (rld[r].in_reg, 0);
7763 in_regno = REGNO (in);
7765 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7766 : hard_regno_nregs[in_regno][mode]);
7768 reg_last_reload_reg[in_regno] = reg;
7770 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
7771 && nregs == in_nregs
7772 && inherit_piecemeal_p (regno, in_regno, mode));
7774 if (HARD_REGISTER_NUM_P (in_regno))
7775 for (k = 1; k < in_nregs; k++)
7776 reg_last_reload_reg[in_regno + k]
7777 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7779 /* Unless we inherited this reload, show we haven't
7780 recently done a store.
7781 Previous stores of inherited auto_inc expressions
7782 also have to be discarded. */
7783 if (! reload_inherited[r]
7784 || (rld[r].out && ! rld[r].out_reg))
7785 spill_reg_store[regno] = 0;
7787 for (k = 0; k < nregs; k++)
7789 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7790 reg_reloaded_contents[regno + k]
7791 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
7794 reg_reloaded_insn[regno + k] = insn;
7795 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7796 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7797 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7800 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7807 /* The following if-statement was #if 0'd in 1.34 (or before...).
7808 It's reenabled in 1.35 because supposedly nothing else
7809 deals with this problem. */
7811 /* If a register gets output-reloaded from a non-spill register,
7812 that invalidates any previous reloaded copy of it.
7813 But forget_old_reloads_1 won't get to see it, because
7814 it thinks only about the original insn. So invalidate it here.
7815 Also do the same thing for RELOAD_OTHER constraints where the
7816 output is discarded. */
7818 && ((rld[r].out != 0
7819 && (REG_P (rld[r].out)
7820 || (MEM_P (rld[r].out)
7821 && REG_P (rld[r].out_reg))))
7822 || (rld[r].out == 0 && rld[r].out_reg
7823 && REG_P (rld[r].out_reg))))
7825 rtx out = ((rld[r].out && REG_P (rld[r].out))
7826 ? rld[r].out : rld[r].out_reg);
7827 int out_regno = REGNO (out);
7828 enum machine_mode mode = GET_MODE (out);
7830 /* REG_RTX is now set or clobbered by the main instruction.
7831 As the comment above explains, forget_old_reloads_1 only
7832 sees the original instruction, and there is no guarantee
7833 that the original instruction also clobbered REG_RTX.
7834 For example, if find_reloads sees that the input side of
7835 a matched operand pair dies in this instruction, it may
7836 use the input register as the reload register.
7838 Calling forget_old_reloads_1 is a waste of effort if
7839 REG_RTX is also the output register.
7841 If we know that REG_RTX holds the value of a pseudo
7842 register, the code after the call will record that fact. */
7843 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
7844 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
7846 if (!HARD_REGISTER_NUM_P (out_regno))
7848 rtx src_reg, store_insn = NULL_RTX;
7850 reg_last_reload_reg[out_regno] = 0;
7852 /* If we can find a hard register that is stored, record
7853 the storing insn so that we may delete this insn with
7854 delete_output_reload. */
7855 src_reg = reload_reg_rtx_for_output[r];
7857 /* If this is an optional reload, try to find the source reg
7858 from an input reload. */
7861 rtx set = single_set (insn);
7862 if (set && SET_DEST (set) == rld[r].out)
7866 src_reg = SET_SRC (set);
7868 for (k = 0; k < n_reloads; k++)
7870 if (rld[k].in == src_reg)
7872 src_reg = reload_reg_rtx_for_input[k];
7879 store_insn = new_spill_reg_store[REGNO (src_reg)];
7880 if (src_reg && REG_P (src_reg)
7881 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7883 int src_regno, src_nregs, k;
7886 gcc_assert (GET_MODE (src_reg) == mode);
7887 src_regno = REGNO (src_reg);
7888 src_nregs = hard_regno_nregs[src_regno][mode];
7889 /* The place where to find a death note varies with
7890 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7891 necessarily checked exactly in the code that moves
7892 notes, so just check both locations. */
7893 note = find_regno_note (insn, REG_DEAD, src_regno);
7894 if (! note && store_insn)
7895 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7896 for (k = 0; k < src_nregs; k++)
7898 spill_reg_store[src_regno + k] = store_insn;
7899 spill_reg_stored_to[src_regno + k] = out;
7900 reg_reloaded_contents[src_regno + k] = out_regno;
7901 reg_reloaded_insn[src_regno + k] = store_insn;
7902 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
7903 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
7904 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
7906 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7909 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7911 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
7913 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7915 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7917 reg_last_reload_reg[out_regno] = src_reg;
7918 /* We have to set reg_has_output_reload here, or else
7919 forget_old_reloads_1 will clear reg_last_reload_reg
7921 SET_REGNO_REG_SET (®_has_output_reload,
7927 int k, out_nregs = hard_regno_nregs[out_regno][mode];
7929 for (k = 0; k < out_nregs; k++)
7930 reg_last_reload_reg[out_regno + k] = 0;
7934 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7937 /* Go through the motions to emit INSN and test if it is strictly valid.
7938 Return the emitted insn if valid, else return NULL. */
7941 emit_insn_if_valid_for_reload (rtx insn)
7943 rtx last = get_last_insn ();
7946 insn = emit_insn (insn);
7947 code = recog_memoized (insn);
7951 extract_insn (insn);
7952 /* We want constrain operands to treat this insn strictly in its
7953 validity determination, i.e., the way it would after reload has
7955 if (constrain_operands (1))
7959 delete_insns_since (last);
7963 /* Emit code to perform a reload from IN (which may be a reload register) to
7964 OUT (which may also be a reload register). IN or OUT is from operand
7965 OPNUM with reload type TYPE.
7967 Returns first insn emitted. */
7970 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7972 rtx last = get_last_insn ();
7975 /* If IN is a paradoxical SUBREG, remove it and try to put the
7976 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7977 if (GET_CODE (in) == SUBREG
7978 && (GET_MODE_SIZE (GET_MODE (in))
7979 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7980 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7981 in = SUBREG_REG (in), out = tem;
7982 else if (GET_CODE (out) == SUBREG
7983 && (GET_MODE_SIZE (GET_MODE (out))
7984 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7985 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7986 out = SUBREG_REG (out), in = tem;
7988 /* How to do this reload can get quite tricky. Normally, we are being
7989 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7990 register that didn't get a hard register. In that case we can just
7991 call emit_move_insn.
7993 We can also be asked to reload a PLUS that adds a register or a MEM to
7994 another register, constant or MEM. This can occur during frame pointer
7995 elimination and while reloading addresses. This case is handled by
7996 trying to emit a single insn to perform the add. If it is not valid,
7997 we use a two insn sequence.
7999 Or we can be asked to reload an unary operand that was a fragment of
8000 an addressing mode, into a register. If it isn't recognized as-is,
8001 we try making the unop operand and the reload-register the same:
8002 (set reg:X (unop:X expr:Y))
8003 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8005 Finally, we could be called to handle an 'o' constraint by putting
8006 an address into a register. In that case, we first try to do this
8007 with a named pattern of "reload_load_address". If no such pattern
8008 exists, we just emit a SET insn and hope for the best (it will normally
8009 be valid on machines that use 'o').
8011 This entire process is made complex because reload will never
8012 process the insns we generate here and so we must ensure that
8013 they will fit their constraints and also by the fact that parts of
8014 IN might be being reloaded separately and replaced with spill registers.
8015 Because of this, we are, in some sense, just guessing the right approach
8016 here. The one listed above seems to work.
8018 ??? At some point, this whole thing needs to be rethought. */
8020 if (GET_CODE (in) == PLUS
8021 && (REG_P (XEXP (in, 0))
8022 || GET_CODE (XEXP (in, 0)) == SUBREG
8023 || MEM_P (XEXP (in, 0)))
8024 && (REG_P (XEXP (in, 1))
8025 || GET_CODE (XEXP (in, 1)) == SUBREG
8026 || CONSTANT_P (XEXP (in, 1))
8027 || MEM_P (XEXP (in, 1))))
8029 /* We need to compute the sum of a register or a MEM and another
8030 register, constant, or MEM, and put it into the reload
8031 register. The best possible way of doing this is if the machine
8032 has a three-operand ADD insn that accepts the required operands.
8034 The simplest approach is to try to generate such an insn and see if it
8035 is recognized and matches its constraints. If so, it can be used.
8037 It might be better not to actually emit the insn unless it is valid,
8038 but we need to pass the insn as an operand to `recog' and
8039 `extract_insn' and it is simpler to emit and then delete the insn if
8040 not valid than to dummy things up. */
8042 rtx op0, op1, tem, insn;
8045 op0 = find_replacement (&XEXP (in, 0));
8046 op1 = find_replacement (&XEXP (in, 1));
8048 /* Since constraint checking is strict, commutativity won't be
8049 checked, so we need to do that here to avoid spurious failure
8050 if the add instruction is two-address and the second operand
8051 of the add is the same as the reload reg, which is frequently
8052 the case. If the insn would be A = B + A, rearrange it so
8053 it will be A = A + B as constrain_operands expects. */
8055 if (REG_P (XEXP (in, 1))
8056 && REGNO (out) == REGNO (XEXP (in, 1)))
8057 tem = op0, op0 = op1, op1 = tem;
8059 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8060 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8062 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8066 /* If that failed, we must use a conservative two-insn sequence.
8068 Use a move to copy one operand into the reload register. Prefer
8069 to reload a constant, MEM or pseudo since the move patterns can
8070 handle an arbitrary operand. If OP1 is not a constant, MEM or
8071 pseudo and OP1 is not a valid operand for an add instruction, then
8074 After reloading one of the operands into the reload register, add
8075 the reload register to the output register.
8077 If there is another way to do this for a specific machine, a
8078 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8081 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
8083 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8085 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8086 || (code != CODE_FOR_nothing
8087 && ! ((*insn_data[code].operand[2].predicate)
8088 (op1, insn_data[code].operand[2].mode))))
8089 tem = op0, op0 = op1, op1 = tem;
8091 gen_reload (out, op0, opnum, type);
8093 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8094 This fixes a problem on the 32K where the stack pointer cannot
8095 be used as an operand of an add insn. */
8097 if (rtx_equal_p (op0, op1))
8100 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8103 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8104 set_unique_reg_note (insn, REG_EQUIV, in);
8108 /* If that failed, copy the address register to the reload register.
8109 Then add the constant to the reload register. */
8111 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8112 gen_reload (out, op1, opnum, type);
8113 insn = emit_insn (gen_add2_insn (out, op0));
8114 set_unique_reg_note (insn, REG_EQUIV, in);
8117 #ifdef SECONDARY_MEMORY_NEEDED
8118 /* If we need a memory location to do the move, do it that way. */
8119 else if ((REG_P (in)
8120 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8121 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8123 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8124 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8125 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8126 REGNO_REG_CLASS (reg_or_subregno (out)),
8129 /* Get the memory to use and rewrite both registers to its mode. */
8130 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8132 if (GET_MODE (loc) != GET_MODE (out))
8133 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8135 if (GET_MODE (loc) != GET_MODE (in))
8136 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8138 gen_reload (loc, in, opnum, type);
8139 gen_reload (out, loc, opnum, type);
8142 else if (REG_P (out) && UNARY_P (in))
8149 op1 = find_replacement (&XEXP (in, 0));
8150 if (op1 != XEXP (in, 0))
8151 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8153 /* First, try a plain SET. */
8154 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8158 /* If that failed, move the inner operand to the reload
8159 register, and try the same unop with the inner expression
8160 replaced with the reload register. */
8162 if (GET_MODE (op1) != GET_MODE (out))
8163 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8167 gen_reload (out_moded, op1, opnum, type);
8170 = gen_rtx_SET (VOIDmode, out,
8171 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8173 insn = emit_insn_if_valid_for_reload (insn);
8176 set_unique_reg_note (insn, REG_EQUIV, in);
8180 fatal_insn ("Failure trying to reload:", set);
8182 /* If IN is a simple operand, use gen_move_insn. */
8183 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8185 tem = emit_insn (gen_move_insn (out, in));
8186 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8187 mark_jump_label (in, tem, 0);
8190 #ifdef HAVE_reload_load_address
8191 else if (HAVE_reload_load_address)
8192 emit_insn (gen_reload_load_address (out, in));
8195 /* Otherwise, just write (set OUT IN) and hope for the best. */
8197 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8199 /* Return the first insn emitted.
8200 We can not just return get_last_insn, because there may have
8201 been multiple instructions emitted. Also note that gen_move_insn may
8202 emit more than one insn itself, so we can not assume that there is one
8203 insn emitted per emit_insn_before call. */
8205 return last ? NEXT_INSN (last) : get_insns ();
8208 /* Delete a previously made output-reload whose result we now believe
8209 is not needed. First we double-check.
8211 INSN is the insn now being processed.
8212 LAST_RELOAD_REG is the hard register number for which we want to delete
8213 the last output reload.
8214 J is the reload-number that originally used REG. The caller has made
8215 certain that reload J doesn't use REG any longer for input.
8216 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8219 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8221 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8222 rtx reg = spill_reg_stored_to[last_reload_reg];
8225 int n_inherited = 0;
8229 /* It is possible that this reload has been only used to set another reload
8230 we eliminated earlier and thus deleted this instruction too. */
8231 if (INSN_DELETED_P (output_reload_insn))
8234 /* Get the raw pseudo-register referred to. */
8236 while (GET_CODE (reg) == SUBREG)
8237 reg = SUBREG_REG (reg);
8238 substed = reg_equiv_memory_loc[REGNO (reg)];
8240 /* This is unsafe if the operand occurs more often in the current
8241 insn than it is inherited. */
8242 for (k = n_reloads - 1; k >= 0; k--)
8244 rtx reg2 = rld[k].in;
8247 if (MEM_P (reg2) || reload_override_in[k])
8248 reg2 = rld[k].in_reg;
8250 if (rld[k].out && ! rld[k].out_reg)
8251 reg2 = XEXP (rld[k].in_reg, 0);
8253 while (GET_CODE (reg2) == SUBREG)
8254 reg2 = SUBREG_REG (reg2);
8255 if (rtx_equal_p (reg2, reg))
8257 if (reload_inherited[k] || reload_override_in[k] || k == j)
8263 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8264 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8265 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8268 n_occurrences += count_occurrences (PATTERN (insn),
8269 eliminate_regs (substed, 0,
8271 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8273 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8274 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8276 if (n_occurrences > n_inherited)
8279 /* If the pseudo-reg we are reloading is no longer referenced
8280 anywhere between the store into it and here,
8281 and we're within the same basic block, then the value can only
8282 pass through the reload reg and end up here.
8283 Otherwise, give up--return. */
8284 for (i1 = NEXT_INSN (output_reload_insn);
8285 i1 != insn; i1 = NEXT_INSN (i1))
8287 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8289 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8290 && reg_mentioned_p (reg, PATTERN (i1)))
8292 /* If this is USE in front of INSN, we only have to check that
8293 there are no more references than accounted for by inheritance. */
8294 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8296 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8297 i1 = NEXT_INSN (i1);
8299 if (n_occurrences <= n_inherited && i1 == insn)
8305 /* We will be deleting the insn. Remove the spill reg information. */
8306 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8308 spill_reg_store[last_reload_reg + k] = 0;
8309 spill_reg_stored_to[last_reload_reg + k] = 0;
8312 /* The caller has already checked that REG dies or is set in INSN.
8313 It has also checked that we are optimizing, and thus some
8314 inaccuracies in the debugging information are acceptable.
8315 So we could just delete output_reload_insn. But in some cases
8316 we can improve the debugging information without sacrificing
8317 optimization - maybe even improving the code: See if the pseudo
8318 reg has been completely replaced with reload regs. If so, delete
8319 the store insn and forget we had a stack slot for the pseudo. */
8320 if (rld[j].out != rld[j].in
8321 && REG_N_DEATHS (REGNO (reg)) == 1
8322 && REG_N_SETS (REGNO (reg)) == 1
8323 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8324 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8328 /* We know that it was used only between here and the beginning of
8329 the current basic block. (We also know that the last use before
8330 INSN was the output reload we are thinking of deleting, but never
8331 mind that.) Search that range; see if any ref remains. */
8332 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8334 rtx set = single_set (i2);
8336 /* Uses which just store in the pseudo don't count,
8337 since if they are the only uses, they are dead. */
8338 if (set != 0 && SET_DEST (set) == reg)
8343 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8344 && reg_mentioned_p (reg, PATTERN (i2)))
8346 /* Some other ref remains; just delete the output reload we
8348 delete_address_reloads (output_reload_insn, insn);
8349 delete_insn (output_reload_insn);
8354 /* Delete the now-dead stores into this pseudo. Note that this
8355 loop also takes care of deleting output_reload_insn. */
8356 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8358 rtx set = single_set (i2);
8360 if (set != 0 && SET_DEST (set) == reg)
8362 delete_address_reloads (i2, insn);
8370 /* For the debugging info, say the pseudo lives in this reload reg. */
8371 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8372 if (ira_conflicts_p)
8373 /* Inform IRA about the change. */
8374 ira_mark_allocation_change (REGNO (reg));
8375 alter_reg (REGNO (reg), -1, false);
8379 delete_address_reloads (output_reload_insn, insn);
8380 delete_insn (output_reload_insn);
8384 /* We are going to delete DEAD_INSN. Recursively delete loads of
8385 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8386 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8388 delete_address_reloads (rtx dead_insn, rtx current_insn)
8390 rtx set = single_set (dead_insn);
8391 rtx set2, dst, prev, next;
8394 rtx dst = SET_DEST (set);
8396 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8398 /* If we deleted the store from a reloaded post_{in,de}c expression,
8399 we can delete the matching adds. */
8400 prev = PREV_INSN (dead_insn);
8401 next = NEXT_INSN (dead_insn);
8402 if (! prev || ! next)
8404 set = single_set (next);
8405 set2 = single_set (prev);
8407 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8408 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8409 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8411 dst = SET_DEST (set);
8412 if (! rtx_equal_p (dst, SET_DEST (set2))
8413 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8414 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8415 || (INTVAL (XEXP (SET_SRC (set), 1))
8416 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8418 delete_related_insns (prev);
8419 delete_related_insns (next);
8422 /* Subfunction of delete_address_reloads: process registers found in X. */
8424 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8426 rtx prev, set, dst, i2;
8428 enum rtx_code code = GET_CODE (x);
8432 const char *fmt = GET_RTX_FORMAT (code);
8433 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8436 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8437 else if (fmt[i] == 'E')
8439 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8440 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8447 if (spill_reg_order[REGNO (x)] < 0)
8450 /* Scan backwards for the insn that sets x. This might be a way back due
8452 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8454 code = GET_CODE (prev);
8455 if (code == CODE_LABEL || code == JUMP_INSN)
8459 if (reg_set_p (x, PATTERN (prev)))
8461 if (reg_referenced_p (x, PATTERN (prev)))
8464 if (! prev || INSN_UID (prev) < reload_first_uid)
8466 /* Check that PREV only sets the reload register. */
8467 set = single_set (prev);
8470 dst = SET_DEST (set);
8472 || ! rtx_equal_p (dst, x))
8474 if (! reg_set_p (dst, PATTERN (dead_insn)))
8476 /* Check if DST was used in a later insn -
8477 it might have been inherited. */
8478 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8484 if (reg_referenced_p (dst, PATTERN (i2)))
8486 /* If there is a reference to the register in the current insn,
8487 it might be loaded in a non-inherited reload. If no other
8488 reload uses it, that means the register is set before
8490 if (i2 == current_insn)
8492 for (j = n_reloads - 1; j >= 0; j--)
8493 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8494 || reload_override_in[j] == dst)
8496 for (j = n_reloads - 1; j >= 0; j--)
8497 if (rld[j].in && rld[j].reg_rtx == dst)
8506 /* If DST is still live at CURRENT_INSN, check if it is used for
8507 any reload. Note that even if CURRENT_INSN sets DST, we still
8508 have to check the reloads. */
8509 if (i2 == current_insn)
8511 for (j = n_reloads - 1; j >= 0; j--)
8512 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8513 || reload_override_in[j] == dst)
8515 /* ??? We can't finish the loop here, because dst might be
8516 allocated to a pseudo in this block if no reload in this
8517 block needs any of the classes containing DST - see
8518 spill_hard_reg. There is no easy way to tell this, so we
8519 have to scan till the end of the basic block. */
8521 if (reg_set_p (dst, PATTERN (i2)))
8525 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8526 reg_reloaded_contents[REGNO (dst)] = -1;
8530 /* Output reload-insns to reload VALUE into RELOADREG.
8531 VALUE is an autoincrement or autodecrement RTX whose operand
8532 is a register or memory location;
8533 so reloading involves incrementing that location.
8534 IN is either identical to VALUE, or some cheaper place to reload from.
8536 INC_AMOUNT is the number to increment or decrement by (always positive).
8537 This cannot be deduced from VALUE.
8539 Return the instruction that stores into RELOADREG. */
8542 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8544 /* REG or MEM to be copied and incremented. */
8545 rtx incloc = find_replacement (&XEXP (value, 0));
8546 /* Nonzero if increment after copying. */
8547 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8548 || GET_CODE (value) == POST_MODIFY);
8554 rtx real_in = in == value ? incloc : in;
8556 /* No hard register is equivalent to this register after
8557 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8558 we could inc/dec that register as well (maybe even using it for
8559 the source), but I'm not sure it's worth worrying about. */
8561 reg_last_reload_reg[REGNO (incloc)] = 0;
8563 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8565 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8566 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8570 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8571 inc_amount = -inc_amount;
8573 inc = GEN_INT (inc_amount);
8576 /* If this is post-increment, first copy the location to the reload reg. */
8577 if (post && real_in != reloadreg)
8578 emit_insn (gen_move_insn (reloadreg, real_in));
8582 /* See if we can directly increment INCLOC. Use a method similar to
8583 that in gen_reload. */
8585 last = get_last_insn ();
8586 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8587 gen_rtx_PLUS (GET_MODE (incloc),
8590 code = recog_memoized (add_insn);
8593 extract_insn (add_insn);
8594 if (constrain_operands (1))
8596 /* If this is a pre-increment and we have incremented the value
8597 where it lives, copy the incremented value to RELOADREG to
8598 be used as an address. */
8601 emit_insn (gen_move_insn (reloadreg, incloc));
8606 delete_insns_since (last);
8609 /* If couldn't do the increment directly, must increment in RELOADREG.
8610 The way we do this depends on whether this is pre- or post-increment.
8611 For pre-increment, copy INCLOC to the reload register, increment it
8612 there, then save back. */
8616 if (in != reloadreg)
8617 emit_insn (gen_move_insn (reloadreg, real_in));
8618 emit_insn (gen_add2_insn (reloadreg, inc));
8619 store = emit_insn (gen_move_insn (incloc, reloadreg));
8624 Because this might be a jump insn or a compare, and because RELOADREG
8625 may not be available after the insn in an input reload, we must do
8626 the incrementation before the insn being reloaded for.
8628 We have already copied IN to RELOADREG. Increment the copy in
8629 RELOADREG, save that back, then decrement RELOADREG so it has
8630 the original value. */
8632 emit_insn (gen_add2_insn (reloadreg, inc));
8633 store = emit_insn (gen_move_insn (incloc, reloadreg));
8634 if (GET_CODE (inc) == CONST_INT)
8635 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8637 emit_insn (gen_sub2_insn (reloadreg, inc));
8645 add_auto_inc_notes (rtx insn, rtx x)
8647 enum rtx_code code = GET_CODE (x);
8651 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8653 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
8657 /* Scan all the operand sub-expressions. */
8658 fmt = GET_RTX_FORMAT (code);
8659 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8662 add_auto_inc_notes (insn, XEXP (x, i));
8663 else if (fmt[i] == 'E')
8664 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8665 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8670 /* Copy EH notes from an insn to its reloads. */
8672 copy_eh_notes (rtx insn, rtx x)
8674 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8677 for (; x != 0; x = NEXT_INSN (x))
8679 if (may_trap_p (PATTERN (x)))
8680 add_reg_note (x, REG_EH_REGION, XEXP (eh_note, 0));
8685 /* This is used by reload pass, that does emit some instructions after
8686 abnormal calls moving basic block end, but in fact it wants to emit
8687 them on the edge. Looks for abnormal call edges, find backward the
8688 proper call and fix the damage.
8690 Similar handle instructions throwing exceptions internally. */
8692 fixup_abnormal_edges (void)
8694 bool inserted = false;
8702 /* Look for cases we are interested in - calls or instructions causing
8704 FOR_EACH_EDGE (e, ei, bb->succs)
8706 if (e->flags & EDGE_ABNORMAL_CALL)
8708 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8709 == (EDGE_ABNORMAL | EDGE_EH))
8712 if (e && !CALL_P (BB_END (bb))
8713 && !can_throw_internal (BB_END (bb)))
8717 /* Get past the new insns generated. Allow notes, as the insns
8718 may be already deleted. */
8720 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8721 && !can_throw_internal (insn)
8722 && insn != BB_HEAD (bb))
8723 insn = PREV_INSN (insn);
8725 if (CALL_P (insn) || can_throw_internal (insn))
8729 stop = NEXT_INSN (BB_END (bb));
8731 insn = NEXT_INSN (insn);
8733 FOR_EACH_EDGE (e, ei, bb->succs)
8734 if (e->flags & EDGE_FALLTHRU)
8737 while (insn && insn != stop)
8739 next = NEXT_INSN (insn);
8744 /* Sometimes there's still the return value USE.
8745 If it's placed after a trapping call (i.e. that
8746 call is the last insn anyway), we have no fallthru
8747 edge. Simply delete this use and don't try to insert
8748 on the non-existent edge. */
8749 if (GET_CODE (PATTERN (insn)) != USE)
8751 /* We're not deleting it, we're moving it. */
8752 INSN_DELETED_P (insn) = 0;
8753 PREV_INSN (insn) = NULL_RTX;
8754 NEXT_INSN (insn) = NULL_RTX;
8756 insert_insn_on_edge (insn, e);
8760 else if (!BARRIER_P (insn))
8761 set_block_for_insn (insn, NULL);
8766 /* It may be that we don't find any such trapping insn. In this
8767 case we discovered quite late that the insn that had been
8768 marked as can_throw_internal in fact couldn't trap at all.
8769 So we should in fact delete the EH edges out of the block. */
8771 purge_dead_edges (bb);
8775 /* We've possibly turned single trapping insn into multiple ones. */
8776 if (flag_non_call_exceptions)
8779 blocks = sbitmap_alloc (last_basic_block);
8780 sbitmap_ones (blocks);
8781 find_many_sub_basic_blocks (blocks);
8782 sbitmap_free (blocks);
8786 commit_edge_insertions ();
8788 #ifdef ENABLE_CHECKING
8789 /* Verify that we didn't turn one trapping insn into many, and that
8790 we found and corrected all of the problems wrt fixups on the
8792 verify_flow_info ();
tuxillo's projects / dragonfly.git / blob