2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
29 #include <drm/drm_crtc.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/drm_edid.h>
32 #include "intel_drv.h"
33 #include <drm/i915_drm.h>
35 #include <linux/err.h>
37 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
41 * @intel_dp: DP struct
43 * If a CPU or PCH DP output is attached to an eDP panel, this function
44 * will return true, and false otherwise.
46 static bool is_edp(struct intel_dp *intel_dp)
48 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
50 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
54 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
55 * @intel_dp: DP struct
57 * Returns true if the given DP struct corresponds to a PCH DP port attached
58 * to an eDP panel, false otherwise. Helpful for determining whether we
59 * may need FDI resources for a given DP output or not.
61 static bool is_pch_edp(struct intel_dp *intel_dp)
63 return intel_dp->is_pch_edp;
67 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
68 * @intel_dp: DP struct
70 * Returns true if the given DP struct corresponds to a CPU eDP port.
72 static bool is_cpu_edp(struct intel_dp *intel_dp)
74 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
79 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
81 return intel_dig_port->base.base.dev;
84 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
86 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
90 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
91 * @encoder: DRM encoder
93 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
98 struct intel_dp *intel_dp;
103 intel_dp = enc_to_intel_dp(encoder);
105 return is_pch_edp(intel_dp);
108 static void intel_dp_link_down(struct intel_dp *intel_dp);
111 intel_edp_link_config(struct intel_encoder *intel_encoder,
112 int *lane_num, int *link_bw)
114 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
116 *lane_num = intel_dp->lane_count;
117 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
121 intel_edp_target_clock(struct intel_encoder *intel_encoder,
122 struct drm_display_mode *mode)
124 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
125 struct intel_connector *intel_connector = intel_dp->attached_connector;
127 if (intel_connector->panel.fixed_mode)
128 return intel_connector->panel.fixed_mode->clock;
134 intel_dp_max_link_bw(struct intel_dp *intel_dp)
136 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
138 switch (max_link_bw) {
139 case DP_LINK_BW_1_62:
143 max_link_bw = DP_LINK_BW_1_62;
150 intel_dp_link_clock(uint8_t link_bw)
152 if (link_bw == DP_LINK_BW_2_7)
159 * The units on the numbers in the next two are... bizarre. Examples will
160 * make it clearer; this one parallels an example in the eDP spec.
162 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
164 * 270000 * 1 * 8 / 10 == 216000
166 * The actual data capacity of that configuration is 2.16Gbit/s, so the
167 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
168 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
169 * 119000. At 18bpp that's 2142000 kilobits per second.
171 * Thus the strange-looking division by 10 in intel_dp_link_required, to
172 * get the result in decakilobits instead of kilobits.
176 intel_dp_link_required(int pixel_clock, int bpp)
178 return (pixel_clock * bpp + 9) / 10;
182 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
184 return (max_link_clock * max_lanes * 8) / 10;
188 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
189 struct drm_display_mode *mode,
192 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
193 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
194 int max_rate, mode_rate;
196 mode_rate = intel_dp_link_required(mode->clock, 24);
197 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
199 if (mode_rate > max_rate) {
200 mode_rate = intel_dp_link_required(mode->clock, 18);
201 if (mode_rate > max_rate)
206 |= INTEL_MODE_DP_FORCE_6BPC;
215 intel_dp_mode_valid(struct drm_connector *connector,
216 struct drm_display_mode *mode)
218 struct intel_dp *intel_dp = intel_attached_dp(connector);
219 struct intel_connector *intel_connector = to_intel_connector(connector);
220 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
222 if (is_edp(intel_dp) && fixed_mode) {
223 if (mode->hdisplay > fixed_mode->hdisplay)
226 if (mode->vdisplay > fixed_mode->vdisplay)
230 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
231 return MODE_CLOCK_HIGH;
233 if (mode->clock < 10000)
234 return MODE_CLOCK_LOW;
236 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
237 return MODE_H_ILLEGAL;
243 pack_aux(uint8_t *src, int src_bytes)
250 for (i = 0; i < src_bytes; i++)
251 v |= ((uint32_t) src[i]) << ((3-i) * 8);
256 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
261 for (i = 0; i < dst_bytes; i++)
262 dst[i] = src >> ((3-i) * 8);
265 /* hrawclock is 1/4 the FSB frequency */
267 intel_hrawclk(struct drm_device *dev)
269 struct drm_i915_private *dev_priv = dev->dev_private;
272 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
273 if (IS_VALLEYVIEW(dev))
276 clkcfg = I915_READ(CLKCFG);
277 switch (clkcfg & CLKCFG_FSB_MASK) {
286 case CLKCFG_FSB_1067:
288 case CLKCFG_FSB_1333:
290 /* these two are just a guess; one of them might be right */
291 case CLKCFG_FSB_1600:
292 case CLKCFG_FSB_1600_ALT:
299 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
301 struct drm_device *dev = intel_dp_to_dev(intel_dp);
302 struct drm_i915_private *dev_priv = dev->dev_private;
304 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
307 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
309 struct drm_device *dev = intel_dp_to_dev(intel_dp);
310 struct drm_i915_private *dev_priv = dev->dev_private;
312 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
316 intel_dp_check_edp(struct intel_dp *intel_dp)
318 struct drm_device *dev = intel_dp_to_dev(intel_dp);
319 struct drm_i915_private *dev_priv = dev->dev_private;
321 if (!is_edp(intel_dp))
323 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
324 WARN(1, "eDP powered off while attempting aux channel communication.\n");
325 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
326 I915_READ(PCH_PP_STATUS),
327 I915_READ(PCH_PP_CONTROL));
332 intel_dp_aux_ch(struct intel_dp *intel_dp,
333 uint8_t *send, int send_bytes,
334 uint8_t *recv, int recv_size)
336 uint32_t output_reg = intel_dp->output_reg;
337 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
338 struct drm_device *dev = intel_dig_port->base.base.dev;
339 struct drm_i915_private *dev_priv = dev->dev_private;
340 uint32_t ch_ctl = output_reg + 0x10;
341 uint32_t ch_data = ch_ctl + 4;
345 uint32_t aux_clock_divider;
348 if (IS_HASWELL(dev)) {
349 switch (intel_dig_port->port) {
351 ch_ctl = DPA_AUX_CH_CTL;
352 ch_data = DPA_AUX_CH_DATA1;
355 ch_ctl = PCH_DPB_AUX_CH_CTL;
356 ch_data = PCH_DPB_AUX_CH_DATA1;
359 ch_ctl = PCH_DPC_AUX_CH_CTL;
360 ch_data = PCH_DPC_AUX_CH_DATA1;
363 ch_ctl = PCH_DPD_AUX_CH_CTL;
364 ch_data = PCH_DPD_AUX_CH_DATA1;
371 intel_dp_check_edp(intel_dp);
372 /* The clock divider is based off the hrawclk,
373 * and would like to run at 2MHz. So, take the
374 * hrawclk value and divide by 2 and use that
376 * Note that PCH attached eDP panels should use a 125MHz input
379 if (is_cpu_edp(intel_dp)) {
381 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
382 else if (IS_VALLEYVIEW(dev))
383 aux_clock_divider = 100;
384 else if (IS_GEN6(dev) || IS_GEN7(dev))
385 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
387 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
388 } else if (HAS_PCH_SPLIT(dev))
389 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
391 aux_clock_divider = intel_hrawclk(dev) / 2;
398 /* Try to wait for any previous AUX channel activity */
399 for (try = 0; try < 3; try++) {
400 status = I915_READ(ch_ctl);
401 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
407 WARN(1, "dp_aux_ch not started status 0x%08x\n",
412 /* Must try at least 3 times according to DP spec */
413 for (try = 0; try < 5; try++) {
414 /* Load the send data into the aux channel data registers */
415 for (i = 0; i < send_bytes; i += 4)
416 I915_WRITE(ch_data + i,
417 pack_aux(send + i, send_bytes - i));
419 /* Send the command and wait for it to complete */
421 DP_AUX_CH_CTL_SEND_BUSY |
422 DP_AUX_CH_CTL_TIME_OUT_400us |
423 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
424 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
425 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
427 DP_AUX_CH_CTL_TIME_OUT_ERROR |
428 DP_AUX_CH_CTL_RECEIVE_ERROR);
430 status = I915_READ(ch_ctl);
431 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
436 /* Clear done status and any errors */
440 DP_AUX_CH_CTL_TIME_OUT_ERROR |
441 DP_AUX_CH_CTL_RECEIVE_ERROR);
443 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
444 DP_AUX_CH_CTL_RECEIVE_ERROR))
446 if (status & DP_AUX_CH_CTL_DONE)
450 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
451 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
455 /* Check for timeout or receive error.
456 * Timeouts occur when the sink is not connected
458 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
459 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
463 /* Timeouts occur when the device isn't connected, so they're
464 * "normal" -- don't fill the kernel log with these */
465 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
466 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
470 /* Unload any bytes sent back from the other side */
471 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
472 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
473 if (recv_bytes > recv_size)
474 recv_bytes = recv_size;
476 for (i = 0; i < recv_bytes; i += 4)
477 unpack_aux(I915_READ(ch_data + i),
478 recv + i, recv_bytes - i);
483 /* Write data to the aux channel in native mode */
485 intel_dp_aux_native_write(struct intel_dp *intel_dp,
486 uint16_t address, uint8_t *send, int send_bytes)
493 intel_dp_check_edp(intel_dp);
496 msg[0] = AUX_NATIVE_WRITE << 4;
497 msg[1] = address >> 8;
498 msg[2] = address & 0xff;
499 msg[3] = send_bytes - 1;
500 memcpy(&msg[4], send, send_bytes);
501 msg_bytes = send_bytes + 4;
503 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
506 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
508 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
516 /* Write a single byte to the aux channel in native mode */
518 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
519 uint16_t address, uint8_t byte)
521 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
524 /* read bytes from a native aux channel */
526 intel_dp_aux_native_read(struct intel_dp *intel_dp,
527 uint16_t address, uint8_t *recv, int recv_bytes)
536 intel_dp_check_edp(intel_dp);
537 msg[0] = AUX_NATIVE_READ << 4;
538 msg[1] = address >> 8;
539 msg[2] = address & 0xff;
540 msg[3] = recv_bytes - 1;
543 reply_bytes = recv_bytes + 1;
546 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
553 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
554 memcpy(recv, reply + 1, ret - 1);
557 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
565 intel_dp_i2c_aux_ch(device_t idev, int mode, uint8_t write_byte,
568 struct iic_dp_aux_data *data;
569 struct intel_dp *intel_dp;
578 data = device_get_softc(idev);
579 intel_dp = data->priv;
580 address = data->address;
582 intel_dp_check_edp(intel_dp);
583 /* Set up the command byte */
584 if (mode & MODE_I2C_READ)
585 msg[0] = AUX_I2C_READ << 4;
587 msg[0] = AUX_I2C_WRITE << 4;
589 if (!(mode & MODE_I2C_STOP))
590 msg[0] |= AUX_I2C_MOT << 4;
592 msg[1] = address >> 8;
613 for (retry = 0; retry < 5; retry++) {
614 ret = intel_dp_aux_ch(intel_dp,
618 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
622 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
623 case AUX_NATIVE_REPLY_ACK:
624 /* I2C-over-AUX Reply field is only valid
625 * when paired with AUX ACK.
628 case AUX_NATIVE_REPLY_NACK:
629 DRM_DEBUG_KMS("aux_ch native nack\n");
631 case AUX_NATIVE_REPLY_DEFER:
635 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
640 switch (reply[0] & AUX_I2C_REPLY_MASK) {
641 case AUX_I2C_REPLY_ACK:
642 if (mode == MODE_I2C_READ) {
643 *read_byte = reply[1];
645 return (0/*reply_bytes - 1*/);
646 case AUX_I2C_REPLY_NACK:
647 DRM_DEBUG_KMS("aux_i2c nack\n");
649 case AUX_I2C_REPLY_DEFER:
650 DRM_DEBUG_KMS("aux_i2c defer\n");
654 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
659 DRM_ERROR("too many retries, giving up\n");
664 intel_dp_i2c_init(struct intel_dp *intel_dp,
665 struct intel_connector *intel_connector, const char *name)
669 DRM_DEBUG_KMS("i2c_init %s\n", name);
671 ironlake_edp_panel_vdd_on(intel_dp);
672 ret = iic_dp_aux_add_bus(intel_connector->base.dev->dev, name,
673 intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
675 ironlake_edp_panel_vdd_off(intel_dp, false);
680 intel_dp_mode_fixup(struct drm_encoder *encoder,
681 const struct drm_display_mode *mode,
682 struct drm_display_mode *adjusted_mode)
684 struct drm_device *dev = encoder->dev;
685 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
686 struct intel_connector *intel_connector = intel_dp->attached_connector;
687 int lane_count, clock;
688 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
689 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
691 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
693 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
694 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
696 intel_pch_panel_fitting(dev,
697 intel_connector->panel.fitting_mode,
698 mode, adjusted_mode);
701 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
704 DRM_DEBUG_KMS("DP link computation with max lane count %i "
705 "max bw %02x pixel clock %iKHz\n",
706 max_lane_count, bws[max_clock], adjusted_mode->clock);
708 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
711 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
712 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
714 for (clock = 0; clock <= max_clock; clock++) {
715 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
716 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
718 if (mode_rate <= link_avail) {
719 intel_dp->link_bw = bws[clock];
720 intel_dp->lane_count = lane_count;
721 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
722 DRM_DEBUG_KMS("DP link bw %02x lane "
723 "count %d clock %d bpp %d\n",
724 intel_dp->link_bw, intel_dp->lane_count,
725 adjusted_mode->clock, bpp);
726 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
727 mode_rate, link_avail);
736 struct intel_dp_m_n {
745 intel_reduce_ratio(uint32_t *num, uint32_t *den)
747 while (*num > 0xffffff || *den > 0xffffff) {
754 intel_dp_compute_m_n(int bpp,
758 struct intel_dp_m_n *m_n)
761 m_n->gmch_m = (pixel_clock * bpp) >> 3;
762 m_n->gmch_n = link_clock * nlanes;
763 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
764 m_n->link_m = pixel_clock;
765 m_n->link_n = link_clock;
766 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
770 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
771 struct drm_display_mode *adjusted_mode)
773 struct drm_device *dev = crtc->dev;
774 struct intel_encoder *intel_encoder;
775 struct intel_dp *intel_dp;
776 struct drm_i915_private *dev_priv = dev->dev_private;
777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
779 struct intel_dp_m_n m_n;
780 int pipe = intel_crtc->pipe;
781 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
785 * Find the lane count in the intel_encoder private
787 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
788 intel_dp = enc_to_intel_dp(&intel_encoder->base);
790 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
791 intel_encoder->type == INTEL_OUTPUT_EDP)
793 lane_count = intel_dp->lane_count;
798 target_clock = mode->clock;
799 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
800 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
801 target_clock = intel_edp_target_clock(intel_encoder,
808 * Compute the GMCH and Link ratios. The '3' here is
809 * the number of bytes_per_pixel post-LUT, which we always
810 * set up for 8-bits of R/G/B, or 3 bytes total.
812 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
813 target_clock, adjusted_mode->clock, &m_n);
815 if (IS_HASWELL(dev)) {
816 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
817 TU_SIZE(m_n.tu) | m_n.gmch_m);
818 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
819 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
820 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
821 } else if (HAS_PCH_SPLIT(dev)) {
822 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
823 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
824 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
825 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
826 } else if (IS_VALLEYVIEW(dev)) {
827 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
828 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
829 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
830 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
832 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
833 TU_SIZE(m_n.tu) | m_n.gmch_m);
834 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
835 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
836 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
840 void intel_dp_init_link_config(struct intel_dp *intel_dp)
842 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
843 intel_dp->link_configuration[0] = intel_dp->link_bw;
844 intel_dp->link_configuration[1] = intel_dp->lane_count;
845 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
847 * Check for DPCD version > 1.1 and enhanced framing support
849 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
850 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
851 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
856 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
857 struct drm_display_mode *adjusted_mode)
859 struct drm_device *dev = encoder->dev;
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
862 struct drm_crtc *crtc = encoder->crtc;
863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
866 * There are four kinds of DP registers:
873 * IBX PCH and CPU are the same for almost everything,
874 * except that the CPU DP PLL is configured in this
877 * CPT PCH is quite different, having many bits moved
878 * to the TRANS_DP_CTL register instead. That
879 * configuration happens (oddly) in ironlake_pch_enable
882 /* Preserve the BIOS-computed detected bit. This is
883 * supposed to be read-only.
885 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
887 /* Handle DP bits in common between all three register formats */
888 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
890 switch (intel_dp->lane_count) {
892 intel_dp->DP |= DP_PORT_WIDTH_1;
895 intel_dp->DP |= DP_PORT_WIDTH_2;
898 intel_dp->DP |= DP_PORT_WIDTH_4;
901 if (intel_dp->has_audio) {
902 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
903 pipe_name(intel_crtc->pipe));
904 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
905 intel_write_eld(encoder, adjusted_mode);
908 intel_dp_init_link_config(intel_dp);
910 /* Split out the IBX/CPU vs CPT settings */
912 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
913 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
914 intel_dp->DP |= DP_SYNC_HS_HIGH;
915 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
916 intel_dp->DP |= DP_SYNC_VS_HIGH;
917 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
919 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
920 intel_dp->DP |= DP_ENHANCED_FRAMING;
922 intel_dp->DP |= intel_crtc->pipe << 29;
924 /* don't miss out required setting for eDP */
925 if (adjusted_mode->clock < 200000)
926 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
928 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
929 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
930 intel_dp->DP |= intel_dp->color_range;
932 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
933 intel_dp->DP |= DP_SYNC_HS_HIGH;
934 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
935 intel_dp->DP |= DP_SYNC_VS_HIGH;
936 intel_dp->DP |= DP_LINK_TRAIN_OFF;
938 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
939 intel_dp->DP |= DP_ENHANCED_FRAMING;
941 if (intel_crtc->pipe == 1)
942 intel_dp->DP |= DP_PIPEB_SELECT;
944 if (is_cpu_edp(intel_dp)) {
945 /* don't miss out required setting for eDP */
946 if (adjusted_mode->clock < 200000)
947 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
949 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
952 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
956 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
957 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
959 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
960 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
962 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
963 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
965 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
969 struct drm_device *dev = intel_dp_to_dev(intel_dp);
970 struct drm_i915_private *dev_priv = dev->dev_private;
972 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
974 I915_READ(PCH_PP_STATUS),
975 I915_READ(PCH_PP_CONTROL));
977 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
978 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
979 I915_READ(PCH_PP_STATUS),
980 I915_READ(PCH_PP_CONTROL));
984 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
986 DRM_DEBUG_KMS("Wait for panel power on\n");
987 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
990 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
992 DRM_DEBUG_KMS("Wait for panel power off time\n");
993 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
996 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
998 DRM_DEBUG_KMS("Wait for panel power cycle\n");
999 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1003 /* Read the current pp_control value, unlocking the register if it
1007 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1009 u32 control = I915_READ(PCH_PP_CONTROL);
1011 control &= ~PANEL_UNLOCK_MASK;
1012 control |= PANEL_UNLOCK_REGS;
1016 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1018 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1019 struct drm_i915_private *dev_priv = dev->dev_private;
1022 if (!is_edp(intel_dp))
1024 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1026 WARN(intel_dp->want_panel_vdd,
1027 "eDP VDD already requested on\n");
1029 intel_dp->want_panel_vdd = true;
1031 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1032 DRM_DEBUG_KMS("eDP VDD already on\n");
1036 if (!ironlake_edp_have_panel_power(intel_dp))
1037 ironlake_wait_panel_power_cycle(intel_dp);
1039 pp = ironlake_get_pp_control(dev_priv);
1040 pp |= EDP_FORCE_VDD;
1041 I915_WRITE(PCH_PP_CONTROL, pp);
1042 POSTING_READ(PCH_PP_CONTROL);
1043 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1044 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1047 * If the panel wasn't on, delay before accessing aux channel
1049 if (!ironlake_edp_have_panel_power(intel_dp)) {
1050 DRM_DEBUG_KMS("eDP was not running\n");
1051 msleep(intel_dp->panel_power_up_delay);
1055 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1057 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1058 struct drm_i915_private *dev_priv = dev->dev_private;
1061 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1062 pp = ironlake_get_pp_control(dev_priv);
1063 pp &= ~EDP_FORCE_VDD;
1064 I915_WRITE(PCH_PP_CONTROL, pp);
1065 POSTING_READ(PCH_PP_CONTROL);
1067 /* Make sure sequencer is idle before allowing subsequent activity */
1068 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1069 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1071 DELAY(intel_dp->panel_power_down_delay * 1000);
1075 static void ironlake_panel_vdd_work(struct work_struct *__work)
1077 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1078 struct intel_dp, panel_vdd_work);
1079 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1081 lockmgr(&dev->mode_config.mutex, LK_EXCLUSIVE);
1082 ironlake_panel_vdd_off_sync(intel_dp);
1083 lockmgr(&dev->mode_config.mutex, LK_RELEASE);
1086 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1088 if (!is_edp(intel_dp))
1091 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1092 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1094 intel_dp->want_panel_vdd = false;
1097 ironlake_panel_vdd_off_sync(intel_dp);
1100 * Queue the timer to fire a long
1101 * time from now (relative to the power down delay)
1102 * to keep the panel power up across a sequence of operations
1104 schedule_delayed_work(&intel_dp->panel_vdd_work,
1105 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1109 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1111 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1112 struct drm_i915_private *dev_priv = dev->dev_private;
1115 if (!is_edp(intel_dp))
1118 DRM_DEBUG_KMS("Turn eDP power on\n");
1120 if (ironlake_edp_have_panel_power(intel_dp)) {
1121 DRM_DEBUG_KMS("eDP power already on\n");
1125 ironlake_wait_panel_power_cycle(intel_dp);
1127 pp = ironlake_get_pp_control(dev_priv);
1129 /* ILK workaround: disable reset around power sequence */
1130 pp &= ~PANEL_POWER_RESET;
1131 I915_WRITE(PCH_PP_CONTROL, pp);
1132 POSTING_READ(PCH_PP_CONTROL);
1135 pp |= POWER_TARGET_ON;
1137 pp |= PANEL_POWER_RESET;
1139 I915_WRITE(PCH_PP_CONTROL, pp);
1140 POSTING_READ(PCH_PP_CONTROL);
1142 ironlake_wait_panel_on(intel_dp);
1145 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1146 I915_WRITE(PCH_PP_CONTROL, pp);
1147 POSTING_READ(PCH_PP_CONTROL);
1151 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1153 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1154 struct drm_i915_private *dev_priv = dev->dev_private;
1157 if (!is_edp(intel_dp))
1160 DRM_DEBUG_KMS("Turn eDP power off\n");
1162 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1164 pp = ironlake_get_pp_control(dev_priv);
1165 /* We need to switch off panel power _and_ force vdd, for otherwise some
1166 * panels get very unhappy and cease to work. */
1167 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1168 I915_WRITE(PCH_PP_CONTROL, pp);
1169 POSTING_READ(PCH_PP_CONTROL);
1171 intel_dp->want_panel_vdd = false;
1173 ironlake_wait_panel_off(intel_dp);
1176 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1178 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1179 struct drm_device *dev = intel_dig_port->base.base.dev;
1180 struct drm_i915_private *dev_priv = dev->dev_private;
1181 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1184 if (!is_edp(intel_dp))
1187 DRM_DEBUG_KMS("\n");
1189 * If we enable the backlight right away following a panel power
1190 * on, we may see slight flicker as the panel syncs with the eDP
1191 * link. So delay a bit to make sure the image is solid before
1192 * allowing it to appear.
1194 DELAY(intel_dp->backlight_on_delay * 1000);
1195 pp = ironlake_get_pp_control(dev_priv);
1196 pp |= EDP_BLC_ENABLE;
1197 I915_WRITE(PCH_PP_CONTROL, pp);
1198 POSTING_READ(PCH_PP_CONTROL);
1200 intel_panel_enable_backlight(dev, pipe);
1203 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1205 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1206 struct drm_i915_private *dev_priv = dev->dev_private;
1209 if (!is_edp(intel_dp))
1212 intel_panel_disable_backlight(dev);
1214 DRM_DEBUG_KMS("\n");
1215 pp = ironlake_get_pp_control(dev_priv);
1216 pp &= ~EDP_BLC_ENABLE;
1217 I915_WRITE(PCH_PP_CONTROL, pp);
1218 POSTING_READ(PCH_PP_CONTROL);
1219 DELAY(intel_dp->backlight_off_delay * 1000);
1222 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1224 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1225 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1226 struct drm_device *dev = crtc->dev;
1227 struct drm_i915_private *dev_priv = dev->dev_private;
1230 assert_pipe_disabled(dev_priv,
1231 to_intel_crtc(crtc)->pipe);
1233 DRM_DEBUG_KMS("\n");
1234 dpa_ctl = I915_READ(DP_A);
1235 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1236 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1238 /* We don't adjust intel_dp->DP while tearing down the link, to
1239 * facilitate link retraining (e.g. after hotplug). Hence clear all
1240 * enable bits here to ensure that we don't enable too much. */
1241 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1242 intel_dp->DP |= DP_PLL_ENABLE;
1243 I915_WRITE(DP_A, intel_dp->DP);
1248 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1250 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1251 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1252 struct drm_device *dev = crtc->dev;
1253 struct drm_i915_private *dev_priv = dev->dev_private;
1256 assert_pipe_disabled(dev_priv,
1257 to_intel_crtc(crtc)->pipe);
1259 dpa_ctl = I915_READ(DP_A);
1260 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1261 "dp pll off, should be on\n");
1262 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1264 /* We can't rely on the value tracked for the DP register in
1265 * intel_dp->DP because link_down must not change that (otherwise link
1266 * re-training will fail. */
1267 dpa_ctl &= ~DP_PLL_ENABLE;
1268 I915_WRITE(DP_A, dpa_ctl);
1273 /* If the sink supports it, try to set the power state appropriately */
1274 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1278 /* Should have a valid DPCD by this point */
1279 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1282 if (mode != DRM_MODE_DPMS_ON) {
1283 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1286 DRM_DEBUG("failed to write sink power state\n");
1289 * When turning on, we need to retry for 1ms to give the sink
1292 for (i = 0; i < 3; i++) {
1293 ret = intel_dp_aux_native_write_1(intel_dp,
1303 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1304 enum i915_pipe *pipe)
1306 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1307 struct drm_device *dev = encoder->base.dev;
1308 struct drm_i915_private *dev_priv = dev->dev_private;
1309 u32 tmp = I915_READ(intel_dp->output_reg);
1311 if (!(tmp & DP_PORT_EN))
1314 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1315 *pipe = PORT_TO_PIPE_CPT(tmp);
1316 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1317 *pipe = PORT_TO_PIPE(tmp);
1323 switch (intel_dp->output_reg) {
1325 trans_sel = TRANS_DP_PORT_SEL_B;
1328 trans_sel = TRANS_DP_PORT_SEL_C;
1331 trans_sel = TRANS_DP_PORT_SEL_D;
1338 trans_dp = I915_READ(TRANS_DP_CTL(i));
1339 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1345 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1346 intel_dp->output_reg);
1352 static void intel_disable_dp(struct intel_encoder *encoder)
1354 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1356 /* Make sure the panel is off before trying to change the mode. But also
1357 * ensure that we have vdd while we switch off the panel. */
1358 ironlake_edp_panel_vdd_on(intel_dp);
1359 ironlake_edp_backlight_off(intel_dp);
1360 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1361 ironlake_edp_panel_off(intel_dp);
1363 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1364 if (!is_cpu_edp(intel_dp))
1365 intel_dp_link_down(intel_dp);
1368 static void intel_post_disable_dp(struct intel_encoder *encoder)
1370 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1372 if (is_cpu_edp(intel_dp)) {
1373 intel_dp_link_down(intel_dp);
1374 ironlake_edp_pll_off(intel_dp);
1378 static void intel_enable_dp(struct intel_encoder *encoder)
1380 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1381 struct drm_device *dev = encoder->base.dev;
1382 struct drm_i915_private *dev_priv = dev->dev_private;
1383 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1385 if (WARN_ON(dp_reg & DP_PORT_EN))
1388 ironlake_edp_panel_vdd_on(intel_dp);
1389 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1390 intel_dp_start_link_train(intel_dp);
1391 ironlake_edp_panel_on(intel_dp);
1392 ironlake_edp_panel_vdd_off(intel_dp, true);
1393 intel_dp_complete_link_train(intel_dp);
1394 ironlake_edp_backlight_on(intel_dp);
1397 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1399 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1401 if (is_cpu_edp(intel_dp))
1402 ironlake_edp_pll_on(intel_dp);
1406 * Native read with retry for link status and receiver capability reads for
1407 * cases where the sink may still be asleep.
1410 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1411 uint8_t *recv, int recv_bytes)
1416 * Sinks are *supposed* to come up within 1ms from an off state,
1417 * but we're also supposed to retry 3 times per the spec.
1419 for (i = 0; i < 3; i++) {
1420 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1422 if (ret == recv_bytes)
1431 * Fetch AUX CH registers 0x202 - 0x207 which contain
1432 * link status information
1435 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1437 return intel_dp_aux_native_read_retry(intel_dp,
1440 DP_LINK_STATUS_SIZE);
1444 static char *voltage_names[] = {
1445 "0.4V", "0.6V", "0.8V", "1.2V"
1447 static char *pre_emph_names[] = {
1448 "0dB", "3.5dB", "6dB", "9.5dB"
1450 static char *link_train_names[] = {
1451 "pattern 1", "pattern 2", "idle", "off"
1456 * These are source-specific values; current Intel hardware supports
1457 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1461 intel_dp_voltage_max(struct intel_dp *intel_dp)
1463 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1465 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1466 return DP_TRAIN_VOLTAGE_SWING_800;
1467 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1468 return DP_TRAIN_VOLTAGE_SWING_1200;
1470 return DP_TRAIN_VOLTAGE_SWING_800;
1474 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1476 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1478 if (IS_HASWELL(dev)) {
1479 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1480 case DP_TRAIN_VOLTAGE_SWING_400:
1481 return DP_TRAIN_PRE_EMPHASIS_9_5;
1482 case DP_TRAIN_VOLTAGE_SWING_600:
1483 return DP_TRAIN_PRE_EMPHASIS_6;
1484 case DP_TRAIN_VOLTAGE_SWING_800:
1485 return DP_TRAIN_PRE_EMPHASIS_3_5;
1486 case DP_TRAIN_VOLTAGE_SWING_1200:
1488 return DP_TRAIN_PRE_EMPHASIS_0;
1490 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1491 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1492 case DP_TRAIN_VOLTAGE_SWING_400:
1493 return DP_TRAIN_PRE_EMPHASIS_6;
1494 case DP_TRAIN_VOLTAGE_SWING_600:
1495 case DP_TRAIN_VOLTAGE_SWING_800:
1496 return DP_TRAIN_PRE_EMPHASIS_3_5;
1498 return DP_TRAIN_PRE_EMPHASIS_0;
1501 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1502 case DP_TRAIN_VOLTAGE_SWING_400:
1503 return DP_TRAIN_PRE_EMPHASIS_6;
1504 case DP_TRAIN_VOLTAGE_SWING_600:
1505 return DP_TRAIN_PRE_EMPHASIS_6;
1506 case DP_TRAIN_VOLTAGE_SWING_800:
1507 return DP_TRAIN_PRE_EMPHASIS_3_5;
1508 case DP_TRAIN_VOLTAGE_SWING_1200:
1510 return DP_TRAIN_PRE_EMPHASIS_0;
1516 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1521 uint8_t voltage_max;
1522 uint8_t preemph_max;
1524 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1525 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1526 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1534 voltage_max = intel_dp_voltage_max(intel_dp);
1535 if (v >= voltage_max)
1536 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1538 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1539 if (p >= preemph_max)
1540 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1542 for (lane = 0; lane < 4; lane++)
1543 intel_dp->train_set[lane] = v | p;
1547 intel_dp_signal_levels(uint8_t train_set)
1549 uint32_t signal_levels = 0;
1551 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1552 case DP_TRAIN_VOLTAGE_SWING_400:
1554 signal_levels |= DP_VOLTAGE_0_4;
1556 case DP_TRAIN_VOLTAGE_SWING_600:
1557 signal_levels |= DP_VOLTAGE_0_6;
1559 case DP_TRAIN_VOLTAGE_SWING_800:
1560 signal_levels |= DP_VOLTAGE_0_8;
1562 case DP_TRAIN_VOLTAGE_SWING_1200:
1563 signal_levels |= DP_VOLTAGE_1_2;
1566 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1567 case DP_TRAIN_PRE_EMPHASIS_0:
1569 signal_levels |= DP_PRE_EMPHASIS_0;
1571 case DP_TRAIN_PRE_EMPHASIS_3_5:
1572 signal_levels |= DP_PRE_EMPHASIS_3_5;
1574 case DP_TRAIN_PRE_EMPHASIS_6:
1575 signal_levels |= DP_PRE_EMPHASIS_6;
1577 case DP_TRAIN_PRE_EMPHASIS_9_5:
1578 signal_levels |= DP_PRE_EMPHASIS_9_5;
1581 return signal_levels;
1584 /* Gen6's DP voltage swing and pre-emphasis control */
1586 intel_gen6_edp_signal_levels(uint8_t train_set)
1588 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1589 DP_TRAIN_PRE_EMPHASIS_MASK);
1590 switch (signal_levels) {
1591 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1592 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1593 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1594 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1595 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1596 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1597 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1598 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1599 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1600 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1601 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1602 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1603 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1604 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1606 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1607 "0x%x\n", signal_levels);
1608 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1612 /* Gen7's DP voltage swing and pre-emphasis control */
1614 intel_gen7_edp_signal_levels(uint8_t train_set)
1616 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1617 DP_TRAIN_PRE_EMPHASIS_MASK);
1618 switch (signal_levels) {
1619 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1620 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1621 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1622 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1623 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1624 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1626 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1627 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1628 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1629 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1631 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1632 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1633 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1634 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1637 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1638 "0x%x\n", signal_levels);
1639 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1643 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1645 intel_dp_signal_levels_hsw(uint8_t train_set)
1647 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1648 DP_TRAIN_PRE_EMPHASIS_MASK);
1649 switch (signal_levels) {
1650 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1651 return DDI_BUF_EMP_400MV_0DB_HSW;
1652 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1653 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1654 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1655 return DDI_BUF_EMP_400MV_6DB_HSW;
1656 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1657 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1659 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1660 return DDI_BUF_EMP_600MV_0DB_HSW;
1661 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1662 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1663 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1664 return DDI_BUF_EMP_600MV_6DB_HSW;
1666 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1667 return DDI_BUF_EMP_800MV_0DB_HSW;
1668 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1669 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1671 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1672 "0x%x\n", signal_levels);
1673 return DDI_BUF_EMP_400MV_0DB_HSW;
1678 intel_dp_set_link_train(struct intel_dp *intel_dp,
1679 uint32_t dp_reg_value,
1680 uint8_t dp_train_pat)
1682 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1683 struct drm_device *dev = intel_dig_port->base.base.dev;
1684 struct drm_i915_private *dev_priv = dev->dev_private;
1685 enum port port = intel_dig_port->port;
1689 if (IS_HASWELL(dev)) {
1690 temp = I915_READ(DP_TP_CTL(port));
1692 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1693 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1695 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1697 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1698 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1699 case DP_TRAINING_PATTERN_DISABLE:
1700 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1701 I915_WRITE(DP_TP_CTL(port), temp);
1703 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1704 DP_TP_STATUS_IDLE_DONE), 1))
1705 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1707 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1708 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1711 case DP_TRAINING_PATTERN_1:
1712 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1714 case DP_TRAINING_PATTERN_2:
1715 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1717 case DP_TRAINING_PATTERN_3:
1718 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1721 I915_WRITE(DP_TP_CTL(port), temp);
1723 } else if (HAS_PCH_CPT(dev) &&
1724 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1725 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1727 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1728 case DP_TRAINING_PATTERN_DISABLE:
1729 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1731 case DP_TRAINING_PATTERN_1:
1732 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1734 case DP_TRAINING_PATTERN_2:
1735 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1737 case DP_TRAINING_PATTERN_3:
1738 DRM_ERROR("DP training pattern 3 not supported\n");
1739 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1744 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1746 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1747 case DP_TRAINING_PATTERN_DISABLE:
1748 dp_reg_value |= DP_LINK_TRAIN_OFF;
1750 case DP_TRAINING_PATTERN_1:
1751 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1753 case DP_TRAINING_PATTERN_2:
1754 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1756 case DP_TRAINING_PATTERN_3:
1757 DRM_ERROR("DP training pattern 3 not supported\n");
1758 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1763 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1764 POSTING_READ(intel_dp->output_reg);
1766 intel_dp_aux_native_write_1(intel_dp,
1767 DP_TRAINING_PATTERN_SET,
1770 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1771 DP_TRAINING_PATTERN_DISABLE) {
1772 ret = intel_dp_aux_native_write(intel_dp,
1773 DP_TRAINING_LANE0_SET,
1774 intel_dp->train_set,
1775 intel_dp->lane_count);
1776 if (ret != intel_dp->lane_count)
1783 /* Enable corresponding port and start training pattern 1 */
1785 intel_dp_start_link_train(struct intel_dp *intel_dp)
1787 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1788 struct drm_device *dev = encoder->dev;
1791 bool clock_recovery = false;
1792 int voltage_tries, loop_tries;
1793 uint32_t DP = intel_dp->DP;
1795 if (IS_HASWELL(dev))
1796 intel_ddi_prepare_link_retrain(encoder);
1798 /* Write the link configuration data */
1799 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1800 intel_dp->link_configuration,
1801 DP_LINK_CONFIGURATION_SIZE);
1805 memset(intel_dp->train_set, 0, 4);
1809 clock_recovery = false;
1811 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1812 uint8_t link_status[DP_LINK_STATUS_SIZE];
1813 uint32_t signal_levels;
1815 if (IS_HASWELL(dev)) {
1816 signal_levels = intel_dp_signal_levels_hsw(
1817 intel_dp->train_set[0]);
1818 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1819 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1820 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1821 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1822 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1823 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1824 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1826 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1827 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1829 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1832 /* Set training pattern 1 */
1833 if (!intel_dp_set_link_train(intel_dp, DP,
1834 DP_TRAINING_PATTERN_1 |
1835 DP_LINK_SCRAMBLING_DISABLE))
1838 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1839 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1840 DRM_ERROR("failed to get link status\n");
1844 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1845 DRM_DEBUG_KMS("clock recovery OK\n");
1846 clock_recovery = true;
1850 /* Check to see if we've tried the max voltage */
1851 for (i = 0; i < intel_dp->lane_count; i++)
1852 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1854 if (i == intel_dp->lane_count) {
1855 if (++loop_tries == 5) {
1856 DRM_DEBUG_KMS("too many full retries, give up\n");
1859 memset(intel_dp->train_set, 0, 4);
1864 /* Check to see if we've tried the same voltage 5 times */
1865 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1866 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1871 /* Compute new intel_dp->train_set as requested by target */
1872 intel_get_adjust_train(intel_dp, link_status);
1879 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1881 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1882 bool channel_eq = false;
1883 int tries, cr_tries;
1884 uint32_t DP = intel_dp->DP;
1886 /* channel equalization */
1891 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1892 uint32_t signal_levels;
1893 uint8_t link_status[DP_LINK_STATUS_SIZE];
1896 DRM_ERROR("failed to train DP, aborting\n");
1897 intel_dp_link_down(intel_dp);
1901 if (IS_HASWELL(dev)) {
1902 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1903 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1904 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1905 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1906 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1907 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1908 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1909 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1911 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1912 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1915 /* channel eq pattern */
1916 if (!intel_dp_set_link_train(intel_dp, DP,
1917 DP_TRAINING_PATTERN_2 |
1918 DP_LINK_SCRAMBLING_DISABLE))
1921 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1922 if (!intel_dp_get_link_status(intel_dp, link_status))
1925 /* Make sure clock is still ok */
1926 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1927 intel_dp_start_link_train(intel_dp);
1932 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1937 /* Try 5 times, then try clock recovery if that fails */
1939 intel_dp_link_down(intel_dp);
1940 intel_dp_start_link_train(intel_dp);
1946 /* Compute new intel_dp->train_set as requested by target */
1947 intel_get_adjust_train(intel_dp, link_status);
1952 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1954 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1958 intel_dp_link_down(struct intel_dp *intel_dp)
1960 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1961 struct drm_device *dev = intel_dig_port->base.base.dev;
1962 struct drm_i915_private *dev_priv = dev->dev_private;
1963 uint32_t DP = intel_dp->DP;
1966 * DDI code has a strict mode set sequence and we should try to respect
1967 * it, otherwise we might hang the machine in many different ways. So we
1968 * really should be disabling the port only on a complete crtc_disable
1969 * sequence. This function is just called under two conditions on DDI
1971 * - Link train failed while doing crtc_enable, and on this case we
1972 * really should respect the mode set sequence and wait for a
1974 * - Someone turned the monitor off and intel_dp_check_link_status
1975 * called us. We don't need to disable the whole port on this case, so
1976 * when someone turns the monitor on again,
1977 * intel_ddi_prepare_link_retrain will take care of redoing the link
1980 if (IS_HASWELL(dev))
1983 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1986 DRM_DEBUG_KMS("\n");
1988 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1989 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1990 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1992 DP &= ~DP_LINK_TRAIN_MASK;
1993 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1995 POSTING_READ(intel_dp->output_reg);
1999 if (HAS_PCH_IBX(dev) &&
2000 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2001 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2003 /* Hardware workaround: leaving our transcoder select
2004 * set to transcoder B while it's off will prevent the
2005 * corresponding HDMI output on transcoder A.
2007 * Combine this with another hardware workaround:
2008 * transcoder select bit can only be cleared while the
2011 DP &= ~DP_PIPEB_SELECT;
2012 I915_WRITE(intel_dp->output_reg, DP);
2014 /* Changes to enable or select take place the vblank
2015 * after being written.
2018 /* We can arrive here never having been attached
2019 * to a CRTC, for instance, due to inheriting
2020 * random state from the BIOS.
2022 * If the pipe is not running, play safe and
2023 * wait for the clocks to stabilise before
2026 POSTING_READ(intel_dp->output_reg);
2029 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
2032 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2033 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2034 POSTING_READ(intel_dp->output_reg);
2035 msleep(intel_dp->panel_power_down_delay);
2039 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2041 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2042 sizeof(intel_dp->dpcd)) == 0)
2043 return false; /* aux transfer failed */
2045 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2046 return false; /* DPCD not present */
2048 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2049 DP_DWN_STRM_PORT_PRESENT))
2050 return true; /* native DP sink */
2052 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2053 return true; /* no per-port downstream info */
2055 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2056 intel_dp->downstream_ports,
2057 DP_MAX_DOWNSTREAM_PORTS) == 0)
2058 return false; /* downstream port status fetch failed */
2064 intel_dp_probe_oui(struct intel_dp *intel_dp)
2068 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2071 ironlake_edp_panel_vdd_on(intel_dp);
2073 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2074 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2075 buf[0], buf[1], buf[2]);
2077 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2078 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2079 buf[0], buf[1], buf[2]);
2081 ironlake_edp_panel_vdd_off(intel_dp, false);
2085 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2089 ret = intel_dp_aux_native_read_retry(intel_dp,
2090 DP_DEVICE_SERVICE_IRQ_VECTOR,
2091 sink_irq_vector, 1);
2099 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2101 /* NAK by default */
2102 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2106 * According to DP spec
2109 * 2. Configure link according to Receiver Capabilities
2110 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2111 * 4. Check link status on receipt of hot-plug interrupt
2115 intel_dp_check_link_status(struct intel_dp *intel_dp)
2117 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2119 u8 link_status[DP_LINK_STATUS_SIZE];
2121 if (!intel_encoder->connectors_active)
2124 if (WARN_ON(!intel_encoder->base.crtc))
2127 /* Try to read receiver status if the link appears to be up */
2128 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2129 intel_dp_link_down(intel_dp);
2133 /* Now read the DPCD to see if it's actually running */
2134 if (!intel_dp_get_dpcd(intel_dp)) {
2135 intel_dp_link_down(intel_dp);
2139 /* Try to read the source of the interrupt */
2140 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2141 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2142 /* Clear interrupt source */
2143 intel_dp_aux_native_write_1(intel_dp,
2144 DP_DEVICE_SERVICE_IRQ_VECTOR,
2147 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2148 intel_dp_handle_test_request(intel_dp);
2149 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2150 DRM_DEBUG_KMS("CP or sink specific irq unhandled\n");
2153 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2154 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2155 drm_get_encoder_name(&intel_encoder->base));
2156 intel_dp_start_link_train(intel_dp);
2157 intel_dp_complete_link_train(intel_dp);
2161 /* XXX this is probably wrong for multiple downstream ports */
2162 static enum drm_connector_status
2163 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2165 uint8_t *dpcd = intel_dp->dpcd;
2169 if (!intel_dp_get_dpcd(intel_dp))
2170 return connector_status_disconnected;
2172 /* if there's no downstream port, we're done */
2173 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2174 return connector_status_connected;
2176 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2177 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2180 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2182 return connector_status_unknown;
2183 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2184 : connector_status_disconnected;
2187 /* If no HPD, poke DDC gently */
2188 if (drm_probe_ddc(intel_dp->adapter))
2189 return connector_status_connected;
2191 /* Well we tried, say unknown for unreliable port types */
2192 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2193 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2194 return connector_status_unknown;
2196 /* Anything else is out of spec, warn and ignore */
2197 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2198 return connector_status_disconnected;
2201 static enum drm_connector_status
2202 ironlake_dp_detect(struct intel_dp *intel_dp)
2204 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2205 enum drm_connector_status status;
2207 /* Can't disconnect eDP, but you can close the lid... */
2208 if (is_edp(intel_dp)) {
2209 status = intel_panel_detect(dev);
2210 if (status == connector_status_unknown)
2211 status = connector_status_connected;
2215 return intel_dp_detect_dpcd(intel_dp);
2218 static enum drm_connector_status
2219 g4x_dp_detect(struct intel_dp *intel_dp)
2221 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2222 struct drm_i915_private *dev_priv = dev->dev_private;
2225 switch (intel_dp->output_reg) {
2227 bit = DPB_HOTPLUG_LIVE_STATUS;
2230 bit = DPC_HOTPLUG_LIVE_STATUS;
2233 bit = DPD_HOTPLUG_LIVE_STATUS;
2236 return connector_status_unknown;
2239 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2240 return connector_status_disconnected;
2242 return intel_dp_detect_dpcd(intel_dp);
2245 static struct edid *
2246 intel_dp_get_edid(struct drm_connector *connector, struct device *adapter)
2248 struct intel_connector *intel_connector = to_intel_connector(connector);
2250 /* use cached edid if we have one */
2251 if (intel_connector->edid) {
2256 if (IS_ERR(intel_connector->edid))
2259 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2260 edid = kmalloc(size, M_DRM, M_WAITOK);
2264 memcpy(edid, intel_connector->edid, size);
2268 return drm_get_edid(connector, adapter);
2272 intel_dp_get_edid_modes(struct drm_connector *connector, struct device *adapter)
2274 struct intel_connector *intel_connector = to_intel_connector(connector);
2276 /* use cached edid if we have one */
2277 if (intel_connector->edid) {
2279 if (IS_ERR(intel_connector->edid))
2282 return intel_connector_update_modes(connector,
2283 intel_connector->edid);
2286 return intel_ddc_get_modes(connector, adapter);
2290 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2292 * \return true if DP port is connected.
2293 * \return false if DP port is disconnected.
2295 static enum drm_connector_status
2296 intel_dp_detect(struct drm_connector *connector, bool force)
2298 struct intel_dp *intel_dp = intel_attached_dp(connector);
2299 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2300 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2301 struct drm_device *dev = connector->dev;
2302 enum drm_connector_status status;
2303 struct edid *edid = NULL;
2305 intel_dp->has_audio = false;
2307 if (HAS_PCH_SPLIT(dev))
2308 status = ironlake_dp_detect(intel_dp);
2310 status = g4x_dp_detect(intel_dp);
2312 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2313 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2314 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2315 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2317 if (status != connector_status_connected)
2320 intel_dp_probe_oui(intel_dp);
2322 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2323 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2325 edid = intel_dp_get_edid(connector, intel_dp->adapter);
2327 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2332 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2333 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2334 return connector_status_connected;
2337 static int intel_dp_get_modes(struct drm_connector *connector)
2339 struct intel_dp *intel_dp = intel_attached_dp(connector);
2340 struct intel_connector *intel_connector = to_intel_connector(connector);
2341 struct drm_device *dev = connector->dev;
2344 /* We should parse the EDID data and find out if it has an audio sink
2347 ret = intel_dp_get_edid_modes(connector, intel_dp->adapter);
2351 /* if eDP has no EDID, fall back to fixed mode */
2352 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2353 struct drm_display_mode *mode;
2354 mode = drm_mode_duplicate(dev,
2355 intel_connector->panel.fixed_mode);
2357 drm_mode_probed_add(connector, mode);
2365 intel_dp_detect_audio(struct drm_connector *connector)
2367 struct intel_dp *intel_dp = intel_attached_dp(connector);
2369 bool has_audio = false;
2371 edid = intel_dp_get_edid(connector, intel_dp->adapter);
2373 has_audio = drm_detect_monitor_audio(edid);
2375 drm_free(edid, M_DRM);
2382 intel_dp_set_property(struct drm_connector *connector,
2383 struct drm_property *property,
2386 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2387 struct intel_connector *intel_connector = to_intel_connector(connector);
2388 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2389 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2392 ret = drm_object_property_set_value(&connector->base, property, val);
2396 if (property == dev_priv->force_audio_property) {
2400 if (i == intel_dp->force_audio)
2403 intel_dp->force_audio = i;
2405 if (i == HDMI_AUDIO_AUTO)
2406 has_audio = intel_dp_detect_audio(connector);
2408 has_audio = (i == HDMI_AUDIO_ON);
2410 if (has_audio == intel_dp->has_audio)
2413 intel_dp->has_audio = has_audio;
2417 if (property == dev_priv->broadcast_rgb_property) {
2418 if (val == !!intel_dp->color_range)
2421 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2425 if (is_edp(intel_dp) &&
2426 property == connector->dev->mode_config.scaling_mode_property) {
2427 if (val == DRM_MODE_SCALE_NONE) {
2428 DRM_DEBUG_KMS("no scaling not supported\n");
2432 if (intel_connector->panel.fitting_mode == val) {
2433 /* the eDP scaling property is not changed */
2436 intel_connector->panel.fitting_mode = val;
2444 if (intel_encoder->base.crtc) {
2445 struct drm_crtc *crtc = intel_encoder->base.crtc;
2446 intel_set_mode(crtc, &crtc->mode,
2447 crtc->x, crtc->y, crtc->fb);
2454 intel_dp_destroy(struct drm_connector *connector)
2456 struct intel_dp *intel_dp = intel_attached_dp(connector);
2457 struct intel_connector *intel_connector = to_intel_connector(connector);
2459 if (!IS_ERR_OR_NULL(intel_connector->edid))
2460 kfree(intel_connector->edid, M_DRM);
2462 if (is_edp(intel_dp))
2463 intel_panel_fini(&intel_connector->panel);
2466 drm_sysfs_connector_remove(connector);
2468 drm_connector_cleanup(connector);
2469 drm_free(connector, M_DRM);
2472 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2474 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2475 struct intel_dp *intel_dp = &intel_dig_port->dp;
2476 struct drm_device *dev = encoder->dev;
2478 if (intel_dp->dp_iic_bus != NULL) {
2479 if (intel_dp->adapter != NULL) {
2480 device_delete_child(intel_dp->dp_iic_bus,
2483 device_delete_child(dev->dev, intel_dp->dp_iic_bus);
2485 drm_encoder_cleanup(encoder);
2486 if (is_edp(intel_dp)) {
2487 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2488 ironlake_panel_vdd_off_sync(intel_dp);
2490 drm_free(intel_dp, M_DRM);
2493 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2494 .mode_fixup = intel_dp_mode_fixup,
2495 .mode_set = intel_dp_mode_set,
2496 .disable = intel_encoder_noop,
2499 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2500 .dpms = intel_connector_dpms,
2501 .detect = intel_dp_detect,
2502 .fill_modes = drm_helper_probe_single_connector_modes,
2503 .set_property = intel_dp_set_property,
2504 .destroy = intel_dp_destroy,
2507 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2508 .get_modes = intel_dp_get_modes,
2509 .mode_valid = intel_dp_mode_valid,
2510 .best_encoder = intel_best_encoder,
2513 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2514 .destroy = intel_dp_encoder_destroy,
2518 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2520 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2522 intel_dp_check_link_status(intel_dp);
2525 /* Return which DP Port should be selected for Transcoder DP control */
2527 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2529 struct drm_device *dev = crtc->dev;
2530 struct intel_encoder *intel_encoder;
2531 struct intel_dp *intel_dp;
2533 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2534 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2536 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2537 intel_encoder->type == INTEL_OUTPUT_EDP)
2538 return intel_dp->output_reg;
2544 /* check the VBT to see whether the eDP is on DP-D port */
2545 bool intel_dpd_is_edp(struct drm_device *dev)
2547 struct drm_i915_private *dev_priv = dev->dev_private;
2548 struct child_device_config *p_child;
2551 if (!dev_priv->child_dev_num)
2554 for (i = 0; i < dev_priv->child_dev_num; i++) {
2555 p_child = dev_priv->child_dev + i;
2557 if (p_child->dvo_port == PORT_IDPD &&
2558 p_child->device_type == DEVICE_TYPE_eDP)
2565 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2567 struct intel_connector *intel_connector = to_intel_connector(connector);
2569 intel_attach_force_audio_property(connector);
2570 intel_attach_broadcast_rgb_property(connector);
2572 if (is_edp(intel_dp)) {
2573 drm_mode_create_scaling_mode_property(connector->dev);
2574 drm_object_attach_property(
2576 connector->dev->mode_config.scaling_mode_property,
2577 DRM_MODE_SCALE_ASPECT);
2578 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2583 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2584 struct intel_dp *intel_dp,
2585 struct edp_power_seq *out)
2587 struct drm_i915_private *dev_priv = dev->dev_private;
2588 struct edp_power_seq cur, vbt, spec, final;
2589 u32 pp_on, pp_off, pp_div, pp;
2591 /* Workaround: Need to write PP_CONTROL with the unlock key as
2592 * the very first thing. */
2593 pp = ironlake_get_pp_control(dev_priv);
2594 I915_WRITE(PCH_PP_CONTROL, pp);
2596 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2597 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2598 pp_div = I915_READ(PCH_PP_DIVISOR);
2600 /* Pull timing values out of registers */
2601 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2602 PANEL_POWER_UP_DELAY_SHIFT;
2604 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2605 PANEL_LIGHT_ON_DELAY_SHIFT;
2607 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2608 PANEL_LIGHT_OFF_DELAY_SHIFT;
2610 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2611 PANEL_POWER_DOWN_DELAY_SHIFT;
2613 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2614 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2616 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2617 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2619 vbt = dev_priv->edp.pps;
2621 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2622 * our hw here, which are all in 100usec. */
2623 spec.t1_t3 = 210 * 10;
2624 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2625 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2626 spec.t10 = 500 * 10;
2627 /* This one is special and actually in units of 100ms, but zero
2628 * based in the hw (so we need to add 100 ms). But the sw vbt
2629 * table multiplies it with 1000 to make it in units of 100usec,
2631 spec.t11_t12 = (510 + 100) * 10;
2633 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2634 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2636 /* Use the max of the register settings and vbt. If both are
2637 * unset, fall back to the spec limits. */
2638 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2640 max(cur.field, vbt.field))
2641 assign_final(t1_t3);
2645 assign_final(t11_t12);
2648 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2649 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2650 intel_dp->backlight_on_delay = get_delay(t8);
2651 intel_dp->backlight_off_delay = get_delay(t9);
2652 intel_dp->panel_power_down_delay = get_delay(t10);
2653 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2656 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2657 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2658 intel_dp->panel_power_cycle_delay);
2660 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2661 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2668 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2669 struct intel_dp *intel_dp,
2670 struct edp_power_seq *seq)
2672 struct drm_i915_private *dev_priv = dev->dev_private;
2673 u32 pp_on, pp_off, pp_div;
2675 /* And finally store the new values in the power sequencer. */
2676 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2677 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2678 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2679 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2680 /* Compute the divisor for the pp clock, simply match the Bspec
2682 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2683 << PP_REFERENCE_DIVIDER_SHIFT;
2684 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2685 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2687 /* Haswell doesn't have any port selection bits for the panel
2688 * power sequencer any more. */
2689 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2690 if (is_cpu_edp(intel_dp))
2691 pp_on |= PANEL_POWER_PORT_DP_A;
2693 pp_on |= PANEL_POWER_PORT_DP_D;
2696 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2697 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2698 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2700 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2701 I915_READ(PCH_PP_ON_DELAYS),
2702 I915_READ(PCH_PP_OFF_DELAYS),
2703 I915_READ(PCH_PP_DIVISOR));
2707 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2708 struct intel_connector *intel_connector)
2710 struct drm_connector *connector = &intel_connector->base;
2711 struct intel_dp *intel_dp = &intel_dig_port->dp;
2712 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2713 struct drm_device *dev = intel_encoder->base.dev;
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 struct drm_display_mode *fixed_mode = NULL;
2716 struct edp_power_seq power_seq = { 0 };
2717 enum port port = intel_dig_port->port;
2718 const char *name = NULL;
2721 /* Preserve the current hw state. */
2722 intel_dp->DP = I915_READ(intel_dp->output_reg);
2723 intel_dp->attached_connector = intel_connector;
2725 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2726 if (intel_dpd_is_edp(dev))
2727 intel_dp->is_pch_edp = true;
2730 * FIXME : We need to initialize built-in panels before external panels.
2731 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2733 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2734 type = DRM_MODE_CONNECTOR_eDP;
2735 intel_encoder->type = INTEL_OUTPUT_EDP;
2736 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2737 type = DRM_MODE_CONNECTOR_eDP;
2738 intel_encoder->type = INTEL_OUTPUT_EDP;
2740 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2741 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2744 type = DRM_MODE_CONNECTOR_DisplayPort;
2747 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2748 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2750 connector->polled = DRM_CONNECTOR_POLL_HPD;
2751 connector->interlace_allowed = true;
2752 connector->doublescan_allowed = 0;
2754 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2755 ironlake_panel_vdd_work);
2757 intel_connector_attach_encoder(intel_connector, intel_encoder);
2759 drm_sysfs_connector_add(connector);
2762 if (IS_HASWELL(dev))
2763 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2765 intel_connector->get_hw_state = intel_connector_get_hw_state;
2767 /* Set up the DDC bus. */
2773 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2777 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2781 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2785 WARN(1, "Invalid port %c\n", port_name(port));
2789 if (is_edp(intel_dp))
2790 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2792 intel_dp_i2c_init(intel_dp, intel_connector, name);
2794 /* Cache DPCD and EDID for edp. */
2795 if (is_edp(intel_dp)) {
2797 struct drm_display_mode *scan;
2800 ironlake_edp_panel_vdd_on(intel_dp);
2801 ret = intel_dp_get_dpcd(intel_dp);
2802 ironlake_edp_panel_vdd_off(intel_dp, false);
2805 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2806 dev_priv->no_aux_handshake =
2807 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2808 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2810 /* if this fails, presume the device is a ghost */
2811 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2812 intel_dp_encoder_destroy(&intel_encoder->base);
2813 intel_dp_destroy(connector);
2817 /* We now know it's not a ghost, init power sequence regs. */
2818 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2821 ironlake_edp_panel_vdd_on(intel_dp);
2822 edid = drm_get_edid(connector, intel_dp->adapter);
2824 if (drm_add_edid_modes(connector, edid)) {
2825 drm_mode_connector_update_edid_property(connector, edid);
2826 drm_edid_to_eld(connector, edid);
2829 edid = ERR_PTR(-EINVAL);
2832 edid = ERR_PTR(-ENOENT);
2834 intel_connector->edid = edid;
2836 /* prefer fixed mode from EDID if available */
2837 list_for_each_entry(scan, &connector->probed_modes, head) {
2838 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2839 fixed_mode = drm_mode_duplicate(dev, scan);
2844 /* fallback to VBT if available for eDP */
2845 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2846 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2848 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2851 ironlake_edp_panel_vdd_off(intel_dp, false);
2854 if (is_edp(intel_dp)) {
2855 intel_panel_init(&intel_connector->panel, fixed_mode);
2856 intel_panel_setup_backlight(connector);
2859 intel_dp_add_properties(intel_dp, connector);
2861 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2862 * 0xd. Failure to do so will result in spurious interrupts being
2863 * generated on the port when a cable is not attached.
2865 if (IS_G4X(dev) && !IS_GM45(dev)) {
2866 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2867 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2872 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2874 struct intel_digital_port *intel_dig_port;
2875 struct intel_encoder *intel_encoder;
2876 struct drm_encoder *encoder;
2877 struct intel_connector *intel_connector;
2879 intel_dig_port = kmalloc(sizeof(struct intel_digital_port), M_DRM,
2881 if (!intel_dig_port)
2884 intel_connector = kmalloc(sizeof(struct intel_connector), M_DRM,
2886 if (!intel_connector) {
2887 kfree(intel_dig_port, M_DRM);
2891 intel_encoder = &intel_dig_port->base;
2892 encoder = &intel_encoder->base;
2894 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2895 DRM_MODE_ENCODER_TMDS);
2896 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2898 intel_encoder->enable = intel_enable_dp;
2899 intel_encoder->pre_enable = intel_pre_enable_dp;
2900 intel_encoder->disable = intel_disable_dp;
2901 intel_encoder->post_disable = intel_post_disable_dp;
2902 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2904 intel_dig_port->port = port;
2905 intel_dig_port->dp.output_reg = output_reg;
2907 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2908 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2909 intel_encoder->cloneable = false;
2910 intel_encoder->hot_plug = intel_dp_hot_plug;
2912 intel_dp_init_connector(intel_dig_port, intel_connector);