sys/dev/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <uapi_drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "atom.h"
  32
  33 static u8
  34 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  35 {
  36         u8 backlight_level;
  37         u32 bios_2_scratch;
  38
  39         if (rdev->family >= CHIP_R600)
  40                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  41         else
  42                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  43
  44         backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  45                            ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  46
  47         return backlight_level;
  48 }
  49
  50 static void
  51 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  52                                        u8 backlight_level)
  53 {
  54         u32 bios_2_scratch;
  55
  56         if (rdev->family >= CHIP_R600)
  57                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  58         else
  59                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  60
  61         bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  62         bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  63                            ATOM_S2_CURRENT_BL_LEVEL_MASK);
  64
  65         if (rdev->family >= CHIP_R600)
  66                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  67         else
  68                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  69 }
  70
  71 u8
  72 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  73 {
  74         struct drm_device *dev = radeon_encoder->base.dev;
  75         struct radeon_device *rdev = dev->dev_private;
  76
  77         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  78                 return 0;
  79
  80         return radeon_atom_get_backlight_level_from_reg(rdev);
  81 }
  82
  83 void
  84 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  85 {
  86         struct drm_encoder *encoder = &radeon_encoder->base;
  87         struct drm_device *dev = radeon_encoder->base.dev;
  88         struct radeon_device *rdev = dev->dev_private;
  89         struct radeon_encoder_atom_dig *dig;
  90         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  91         int index;
  92
  93         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  94                 return;
  95
  96         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
  97             radeon_encoder->enc_priv) {
  98                 dig = radeon_encoder->enc_priv;
  99                 dig->backlight_level = level;
 100                 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 101
 102                 switch (radeon_encoder->encoder_id) {
 103                 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 104                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 105                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 106                         if (dig->backlight_level == 0) {
 107                                 args.ucAction = ATOM_LCD_BLOFF;
 108                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 109                         } else {
 110                                 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 111                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 112                                 args.ucAction = ATOM_LCD_BLON;
 113                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 114                         }
 115                         break;
 116                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 117                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 118                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 119                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 120                         if (dig->backlight_level == 0)
 121                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 122                         else {
 123                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 124                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 125                         }
 126                         break;
 127                 default:
 128                         break;
 129                 }
 130         }
 131 }
 132
 133 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 134
 135 static u8 radeon_atom_bl_level(struct backlight_device *bd)
 136 {
 137         u8 level;
 138
 139         /* Convert brightness to hardware level */
 140         if (bd->props.brightness < 0)
 141                 level = 0;
 142         else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 143                 level = RADEON_MAX_BL_LEVEL;
 144         else
 145                 level = bd->props.brightness;
 146
 147         return level;
 148 }
 149
 150 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 151 {
 152         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 153         struct radeon_encoder *radeon_encoder = pdata->encoder;
 154
 155         atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 156
 157         return 0;
 158 }
 159
 160 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 161 {
 162         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 163         struct radeon_encoder *radeon_encoder = pdata->encoder;
 164         struct drm_device *dev = radeon_encoder->base.dev;
 165         struct radeon_device *rdev = dev->dev_private;
 166
 167         return radeon_atom_get_backlight_level_from_reg(rdev);
 168 }
 169
 170 static const struct backlight_ops radeon_atom_backlight_ops = {
 171         .get_brightness = radeon_atom_backlight_get_brightness,
 172         .update_status  = radeon_atom_backlight_update_status,
 173 };
 174
 175 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 176                                 struct drm_connector *drm_connector)
 177 {
 178         struct drm_device *dev = radeon_encoder->base.dev;
 179         struct radeon_device *rdev = dev->dev_private;
 180         struct backlight_device *bd;
 181         struct backlight_properties props;
 182         struct radeon_backlight_privdata *pdata;
 183         struct radeon_encoder_atom_dig *dig;
 184         u8 backlight_level;
 185         char bl_name[16];
 186
 187         /* Mac laptops with multiple GPUs use the gmux driver for backlight
 188          * so don't register a backlight device
 189          */
 190         if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 191             (rdev->ddev->pci_device == 0x6741))
 192                 return;
 193
 194         if (!radeon_encoder->enc_priv)
 195                 return;
 196
 197         if (!rdev->is_atom_bios)
 198                 return;
 199
 200         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 201                 return;
 202
 203         pdata = kmalloc(sizeof(struct radeon_backlight_privdata),
 204                         M_DRM, M_WAITOK);
 205         if (!pdata) {
 206                 DRM_ERROR("Memory allocation failed\n");
 207                 goto error;
 208         }
 209
 210         memset(&props, 0, sizeof(props));
 211         props.max_brightness = RADEON_MAX_BL_LEVEL;
 212         props.type = BACKLIGHT_RAW;
 213         snprintf(bl_name, sizeof(bl_name),
 214                  "radeon_bl%d", dev->primary->index);
 215         bd = backlight_device_register(bl_name, &drm_connector->kdev,
 216                                        pdata, &radeon_atom_backlight_ops, &props);
 217         if (IS_ERR(bd)) {
 218                 DRM_ERROR("Backlight registration failed\n");
 219                 goto error;
 220         }
 221
 222         pdata->encoder = radeon_encoder;
 223
 224         backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
 225
 226         dig = radeon_encoder->enc_priv;
 227         dig->bl_dev = bd;
 228
 229         bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 230         bd->props.power = FB_BLANK_UNBLANK;
 231         backlight_update_status(bd);
 232
 233         DRM_INFO("radeon atom DIG backlight initialized\n");
 234
 235         return;
 236
 237 error:
 238         kfree(pdata);
 239         return;
 240 }
 241
 242 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 243 {
 244         struct drm_device *dev = radeon_encoder->base.dev;
 245         struct radeon_device *rdev = dev->dev_private;
 246         struct backlight_device *bd = NULL;
 247         struct radeon_encoder_atom_dig *dig;
 248
 249         if (!radeon_encoder->enc_priv)
 250                 return;
 251
 252         if (!rdev->is_atom_bios)
 253                 return;
 254
 255         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 256                 return;
 257
 258         dig = radeon_encoder->enc_priv;
 259         bd = dig->bl_dev;
 260         dig->bl_dev = NULL;
 261
 262         if (bd) {
 263                 struct radeon_legacy_backlight_privdata *pdata;
 264
 265                 pdata = bl_get_data(bd);
 266                 backlight_device_unregister(bd);
 267                 kfree(pdata);
 268
 269                 DRM_INFO("radeon atom LVDS backlight unloaded\n");
 270         }
 271 }
 272
 273 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 274
 275 /*
 276  * Read max backlight level
 277  */
 278 static int
 279 sysctl_backlight_max(SYSCTL_HANDLER_ARGS)
 280 {
 281         int err, val;
 282
 283         val = RADEON_MAX_BL_LEVEL;
 284         err = sysctl_handle_int(oidp, &val, 0, req);
 285         return(err);
 286 }
 287
 288 /*
 289  * Read/write backlight level
 290  */
 291 static int
 292 sysctl_backlight_handler(SYSCTL_HANDLER_ARGS)
 293 {
 294         struct radeon_encoder *encoder;
 295         struct radeon_encoder_atom_dig *dig;
 296         int err, val;
 297
 298         encoder = (struct radeon_encoder *)arg1;
 299         dig = encoder->enc_priv;
 300         val = dig->backlight_level;
 301
 302         err = sysctl_handle_int(oidp, &val, 0, req);
 303         if (err != 0 || req->newptr == NULL) {
 304                 return(err);
 305         }
 306         if (dig->backlight_level != val && val >= 0 &&
 307             val <= RADEON_MAX_BL_LEVEL) {
 308                 atombios_set_backlight_level(encoder, val);
 309         }
 310
 311         return(err);
 312 }
 313
 314 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 315                                 struct drm_connector *drm_connector)
 316 {
 317         struct drm_device *dev = radeon_encoder->base.dev;
 318         struct radeon_device *rdev = dev->dev_private;
 319         struct radeon_encoder_atom_dig *dig;
 320
 321         if (!radeon_encoder->enc_priv)
 322                 return;
 323
 324         if (!rdev->is_atom_bios)
 325                 return;
 326
 327         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 328                 return;
 329
 330         dig = radeon_encoder->enc_priv;
 331         dig->backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
 332
 333         DRM_INFO("radeon atom DIG backlight initialized\n");
 334
 335         SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children,
 336                         OID_AUTO, "backlight_max",
 337                         CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_ANYBODY,
 338                         radeon_encoder, sizeof(int),
 339                         sysctl_backlight_max,
 340                         "I", "Max backlight level");
 341         SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children,
 342                         OID_AUTO, "backlight_level",
 343                         CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_ANYBODY,
 344                         radeon_encoder, sizeof(int),
 345                         sysctl_backlight_handler,
 346                         "I", "Backlight level");
 347         return;
 348 }
 349
 350 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
 351 {
 352 }
 353
 354 #endif
 355
 356
 357 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 358 {
 359         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 360         switch (radeon_encoder->encoder_id) {
 361         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 362         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 363         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 364         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 365         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 366         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 367         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 368         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 369         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 370         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 371         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 372         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
 373                 return true;
 374         default:
 375                 return false;
 376         }
 377 }
 378
 379 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 380                                    const struct drm_display_mode *mode,
 381                                    struct drm_display_mode *adjusted_mode)
 382 {
 383         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 384         struct drm_device *dev = encoder->dev;
 385         struct radeon_device *rdev = dev->dev_private;
 386
 387         /* set the active encoder to connector routing */
 388         radeon_encoder_set_active_device(encoder);
 389         drm_mode_set_crtcinfo(adjusted_mode, 0);
 390
 391         /* hw bug */
 392         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 393             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 394                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 395
 396         /* get the native mode for LVDS */
 397         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 398                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 399
 400         /* get the native mode for TV */
 401         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 402                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 403                 if (tv_dac) {
 404                         if (tv_dac->tv_std == TV_STD_NTSC ||
 405                             tv_dac->tv_std == TV_STD_NTSC_J ||
 406                             tv_dac->tv_std == TV_STD_PAL_M)
 407                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 408                         else
 409                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 410                 }
 411         }
 412
 413         if (ASIC_IS_DCE3(rdev) &&
 414             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 415              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 416                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 417                 radeon_dp_set_link_config(connector, adjusted_mode);
 418         }
 419
 420         return true;
 421 }
 422
 423 static void
 424 atombios_dac_setup(struct drm_encoder *encoder, int action)
 425 {
 426         struct drm_device *dev = encoder->dev;
 427         struct radeon_device *rdev = dev->dev_private;
 428         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 429         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 430         int index = 0;
 431         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 432
 433         memset(&args, 0, sizeof(args));
 434
 435         switch (radeon_encoder->encoder_id) {
 436         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 437         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 438                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 439                 break;
 440         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 441         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 442                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 443                 break;
 444         }
 445
 446         args.ucAction = action;
 447
 448         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 449                 args.ucDacStandard = ATOM_DAC1_PS2;
 450         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 451                 args.ucDacStandard = ATOM_DAC1_CV;
 452         else {
 453                 switch (dac_info->tv_std) {
 454                 case TV_STD_PAL:
 455                 case TV_STD_PAL_M:
 456                 case TV_STD_SCART_PAL:
 457                 case TV_STD_SECAM:
 458                 case TV_STD_PAL_CN:
 459                         args.ucDacStandard = ATOM_DAC1_PAL;
 460                         break;
 461                 case TV_STD_NTSC:
 462                 case TV_STD_NTSC_J:
 463                 case TV_STD_PAL_60:
 464                 default:
 465                         args.ucDacStandard = ATOM_DAC1_NTSC;
 466                         break;
 467                 }
 468         }
 469         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 470
 471         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 472
 473 }
 474
 475 static void
 476 atombios_tv_setup(struct drm_encoder *encoder, int action)
 477 {
 478         struct drm_device *dev = encoder->dev;
 479         struct radeon_device *rdev = dev->dev_private;
 480         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 481         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 482         int index = 0;
 483         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 484
 485         memset(&args, 0, sizeof(args));
 486
 487         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 488
 489         args.sTVEncoder.ucAction = action;
 490
 491         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 492                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 493         else {
 494                 switch (dac_info->tv_std) {
 495                 case TV_STD_NTSC:
 496                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 497                         break;
 498                 case TV_STD_PAL:
 499                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 500                         break;
 501                 case TV_STD_PAL_M:
 502                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 503                         break;
 504                 case TV_STD_PAL_60:
 505                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 506                         break;
 507                 case TV_STD_NTSC_J:
 508                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 509                         break;
 510                 case TV_STD_SCART_PAL:
 511                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 512                         break;
 513                 case TV_STD_SECAM:
 514                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 515                         break;
 516                 case TV_STD_PAL_CN:
 517                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 518                         break;
 519                 default:
 520                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 521                         break;
 522                 }
 523         }
 524
 525         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 526
 527         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 528
 529 }
 530
 531 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 532 {
 533         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 534         int bpc = 8;
 535
 536         if (connector)
 537                 bpc = radeon_get_monitor_bpc(connector);
 538
 539         switch (bpc) {
 540         case 0:
 541                 return PANEL_BPC_UNDEFINE;
 542         case 6:
 543                 return PANEL_6BIT_PER_COLOR;
 544         case 8:
 545         default:
 546                 return PANEL_8BIT_PER_COLOR;
 547         case 10:
 548                 return PANEL_10BIT_PER_COLOR;
 549         case 12:
 550                 return PANEL_12BIT_PER_COLOR;
 551         case 16:
 552                 return PANEL_16BIT_PER_COLOR;
 553         }
 554 }
 555
 556 union dvo_encoder_control {
 557         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 558         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 559         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 560         DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
 561 };
 562
 563 void
 564 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 565 {
 566         struct drm_device *dev = encoder->dev;
 567         struct radeon_device *rdev = dev->dev_private;
 568         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 569         union dvo_encoder_control args;
 570         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 571         uint8_t frev, crev;
 572
 573         memset(&args, 0, sizeof(args));
 574
 575         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 576                 return;
 577
 578         /* some R4xx chips have the wrong frev */
 579         if (rdev->family <= CHIP_RV410)
 580                 frev = 1;
 581
 582         switch (frev) {
 583         case 1:
 584                 switch (crev) {
 585                 case 1:
 586                         /* R4xx, R5xx */
 587                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 588
 589                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 590                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 591
 592                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 593                         break;
 594                 case 2:
 595                         /* RS600/690/740 */
 596                         args.dvo.sDVOEncoder.ucAction = action;
 597                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 598                         /* DFP1, CRT1, TV1 depending on the type of port */
 599                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 600
 601                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 602                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 603                         break;
 604                 case 3:
 605                         /* R6xx */
 606                         args.dvo_v3.ucAction = action;
 607                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 608                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 609                         break;
 610                 case 4:
 611                         /* DCE8 */
 612                         args.dvo_v4.ucAction = action;
 613                         args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 614                         args.dvo_v4.ucDVOConfig = 0; /* XXX */
 615                         args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 616                         break;
 617                 default:
 618                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 619                         break;
 620                 }
 621                 break;
 622         default:
 623                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 624                 break;
 625         }
 626
 627         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 628 }
 629
 630 union lvds_encoder_control {
 631         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 632         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 633 };
 634
 635 void
 636 atombios_digital_setup(struct drm_encoder *encoder, int action)
 637 {
 638         struct drm_device *dev = encoder->dev;
 639         struct radeon_device *rdev = dev->dev_private;
 640         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 641         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 642         union lvds_encoder_control args;
 643         int index = 0;
 644         int hdmi_detected = 0;
 645         uint8_t frev, crev;
 646
 647         if (!dig)
 648                 return;
 649
 650         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 651                 hdmi_detected = 1;
 652
 653         memset(&args, 0, sizeof(args));
 654
 655         switch (radeon_encoder->encoder_id) {
 656         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 657                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 658                 break;
 659         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 660         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 661                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 662                 break;
 663         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 664                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 665                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 666                 else
 667                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 668                 break;
 669         }
 670
 671         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 672                 return;
 673
 674         switch (frev) {
 675         case 1:
 676         case 2:
 677                 switch (crev) {
 678                 case 1:
 679                         args.v1.ucMisc = 0;
 680                         args.v1.ucAction = action;
 681                         if (hdmi_detected)
 682                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 683                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 684                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 685                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 686                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 687                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 688                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 689                         } else {
 690                                 if (dig->linkb)
 691                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 692                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 693                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 694                                 /*if (pScrn->rgbBits == 8) */
 695                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 696                         }
 697                         break;
 698                 case 2:
 699                 case 3:
 700                         args.v2.ucMisc = 0;
 701                         args.v2.ucAction = action;
 702                         if (crev == 3) {
 703                                 if (dig->coherent_mode)
 704                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 705                         }
 706                         if (hdmi_detected)
 707                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 708                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 709                         args.v2.ucTruncate = 0;
 710                         args.v2.ucSpatial = 0;
 711                         args.v2.ucTemporal = 0;
 712                         args.v2.ucFRC = 0;
 713                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 714                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 715                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 716                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 717                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 718                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 719                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 720                                 }
 721                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 722                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 723                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 724                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 725                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 726                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 727                                 }
 728                         } else {
 729                                 if (dig->linkb)
 730                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 731                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 732                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 733                         }
 734                         break;
 735                 default:
 736                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 737                         break;
 738                 }
 739                 break;
 740         default:
 741                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 742                 break;
 743         }
 744
 745         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 746 }
 747
 748 int
 749 atombios_get_encoder_mode(struct drm_encoder *encoder)
 750 {
 751         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 752         struct drm_connector *connector;
 753         struct radeon_connector *radeon_connector;
 754         struct radeon_connector_atom_dig *dig_connector;
 755
 756         /* dp bridges are always DP */
 757         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 758                 return ATOM_ENCODER_MODE_DP;
 759
 760         /* DVO is always DVO */
 761         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 762             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 763                 return ATOM_ENCODER_MODE_DVO;
 764
 765         connector = radeon_get_connector_for_encoder(encoder);
 766         /* if we don't have an active device yet, just use one of
 767          * the connectors tied to the encoder.
 768          */
 769         if (!connector)
 770                 connector = radeon_get_connector_for_encoder_init(encoder);
 771         radeon_connector = to_radeon_connector(connector);
 772
 773         switch (connector->connector_type) {
 774         case DRM_MODE_CONNECTOR_DVII:
 775         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 776                 if (radeon_audio != 0) {
 777                         if (radeon_connector->use_digital &&
 778                             (radeon_connector->audio == RADEON_AUDIO_ENABLE))
 779                                 return ATOM_ENCODER_MODE_HDMI;
 780                         else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 781                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 782                                 return ATOM_ENCODER_MODE_HDMI;
 783                         else if (radeon_connector->use_digital)
 784                                 return ATOM_ENCODER_MODE_DVI;
 785                         else
 786                                 return ATOM_ENCODER_MODE_CRT;
 787                 } else if (radeon_connector->use_digital) {
 788                         return ATOM_ENCODER_MODE_DVI;
 789                 } else {
 790                         return ATOM_ENCODER_MODE_CRT;
 791                 }
 792                 break;
 793         case DRM_MODE_CONNECTOR_DVID:
 794         case DRM_MODE_CONNECTOR_HDMIA:
 795         default:
 796                 if (radeon_audio != 0) {
 797                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 798                                 return ATOM_ENCODER_MODE_HDMI;
 799                         else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 800                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 801                                 return ATOM_ENCODER_MODE_HDMI;
 802                         else
 803                                 return ATOM_ENCODER_MODE_DVI;
 804                 } else {
 805                         return ATOM_ENCODER_MODE_DVI;
 806                 }
 807                 break;
 808         case DRM_MODE_CONNECTOR_LVDS:
 809                 return ATOM_ENCODER_MODE_LVDS;
 810                 break;
 811         case DRM_MODE_CONNECTOR_DisplayPort:
 812                 dig_connector = radeon_connector->con_priv;
 813                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 814                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 815                         return ATOM_ENCODER_MODE_DP;
 816                 } else if (radeon_audio != 0) {
 817                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 818                                 return ATOM_ENCODER_MODE_HDMI;
 819                         else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 820                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 821                                 return ATOM_ENCODER_MODE_HDMI;
 822                         else
 823                                 return ATOM_ENCODER_MODE_DVI;
 824                 } else {
 825                         return ATOM_ENCODER_MODE_DVI;
 826                 }
 827                 break;
 828         case DRM_MODE_CONNECTOR_eDP:
 829                 return ATOM_ENCODER_MODE_DP;
 830         case DRM_MODE_CONNECTOR_DVIA:
 831         case DRM_MODE_CONNECTOR_VGA:
 832                 return ATOM_ENCODER_MODE_CRT;
 833                 break;
 834         case DRM_MODE_CONNECTOR_Composite:
 835         case DRM_MODE_CONNECTOR_SVIDEO:
 836         case DRM_MODE_CONNECTOR_9PinDIN:
 837                 /* fix me */
 838                 return ATOM_ENCODER_MODE_TV;
 839                 /*return ATOM_ENCODER_MODE_CV;*/
 840                 break;
 841         }
 842 }
 843
 844 /*
 845  * DIG Encoder/Transmitter Setup
 846  *
 847  * DCE 3.0/3.1
 848  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 849  * Supports up to 3 digital outputs
 850  * - 2 DIG encoder blocks.
 851  * DIG1 can drive UNIPHY link A or link B
 852  * DIG2 can drive UNIPHY link B or LVTMA
 853  *
 854  * DCE 3.2
 855  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 856  * Supports up to 5 digital outputs
 857  * - 2 DIG encoder blocks.
 858  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 859  *
 860  * DCE 4.0/5.0/6.0
 861  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 862  * Supports up to 6 digital outputs
 863  * - 6 DIG encoder blocks.
 864  * - DIG to PHY mapping is hardcoded
 865  * DIG1 drives UNIPHY0 link A, A+B
 866  * DIG2 drives UNIPHY0 link B
 867  * DIG3 drives UNIPHY1 link A, A+B
 868  * DIG4 drives UNIPHY1 link B
 869  * DIG5 drives UNIPHY2 link A, A+B
 870  * DIG6 drives UNIPHY2 link B
 871  *
 872  * DCE 4.1
 873  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 874  * Supports up to 6 digital outputs
 875  * - 2 DIG encoder blocks.
 876  * llano
 877  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 878  * ontario
 879  * DIG1 drives UNIPHY0/1/2 link A
 880  * DIG2 drives UNIPHY0/1/2 link B
 881  *
 882  * Routing
 883  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 884  * Examples:
 885  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 886  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 887  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 888  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 889  */
 890
 891 union dig_encoder_control {
 892         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 893         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 894         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 895         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 896 };
 897
 898 void
 899 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 900 {
 901         struct drm_device *dev = encoder->dev;
 902         struct radeon_device *rdev = dev->dev_private;
 903         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 904         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 905         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 906         union dig_encoder_control args;
 907         int index = 0;
 908         uint8_t frev, crev;
 909         int dp_clock = 0;
 910         int dp_lane_count = 0;
 911         int hpd_id = RADEON_HPD_NONE;
 912
 913         if (connector) {
 914                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 915                 struct radeon_connector_atom_dig *dig_connector =
 916                         radeon_connector->con_priv;
 917
 918                 dp_clock = dig_connector->dp_clock;
 919                 dp_lane_count = dig_connector->dp_lane_count;
 920                 hpd_id = radeon_connector->hpd.hpd;
 921         }
 922
 923         /* no dig encoder assigned */
 924         if (dig->dig_encoder == -1)
 925                 return;
 926
 927         memset(&args, 0, sizeof(args));
 928
 929         if (ASIC_IS_DCE4(rdev))
 930                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 931         else {
 932                 if (dig->dig_encoder)
 933                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 934                 else
 935                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 936         }
 937
 938         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 939                 return;
 940
 941         switch (frev) {
 942         case 1:
 943                 switch (crev) {
 944                 case 1:
 945                         args.v1.ucAction = action;
 946                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 947                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 948                                 args.v3.ucPanelMode = panel_mode;
 949                         else
 950                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 951
 952                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 953                                 args.v1.ucLaneNum = dp_lane_count;
 954                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 955                                 args.v1.ucLaneNum = 8;
 956                         else
 957                                 args.v1.ucLaneNum = 4;
 958
 959                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 960                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 961                         switch (radeon_encoder->encoder_id) {
 962                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 963                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 964                                 break;
 965                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 966                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 967                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 968                                 break;
 969                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 970                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 971                                 break;
 972                         }
 973                         if (dig->linkb)
 974                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 975                         else
 976                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 977                         break;
 978                 case 2:
 979                 case 3:
 980                         args.v3.ucAction = action;
 981                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 982                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 983                                 args.v3.ucPanelMode = panel_mode;
 984                         else
 985                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 986
 987                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 988                                 args.v3.ucLaneNum = dp_lane_count;
 989                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 990                                 args.v3.ucLaneNum = 8;
 991                         else
 992                                 args.v3.ucLaneNum = 4;
 993
 994                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 995                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 996                         args.v3.acConfig.ucDigSel = dig->dig_encoder;
 997                         args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 998                         break;
 999                 case 4:
1000                         args.v4.ucAction = action;
1001                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1002                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
1003                                 args.v4.ucPanelMode = panel_mode;
1004                         else
1005                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
1006
1007                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
1008                                 args.v4.ucLaneNum = dp_lane_count;
1009                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1010                                 args.v4.ucLaneNum = 8;
1011                         else
1012                                 args.v4.ucLaneNum = 4;
1013
1014                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
1015                                 if (dp_clock == 540000)
1016                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
1017                                 else if (dp_clock == 324000)
1018                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
1019                                 else if (dp_clock == 270000)
1020                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
1021                                 else
1022                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
1023                         }
1024                         args.v4.acConfig.ucDigSel = dig->dig_encoder;
1025                         args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
1026                         if (hpd_id == RADEON_HPD_NONE)
1027                                 args.v4.ucHPD_ID = 0;
1028                         else
1029                                 args.v4.ucHPD_ID = hpd_id + 1;
1030                         break;
1031                 default:
1032                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1033                         break;
1034                 }
1035                 break;
1036         default:
1037                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1038                 break;
1039         }
1040
1041         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1042
1043 }
1044
1045 union dig_transmitter_control {
1046         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
1047         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
1048         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
1049         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
1050         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
1051 };
1052
1053 void
1054 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1055 {
1056         struct drm_device *dev = encoder->dev;
1057         struct radeon_device *rdev = dev->dev_private;
1058         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1059         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1060         struct drm_connector *connector;
1061         union dig_transmitter_control args;
1062         int index = 0;
1063         uint8_t frev, crev;
1064         bool is_dp = false;
1065         int pll_id = 0;
1066         int dp_clock = 0;
1067         int dp_lane_count = 0;
1068         int connector_object_id = 0;
1069         int igp_lane_info = 0;
1070         int dig_encoder = dig->dig_encoder;
1071         int hpd_id = RADEON_HPD_NONE;
1072
1073         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1074                 connector = radeon_get_connector_for_encoder_init(encoder);
1075                 /* just needed to avoid bailing in the encoder check.  the encoder
1076                  * isn't used for init
1077                  */
1078                 dig_encoder = 0;
1079         } else
1080                 connector = radeon_get_connector_for_encoder(encoder);
1081
1082         if (connector) {
1083                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1084                 struct radeon_connector_atom_dig *dig_connector =
1085                         radeon_connector->con_priv;
1086
1087                 hpd_id = radeon_connector->hpd.hpd;
1088                 dp_clock = dig_connector->dp_clock;
1089                 dp_lane_count = dig_connector->dp_lane_count;
1090                 connector_object_id =
1091                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1092                 igp_lane_info = dig_connector->igp_lane_info;
1093         }
1094
1095         if (encoder->crtc) {
1096                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1097                 pll_id = radeon_crtc->pll_id;
1098         }
1099
1100         /* no dig encoder assigned */
1101         if (dig_encoder == -1)
1102                 return;
1103
1104         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1105                 is_dp = true;
1106
1107         memset(&args, 0, sizeof(args));
1108
1109         switch (radeon_encoder->encoder_id) {
1110         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1111                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1112                 break;
1113         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1114         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1115         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1116         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1117                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1118                 break;
1119         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1120                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1121                 break;
1122         }
1123
1124         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1125                 return;
1126
1127         switch (frev) {
1128         case 1:
1129                 switch (crev) {
1130                 case 1:
1131                         args.v1.ucAction = action;
1132                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1133                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1134                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1135                                 args.v1.asMode.ucLaneSel = lane_num;
1136                                 args.v1.asMode.ucLaneSet = lane_set;
1137                         } else {
1138                                 if (is_dp)
1139                                         args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1140                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1141                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1142                                 else
1143                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1144                         }
1145
1146                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1147
1148                         if (dig_encoder)
1149                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1150                         else
1151                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1152
1153                         if ((rdev->flags & RADEON_IS_IGP) &&
1154                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1155                                 if (is_dp ||
1156                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1157                                         if (igp_lane_info & 0x1)
1158                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1159                                         else if (igp_lane_info & 0x2)
1160                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1161                                         else if (igp_lane_info & 0x4)
1162                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1163                                         else if (igp_lane_info & 0x8)
1164                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1165                                 } else {
1166                                         if (igp_lane_info & 0x3)
1167                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1168                                         else if (igp_lane_info & 0xc)
1169                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1170                                 }
1171                         }
1172
1173                         if (dig->linkb)
1174                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1175                         else
1176                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1177
1178                         if (is_dp)
1179                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1180                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1181                                 if (dig->coherent_mode)
1182                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1183                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1184                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1185                         }
1186                         break;
1187                 case 2:
1188                         args.v2.ucAction = action;
1189                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1190                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1191                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1192                                 args.v2.asMode.ucLaneSel = lane_num;
1193                                 args.v2.asMode.ucLaneSet = lane_set;
1194                         } else {
1195                                 if (is_dp)
1196                                         args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1197                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1198                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1199                                 else
1200                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1201                         }
1202
1203                         args.v2.acConfig.ucEncoderSel = dig_encoder;
1204                         if (dig->linkb)
1205                                 args.v2.acConfig.ucLinkSel = 1;
1206
1207                         switch (radeon_encoder->encoder_id) {
1208                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1209                                 args.v2.acConfig.ucTransmitterSel = 0;
1210                                 break;
1211                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1212                                 args.v2.acConfig.ucTransmitterSel = 1;
1213                                 break;
1214                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1215                                 args.v2.acConfig.ucTransmitterSel = 2;
1216                                 break;
1217                         }
1218
1219                         if (is_dp) {
1220                                 args.v2.acConfig.fCoherentMode = 1;
1221                                 args.v2.acConfig.fDPConnector = 1;
1222                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1223                                 if (dig->coherent_mode)
1224                                         args.v2.acConfig.fCoherentMode = 1;
1225                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1226                                         args.v2.acConfig.fDualLinkConnector = 1;
1227                         }
1228                         break;
1229                 case 3:
1230                         args.v3.ucAction = action;
1231                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1232                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1233                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1234                                 args.v3.asMode.ucLaneSel = lane_num;
1235                                 args.v3.asMode.ucLaneSet = lane_set;
1236                         } else {
1237                                 if (is_dp)
1238                                         args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1239                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1240                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1241                                 else
1242                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1243                         }
1244
1245                         if (is_dp)
1246                                 args.v3.ucLaneNum = dp_lane_count;
1247                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1248                                 args.v3.ucLaneNum = 8;
1249                         else
1250                                 args.v3.ucLaneNum = 4;
1251
1252                         if (dig->linkb)
1253                                 args.v3.acConfig.ucLinkSel = 1;
1254                         if (dig_encoder & 1)
1255                                 args.v3.acConfig.ucEncoderSel = 1;
1256
1257                         /* Select the PLL for the PHY
1258                          * DP PHY should be clocked from external src if there is
1259                          * one.
1260                          */
1261                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1262                         if (is_dp && rdev->clock.dp_extclk)
1263                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1264                         else
1265                                 args.v3.acConfig.ucRefClkSource = pll_id;
1266
1267                         switch (radeon_encoder->encoder_id) {
1268                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1269                                 args.v3.acConfig.ucTransmitterSel = 0;
1270                                 break;
1271                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1272                                 args.v3.acConfig.ucTransmitterSel = 1;
1273                                 break;
1274                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1275                                 args.v3.acConfig.ucTransmitterSel = 2;
1276                                 break;
1277                         }
1278
1279                         if (is_dp)
1280                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1281                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1282                                 if (dig->coherent_mode)
1283                                         args.v3.acConfig.fCoherentMode = 1;
1284                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1285                                         args.v3.acConfig.fDualLinkConnector = 1;
1286                         }
1287                         break;
1288                 case 4:
1289                         args.v4.ucAction = action;
1290                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1291                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1292                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1293                                 args.v4.asMode.ucLaneSel = lane_num;
1294                                 args.v4.asMode.ucLaneSet = lane_set;
1295                         } else {
1296                                 if (is_dp)
1297                                         args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1298                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1299                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1300                                 else
1301                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1302                         }
1303
1304                         if (is_dp)
1305                                 args.v4.ucLaneNum = dp_lane_count;
1306                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1307                                 args.v4.ucLaneNum = 8;
1308                         else
1309                                 args.v4.ucLaneNum = 4;
1310
1311                         if (dig->linkb)
1312                                 args.v4.acConfig.ucLinkSel = 1;
1313                         if (dig_encoder & 1)
1314                                 args.v4.acConfig.ucEncoderSel = 1;
1315
1316                         /* Select the PLL for the PHY
1317                          * DP PHY should be clocked from external src if there is
1318                          * one.
1319                          */
1320                         /* On DCE5 DCPLL usually generates the DP ref clock */
1321                         if (is_dp) {
1322                                 if (rdev->clock.dp_extclk)
1323                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1324                                 else
1325                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1326                         } else
1327                                 args.v4.acConfig.ucRefClkSource = pll_id;
1328
1329                         switch (radeon_encoder->encoder_id) {
1330                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1331                                 args.v4.acConfig.ucTransmitterSel = 0;
1332                                 break;
1333                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1334                                 args.v4.acConfig.ucTransmitterSel = 1;
1335                                 break;
1336                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1337                                 args.v4.acConfig.ucTransmitterSel = 2;
1338                                 break;
1339                         }
1340
1341                         if (is_dp)
1342                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1343                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1344                                 if (dig->coherent_mode)
1345                                         args.v4.acConfig.fCoherentMode = 1;
1346                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1347                                         args.v4.acConfig.fDualLinkConnector = 1;
1348                         }
1349                         break;
1350                 case 5:
1351                         args.v5.ucAction = action;
1352                         if (is_dp)
1353                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1354                         else
1355                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1356
1357                         switch (radeon_encoder->encoder_id) {
1358                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1359                                 if (dig->linkb)
1360                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1361                                 else
1362                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1363                                 break;
1364                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1365                                 if (dig->linkb)
1366                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1367                                 else
1368                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1369                                 break;
1370                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1371                                 if (dig->linkb)
1372                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1373                                 else
1374                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1375                                 break;
1376                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1377                                 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1378                                 break;
1379                         }
1380                         if (is_dp)
1381                                 args.v5.ucLaneNum = dp_lane_count;
1382                         else if (radeon_encoder->pixel_clock > 165000)
1383                                 args.v5.ucLaneNum = 8;
1384                         else
1385                                 args.v5.ucLaneNum = 4;
1386                         args.v5.ucConnObjId = connector_object_id;
1387                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1388
1389                         if (is_dp && rdev->clock.dp_extclk)
1390                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1391                         else
1392                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1393
1394                         if (is_dp)
1395                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1396                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1397                                 if (dig->coherent_mode)
1398                                         args.v5.asConfig.ucCoherentMode = 1;
1399                         }
1400                         if (hpd_id == RADEON_HPD_NONE)
1401                                 args.v5.asConfig.ucHPDSel = 0;
1402                         else
1403                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1404                         args.v5.ucDigEncoderSel = 1 << dig_encoder;
1405                         args.v5.ucDPLaneSet = lane_set;
1406                         break;
1407                 default:
1408                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1409                         break;
1410                 }
1411                 break;
1412         default:
1413                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1414                 break;
1415         }
1416
1417         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1418 }
1419
1420 bool
1421 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1422 {
1423         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1424         struct drm_device *dev = radeon_connector->base.dev;
1425         struct radeon_device *rdev = dev->dev_private;
1426         union dig_transmitter_control args;
1427         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1428         uint8_t frev, crev;
1429
1430         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1431                 goto done;
1432
1433         if (!ASIC_IS_DCE4(rdev))
1434                 goto done;
1435
1436         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1437             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1438                 goto done;
1439
1440         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1441                 goto done;
1442
1443         memset(&args, 0, sizeof(args));
1444
1445         args.v1.ucAction = action;
1446
1447         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1448
1449         /* wait for the panel to power up */
1450         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1451                 int i;
1452
1453                 for (i = 0; i < 300; i++) {
1454                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1455                                 return true;
1456                         mdelay(1);
1457                 }
1458                 return false;
1459         }
1460 done:
1461         return true;
1462 }
1463
1464 union external_encoder_control {
1465         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1466         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1467 };
1468
1469 static void
1470 atombios_external_encoder_setup(struct drm_encoder *encoder,
1471                                 struct drm_encoder *ext_encoder,
1472                                 int action)
1473 {
1474         struct drm_device *dev = encoder->dev;
1475         struct radeon_device *rdev = dev->dev_private;
1476         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1477         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1478         union external_encoder_control args;
1479         struct drm_connector *connector;
1480         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1481         u8 frev, crev;
1482         int dp_clock = 0;
1483         int dp_lane_count = 0;
1484         int connector_object_id = 0;
1485         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1486
1487         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1488                 connector = radeon_get_connector_for_encoder_init(encoder);
1489         else
1490                 connector = radeon_get_connector_for_encoder(encoder);
1491
1492         if (connector) {
1493                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1494                 struct radeon_connector_atom_dig *dig_connector =
1495                         radeon_connector->con_priv;
1496
1497                 dp_clock = dig_connector->dp_clock;
1498                 dp_lane_count = dig_connector->dp_lane_count;
1499                 connector_object_id =
1500                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1501         }
1502
1503         memset(&args, 0, sizeof(args));
1504
1505         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1506                 return;
1507
1508         switch (frev) {
1509         case 1:
1510                 /* no params on frev 1 */
1511                 break;
1512         case 2:
1513                 switch (crev) {
1514                 case 1:
1515                 case 2:
1516                         args.v1.sDigEncoder.ucAction = action;
1517                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1518                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1519
1520                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1521                                 if (dp_clock == 270000)
1522                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1523                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1524                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1525                                 args.v1.sDigEncoder.ucLaneNum = 8;
1526                         else
1527                                 args.v1.sDigEncoder.ucLaneNum = 4;
1528                         break;
1529                 case 3:
1530                         args.v3.sExtEncoder.ucAction = action;
1531                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1532                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1533                         else
1534                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1535                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1536
1537                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1538                                 if (dp_clock == 270000)
1539                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1540                                 else if (dp_clock == 540000)
1541                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1542                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1543                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1544                                 args.v3.sExtEncoder.ucLaneNum = 8;
1545                         else
1546                                 args.v3.sExtEncoder.ucLaneNum = 4;
1547                         switch (ext_enum) {
1548                         case GRAPH_OBJECT_ENUM_ID1:
1549                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1550                                 break;
1551                         case GRAPH_OBJECT_ENUM_ID2:
1552                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1553                                 break;
1554                         case GRAPH_OBJECT_ENUM_ID3:
1555                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1556                                 break;
1557                         }
1558                         args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1559                         break;
1560                 default:
1561                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1562                         return;
1563                 }
1564                 break;
1565         default:
1566                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1567                 return;
1568         }
1569         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1570 }
1571
1572 static void
1573 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1574 {
1575         struct drm_device *dev = encoder->dev;
1576         struct radeon_device *rdev = dev->dev_private;
1577         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1578         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1579         ENABLE_YUV_PS_ALLOCATION args;
1580         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1581         uint32_t temp, reg;
1582
1583         memset(&args, 0, sizeof(args));
1584
1585         if (rdev->family >= CHIP_R600)
1586                 reg = R600_BIOS_3_SCRATCH;
1587         else
1588                 reg = RADEON_BIOS_3_SCRATCH;
1589
1590         /* XXX: fix up scratch reg handling */
1591         temp = RREG32(reg);
1592         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1593                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1594                              (radeon_crtc->crtc_id << 18)));
1595         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1596                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1597         else
1598                 WREG32(reg, 0);
1599
1600         if (enable)
1601                 args.ucEnable = ATOM_ENABLE;
1602         args.ucCRTC = radeon_crtc->crtc_id;
1603
1604         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1605
1606         WREG32(reg, temp);
1607 }
1608
1609 static void
1610 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1611 {
1612         struct drm_device *dev = encoder->dev;
1613         struct radeon_device *rdev = dev->dev_private;
1614         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1615         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1616         int index = 0;
1617
1618         memset(&args, 0, sizeof(args));
1619
1620         switch (radeon_encoder->encoder_id) {
1621         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1622         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1623                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1624                 break;
1625         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1626         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1627         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1628                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1629                 break;
1630         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1631                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1632                 break;
1633         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1634                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1635                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1636                 else
1637                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1638                 break;
1639         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1640         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1641                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1642                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1643                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1644                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1645                 else
1646                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1647                 break;
1648         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1649         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1650                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1651                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1652                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1653                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1654                 else
1655                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1656                 break;
1657         default:
1658                 return;
1659         }
1660
1661         switch (mode) {
1662         case DRM_MODE_DPMS_ON:
1663                 args.ucAction = ATOM_ENABLE;
1664                 /* workaround for DVOOutputControl on some RS690 systems */
1665                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1666                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1667                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1668                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1669                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1670                 } else
1671                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1672                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1673                         args.ucAction = ATOM_LCD_BLON;
1674                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1675                 }
1676                 break;
1677         case DRM_MODE_DPMS_STANDBY:
1678         case DRM_MODE_DPMS_SUSPEND:
1679         case DRM_MODE_DPMS_OFF:
1680                 args.ucAction = ATOM_DISABLE;
1681                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1682                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1683                         args.ucAction = ATOM_LCD_BLOFF;
1684                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1685                 }
1686                 break;
1687         }
1688 }
1689
1690 static void
1691 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1692 {
1693         struct drm_device *dev = encoder->dev;
1694         struct radeon_device *rdev = dev->dev_private;
1695         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1696         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1697         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1698         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1699         struct radeon_connector *radeon_connector = NULL;
1700         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1701
1702         if (connector) {
1703                 radeon_connector = to_radeon_connector(connector);
1704                 radeon_dig_connector = radeon_connector->con_priv;
1705         }
1706
1707         switch (mode) {
1708         case DRM_MODE_DPMS_ON:
1709                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1710                         if (!connector)
1711                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1712                         else
1713                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1714
1715                         /* setup and enable the encoder */
1716                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1717                         atombios_dig_encoder_setup(encoder,
1718                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1719                                                    dig->panel_mode);
1720                         if (ext_encoder) {
1721                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1722                                         atombios_external_encoder_setup(encoder, ext_encoder,
1723                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1724                         }
1725                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1726                 } else if (ASIC_IS_DCE4(rdev)) {
1727                         /* setup and enable the encoder */
1728                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1729                         /* enable the transmitter */
1730                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1731                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1732                 } else {
1733                         /* setup and enable the encoder and transmitter */
1734                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1735                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1736                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1737                         /* some dce3.x boards have a bug in their transmitter control table.
1738                          * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE
1739                          * does the same thing and more.
1740                          */
1741                         if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) &&
1742                             (rdev->family != CHIP_RS780) && (rdev->family != CHIP_RS880))
1743                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1744                 }
1745                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1746                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1747                                 atombios_set_edp_panel_power(connector,
1748                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1749                                 radeon_dig_connector->edp_on = true;
1750                         }
1751                         radeon_dp_link_train(encoder, connector);
1752                         if (ASIC_IS_DCE4(rdev))
1753                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1754                 }
1755                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1756                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1757                 break;
1758         case DRM_MODE_DPMS_STANDBY:
1759         case DRM_MODE_DPMS_SUSPEND:
1760         case DRM_MODE_DPMS_OFF:
1761                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1762                         /* disable the transmitter */
1763                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1764                 } else if (ASIC_IS_DCE4(rdev)) {
1765                         /* disable the transmitter */
1766                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1767                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1768                 } else {
1769                         /* disable the encoder and transmitter */
1770                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1771                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1772                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1773                 }
1774                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1775                         if (ASIC_IS_DCE4(rdev))
1776                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1777                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1778                                 atombios_set_edp_panel_power(connector,
1779                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1780                                 radeon_dig_connector->edp_on = false;
1781                         }
1782                 }
1783                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1784                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1785                 break;
1786         }
1787 }
1788
1789 static void
1790 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1791                              struct drm_encoder *ext_encoder,
1792                              int mode)
1793 {
1794         struct drm_device *dev = encoder->dev;
1795         struct radeon_device *rdev = dev->dev_private;
1796
1797         switch (mode) {
1798         case DRM_MODE_DPMS_ON:
1799         default:
1800                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1801                         atombios_external_encoder_setup(encoder, ext_encoder,
1802                                                         EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1803                         atombios_external_encoder_setup(encoder, ext_encoder,
1804                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1805                 } else
1806                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1807                 break;
1808         case DRM_MODE_DPMS_STANDBY:
1809         case DRM_MODE_DPMS_SUSPEND:
1810         case DRM_MODE_DPMS_OFF:
1811                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1812                         atombios_external_encoder_setup(encoder, ext_encoder,
1813                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1814                         atombios_external_encoder_setup(encoder, ext_encoder,
1815                                                         EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1816                 } else
1817                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1818                 break;
1819         }
1820 }
1821
1822 static void
1823 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1824 {
1825         struct drm_device *dev = encoder->dev;
1826         struct radeon_device *rdev = dev->dev_private;
1827         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1828         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1829
1830         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1831                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1832                   radeon_encoder->active_device);
1833         switch (radeon_encoder->encoder_id) {
1834         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1835         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1836         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1837         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1838         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1839         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1840         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1841         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1842                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1843                 break;
1844         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1845         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1846         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1847         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1848         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1849                 radeon_atom_encoder_dpms_dig(encoder, mode);
1850                 break;
1851         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1852                 if (ASIC_IS_DCE5(rdev)) {
1853                         switch (mode) {
1854                         case DRM_MODE_DPMS_ON:
1855                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1856                                 break;
1857                         case DRM_MODE_DPMS_STANDBY:
1858                         case DRM_MODE_DPMS_SUSPEND:
1859                         case DRM_MODE_DPMS_OFF:
1860                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1861                                 break;
1862                         }
1863                 } else if (ASIC_IS_DCE3(rdev))
1864                         radeon_atom_encoder_dpms_dig(encoder, mode);
1865                 else
1866                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1867                 break;
1868         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1869         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1870                 if (ASIC_IS_DCE5(rdev)) {
1871                         switch (mode) {
1872                         case DRM_MODE_DPMS_ON:
1873                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1874                                 break;
1875                         case DRM_MODE_DPMS_STANDBY:
1876                         case DRM_MODE_DPMS_SUSPEND:
1877                         case DRM_MODE_DPMS_OFF:
1878                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1879                                 break;
1880                         }
1881                 } else
1882                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1883                 break;
1884         default:
1885                 return;
1886         }
1887
1888         if (ext_encoder)
1889                 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1890
1891         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1892
1893 }
1894
1895 union crtc_source_param {
1896         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1897         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1898 };
1899
1900 static void
1901 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1902 {
1903         struct drm_device *dev = encoder->dev;
1904         struct radeon_device *rdev = dev->dev_private;
1905         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1906         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1907         union crtc_source_param args;
1908         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1909         uint8_t frev, crev;
1910         struct radeon_encoder_atom_dig *dig;
1911
1912         memset(&args, 0, sizeof(args));
1913
1914         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1915                 return;
1916
1917         switch (frev) {
1918         case 1:
1919                 switch (crev) {
1920                 case 1:
1921                 default:
1922                         if (ASIC_IS_AVIVO(rdev))
1923                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1924                         else {
1925                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1926                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1927                                 } else {
1928                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1929                                 }
1930                         }
1931                         switch (radeon_encoder->encoder_id) {
1932                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1933                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1934                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1935                                 break;
1936                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1937                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1938                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1939                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1940                                 else
1941                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1942                                 break;
1943                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1944                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1945                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1946                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1947                                 break;
1948                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1949                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1950                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1951                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1952                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1953                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1954                                 else
1955                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1956                                 break;
1957                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1958                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1959                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1960                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1961                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1962                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1963                                 else
1964                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1965                                 break;
1966                         }
1967                         break;
1968                 case 2:
1969                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1970                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1971                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1972
1973                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1974                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1975                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1976                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1977                                 else
1978                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1979                         } else
1980                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1981                         switch (radeon_encoder->encoder_id) {
1982                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1983                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1984                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1985                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1986                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1987                                 dig = radeon_encoder->enc_priv;
1988                                 switch (dig->dig_encoder) {
1989                                 case 0:
1990                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1991                                         break;
1992                                 case 1:
1993                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1994                                         break;
1995                                 case 2:
1996                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1997                                         break;
1998                                 case 3:
1999                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2000                                         break;
2001                                 case 4:
2002                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2003                                         break;
2004                                 case 5:
2005                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2006                                         break;
2007                                 case 6:
2008                                         args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2009                                         break;
2010                                 }
2011                                 break;
2012                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2013                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
2014                                 break;
2015                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2016                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
2017                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
2018                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
2019                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
2020                                 else
2021                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
2022                                 break;
2023                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2024                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
2025                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
2026                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
2027                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
2028                                 else
2029                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
2030                                 break;
2031                         }
2032                         break;
2033                 }
2034                 break;
2035         default:
2036                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
2037                 return;
2038         }
2039
2040         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2041
2042         /* update scratch regs with new routing */
2043         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
2044 }
2045
2046 static void
2047 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2048                               struct drm_display_mode *mode)
2049 {
2050         struct drm_device *dev = encoder->dev;
2051         struct radeon_device *rdev = dev->dev_private;
2052         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2053         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2054
2055         /* Funky macbooks */
2056         if ((dev->pci_device == 0x71C5) &&
2057             (dev->pci_subvendor == 0x106b) &&
2058             (dev->pci_subdevice == 0x0080)) {
2059                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2060                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2061
2062                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2063                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2064
2065                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2066                 }
2067         }
2068
2069         /* set scaler clears this on some chips */
2070         if (ASIC_IS_AVIVO(rdev) &&
2071             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2072                 if (ASIC_IS_DCE8(rdev)) {
2073                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2074                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2075                                        CIK_INTERLEAVE_EN);
2076                         else
2077                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2078                 } else if (ASIC_IS_DCE4(rdev)) {
2079                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2080                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2081                                        EVERGREEN_INTERLEAVE_EN);
2082                         else
2083                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2084                 } else {
2085                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2086                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2087                                        AVIVO_D1MODE_INTERLEAVE_EN);
2088                         else
2089                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2090                 }
2091         }
2092 }
2093
2094 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
2095 {
2096         struct drm_device *dev = encoder->dev;
2097         struct radeon_device *rdev = dev->dev_private;
2098         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2099         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2100         struct drm_encoder *test_encoder;
2101         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2102         uint32_t dig_enc_in_use = 0;
2103
2104         if (ASIC_IS_DCE6(rdev)) {
2105                 /* DCE6 */
2106                 switch (radeon_encoder->encoder_id) {
2107                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2108                         if (dig->linkb)
2109                                 return 1;
2110                         else
2111                                 return 0;
2112                         break;
2113                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2114                         if (dig->linkb)
2115                                 return 3;
2116                         else
2117                                 return 2;
2118                         break;
2119                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2120                         if (dig->linkb)
2121                                 return 5;
2122                         else
2123                                 return 4;
2124                         break;
2125                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2126                         return 6;
2127                         break;
2128                 }
2129         } else if (ASIC_IS_DCE4(rdev)) {
2130                 /* DCE4/5 */
2131                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2132                         /* ontario follows DCE4 */
2133                         if (rdev->family == CHIP_PALM) {
2134                                 if (dig->linkb)
2135                                         return 1;
2136                                 else
2137                                         return 0;
2138                         } else
2139                                 /* llano follows DCE3.2 */
2140                                 return radeon_crtc->crtc_id;
2141                 } else {
2142                         switch (radeon_encoder->encoder_id) {
2143                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2144                                 if (dig->linkb)
2145                                         return 1;
2146                                 else
2147                                         return 0;
2148                                 break;
2149                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2150                                 if (dig->linkb)
2151                                         return 3;
2152                                 else
2153                                         return 2;
2154                                 break;
2155                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2156                                 if (dig->linkb)
2157                                         return 5;
2158                                 else
2159                                         return 4;
2160                                 break;
2161                         }
2162                 }
2163         }
2164
2165         /* on DCE32 and encoder can driver any block so just crtc id */
2166         if (ASIC_IS_DCE32(rdev)) {
2167                 return radeon_crtc->crtc_id;
2168         }
2169
2170         /* on DCE3 - LVTMA can only be driven by DIGB */
2171         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2172                 struct radeon_encoder *radeon_test_encoder;
2173
2174                 if (encoder == test_encoder)
2175                         continue;
2176
2177                 if (!radeon_encoder_is_digital(test_encoder))
2178                         continue;
2179
2180                 radeon_test_encoder = to_radeon_encoder(test_encoder);
2181                 dig = radeon_test_encoder->enc_priv;
2182
2183                 if (dig->dig_encoder >= 0)
2184                         dig_enc_in_use |= (1 << dig->dig_encoder);
2185         }
2186
2187         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2188                 if (dig_enc_in_use & 0x2)
2189                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2190                 return 1;
2191         }
2192         if (!(dig_enc_in_use & 1))
2193                 return 0;
2194         return 1;
2195 }
2196
2197 /* This only needs to be called once at startup */
2198 void
2199 radeon_atom_encoder_init(struct radeon_device *rdev)
2200 {
2201         struct drm_device *dev = rdev->ddev;
2202         struct drm_encoder *encoder;
2203
2204         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2205                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2206                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2207
2208                 switch (radeon_encoder->encoder_id) {
2209                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2210                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2211                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2212                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2213                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2214                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2215                         break;
2216                 default:
2217                         break;
2218                 }
2219
2220                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2221                         atombios_external_encoder_setup(encoder, ext_encoder,
2222                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2223         }
2224 }
2225
2226 static void
2227 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2228                              struct drm_display_mode *mode,
2229                              struct drm_display_mode *adjusted_mode)
2230 {
2231         struct drm_device *dev = encoder->dev;
2232         struct radeon_device *rdev = dev->dev_private;
2233         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2234
2235         radeon_encoder->pixel_clock = adjusted_mode->clock;
2236
2237         /* need to call this here rather than in prepare() since we need some crtc info */
2238         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2239
2240         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2241                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2242                         atombios_yuv_setup(encoder, true);
2243                 else
2244                         atombios_yuv_setup(encoder, false);
2245         }
2246
2247         switch (radeon_encoder->encoder_id) {
2248         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2249         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2250         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2251         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2252                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2253                 break;
2254         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2255         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2256         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2257         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2258         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2259                 /* handled in dpms */
2260                 break;
2261         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2262         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2263         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2264                 atombios_dvo_setup(encoder, ATOM_ENABLE);
2265                 break;
2266         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2267         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2268         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2269         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2270                 atombios_dac_setup(encoder, ATOM_ENABLE);
2271                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2272                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2273                                 atombios_tv_setup(encoder, ATOM_ENABLE);
2274                         else
2275                                 atombios_tv_setup(encoder, ATOM_DISABLE);
2276                 }
2277                 break;
2278         }
2279
2280         atombios_apply_encoder_quirks(encoder, adjusted_mode);
2281
2282         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2283                 if (rdev->asic->display.hdmi_enable)
2284                         radeon_hdmi_enable(rdev, encoder, true);
2285                 if (rdev->asic->display.hdmi_setmode)
2286                         radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
2287         }
2288 }
2289
2290 static bool
2291 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2292 {
2293         struct drm_device *dev = encoder->dev;
2294         struct radeon_device *rdev = dev->dev_private;
2295         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2296         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2297
2298         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2299                                        ATOM_DEVICE_CV_SUPPORT |
2300                                        ATOM_DEVICE_CRT_SUPPORT)) {
2301                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2302                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2303                 uint8_t frev, crev;
2304
2305                 memset(&args, 0, sizeof(args));
2306
2307                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2308                         return false;
2309
2310                 args.sDacload.ucMisc = 0;
2311
2312                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2313                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2314                         args.sDacload.ucDacType = ATOM_DAC_A;
2315                 else
2316                         args.sDacload.ucDacType = ATOM_DAC_B;
2317
2318                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2319                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2320                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2321                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2322                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2323                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2324                         if (crev >= 3)
2325                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2326                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2327                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2328                         if (crev >= 3)
2329                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2330                 }
2331
2332                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2333
2334                 return true;
2335         } else
2336                 return false;
2337 }
2338
2339 static enum drm_connector_status
2340 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2341 {
2342         struct drm_device *dev = encoder->dev;
2343         struct radeon_device *rdev = dev->dev_private;
2344         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2345         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2346         uint32_t bios_0_scratch;
2347
2348         if (!atombios_dac_load_detect(encoder, connector)) {
2349                 DRM_DEBUG_KMS("detect returned false \n");
2350                 return connector_status_unknown;
2351         }
2352
2353         if (rdev->family >= CHIP_R600)
2354                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2355         else
2356                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2357
2358         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2359         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2360                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2361                         return connector_status_connected;
2362         }
2363         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2364                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2365                         return connector_status_connected;
2366         }
2367         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2368                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2369                         return connector_status_connected;
2370         }
2371         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2372                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2373                         return connector_status_connected; /* CTV */
2374                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2375                         return connector_status_connected; /* STV */
2376         }
2377         return connector_status_disconnected;
2378 }
2379
2380 static enum drm_connector_status
2381 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2382 {
2383         struct drm_device *dev = encoder->dev;
2384         struct radeon_device *rdev = dev->dev_private;
2385         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2386         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2387         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2388         u32 bios_0_scratch;
2389
2390         if (!ASIC_IS_DCE4(rdev))
2391                 return connector_status_unknown;
2392
2393         if (!ext_encoder)
2394                 return connector_status_unknown;
2395
2396         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2397                 return connector_status_unknown;
2398
2399         /* load detect on the dp bridge */
2400         atombios_external_encoder_setup(encoder, ext_encoder,
2401                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2402
2403         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2404
2405         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2406         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2407                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2408                         return connector_status_connected;
2409         }
2410         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2411                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2412                         return connector_status_connected;
2413         }
2414         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2415                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2416                         return connector_status_connected;
2417         }
2418         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2419                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2420                         return connector_status_connected; /* CTV */
2421                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2422                         return connector_status_connected; /* STV */
2423         }
2424         return connector_status_disconnected;
2425 }
2426
2427 void
2428 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2429 {
2430         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2431
2432         if (ext_encoder)
2433                 /* ddc_setup on the dp bridge */
2434                 atombios_external_encoder_setup(encoder, ext_encoder,
2435                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2436
2437 }
2438
2439 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2440 {
2441         struct radeon_device *rdev = encoder->dev->dev_private;
2442         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2443         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2444
2445         if ((radeon_encoder->active_device &
2446              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2447             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2448              ENCODER_OBJECT_ID_NONE)) {
2449                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2450                 if (dig) {
2451                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2452                         if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2453                                 if (rdev->family >= CHIP_R600)
2454                                         dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2455                                 else
2456                                         /* RS600/690/740 have only 1 afmt block */
2457                                         dig->afmt = rdev->mode_info.afmt[0];
2458                         }
2459                 }
2460         }
2461
2462         radeon_atom_output_lock(encoder, true);
2463
2464         if (connector) {
2465                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2466
2467                 /* select the clock/data port if it uses a router */
2468                 if (radeon_connector->router.cd_valid)
2469                         radeon_router_select_cd_port(radeon_connector);
2470
2471                 /* turn eDP panel on for mode set */
2472                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2473                         atombios_set_edp_panel_power(connector,
2474                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2475         }
2476
2477         /* this is needed for the pll/ss setup to work correctly in some cases */
2478         atombios_set_encoder_crtc_source(encoder);
2479 }
2480
2481 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2482 {
2483         /* need to call this here as we need the crtc set up */
2484         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2485         radeon_atom_output_lock(encoder, false);
2486 }
2487
2488 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2489 {
2490         struct drm_device *dev = encoder->dev;
2491         struct radeon_device *rdev = dev->dev_private;
2492         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2493         struct radeon_encoder_atom_dig *dig;
2494
2495         /* check for pre-DCE3 cards with shared encoders;
2496          * can't really use the links individually, so don't disable
2497          * the encoder if it's in use by another connector
2498          */
2499         if (!ASIC_IS_DCE3(rdev)) {
2500                 struct drm_encoder *other_encoder;
2501                 struct radeon_encoder *other_radeon_encoder;
2502
2503                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2504                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2505                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2506                             drm_helper_encoder_in_use(other_encoder))
2507                                 goto disable_done;
2508                 }
2509         }
2510
2511         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2512
2513         switch (radeon_encoder->encoder_id) {
2514         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2515         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2516         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2517         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2518                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2519                 break;
2520         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2521         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2522         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2523         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2524         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2525                 /* handled in dpms */
2526                 break;
2527         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2528         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2529         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2530                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2531                 break;
2532         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2533         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2534         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2535         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2536                 atombios_dac_setup(encoder, ATOM_DISABLE);
2537                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2538                         atombios_tv_setup(encoder, ATOM_DISABLE);
2539                 break;
2540         }
2541
2542 disable_done:
2543         if (radeon_encoder_is_digital(encoder)) {
2544                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2545                         if (rdev->asic->display.hdmi_enable)
2546                                 radeon_hdmi_enable(rdev, encoder, false);
2547                 }
2548                 dig = radeon_encoder->enc_priv;
2549                 dig->dig_encoder = -1;
2550         }
2551         radeon_encoder->active_device = 0;
2552 }
2553
2554 /* these are handled by the primary encoders */
2555 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2556 {
2557
2558 }
2559
2560 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2561 {
2562
2563 }
2564
2565 static void
2566 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2567                          struct drm_display_mode *mode,
2568                          struct drm_display_mode *adjusted_mode)
2569 {
2570
2571 }
2572
2573 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2574 {
2575
2576 }
2577
2578 static void
2579 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2580 {
2581
2582 }
2583
2584 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2585                                        const struct drm_display_mode *mode,
2586                                        struct drm_display_mode *adjusted_mode)
2587 {
2588         return true;
2589 }
2590
2591 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2592         .dpms = radeon_atom_ext_dpms,
2593         .mode_fixup = radeon_atom_ext_mode_fixup,
2594         .prepare = radeon_atom_ext_prepare,
2595         .mode_set = radeon_atom_ext_mode_set,
2596         .commit = radeon_atom_ext_commit,
2597         .disable = radeon_atom_ext_disable,
2598         /* no detect for TMDS/LVDS yet */
2599 };
2600
2601 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2602         .dpms = radeon_atom_encoder_dpms,
2603         .mode_fixup = radeon_atom_mode_fixup,
2604         .prepare = radeon_atom_encoder_prepare,
2605         .mode_set = radeon_atom_encoder_mode_set,
2606         .commit = radeon_atom_encoder_commit,
2607         .disable = radeon_atom_encoder_disable,
2608         .detect = radeon_atom_dig_detect,
2609 };
2610
2611 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2612         .dpms = radeon_atom_encoder_dpms,
2613         .mode_fixup = radeon_atom_mode_fixup,
2614         .prepare = radeon_atom_encoder_prepare,
2615         .mode_set = radeon_atom_encoder_mode_set,
2616         .commit = radeon_atom_encoder_commit,
2617         .detect = radeon_atom_dac_detect,
2618 };
2619
2620 void radeon_enc_destroy(struct drm_encoder *encoder)
2621 {
2622         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2623         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2624                 radeon_atom_backlight_exit(radeon_encoder);
2625         kfree(radeon_encoder->enc_priv);
2626         drm_encoder_cleanup(encoder);
2627         kfree(radeon_encoder);
2628 }
2629
2630 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2631         .destroy = radeon_enc_destroy,
2632 };
2633
2634 static struct radeon_encoder_atom_dac *
2635 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2636 {
2637         struct drm_device *dev = radeon_encoder->base.dev;
2638         struct radeon_device *rdev = dev->dev_private;
2639         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2640
2641         if (!dac)
2642                 return NULL;
2643
2644         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2645         return dac;
2646 }
2647
2648 static struct radeon_encoder_atom_dig *
2649 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2650 {
2651         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2652         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2653
2654         if (!dig)
2655                 return NULL;
2656
2657         /* coherent mode by default */
2658         dig->coherent_mode = true;
2659         dig->dig_encoder = -1;
2660
2661         if (encoder_enum == 2)
2662                 dig->linkb = true;
2663         else
2664                 dig->linkb = false;
2665
2666         return dig;
2667 }
2668
2669 void
2670 radeon_add_atom_encoder(struct drm_device *dev,
2671                         uint32_t encoder_enum,
2672                         uint32_t supported_device,
2673                         u16 caps)
2674 {
2675         struct radeon_device *rdev = dev->dev_private;
2676         struct drm_encoder *encoder;
2677         struct radeon_encoder *radeon_encoder;
2678
2679         /* see if we already added it */
2680         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2681                 radeon_encoder = to_radeon_encoder(encoder);
2682                 if (radeon_encoder->encoder_enum == encoder_enum) {
2683                         radeon_encoder->devices |= supported_device;
2684                         return;
2685                 }
2686
2687         }
2688
2689         /* add a new one */
2690         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2691         if (!radeon_encoder)
2692                 return;
2693
2694         encoder = &radeon_encoder->base;
2695         switch (rdev->num_crtc) {
2696         case 1:
2697                 encoder->possible_crtcs = 0x1;
2698                 break;
2699         case 2:
2700         default:
2701                 encoder->possible_crtcs = 0x3;
2702                 break;
2703         case 4:
2704                 encoder->possible_crtcs = 0xf;
2705                 break;
2706         case 6:
2707                 encoder->possible_crtcs = 0x3f;
2708                 break;
2709         }
2710
2711         radeon_encoder->enc_priv = NULL;
2712
2713         radeon_encoder->encoder_enum = encoder_enum;
2714         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2715         radeon_encoder->devices = supported_device;
2716         radeon_encoder->rmx_type = RMX_OFF;
2717         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2718         radeon_encoder->is_ext_encoder = false;
2719         radeon_encoder->caps = caps;
2720
2721         switch (radeon_encoder->encoder_id) {
2722         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2723         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2724         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2725         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2726                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2727                         radeon_encoder->rmx_type = RMX_FULL;
2728                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2729                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2730                 } else {
2731                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2732                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2733                 }
2734                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2735                 break;
2736         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2737                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2738                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2739                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2740                 break;
2741         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2742         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2743         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2744                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2745                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2746                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2747                 break;
2748         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2749         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2750         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2751         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2752         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2753         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2754         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2755         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2756                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2757                         radeon_encoder->rmx_type = RMX_FULL;
2758                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2759                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2760                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2761                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2762                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2763                 } else {
2764                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2765                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2766                 }
2767                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2768                 break;
2769         case ENCODER_OBJECT_ID_SI170B:
2770         case ENCODER_OBJECT_ID_CH7303:
2771         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2772         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2773         case ENCODER_OBJECT_ID_TITFP513:
2774         case ENCODER_OBJECT_ID_VT1623:
2775         case ENCODER_OBJECT_ID_HDMI_SI1930:
2776         case ENCODER_OBJECT_ID_TRAVIS:
2777         case ENCODER_OBJECT_ID_NUTMEG:
2778                 /* these are handled by the primary encoders */
2779                 radeon_encoder->is_ext_encoder = true;
2780                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2781                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2782                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2783                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2784                 else
2785                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2786                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2787                 break;
2788         }
2789 }