2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_device.c 255573 2013-09-14 17:24:41Z dumbbell $
31 #include <drm/drm_crtc_helper.h>
32 #include <uapi_drm/radeon_drm.h>
34 #include "radeon_reg.h"
38 static const char radeon_family_name[][16] = {
103 * radeon_program_register_sequence - program an array of registers.
105 * @rdev: radeon_device pointer
106 * @registers: pointer to the register array
107 * @array_size: size of the register array
109 * Programs an array or registers with and and or masks.
110 * This is a helper for setting golden registers.
112 void radeon_program_register_sequence(struct radeon_device *rdev,
113 const u32 *registers,
114 const u32 array_size)
116 u32 tmp, reg, and_mask, or_mask;
122 for (i = 0; i < array_size; i +=3) {
123 reg = registers[i + 0];
124 and_mask = registers[i + 1];
125 or_mask = registers[i + 2];
127 if (and_mask == 0xffffffff) {
139 * radeon_surface_init - Clear GPU surface registers.
141 * @rdev: radeon_device pointer
143 * Clear GPU surface registers (r1xx-r5xx).
145 void radeon_surface_init(struct radeon_device *rdev)
147 /* FIXME: check this out */
148 if (rdev->family < CHIP_R600) {
151 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
152 if (rdev->surface_regs[i].bo)
153 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
155 radeon_clear_surface_reg(rdev, i);
157 /* enable surfaces */
158 WREG32(RADEON_SURFACE_CNTL, 0);
163 * GPU scratch registers helpers function.
166 * radeon_scratch_init - Init scratch register driver information.
168 * @rdev: radeon_device pointer
170 * Init CP scratch register driver information (r1xx-r5xx)
172 void radeon_scratch_init(struct radeon_device *rdev)
176 /* FIXME: check this out */
177 if (rdev->family < CHIP_R300) {
178 rdev->scratch.num_reg = 5;
180 rdev->scratch.num_reg = 7;
182 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
183 for (i = 0; i < rdev->scratch.num_reg; i++) {
184 rdev->scratch.free[i] = true;
185 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
190 * radeon_scratch_get - Allocate a scratch register
192 * @rdev: radeon_device pointer
193 * @reg: scratch register mmio offset
195 * Allocate a CP scratch register for use by the driver (all asics).
196 * Returns 0 on success or -EINVAL on failure.
198 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
202 for (i = 0; i < rdev->scratch.num_reg; i++) {
203 if (rdev->scratch.free[i]) {
204 rdev->scratch.free[i] = false;
205 *reg = rdev->scratch.reg[i];
213 * radeon_scratch_free - Free a scratch register
215 * @rdev: radeon_device pointer
216 * @reg: scratch register mmio offset
218 * Free a CP scratch register allocated for use by the driver (all asics)
220 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
224 for (i = 0; i < rdev->scratch.num_reg; i++) {
225 if (rdev->scratch.reg[i] == reg) {
226 rdev->scratch.free[i] = true;
233 * GPU doorbell aperture helpers function.
236 * radeon_doorbell_init - Init doorbell driver information.
238 * @rdev: radeon_device pointer
240 * Init doorbell driver information (CIK)
241 * Returns 0 on success, error on failure.
243 int radeon_doorbell_init(struct radeon_device *rdev)
247 /* doorbell bar mapping */
248 rdev->doorbell.base = drm_get_resource_start(rdev->ddev, 2);
249 rdev->doorbell.size = drm_get_resource_len(rdev->ddev, 2);
251 /* limit to 4 MB for now */
252 if (rdev->doorbell.size > (4 * 1024 * 1024))
253 rdev->doorbell.size = 4 * 1024 * 1024;
255 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.size);
256 if (rdev->doorbell.ptr == NULL) {
259 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
260 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
262 rdev->doorbell.num_pages = rdev->doorbell.size / PAGE_SIZE;
264 for (i = 0; i < rdev->doorbell.num_pages; i++) {
265 rdev->doorbell.free[i] = true;
271 * radeon_doorbell_fini - Tear down doorbell driver information.
273 * @rdev: radeon_device pointer
275 * Tear down doorbell driver information (CIK)
277 void radeon_doorbell_fini(struct radeon_device *rdev)
279 iounmap(rdev->doorbell.ptr, rdev->doorbell.size);
280 rdev->doorbell.ptr = NULL;
284 * radeon_doorbell_get - Allocate a doorbell page
286 * @rdev: radeon_device pointer
287 * @doorbell: doorbell page number
289 * Allocate a doorbell page for use by the driver (all asics).
290 * Returns 0 on success or -EINVAL on failure.
292 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
296 for (i = 0; i < rdev->doorbell.num_pages; i++) {
297 if (rdev->doorbell.free[i]) {
298 rdev->doorbell.free[i] = false;
307 * radeon_doorbell_free - Free a doorbell page
309 * @rdev: radeon_device pointer
310 * @doorbell: doorbell page number
312 * Free a doorbell page allocated for use by the driver (all asics)
314 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
316 if (doorbell < rdev->doorbell.num_pages)
317 rdev->doorbell.free[doorbell] = true;
322 * Writeback is the the method by which the the GPU updates special pages
323 * in memory with the status of certain GPU events (fences, ring pointers,
328 * radeon_wb_disable - Disable Writeback
330 * @rdev: radeon_device pointer
332 * Disables Writeback (all asics). Used for suspend.
334 void radeon_wb_disable(struct radeon_device *rdev)
336 rdev->wb.enabled = false;
340 * radeon_wb_fini - Disable Writeback and free memory
342 * @rdev: radeon_device pointer
344 * Disables Writeback and frees the Writeback memory (all asics).
345 * Used at driver shutdown.
347 void radeon_wb_fini(struct radeon_device *rdev)
349 radeon_wb_disable(rdev);
350 if (rdev->wb.wb_obj) {
351 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
352 radeon_bo_kunmap(rdev->wb.wb_obj);
353 radeon_bo_unpin(rdev->wb.wb_obj);
354 radeon_bo_unreserve(rdev->wb.wb_obj);
356 radeon_bo_unref(&rdev->wb.wb_obj);
358 rdev->wb.wb_obj = NULL;
363 * radeon_wb_init- Init Writeback driver info and allocate memory
365 * @rdev: radeon_device pointer
367 * Disables Writeback and frees the Writeback memory (all asics).
368 * Used at driver startup.
369 * Returns 0 on success or an -error on failure.
371 int radeon_wb_init(struct radeon_device *rdev)
376 if (rdev->wb.wb_obj == NULL) {
377 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
378 RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
380 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
383 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
384 if (unlikely(r != 0)) {
385 radeon_wb_fini(rdev);
388 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
391 radeon_bo_unreserve(rdev->wb.wb_obj);
392 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
393 radeon_wb_fini(rdev);
396 wb_ptr = &rdev->wb.wb;
397 r = radeon_bo_kmap(rdev->wb.wb_obj, wb_ptr);
398 radeon_bo_unreserve(rdev->wb.wb_obj);
400 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
401 radeon_wb_fini(rdev);
404 /* clear wb memory */
405 memset(*(void **)wb_ptr, 0, RADEON_GPU_PAGE_SIZE);
408 /* disable event_write fences */
409 rdev->wb.use_event = false;
410 /* disabled via module param */
411 if (radeon_no_wb == 1) {
412 rdev->wb.enabled = false;
414 if (rdev->flags & RADEON_IS_AGP) {
415 /* often unreliable on AGP */
416 rdev->wb.enabled = false;
417 } else if (rdev->family < CHIP_R300) {
418 /* often unreliable on pre-r300 */
419 rdev->wb.enabled = false;
421 rdev->wb.enabled = true;
422 /* event_write fences are only available on r600+ */
423 if (rdev->family >= CHIP_R600) {
424 rdev->wb.use_event = true;
428 /* always use writeback/events on NI, APUs */
429 if (rdev->family >= CHIP_PALM) {
430 rdev->wb.enabled = true;
431 rdev->wb.use_event = true;
434 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
440 * radeon_vram_location - try to find VRAM location
441 * @rdev: radeon device structure holding all necessary informations
442 * @mc: memory controller structure holding memory informations
443 * @base: base address at which to put VRAM
445 * Function will place try to place VRAM at base address provided
446 * as parameter (which is so far either PCI aperture address or
447 * for IGP TOM base address).
449 * If there is not enough space to fit the unvisible VRAM in the 32bits
450 * address space then we limit the VRAM size to the aperture.
452 * If we are using AGP and if the AGP aperture doesn't allow us to have
453 * room for all the VRAM than we restrict the VRAM to the PCI aperture
454 * size and print a warning.
456 * This function will never fails, worst case are limiting VRAM.
458 * Note: GTT start, end, size should be initialized before calling this
459 * function on AGP platform.
461 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
462 * this shouldn't be a problem as we are using the PCI aperture as a reference.
463 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
466 * Note: we use mc_vram_size as on some board we need to program the mc to
467 * cover the whole aperture even if VRAM size is inferior to aperture size
468 * Novell bug 204882 + along with lots of ubuntu ones
470 * Note: when limiting vram it's safe to overwritte real_vram_size because
471 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
472 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
475 * Note: IGP TOM addr should be the same as the aperture addr, we don't
476 * explicitly check for that thought.
478 * FIXME: when reducing VRAM size align new size on power of 2.
480 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
482 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
484 mc->vram_start = base;
485 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
486 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
487 mc->real_vram_size = mc->aper_size;
488 mc->mc_vram_size = mc->aper_size;
490 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
491 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
492 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
493 mc->real_vram_size = mc->aper_size;
494 mc->mc_vram_size = mc->aper_size;
496 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
497 if (limit && limit < mc->real_vram_size)
498 mc->real_vram_size = limit;
499 dev_info(rdev->dev, "VRAM: %juM 0x%016jX - 0x%016jX (%juM used)\n",
500 mc->mc_vram_size >> 20, mc->vram_start,
501 mc->vram_end, mc->real_vram_size >> 20);
505 * radeon_gtt_location - try to find GTT location
506 * @rdev: radeon device structure holding all necessary informations
507 * @mc: memory controller structure holding memory informations
509 * Function will place try to place GTT before or after VRAM.
511 * If GTT size is bigger than space left then we ajust GTT size.
512 * Thus function will never fails.
514 * FIXME: when reducing GTT size align new size on power of 2.
516 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
518 u64 size_af, size_bf;
520 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
521 size_bf = mc->vram_start & ~mc->gtt_base_align;
522 if (size_bf > size_af) {
523 if (mc->gtt_size > size_bf) {
524 dev_warn(rdev->dev, "limiting GTT\n");
525 mc->gtt_size = size_bf;
527 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
529 if (mc->gtt_size > size_af) {
530 dev_warn(rdev->dev, "limiting GTT\n");
531 mc->gtt_size = size_af;
533 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
535 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
536 dev_info(rdev->dev, "GTT: %juM 0x%016jX - 0x%016jX\n",
537 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
541 * GPU helpers function.
544 * radeon_card_posted - check if the hw has already been initialized
546 * @rdev: radeon_device pointer
548 * Check if the asic has been initialized (all asics).
549 * Used at driver startup.
550 * Returns true if initialized or false if not.
552 bool radeon_card_posted(struct radeon_device *rdev)
557 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
558 if (efi_enabled(EFI_BOOT) &&
559 (rdev->dev->pci_subvendor == PCI_VENDOR_ID_APPLE) &&
560 (rdev->family < CHIP_R600))
562 #endif /* DUMBBELL_WIP */
564 if (ASIC_IS_NODCE(rdev))
567 /* first check CRTCs */
568 if (ASIC_IS_DCE4(rdev)) {
569 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
570 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
571 if (rdev->num_crtc >= 4) {
572 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
573 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
575 if (rdev->num_crtc >= 6) {
576 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
577 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
579 if (reg & EVERGREEN_CRTC_MASTER_EN)
581 } else if (ASIC_IS_AVIVO(rdev)) {
582 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
583 RREG32(AVIVO_D2CRTC_CONTROL);
584 if (reg & AVIVO_CRTC_EN) {
588 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
589 RREG32(RADEON_CRTC2_GEN_CNTL);
590 if (reg & RADEON_CRTC_EN) {
596 /* then check MEM_SIZE, in case the crtcs are off */
597 if (rdev->family >= CHIP_R600)
598 reg = RREG32(R600_CONFIG_MEMSIZE);
600 reg = RREG32(RADEON_CONFIG_MEMSIZE);
610 * radeon_update_bandwidth_info - update display bandwidth params
612 * @rdev: radeon_device pointer
614 * Used when sclk/mclk are switched or display modes are set.
615 * params are used to calculate display watermarks (all asics)
617 void radeon_update_bandwidth_info(struct radeon_device *rdev)
620 u32 sclk = rdev->pm.current_sclk;
621 u32 mclk = rdev->pm.current_mclk;
623 /* sclk/mclk in Mhz */
624 a.full = dfixed_const(100);
625 rdev->pm.sclk.full = dfixed_const(sclk);
626 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
627 rdev->pm.mclk.full = dfixed_const(mclk);
628 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
630 if (rdev->flags & RADEON_IS_IGP) {
631 a.full = dfixed_const(16);
632 /* core_bandwidth = sclk(Mhz) * 16 */
633 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
638 * radeon_boot_test_post_card - check and possibly initialize the hw
640 * @rdev: radeon_device pointer
642 * Check if the asic is initialized and if not, attempt to initialize
644 * Returns true if initialized or false if not.
646 bool radeon_boot_test_post_card(struct radeon_device *rdev)
648 if (radeon_card_posted(rdev))
652 DRM_INFO("GPU not posted. posting now...\n");
653 if (rdev->is_atom_bios)
654 atom_asic_init(rdev->mode_info.atom_context);
656 radeon_combios_asic_init(rdev->ddev);
659 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
665 * radeon_dummy_page_init - init dummy page used by the driver
667 * @rdev: radeon_device pointer
669 * Allocate the dummy page used by the driver (all asics).
670 * This dummy page is used by the driver as a filler for gart entries
671 * when pages are taken out of the GART
672 * Returns 0 on sucess, -ENOMEM on failure.
674 int radeon_dummy_page_init(struct radeon_device *rdev)
676 if (rdev->dummy_page.dmah)
678 rdev->dummy_page.dmah = drm_pci_alloc(rdev->ddev,
679 PAGE_SIZE, PAGE_SIZE);
680 if (rdev->dummy_page.dmah == NULL)
682 rdev->dummy_page.addr =
683 (dma_addr_t)(uintptr_t)rdev->dummy_page.dmah->vaddr;
688 * radeon_dummy_page_fini - free dummy page used by the driver
690 * @rdev: radeon_device pointer
692 * Frees the dummy page used by the driver (all asics).
694 void radeon_dummy_page_fini(struct radeon_device *rdev)
696 if (rdev->dummy_page.dmah == NULL)
698 drm_pci_free(rdev->ddev, rdev->dummy_page.dmah);
699 rdev->dummy_page.dmah = NULL;
700 rdev->dummy_page.addr = 0;
704 /* ATOM accessor methods */
706 * ATOM is an interpreted byte code stored in tables in the vbios. The
707 * driver registers callbacks to access registers and the interpreter
708 * in the driver parses the tables and executes then to program specific
709 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
710 * atombios.h, and atom.c
714 * cail_pll_read - read PLL register
716 * @info: atom card_info pointer
717 * @reg: PLL register offset
719 * Provides a PLL register accessor for the atom interpreter (r4xx+).
720 * Returns the value of the PLL register.
722 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
724 struct radeon_device *rdev = info->dev->dev_private;
727 r = rdev->pll_rreg(rdev, reg);
732 * cail_pll_write - write PLL register
734 * @info: atom card_info pointer
735 * @reg: PLL register offset
736 * @val: value to write to the pll register
738 * Provides a PLL register accessor for the atom interpreter (r4xx+).
740 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
742 struct radeon_device *rdev = info->dev->dev_private;
744 rdev->pll_wreg(rdev, reg, val);
748 * cail_mc_read - read MC (Memory Controller) register
750 * @info: atom card_info pointer
751 * @reg: MC register offset
753 * Provides an MC register accessor for the atom interpreter (r4xx+).
754 * Returns the value of the MC register.
756 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
758 struct radeon_device *rdev = info->dev->dev_private;
761 r = rdev->mc_rreg(rdev, reg);
766 * cail_mc_write - write MC (Memory Controller) register
768 * @info: atom card_info pointer
769 * @reg: MC register offset
770 * @val: value to write to the pll register
772 * Provides a MC register accessor for the atom interpreter (r4xx+).
774 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
776 struct radeon_device *rdev = info->dev->dev_private;
778 rdev->mc_wreg(rdev, reg, val);
782 * cail_reg_write - write MMIO register
784 * @info: atom card_info pointer
785 * @reg: MMIO register offset
786 * @val: value to write to the pll register
788 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
790 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
792 struct radeon_device *rdev = info->dev->dev_private;
798 * cail_reg_read - read MMIO register
800 * @info: atom card_info pointer
801 * @reg: MMIO register offset
803 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
804 * Returns the value of the MMIO register.
806 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
808 struct radeon_device *rdev = info->dev->dev_private;
816 * cail_ioreg_write - write IO register
818 * @info: atom card_info pointer
819 * @reg: IO register offset
820 * @val: value to write to the pll register
822 * Provides a IO register accessor for the atom interpreter (r4xx+).
824 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
826 struct radeon_device *rdev = info->dev->dev_private;
828 WREG32_IO(reg*4, val);
832 * cail_ioreg_read - read IO register
834 * @info: atom card_info pointer
835 * @reg: IO register offset
837 * Provides an IO register accessor for the atom interpreter (r4xx+).
838 * Returns the value of the IO register.
840 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
842 struct radeon_device *rdev = info->dev->dev_private;
845 r = RREG32_IO(reg*4);
850 * radeon_atombios_init - init the driver info and callbacks for atombios
852 * @rdev: radeon_device pointer
854 * Initializes the driver info and register access callbacks for the
855 * ATOM interpreter (r4xx+).
856 * Returns 0 on sucess, -ENOMEM on failure.
857 * Called at driver startup.
859 int radeon_atombios_init(struct radeon_device *rdev)
861 struct card_info *atom_card_info =
862 kzalloc(sizeof(struct card_info), GFP_KERNEL);
867 rdev->mode_info.atom_card_info = atom_card_info;
868 atom_card_info->dev = rdev->ddev;
869 atom_card_info->reg_read = cail_reg_read;
870 atom_card_info->reg_write = cail_reg_write;
871 /* needed for iio ops */
873 atom_card_info->ioreg_read = cail_ioreg_read;
874 atom_card_info->ioreg_write = cail_ioreg_write;
876 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
877 atom_card_info->ioreg_read = cail_reg_read;
878 atom_card_info->ioreg_write = cail_reg_write;
880 atom_card_info->mc_read = cail_mc_read;
881 atom_card_info->mc_write = cail_mc_write;
882 atom_card_info->pll_read = cail_pll_read;
883 atom_card_info->pll_write = cail_pll_write;
885 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
886 if (!rdev->mode_info.atom_context) {
887 radeon_atombios_fini(rdev);
891 lockinit(&rdev->mode_info.atom_context->mutex, "rmiacmtx", 0,
893 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
894 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
899 * radeon_atombios_fini - free the driver info and callbacks for atombios
901 * @rdev: radeon_device pointer
903 * Frees the driver info and register access callbacks for the ATOM
904 * interpreter (r4xx+).
905 * Called at driver shutdown.
907 void radeon_atombios_fini(struct radeon_device *rdev)
909 if (rdev->mode_info.atom_context) {
910 kfree(rdev->mode_info.atom_context->scratch);
912 kfree(rdev->mode_info.atom_context);
913 rdev->mode_info.atom_context = NULL;
914 kfree(rdev->mode_info.atom_card_info);
915 rdev->mode_info.atom_card_info = NULL;
920 * COMBIOS is the bios format prior to ATOM. It provides
921 * command tables similar to ATOM, but doesn't have a unified
922 * parser. See radeon_combios.c
926 * radeon_combios_init - init the driver info for combios
928 * @rdev: radeon_device pointer
930 * Initializes the driver info for combios (r1xx-r3xx).
931 * Returns 0 on sucess.
932 * Called at driver startup.
934 int radeon_combios_init(struct radeon_device *rdev)
936 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
941 * radeon_combios_fini - free the driver info for combios
943 * @rdev: radeon_device pointer
945 * Frees the driver info for combios (r1xx-r3xx).
946 * Called at driver shutdown.
948 void radeon_combios_fini(struct radeon_device *rdev)
953 /* if we get transitioned to only one device, take VGA back */
955 * radeon_vga_set_decode - enable/disable vga decode
957 * @cookie: radeon_device pointer
958 * @state: enable/disable vga decode
960 * Enable/disable vga decode (all asics).
961 * Returns VGA resource flags.
963 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
965 struct radeon_device *rdev = cookie;
966 radeon_vga_set_state(rdev, state);
968 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
969 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
971 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
973 #endif /* DUMBBELL_WIP */
976 * radeon_check_pot_argument - check that argument is a power of two
978 * @arg: value to check
980 * Validates that a certain argument is a power of two (all asics).
981 * Returns true if argument is valid.
983 static bool radeon_check_pot_argument(int arg)
985 return (arg & (arg - 1)) == 0;
989 * radeon_check_arguments - validate module params
991 * @rdev: radeon_device pointer
993 * Validates certain module parameters and updates
994 * the associated values used by the driver (all asics).
996 static void radeon_check_arguments(struct radeon_device *rdev)
998 /* vramlimit must be a power of two */
999 if (!radeon_check_pot_argument(radeon_vram_limit)) {
1000 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1002 radeon_vram_limit = 0;
1005 if (radeon_gart_size == -1) {
1006 /* default to a larger gart size on newer asics */
1007 if (rdev->family >= CHIP_RV770)
1008 radeon_gart_size = 1024;
1010 radeon_gart_size = 512;
1012 /* gtt size must be power of two and greater or equal to 32M */
1013 if (radeon_gart_size < 32) {
1014 dev_warn(rdev->dev, "gart size (%d) too small\n",
1016 if (rdev->family >= CHIP_RV770)
1017 radeon_gart_size = 1024;
1019 radeon_gart_size = 512;
1020 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
1021 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1023 if (rdev->family >= CHIP_RV770)
1024 radeon_gart_size = 1024;
1026 radeon_gart_size = 512;
1028 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1030 /* AGP mode can only be -1, 1, 2, 4, 8 */
1031 switch (radeon_agpmode) {
1040 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1041 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1048 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
1049 * needed for waking up.
1051 * @pdev: pci dev pointer
1054 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
1057 /* 6600m in a macbook pro */
1058 if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1059 pdev->subsystem_device == 0x00e2) {
1060 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
1066 #endif /* DUMBBELL_WIP */
1069 * radeon_switcheroo_set_state - set switcheroo state
1071 * @pdev: pci dev pointer
1072 * @state: vga switcheroo state
1074 * Callback for the switcheroo driver. Suspends or resumes the
1075 * the asics before or after it is powered up using ACPI methods.
1078 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1080 struct drm_device *dev = pci_get_drvdata(pdev);
1081 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1082 if (state == VGA_SWITCHEROO_ON) {
1083 unsigned d3_delay = dev->pdev->d3_delay;
1085 printk(KERN_INFO "radeon: switched on\n");
1086 /* don't suspend or resume card normally */
1087 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1089 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
1090 dev->pdev->d3_delay = 20;
1092 radeon_resume_kms(dev);
1094 dev->pdev->d3_delay = d3_delay;
1096 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1097 drm_kms_helper_poll_enable(dev);
1099 printk(KERN_INFO "radeon: switched off\n");
1100 drm_kms_helper_poll_disable(dev);
1101 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1102 radeon_suspend_kms(dev, pmm);
1103 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1106 #endif /* DUMBBELL_WIP */
1109 * radeon_switcheroo_can_switch - see if switcheroo state can change
1111 * @pdev: pci dev pointer
1113 * Callback for the switcheroo driver. Check of the switcheroo
1114 * state can be changed.
1115 * Returns true if the state can be changed, false if not.
1118 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1120 struct drm_device *dev = pci_get_drvdata(pdev);
1123 spin_lock(&dev->count_lock);
1124 can_switch = (dev->open_count == 0);
1125 spin_unlock(&dev->count_lock);
1129 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1130 .set_gpu_state = radeon_switcheroo_set_state,
1132 .can_switch = radeon_switcheroo_can_switch,
1134 #endif /* DUMBBELL_WIP */
1137 * radeon_device_init - initialize the driver
1139 * @rdev: radeon_device pointer
1140 * @pdev: drm dev pointer
1141 * @flags: driver flags
1143 * Initializes the driver info and hw (all asics).
1144 * Returns 0 for success or an error on failure.
1145 * Called at driver startup.
1147 int radeon_device_init(struct radeon_device *rdev,
1148 struct drm_device *ddev,
1154 rdev->shutdown = false;
1155 rdev->dev = ddev->dev;
1157 rdev->flags = flags;
1158 rdev->family = flags & RADEON_FAMILY_MASK;
1159 rdev->is_atom_bios = false;
1160 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1161 rdev->mc.gtt_size = 512 * 1024 * 1024;
1162 rdev->accel_working = false;
1163 rdev->fictitious_range_registered = false;
1164 /* set up ring ids */
1165 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1166 rdev->ring[i].idx = i;
1169 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1170 radeon_family_name[rdev->family], ddev->pci_vendor, ddev->pci_device,
1171 ddev->pci_subvendor, ddev->pci_subdevice);
1173 /* mutex initialization are all done here so we
1174 * can recall function without having locking issues */
1175 lockinit(&rdev->ring_lock, "drm__radeon_device__ring_lock", 0,
1177 lockinit(&rdev->dc_hw_i2c_mutex,
1178 "drm__radeon_device__dc_hw_i2c_mutex", 0, LK_CANRECURSE);
1179 atomic_set(&rdev->ih.lock, 0);
1180 spin_init(&rdev->gem.mutex, "radeon_gemmtx");
1181 lockinit(&rdev->pm.mutex, "drm__radeon_device__pm__mutex", 0,
1183 spin_init(&rdev->gpu_clock_mutex, "radeon_clockmtx");
1184 spin_init(&rdev->srbm_mutex, "radeon_srbm_mutex");
1185 lockinit(&rdev->pm.mclk_lock, "drm__radeon_device__pm__mclk_lock", 0,
1187 lockinit(&rdev->exclusive_lock, "drm__radeon_device__exclusive_lock",
1189 DRM_INIT_WAITQUEUE(&rdev->irq.vblank_queue);
1190 r = radeon_gem_init(rdev);
1193 /* initialize vm here */
1194 lockinit(&rdev->vm_manager.lock,
1195 "drm__radeon_device__vm_manager__lock", 0, LK_CANRECURSE);
1196 /* Adjust VM size here.
1197 * Currently set to 4GB ((1 << 20) 4k pages).
1198 * Max GPUVM size for cayman and SI is 40 bits.
1200 rdev->vm_manager.max_pfn = 1 << 20;
1201 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
1203 /* Set asic functions */
1204 r = radeon_asic_init(rdev);
1207 radeon_check_arguments(rdev);
1209 /* all of the newer IGP chips have an internal gart
1210 * However some rs4xx report as AGP, so remove that here.
1212 if ((rdev->family >= CHIP_RS400) &&
1213 (rdev->flags & RADEON_IS_IGP)) {
1214 rdev->flags &= ~RADEON_IS_AGP;
1217 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1218 radeon_agp_disable(rdev);
1221 /* Set the internal MC address mask
1222 * This is the max address of the GPU's
1223 * internal address space.
1225 if (rdev->family >= CHIP_CAYMAN)
1226 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1227 else if (rdev->family >= CHIP_CEDAR)
1228 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1230 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1232 /* set DMA mask + need_dma32 flags.
1233 * PCIE - can handle 40-bits.
1234 * IGP - can handle 40-bits
1235 * AGP - generally dma32 is safest
1236 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1238 rdev->need_dma32 = false;
1239 if (rdev->flags & RADEON_IS_AGP)
1240 rdev->need_dma32 = true;
1241 if ((rdev->flags & RADEON_IS_PCI) &&
1242 (rdev->family <= CHIP_RS740))
1243 rdev->need_dma32 = true;
1245 dma_bits = rdev->need_dma32 ? 32 : 40;
1247 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1249 rdev->need_dma32 = true;
1251 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1253 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1255 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1256 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1258 #endif /* DUMBBELL_WIP */
1260 /* Registers mapping */
1261 /* TODO: block userspace mapping of io register */
1262 spin_init(&rdev->mmio_idx_lock, "radeon_mpio");
1263 if (rdev->family >= CHIP_BONAIRE) {
1264 rdev->rmmio_rid = PCIR_BAR(5);
1266 rdev->rmmio_rid = PCIR_BAR(2);
1268 rdev->rmmio = bus_alloc_resource_any(rdev->dev, SYS_RES_MEMORY,
1269 &rdev->rmmio_rid, RF_ACTIVE | RF_SHAREABLE);
1270 if (rdev->rmmio == NULL) {
1273 rdev->rmmio_base = rman_get_start(rdev->rmmio);
1274 rdev->rmmio_size = rman_get_size(rdev->rmmio);
1275 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1276 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1278 /* doorbell bar mapping */
1279 if (rdev->family >= CHIP_BONAIRE)
1280 radeon_doorbell_init(rdev);
1282 /* io port mapping */
1283 for (i = 0; i < DRM_MAX_PCI_RESOURCE; i++) {
1286 data = pci_read_config(rdev->dev, PCIR_BAR(i), 4);
1287 if (PCI_BAR_IO(data)) {
1288 rdev->rio_rid = PCIR_BAR(i);
1289 rdev->rio_mem = bus_alloc_resource_any(rdev->dev,
1290 SYS_RES_IOPORT, &rdev->rio_rid,
1291 RF_ACTIVE | RF_SHAREABLE);
1295 if (rdev->rio_mem == NULL)
1296 DRM_ERROR("Unable to find PCI I/O BAR\n");
1298 rdev->tq = taskqueue_create("radeonkms", M_WAITOK,
1299 taskqueue_thread_enqueue, &rdev->tq);
1300 taskqueue_start_threads(&rdev->tq, 1, 0, -1, "radeon taskq");
1303 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1304 /* this will fail for cards that aren't VGA class devices, just
1306 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1307 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, false);
1308 #endif /* DUMBBELL_WIP */
1310 r = radeon_init(rdev);
1314 r = radeon_ib_ring_tests(rdev);
1316 DRM_ERROR("ib ring test failed (%d).\n", r);
1318 r = radeon_gem_debugfs_init(rdev);
1320 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1323 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1324 /* Acceleration not working on AGP card try again
1325 * with fallback to PCI or PCIE GART
1327 radeon_asic_reset(rdev);
1329 radeon_agp_disable(rdev);
1330 r = radeon_init(rdev);
1335 DRM_INFO("%s: Taking over the fictitious range 0x%jx-0x%jx\n",
1336 __func__, (uintmax_t)rdev->mc.aper_base,
1337 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size);
1338 r = vm_phys_fictitious_reg_range(
1340 rdev->mc.aper_base + rdev->mc.visible_vram_size,
1341 VM_MEMATTR_WRITE_COMBINING);
1343 DRM_ERROR("Failed to register fictitious range "
1344 "0x%jx-0x%jx (%d).\n", (uintmax_t)rdev->mc.aper_base,
1345 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size, r);
1348 rdev->fictitious_range_registered = true;
1350 if ((radeon_testing & 1)) {
1351 if (rdev->accel_working)
1352 radeon_test_moves(rdev);
1354 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1356 if ((radeon_testing & 2)) {
1357 if (rdev->accel_working)
1358 radeon_test_syncing(rdev);
1360 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1362 if (radeon_benchmarking) {
1363 if (rdev->accel_working)
1364 radeon_benchmark(rdev, radeon_benchmarking);
1366 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1372 static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1373 #endif /* DUMBBELL_WIP */
1376 * radeon_device_fini - tear down the driver
1378 * @rdev: radeon_device pointer
1380 * Tear down the driver info (all asics).
1381 * Called at driver shutdown.
1383 void radeon_device_fini(struct radeon_device *rdev)
1385 DRM_INFO("radeon: finishing device.\n");
1386 rdev->shutdown = true;
1387 /* evict vram memory */
1388 radeon_bo_evict_vram(rdev);
1390 if (rdev->fictitious_range_registered) {
1391 vm_phys_fictitious_unreg_range(
1393 rdev->mc.aper_base + rdev->mc.visible_vram_size);
1398 vga_switcheroo_unregister_client(rdev->pdev);
1399 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1400 #endif /* DUMBBELL_WIP */
1402 if (rdev->tq != NULL) {
1403 taskqueue_free(rdev->tq);
1408 bus_release_resource(rdev->dev, SYS_RES_IOPORT, rdev->rio_rid,
1410 rdev->rio_mem = NULL;
1411 bus_release_resource(rdev->dev, SYS_RES_MEMORY, rdev->rmmio_rid,
1414 if (rdev->family >= CHIP_BONAIRE)
1415 radeon_doorbell_fini(rdev);
1417 radeon_debugfs_remove_files(rdev);
1418 #endif /* DUMBBELL_WIP */
1426 * radeon_suspend_kms - initiate device suspend
1428 * @pdev: drm dev pointer
1429 * @state: suspend state
1431 * Puts the hw in the suspend state (all asics).
1432 * Returns 0 for success or an error on failure.
1433 * Called at driver suspend.
1435 int radeon_suspend_kms(struct drm_device *dev)
1437 struct radeon_device *rdev;
1438 struct drm_crtc *crtc;
1439 struct drm_connector *connector;
1441 bool force_completion = false;
1443 if (dev == NULL || dev->dev_private == NULL) {
1447 if (state.event == PM_EVENT_PRETHAW) {
1450 #endif /* DUMBBELL_WIP */
1451 rdev = dev->dev_private;
1453 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1456 drm_kms_helper_poll_disable(dev);
1458 /* turn off display hw */
1459 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1460 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1463 /* unpin the front buffers */
1464 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1465 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
1466 struct radeon_bo *robj;
1468 if (rfb == NULL || rfb->obj == NULL) {
1471 robj = gem_to_radeon_bo(rfb->obj);
1472 /* don't unpin kernel fb objects */
1473 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1474 r = radeon_bo_reserve(robj, false);
1476 radeon_bo_unpin(robj);
1477 radeon_bo_unreserve(robj);
1481 /* evict vram memory */
1482 radeon_bo_evict_vram(rdev);
1484 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
1485 /* wait for gpu to finish processing current batch */
1486 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1487 r = radeon_fence_wait_empty_locked(rdev, i);
1489 /* delay GPU reset to resume */
1490 force_completion = true;
1493 if (force_completion) {
1494 radeon_fence_driver_force_completion(rdev);
1496 lockmgr(&rdev->ring_lock, LK_RELEASE);
1498 radeon_save_bios_scratch_regs(rdev);
1500 radeon_pm_suspend(rdev);
1501 radeon_suspend(rdev);
1502 radeon_hpd_fini(rdev);
1503 /* evict remaining vram memory */
1504 radeon_bo_evict_vram(rdev);
1506 radeon_agp_suspend(rdev);
1508 pci_save_state(device_get_parent(rdev->dev));
1510 if (state.event == PM_EVENT_SUSPEND) {
1511 /* Shut down the device */
1512 pci_disable_device(dev->pdev);
1513 #endif /* DUMBBELL_WIP */
1514 pci_set_powerstate(dev->dev, PCI_POWERSTATE_D3);
1518 #endif /* DUMBBELL_WIP */
1519 radeon_fbdev_set_suspend(rdev, 1);
1522 #endif /* DUMBBELL_WIP */
1527 * radeon_resume_kms - initiate device resume
1529 * @pdev: drm dev pointer
1531 * Bring the hw back to operating state (all asics).
1532 * Returns 0 for success or an error on failure.
1533 * Called at driver resume.
1535 int radeon_resume_kms(struct drm_device *dev)
1537 struct drm_connector *connector;
1538 struct radeon_device *rdev = dev->dev_private;
1541 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1546 #endif /* DUMBBELL_WIP */
1547 pci_set_powerstate(dev->dev, PCI_POWERSTATE_D0);
1548 pci_restore_state(device_get_parent(rdev->dev));
1550 if (pci_enable_device(dev->pdev)) {
1554 #endif /* DUMBBELL_WIP */
1555 /* resume AGP if in use */
1556 radeon_agp_resume(rdev);
1557 radeon_resume(rdev);
1559 r = radeon_ib_ring_tests(rdev);
1561 DRM_ERROR("ib ring test failed (%d).\n", r);
1563 radeon_pm_resume(rdev);
1564 radeon_restore_bios_scratch_regs(rdev);
1566 radeon_fbdev_set_suspend(rdev, 0);
1569 #endif /* DUMBBELL_WIP */
1571 /* init dig PHYs, disp eng pll */
1572 if (rdev->is_atom_bios) {
1573 radeon_atom_encoder_init(rdev);
1574 radeon_atom_disp_eng_pll_init(rdev);
1575 /* turn on the BL */
1576 if (rdev->mode_info.bl_encoder) {
1577 u8 bl_level = radeon_get_backlight_level(rdev,
1578 rdev->mode_info.bl_encoder);
1579 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1583 /* reset hpd state */
1584 radeon_hpd_init(rdev);
1585 /* blat the mode back in */
1586 drm_helper_resume_force_mode(dev);
1587 /* turn on display hw */
1588 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1589 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1592 drm_kms_helper_poll_enable(dev);
1597 * radeon_gpu_reset - reset the asic
1599 * @rdev: radeon device pointer
1601 * Attempt the reset the GPU if it has hung (all asics).
1602 * Returns 0 for success or an error on failure.
1604 int radeon_gpu_reset(struct radeon_device *rdev)
1606 unsigned ring_sizes[RADEON_NUM_RINGS];
1607 uint32_t *ring_data[RADEON_NUM_RINGS];
1614 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE);
1615 radeon_save_bios_scratch_regs(rdev);
1617 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1618 radeon_pm_suspend(rdev);
1619 radeon_suspend(rdev);
1621 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1622 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1624 if (ring_sizes[i]) {
1626 dev_info(rdev->dev, "Saved %d dwords of commands "
1627 "on ring %d.\n", ring_sizes[i], i);
1632 r = radeon_asic_reset(rdev);
1634 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1635 radeon_resume(rdev);
1638 radeon_restore_bios_scratch_regs(rdev);
1641 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1642 radeon_ring_restore(rdev, &rdev->ring[i],
1643 ring_sizes[i], ring_data[i]);
1645 ring_data[i] = NULL;
1648 r = radeon_ib_ring_tests(rdev);
1650 dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1653 radeon_suspend(rdev);
1658 radeon_fence_driver_force_completion(rdev);
1659 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1660 kfree(ring_data[i]);
1664 radeon_pm_resume(rdev);
1665 drm_helper_resume_force_mode(rdev->ddev);
1667 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1669 /* bad news, how to tell it to userspace ? */
1670 dev_info(rdev->dev, "GPU reset failed\n");
1673 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
1682 int radeon_debugfs_add_files(struct radeon_device *rdev,
1683 struct drm_info_list *files,
1688 for (i = 0; i < rdev->debugfs_count; i++) {
1689 if (rdev->debugfs[i].files == files) {
1690 /* Already registered */
1695 i = rdev->debugfs_count + 1;
1696 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1697 DRM_ERROR("Reached maximum number of debugfs components.\n");
1698 DRM_ERROR("Report so we increase "
1699 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1702 rdev->debugfs[rdev->debugfs_count].files = files;
1703 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1704 rdev->debugfs_count = i;
1705 #if defined(CONFIG_DEBUG_FS)
1706 drm_debugfs_create_files(files, nfiles,
1707 rdev->ddev->control->debugfs_root,
1708 rdev->ddev->control);
1709 drm_debugfs_create_files(files, nfiles,
1710 rdev->ddev->primary->debugfs_root,
1711 rdev->ddev->primary);
1716 static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1718 #if defined(CONFIG_DEBUG_FS)
1721 for (i = 0; i < rdev->debugfs_count; i++) {
1722 drm_debugfs_remove_files(rdev->debugfs[i].files,
1723 rdev->debugfs[i].num_files,
1724 rdev->ddev->control);
1725 drm_debugfs_remove_files(rdev->debugfs[i].files,
1726 rdev->debugfs[i].num_files,
1727 rdev->ddev->primary);
1732 #if defined(CONFIG_DEBUG_FS)
1733 int radeon_debugfs_init(struct drm_minor *minor)
1738 void radeon_debugfs_cleanup(struct drm_minor *minor)
1741 #endif /* DUMBBELL_WIP */