2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
26 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_display.c 254885 2013-08-25 19:37:15Z dumbbell $
30 #include <uapi_drm/radeon_drm.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include <linux/err.h>
39 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 struct drm_device *dev = crtc->dev;
43 struct radeon_device *rdev = dev->dev_private;
46 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
47 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
57 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
58 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
59 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
61 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
62 for (i = 0; i < 256; i++) {
63 WREG32(AVIVO_DC_LUT_30_COLOR,
64 (radeon_crtc->lut_r[i] << 20) |
65 (radeon_crtc->lut_g[i] << 10) |
66 (radeon_crtc->lut_b[i] << 0));
69 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
72 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
74 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
75 struct drm_device *dev = crtc->dev;
76 struct radeon_device *rdev = dev->dev_private;
79 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
80 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
90 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
91 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
93 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
94 for (i = 0; i < 256; i++) {
95 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
96 (radeon_crtc->lut_r[i] << 20) |
97 (radeon_crtc->lut_g[i] << 10) |
98 (radeon_crtc->lut_b[i] << 0));
102 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
104 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
105 struct drm_device *dev = crtc->dev;
106 struct radeon_device *rdev = dev->dev_private;
109 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
111 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
112 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
113 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
114 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
115 NI_GRPH_PRESCALE_BYPASS);
116 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
117 NI_OVL_PRESCALE_BYPASS);
118 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
119 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
120 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
122 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
124 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
128 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
132 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
133 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
135 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
136 for (i = 0; i < 256; i++) {
137 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
138 (radeon_crtc->lut_r[i] << 20) |
139 (radeon_crtc->lut_g[i] << 10) |
140 (radeon_crtc->lut_b[i] << 0));
143 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
144 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
145 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
147 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
148 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
149 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
150 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
151 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
152 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
153 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
154 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
155 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
156 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
157 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
158 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
159 if (ASIC_IS_DCE8(rdev)) {
160 /* XXX this only needs to be programmed once per crtc at startup,
161 * not sure where the best place for it is
163 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
164 CIK_CURSOR_ALPHA_BLND_ENA);
168 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
170 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
171 struct drm_device *dev = crtc->dev;
172 struct radeon_device *rdev = dev->dev_private;
176 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
177 if (radeon_crtc->crtc_id == 0)
178 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
180 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
181 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
183 WREG8(RADEON_PALETTE_INDEX, 0);
184 for (i = 0; i < 256; i++) {
185 WREG32(RADEON_PALETTE_30_DATA,
186 (radeon_crtc->lut_r[i] << 20) |
187 (radeon_crtc->lut_g[i] << 10) |
188 (radeon_crtc->lut_b[i] << 0));
192 void radeon_crtc_load_lut(struct drm_crtc *crtc)
194 struct drm_device *dev = crtc->dev;
195 struct radeon_device *rdev = dev->dev_private;
200 if (ASIC_IS_DCE5(rdev))
201 dce5_crtc_load_lut(crtc);
202 else if (ASIC_IS_DCE4(rdev))
203 dce4_crtc_load_lut(crtc);
204 else if (ASIC_IS_AVIVO(rdev))
205 avivo_crtc_load_lut(crtc);
207 legacy_crtc_load_lut(crtc);
210 /** Sets the color ramps on behalf of fbcon */
211 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
216 radeon_crtc->lut_r[regno] = red >> 6;
217 radeon_crtc->lut_g[regno] = green >> 6;
218 radeon_crtc->lut_b[regno] = blue >> 6;
221 /** Gets the color ramps on behalf of fbcon */
222 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
223 u16 *blue, int regno)
225 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 *red = radeon_crtc->lut_r[regno] << 6;
228 *green = radeon_crtc->lut_g[regno] << 6;
229 *blue = radeon_crtc->lut_b[regno] << 6;
232 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
233 u16 *blue, uint32_t start, uint32_t size)
235 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
236 int end = (start + size > 256) ? 256 : start + size, i;
238 /* userspace palettes are always correct as is */
239 for (i = start; i < end; i++) {
240 radeon_crtc->lut_r[i] = red[i] >> 6;
241 radeon_crtc->lut_g[i] = green[i] >> 6;
242 radeon_crtc->lut_b[i] = blue[i] >> 6;
244 radeon_crtc_load_lut(crtc);
247 static void radeon_crtc_destroy(struct drm_crtc *crtc)
249 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
251 drm_crtc_cleanup(crtc);
256 * Handle unpin events outside the interrupt handler proper.
258 static void radeon_unpin_work_func(void *arg, int pending)
260 struct radeon_unpin_work *work = arg;
263 /* unpin of the old buffer */
264 r = radeon_bo_reserve(work->old_rbo, false);
265 if (likely(r == 0)) {
266 r = radeon_bo_unpin(work->old_rbo);
267 if (unlikely(r != 0)) {
268 DRM_ERROR("failed to unpin buffer after flip\n");
270 radeon_bo_unreserve(work->old_rbo);
272 DRM_ERROR("failed to reserve buffer after flip\n");
274 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
278 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
280 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
281 struct radeon_unpin_work *work;
285 lockmgr(&rdev->ddev->event_lock, LK_EXCLUSIVE);
286 work = radeon_crtc->unpin_work;
288 (work->fence && !radeon_fence_signaled(work->fence))) {
289 lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
292 /* New pageflip, or just completion of a previous one? */
293 if (!radeon_crtc->deferred_flip_completion) {
294 /* do the flip (mmio) */
295 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
297 /* This is just a completion of a flip queued in crtc
298 * at last invocation. Make sure we go directly to
299 * completion routine.
302 radeon_crtc->deferred_flip_completion = 0;
305 /* Has the pageflip already completed in crtc, or is it certain
306 * to complete in this vblank?
308 if (update_pending &&
309 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
310 &vpos, &hpos, NULL, NULL)) &&
311 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
312 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
313 /* crtc didn't flip in this target vblank interval,
314 * but flip is pending in crtc. Based on the current
315 * scanout position we know that the current frame is
316 * (nearly) complete and the flip will (likely)
317 * complete before the start of the next frame.
321 if (update_pending) {
322 /* crtc didn't flip in this target vblank interval,
323 * but flip is pending in crtc. It will complete it
324 * in next vblank interval, so complete the flip at
327 radeon_crtc->deferred_flip_completion = 1;
328 lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
332 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
333 radeon_crtc->unpin_work = NULL;
335 /* wakeup userspace */
337 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
339 lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
341 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
342 radeon_fence_unref(&work->fence);
343 radeon_post_page_flip(work->rdev, work->crtc_id);
344 taskqueue_enqueue(rdev->tq, &work->work);
347 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
348 struct drm_framebuffer *fb,
349 struct drm_pending_vblank_event *event,
350 uint32_t page_flip_flags)
352 struct drm_device *dev = crtc->dev;
353 struct radeon_device *rdev = dev->dev_private;
354 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
355 struct radeon_framebuffer *old_radeon_fb;
356 struct radeon_framebuffer *new_radeon_fb;
357 struct drm_gem_object *obj;
358 struct radeon_bo *rbo;
359 struct radeon_unpin_work *work;
360 u32 tiling_flags, pitch_pixels;
364 work = kzalloc(sizeof *work, GFP_KERNEL);
370 work->crtc_id = radeon_crtc->crtc_id;
371 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
372 new_radeon_fb = to_radeon_framebuffer(fb);
373 /* schedule unpin of the old buffer */
374 obj = old_radeon_fb->obj;
375 /* take a reference to the old object */
376 drm_gem_object_reference(obj);
377 rbo = gem_to_radeon_bo(obj);
379 obj = new_radeon_fb->obj;
380 rbo = gem_to_radeon_bo(obj);
382 lockmgr(&rbo->tbo.bdev->fence_lock, LK_EXCLUSIVE);
383 if (rbo->tbo.sync_obj)
384 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
385 lockmgr(&rbo->tbo.bdev->fence_lock, LK_RELEASE);
387 TASK_INIT(&work->work, 0, radeon_unpin_work_func, work);
389 /* We borrow the event spin lock for protecting unpin_work */
390 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
391 if (radeon_crtc->unpin_work) {
392 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
396 radeon_crtc->unpin_work = work;
397 radeon_crtc->deferred_flip_completion = 0;
398 lockmgr(&dev->event_lock, LK_RELEASE);
400 /* pin the new buffer */
401 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
404 r = radeon_bo_reserve(rbo, false);
405 if (unlikely(r != 0)) {
406 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
409 /* Only 27 bit offset for legacy CRTC */
410 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
411 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
412 if (unlikely(r != 0)) {
413 radeon_bo_unreserve(rbo);
415 DRM_ERROR("failed to pin new rbo buffer before flip\n");
418 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
419 radeon_bo_unreserve(rbo);
421 if (!ASIC_IS_AVIVO(rdev)) {
422 /* crtc offset is from display base addr not FB location */
423 base -= radeon_crtc->legacy_display_base_addr;
424 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
426 if (tiling_flags & RADEON_TILING_MACRO) {
427 if (ASIC_IS_R300(rdev)) {
430 int byteshift = fb->bits_per_pixel >> 4;
431 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
432 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
435 int offset = crtc->y * pitch_pixels + crtc->x;
436 switch (fb->bits_per_pixel) {
457 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
458 work->new_crtc_base = base;
459 lockmgr(&dev->event_lock, LK_RELEASE);
462 crtc->primary->fb = fb;
464 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
466 DRM_ERROR("failed to get vblank before flip\n");
470 /* set the proper interrupt */
471 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
476 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
477 DRM_ERROR("failed to reserve new rbo in error path\n");
480 if (unlikely(radeon_bo_unpin(rbo) != 0)) {
481 DRM_ERROR("failed to unpin new rbo in error path\n");
483 radeon_bo_unreserve(rbo);
486 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
487 radeon_crtc->unpin_work = NULL;
489 lockmgr(&dev->event_lock, LK_RELEASE);
490 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
491 radeon_fence_unref(&work->fence);
497 static const struct drm_crtc_funcs radeon_crtc_funcs = {
498 .cursor_set = radeon_crtc_cursor_set,
499 .cursor_move = radeon_crtc_cursor_move,
500 .gamma_set = radeon_crtc_gamma_set,
501 .set_config = drm_crtc_helper_set_config,
502 .destroy = radeon_crtc_destroy,
503 .page_flip = radeon_crtc_page_flip,
506 static void radeon_crtc_init(struct drm_device *dev, int index)
508 struct radeon_device *rdev = dev->dev_private;
509 struct radeon_crtc *radeon_crtc;
512 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
513 if (radeon_crtc == NULL)
516 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
518 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
519 radeon_crtc->crtc_id = index;
520 rdev->mode_info.crtcs[index] = radeon_crtc;
522 if (rdev->family >= CHIP_BONAIRE) {
523 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
524 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
526 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
527 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
531 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
532 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
533 radeon_crtc->mode_set.num_connectors = 0;
536 for (i = 0; i < 256; i++) {
537 radeon_crtc->lut_r[i] = i << 2;
538 radeon_crtc->lut_g[i] = i << 2;
539 radeon_crtc->lut_b[i] = i << 2;
542 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
543 radeon_atombios_init_crtc(dev, radeon_crtc);
545 radeon_legacy_init_crtc(dev, radeon_crtc);
548 static const char *encoder_names[38] = {
568 "INTERNAL_KLDSCP_TMDS1",
569 "INTERNAL_KLDSCP_DVO1",
570 "INTERNAL_KLDSCP_DAC1",
571 "INTERNAL_KLDSCP_DAC2",
580 "INTERNAL_KLDSCP_LVTMA",
589 static const char *hpd_names[6] = {
598 static void radeon_print_display_setup(struct drm_device *dev)
600 struct drm_connector *connector;
601 struct radeon_connector *radeon_connector;
602 struct drm_encoder *encoder;
603 struct radeon_encoder *radeon_encoder;
607 DRM_INFO("Radeon Display Connectors\n");
608 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
609 radeon_connector = to_radeon_connector(connector);
610 DRM_INFO("Connector %d:\n", i);
611 DRM_INFO(" %s\n", connector->name);
612 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
613 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
614 if (radeon_connector->ddc_bus) {
615 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
616 radeon_connector->ddc_bus->rec.mask_clk_reg,
617 radeon_connector->ddc_bus->rec.mask_data_reg,
618 radeon_connector->ddc_bus->rec.a_clk_reg,
619 radeon_connector->ddc_bus->rec.a_data_reg,
620 radeon_connector->ddc_bus->rec.en_clk_reg,
621 radeon_connector->ddc_bus->rec.en_data_reg,
622 radeon_connector->ddc_bus->rec.y_clk_reg,
623 radeon_connector->ddc_bus->rec.y_data_reg);
624 if (radeon_connector->router.ddc_valid)
625 DRM_INFO(" DDC Router 0x%x/0x%x\n",
626 radeon_connector->router.ddc_mux_control_pin,
627 radeon_connector->router.ddc_mux_state);
628 if (radeon_connector->router.cd_valid)
629 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
630 radeon_connector->router.cd_mux_control_pin,
631 radeon_connector->router.cd_mux_state);
633 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
634 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
635 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
636 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
637 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
638 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
639 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
641 DRM_INFO(" Encoders:\n");
642 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
643 radeon_encoder = to_radeon_encoder(encoder);
644 devices = radeon_encoder->devices & radeon_connector->devices;
646 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
647 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
648 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
649 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
650 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
651 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
652 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
653 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
654 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
655 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
656 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
657 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
658 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
659 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
660 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
661 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
662 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
663 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
664 if (devices & ATOM_DEVICE_TV1_SUPPORT)
665 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
666 if (devices & ATOM_DEVICE_CV_SUPPORT)
667 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
674 static bool radeon_setup_enc_conn(struct drm_device *dev)
676 struct radeon_device *rdev = dev->dev_private;
680 if (rdev->is_atom_bios) {
681 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
683 ret = radeon_get_atom_connector_info_from_object_table(dev);
685 ret = radeon_get_legacy_connector_info_from_bios(dev);
687 ret = radeon_get_legacy_connector_info_from_table(dev);
690 if (!ASIC_IS_AVIVO(rdev))
691 ret = radeon_get_legacy_connector_info_from_table(dev);
694 radeon_setup_encoder_clones(dev);
695 radeon_print_display_setup(dev);
701 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
703 struct drm_device *dev = radeon_connector->base.dev;
704 struct radeon_device *rdev = dev->dev_private;
707 /* on hw with routers, select right port */
708 if (radeon_connector->router.ddc_valid)
709 radeon_router_select_ddc_port(radeon_connector);
711 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
712 ENCODER_OBJECT_ID_NONE) {
713 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
716 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
717 dig->dp_i2c_bus->adapter);
718 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
719 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
720 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
722 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
723 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
724 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
725 dig->dp_i2c_bus->adapter);
726 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
727 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
728 radeon_connector->ddc_bus->adapter);
730 if (radeon_connector->ddc_bus && !radeon_connector->edid)
731 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
732 radeon_connector->ddc_bus->adapter);
735 if (!radeon_connector->edid) {
736 if (rdev->is_atom_bios) {
737 /* some laptops provide a hardcoded edid in rom for LCDs */
738 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
739 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
740 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
742 /* some servers provide a hardcoded edid in rom for KVMs */
743 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
745 if (radeon_connector->edid) {
746 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
747 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
748 /* XXX Dragonfly does not support HDMI deep colors safely for now */
749 if (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
750 radeon_connector->base.display_info.bpc = 8;
754 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
759 static void avivo_get_fb_div(struct radeon_pll *pll,
766 u32 tmp = post_div * ref_div;
769 *fb_div = tmp / pll->reference_freq;
770 *frac_fb_div = tmp % pll->reference_freq;
772 if (*fb_div > pll->max_feedback_div)
773 *fb_div = pll->max_feedback_div;
774 else if (*fb_div < pll->min_feedback_div)
775 *fb_div = pll->min_feedback_div;
778 static u32 avivo_get_post_div(struct radeon_pll *pll,
781 u32 vco, post_div, tmp;
783 if (pll->flags & RADEON_PLL_USE_POST_DIV)
784 return pll->post_div;
786 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
787 if (pll->flags & RADEON_PLL_IS_LCD)
788 vco = pll->lcd_pll_out_min;
790 vco = pll->pll_out_min;
792 if (pll->flags & RADEON_PLL_IS_LCD)
793 vco = pll->lcd_pll_out_max;
795 vco = pll->pll_out_max;
798 post_div = vco / target_clock;
799 tmp = vco % target_clock;
801 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
809 if (post_div > pll->max_post_div)
810 post_div = pll->max_post_div;
811 else if (post_div < pll->min_post_div)
812 post_div = pll->min_post_div;
817 #define MAX_TOLERANCE 10
819 void radeon_compute_pll_avivo(struct radeon_pll *pll,
827 u32 target_clock = freq / 10;
828 u32 post_div = avivo_get_post_div(pll, target_clock);
829 u32 ref_div = pll->min_ref_div;
830 u32 fb_div = 0, frac_fb_div = 0, tmp;
832 if (pll->flags & RADEON_PLL_USE_REF_DIV)
833 ref_div = pll->reference_div;
835 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
836 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
837 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
838 if (frac_fb_div >= 5) {
840 frac_fb_div = frac_fb_div / 10;
843 if (frac_fb_div >= 10) {
848 while (ref_div <= pll->max_ref_div) {
849 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
850 &fb_div, &frac_fb_div);
851 if (frac_fb_div >= (pll->reference_freq / 2))
854 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
855 tmp = (tmp * 10000) / target_clock;
857 if (tmp > (10000 + MAX_TOLERANCE))
859 else if (tmp >= (10000 - MAX_TOLERANCE))
866 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
867 (ref_div * post_div * 10);
869 *frac_fb_div_p = frac_fb_div;
870 *ref_div_p = ref_div;
871 *post_div_p = post_div;
872 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
873 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
877 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
887 void radeon_compute_pll_legacy(struct radeon_pll *pll,
889 uint32_t *dot_clock_p,
891 uint32_t *frac_fb_div_p,
893 uint32_t *post_div_p)
895 uint32_t min_ref_div = pll->min_ref_div;
896 uint32_t max_ref_div = pll->max_ref_div;
897 uint32_t min_post_div = pll->min_post_div;
898 uint32_t max_post_div = pll->max_post_div;
899 uint32_t min_fractional_feed_div = 0;
900 uint32_t max_fractional_feed_div = 0;
901 uint32_t best_vco = pll->best_vco;
902 uint32_t best_post_div = 1;
903 uint32_t best_ref_div = 1;
904 uint32_t best_feedback_div = 1;
905 uint32_t best_frac_feedback_div = 0;
906 uint32_t best_freq = -1;
907 uint32_t best_error = 0xffffffff;
908 uint32_t best_vco_diff = 1;
910 u32 pll_out_min, pll_out_max;
912 DRM_DEBUG_KMS("PLL freq %ju %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
915 if (pll->flags & RADEON_PLL_IS_LCD) {
916 pll_out_min = pll->lcd_pll_out_min;
917 pll_out_max = pll->lcd_pll_out_max;
919 pll_out_min = pll->pll_out_min;
920 pll_out_max = pll->pll_out_max;
923 if (pll_out_min > 64800)
926 if (pll->flags & RADEON_PLL_USE_REF_DIV)
927 min_ref_div = max_ref_div = pll->reference_div;
929 while (min_ref_div < max_ref_div-1) {
930 uint32_t mid = (min_ref_div + max_ref_div) / 2;
931 uint32_t pll_in = pll->reference_freq / mid;
932 if (pll_in < pll->pll_in_min)
934 else if (pll_in > pll->pll_in_max)
941 if (pll->flags & RADEON_PLL_USE_POST_DIV)
942 min_post_div = max_post_div = pll->post_div;
944 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
945 min_fractional_feed_div = pll->min_frac_feedback_div;
946 max_fractional_feed_div = pll->max_frac_feedback_div;
949 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
952 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
955 /* legacy radeons only have a few post_divs */
956 if (pll->flags & RADEON_PLL_LEGACY) {
957 if ((post_div == 5) ||
968 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
969 uint32_t feedback_div, current_freq = 0, error, vco_diff;
970 uint32_t pll_in = pll->reference_freq / ref_div;
971 uint32_t min_feed_div = pll->min_feedback_div;
972 uint32_t max_feed_div = pll->max_feedback_div + 1;
974 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
977 while (min_feed_div < max_feed_div) {
979 uint32_t min_frac_feed_div = min_fractional_feed_div;
980 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
981 uint32_t frac_feedback_div;
984 feedback_div = (min_feed_div + max_feed_div) / 2;
986 tmp = (uint64_t)pll->reference_freq * feedback_div;
987 vco = radeon_div(tmp, ref_div);
989 if (vco < pll_out_min) {
990 min_feed_div = feedback_div + 1;
992 } else if (vco > pll_out_max) {
993 max_feed_div = feedback_div;
997 while (min_frac_feed_div < max_frac_feed_div) {
998 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
999 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1000 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1001 current_freq = radeon_div(tmp, ref_div * post_div);
1003 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1004 if (freq < current_freq)
1007 error = freq - current_freq;
1009 error = abs(current_freq - freq);
1010 vco_diff = abs(vco - best_vco);
1012 if ((best_vco == 0 && error < best_error) ||
1014 ((best_error > 100 && error < best_error - 100) ||
1015 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1016 best_post_div = post_div;
1017 best_ref_div = ref_div;
1018 best_feedback_div = feedback_div;
1019 best_frac_feedback_div = frac_feedback_div;
1020 best_freq = current_freq;
1022 best_vco_diff = vco_diff;
1023 } else if (current_freq == freq) {
1024 if (best_freq == -1) {
1025 best_post_div = post_div;
1026 best_ref_div = ref_div;
1027 best_feedback_div = feedback_div;
1028 best_frac_feedback_div = frac_feedback_div;
1029 best_freq = current_freq;
1031 best_vco_diff = vco_diff;
1032 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1033 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1034 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1035 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1036 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1037 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1038 best_post_div = post_div;
1039 best_ref_div = ref_div;
1040 best_feedback_div = feedback_div;
1041 best_frac_feedback_div = frac_feedback_div;
1042 best_freq = current_freq;
1044 best_vco_diff = vco_diff;
1047 if (current_freq < freq)
1048 min_frac_feed_div = frac_feedback_div + 1;
1050 max_frac_feed_div = frac_feedback_div;
1052 if (current_freq < freq)
1053 min_feed_div = feedback_div + 1;
1055 max_feed_div = feedback_div;
1060 *dot_clock_p = best_freq / 10000;
1061 *fb_div_p = best_feedback_div;
1062 *frac_fb_div_p = best_frac_feedback_div;
1063 *ref_div_p = best_ref_div;
1064 *post_div_p = best_post_div;
1065 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1067 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1068 best_ref_div, best_post_div);
1072 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1074 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1076 if (radeon_fb->obj) {
1077 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1079 drm_framebuffer_cleanup(fb);
1083 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1084 struct drm_file *file_priv,
1085 unsigned int *handle)
1087 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1089 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1092 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1093 .destroy = radeon_user_framebuffer_destroy,
1094 .create_handle = radeon_user_framebuffer_create_handle,
1098 radeon_framebuffer_init(struct drm_device *dev,
1099 struct radeon_framebuffer *rfb,
1100 struct drm_mode_fb_cmd2 *mode_cmd,
1101 struct drm_gem_object *obj)
1105 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1106 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1114 static struct drm_framebuffer *
1115 radeon_user_framebuffer_create(struct drm_device *dev,
1116 struct drm_file *file_priv,
1117 struct drm_mode_fb_cmd2 *mode_cmd)
1119 struct drm_gem_object *obj;
1120 struct radeon_framebuffer *radeon_fb;
1123 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1125 dev_err(dev->dev, "No GEM object associated to handle 0x%08X, "
1126 "can't create framebuffer\n", mode_cmd->handles[0]);
1127 return ERR_PTR(-ENOENT);
1130 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1131 if (radeon_fb == NULL) {
1132 drm_gem_object_unreference_unlocked(obj);
1133 return ERR_PTR(-ENOMEM);
1136 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1139 drm_gem_object_unreference_unlocked(obj);
1140 return ERR_PTR(ret);
1143 return &radeon_fb->base;
1146 static void radeon_output_poll_changed(struct drm_device *dev)
1148 struct radeon_device *rdev = dev->dev_private;
1149 radeon_fb_output_poll_changed(rdev);
1152 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1153 .fb_create = radeon_user_framebuffer_create,
1154 .output_poll_changed = radeon_output_poll_changed
1157 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1162 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1163 { { TV_STD_NTSC, "ntsc" },
1164 { TV_STD_PAL, "pal" },
1165 { TV_STD_PAL_M, "pal-m" },
1166 { TV_STD_PAL_60, "pal-60" },
1167 { TV_STD_NTSC_J, "ntsc-j" },
1168 { TV_STD_SCART_PAL, "scart-pal" },
1169 { TV_STD_PAL_CN, "pal-cn" },
1170 { TV_STD_SECAM, "secam" },
1173 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1174 { { UNDERSCAN_OFF, "off" },
1175 { UNDERSCAN_ON, "on" },
1176 { UNDERSCAN_AUTO, "auto" },
1179 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1180 { { RADEON_AUDIO_DISABLE, "off" },
1181 { RADEON_AUDIO_ENABLE, "on" },
1182 { RADEON_AUDIO_AUTO, "auto" },
1185 static int radeon_modeset_create_props(struct radeon_device *rdev)
1189 if (rdev->is_atom_bios) {
1190 rdev->mode_info.coherent_mode_property =
1191 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1192 if (!rdev->mode_info.coherent_mode_property)
1196 if (!ASIC_IS_AVIVO(rdev)) {
1197 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1198 rdev->mode_info.tmds_pll_property =
1199 drm_property_create_enum(rdev->ddev, 0,
1201 radeon_tmds_pll_enum_list, sz);
1204 rdev->mode_info.load_detect_property =
1205 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1206 if (!rdev->mode_info.load_detect_property)
1209 drm_mode_create_scaling_mode_property(rdev->ddev);
1211 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1212 rdev->mode_info.tv_std_property =
1213 drm_property_create_enum(rdev->ddev, 0,
1215 radeon_tv_std_enum_list, sz);
1217 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1218 rdev->mode_info.underscan_property =
1219 drm_property_create_enum(rdev->ddev, 0,
1221 radeon_underscan_enum_list, sz);
1223 rdev->mode_info.underscan_hborder_property =
1224 drm_property_create_range(rdev->ddev, 0,
1225 "underscan hborder", 0, 128);
1226 if (!rdev->mode_info.underscan_hborder_property)
1229 rdev->mode_info.underscan_vborder_property =
1230 drm_property_create_range(rdev->ddev, 0,
1231 "underscan vborder", 0, 128);
1232 if (!rdev->mode_info.underscan_vborder_property)
1235 sz = ARRAY_SIZE(radeon_audio_enum_list);
1236 rdev->mode_info.audio_property =
1237 drm_property_create_enum(rdev->ddev, 0,
1239 radeon_audio_enum_list, sz);
1244 void radeon_update_display_priority(struct radeon_device *rdev)
1246 /* adjustment options for the display watermarks */
1247 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1248 /* set display priority to high for r3xx, rv515 chips
1249 * this avoids flickering due to underflow to the
1250 * display controllers during heavy acceleration.
1251 * Don't force high on rs4xx igp chips as it seems to
1252 * affect the sound card. See kernel bug 15982.
1254 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1255 !(rdev->flags & RADEON_IS_IGP))
1256 rdev->disp_priority = 2;
1258 rdev->disp_priority = 0;
1260 rdev->disp_priority = radeon_disp_priority;
1265 * Allocate hdmi structs and determine register offsets
1267 static void radeon_afmt_init(struct radeon_device *rdev)
1271 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1272 rdev->mode_info.afmt[i] = NULL;
1274 if (ASIC_IS_NODCE(rdev)) {
1276 } else if (ASIC_IS_DCE4(rdev)) {
1277 static uint32_t eg_offsets[] = {
1278 EVERGREEN_CRTC0_REGISTER_OFFSET,
1279 EVERGREEN_CRTC1_REGISTER_OFFSET,
1280 EVERGREEN_CRTC2_REGISTER_OFFSET,
1281 EVERGREEN_CRTC3_REGISTER_OFFSET,
1282 EVERGREEN_CRTC4_REGISTER_OFFSET,
1283 EVERGREEN_CRTC5_REGISTER_OFFSET,
1288 /* DCE8 has 7 audio blocks tied to DIG encoders */
1289 /* DCE6 has 6 audio blocks tied to DIG encoders */
1290 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1291 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1292 if (ASIC_IS_DCE8(rdev))
1294 else if (ASIC_IS_DCE6(rdev))
1296 else if (ASIC_IS_DCE5(rdev))
1298 else if (ASIC_IS_DCE41(rdev))
1303 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1304 for (i = 0; i < num_afmt; i++) {
1305 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1306 if (rdev->mode_info.afmt[i]) {
1307 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1308 rdev->mode_info.afmt[i]->id = i;
1311 } else if (ASIC_IS_DCE3(rdev)) {
1312 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1313 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1314 if (rdev->mode_info.afmt[0]) {
1315 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1316 rdev->mode_info.afmt[0]->id = 0;
1318 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1319 if (rdev->mode_info.afmt[1]) {
1320 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1321 rdev->mode_info.afmt[1]->id = 1;
1323 } else if (ASIC_IS_DCE2(rdev)) {
1324 /* DCE2 has at least 1 routable audio block */
1325 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1326 if (rdev->mode_info.afmt[0]) {
1327 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1328 rdev->mode_info.afmt[0]->id = 0;
1330 /* r6xx has 2 routable audio blocks */
1331 if (rdev->family >= CHIP_R600) {
1332 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1333 if (rdev->mode_info.afmt[1]) {
1334 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1335 rdev->mode_info.afmt[1]->id = 1;
1341 static void radeon_afmt_fini(struct radeon_device *rdev)
1345 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1346 kfree(rdev->mode_info.afmt[i]);
1347 rdev->mode_info.afmt[i] = NULL;
1351 int radeon_modeset_init(struct radeon_device *rdev)
1356 drm_mode_config_init(rdev->ddev);
1357 rdev->mode_info.mode_config_initialized = true;
1359 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1361 if (ASIC_IS_DCE5(rdev)) {
1362 rdev->ddev->mode_config.max_width = 16384;
1363 rdev->ddev->mode_config.max_height = 16384;
1364 } else if (ASIC_IS_AVIVO(rdev)) {
1365 rdev->ddev->mode_config.max_width = 8192;
1366 rdev->ddev->mode_config.max_height = 8192;
1368 rdev->ddev->mode_config.max_width = 4096;
1369 rdev->ddev->mode_config.max_height = 4096;
1372 rdev->ddev->mode_config.preferred_depth = 24;
1373 rdev->ddev->mode_config.prefer_shadow = 1;
1375 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1377 ret = radeon_modeset_create_props(rdev);
1382 /* init i2c buses */
1383 radeon_i2c_init(rdev);
1385 /* check combios for a valid hardcoded EDID - Sun servers */
1386 if (!rdev->is_atom_bios) {
1387 /* check for hardcoded EDID in BIOS */
1388 radeon_combios_check_hardcoded_edid(rdev);
1391 /* allocate crtcs */
1392 for (i = 0; i < rdev->num_crtc; i++) {
1393 radeon_crtc_init(rdev->ddev, i);
1396 /* okay we should have all the bios connectors */
1397 ret = radeon_setup_enc_conn(rdev->ddev);
1402 /* init dig PHYs, disp eng pll */
1403 if (rdev->is_atom_bios) {
1404 radeon_atom_encoder_init(rdev);
1405 radeon_atom_disp_eng_pll_init(rdev);
1408 /* initialize hpd */
1409 radeon_hpd_init(rdev);
1412 radeon_afmt_init(rdev);
1414 /* Initialize power management */
1415 radeon_pm_init(rdev);
1417 radeon_fbdev_init(rdev);
1418 drm_kms_helper_poll_init(rdev->ddev);
1423 void radeon_modeset_fini(struct radeon_device *rdev)
1425 radeon_fbdev_fini(rdev);
1426 kfree(rdev->mode_info.bios_hardcoded_edid);
1427 radeon_pm_fini(rdev);
1429 if (rdev->mode_info.mode_config_initialized) {
1430 radeon_afmt_fini(rdev);
1431 drm_kms_helper_poll_fini(rdev->ddev);
1432 radeon_hpd_fini(rdev);
1433 DRM_UNLOCK(rdev->ddev); /* Work around lock recursion. dumbbell@ */
1434 drm_mode_config_cleanup(rdev->ddev);
1435 DRM_LOCK(rdev->ddev);
1436 rdev->mode_info.mode_config_initialized = false;
1438 /* free i2c buses */
1439 radeon_i2c_fini(rdev);
1442 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1444 /* try and guess if this is a tv or a monitor */
1445 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1446 (mode->vdisplay == 576) || /* 576p */
1447 (mode->vdisplay == 720) || /* 720p */
1448 (mode->vdisplay == 1080)) /* 1080p */
1454 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1455 const struct drm_display_mode *mode,
1456 struct drm_display_mode *adjusted_mode)
1458 struct drm_device *dev = crtc->dev;
1459 struct radeon_device *rdev = dev->dev_private;
1460 struct drm_encoder *encoder;
1461 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1462 struct radeon_encoder *radeon_encoder;
1463 struct drm_connector *connector;
1464 struct radeon_connector *radeon_connector;
1466 u32 src_v = 1, dst_v = 1;
1467 u32 src_h = 1, dst_h = 1;
1469 radeon_crtc->h_border = 0;
1470 radeon_crtc->v_border = 0;
1472 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1473 if (encoder->crtc != crtc)
1475 radeon_encoder = to_radeon_encoder(encoder);
1476 connector = radeon_get_connector_for_encoder(encoder);
1477 radeon_connector = to_radeon_connector(connector);
1481 if (radeon_encoder->rmx_type == RMX_OFF)
1482 radeon_crtc->rmx_type = RMX_OFF;
1483 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1484 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1485 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1487 radeon_crtc->rmx_type = RMX_OFF;
1488 /* copy native mode */
1489 memcpy(&radeon_crtc->native_mode,
1490 &radeon_encoder->native_mode,
1491 sizeof(struct drm_display_mode));
1492 src_v = crtc->mode.vdisplay;
1493 dst_v = radeon_crtc->native_mode.vdisplay;
1494 src_h = crtc->mode.hdisplay;
1495 dst_h = radeon_crtc->native_mode.hdisplay;
1497 /* fix up for overscan on hdmi */
1498 if (ASIC_IS_AVIVO(rdev) &&
1499 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1500 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1501 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1502 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1503 is_hdtv_mode(mode)))) {
1504 if (radeon_encoder->underscan_hborder != 0)
1505 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1507 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1508 if (radeon_encoder->underscan_vborder != 0)
1509 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1511 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1512 radeon_crtc->rmx_type = RMX_FULL;
1513 src_v = crtc->mode.vdisplay;
1514 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1515 src_h = crtc->mode.hdisplay;
1516 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1520 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1521 /* WARNING: Right now this can't happen but
1522 * in the future we need to check that scaling
1523 * are consistent across different encoder
1524 * (ie all encoder can work with the same
1527 DRM_ERROR("Scaling not consistent across encoder.\n");
1532 if (radeon_crtc->rmx_type != RMX_OFF) {
1534 a.full = dfixed_const(src_v);
1535 b.full = dfixed_const(dst_v);
1536 radeon_crtc->vsc.full = dfixed_div(a, b);
1537 a.full = dfixed_const(src_h);
1538 b.full = dfixed_const(dst_h);
1539 radeon_crtc->hsc.full = dfixed_div(a, b);
1541 radeon_crtc->vsc.full = dfixed_const(1);
1542 radeon_crtc->hsc.full = dfixed_const(1);
1548 * Retrieve current video scanout position of crtc on a given gpu, and
1549 * an optional accurate timestamp of when query happened.
1551 * \param dev Device to query.
1552 * \param crtc Crtc to query.
1553 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1554 * \param *vpos Location where vertical scanout position should be stored.
1555 * \param *hpos Location where horizontal scanout position should go.
1556 * \param *stime Target location for timestamp taken immediately before
1557 * scanout position query. Can be NULL to skip timestamp.
1558 * \param *etime Target location for timestamp taken immediately after
1559 * scanout position query. Can be NULL to skip timestamp.
1561 * Returns vpos as a positive number while in active scanout area.
1562 * Returns vpos as a negative number inside vblank, counting the number
1563 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1564 * until start of active scanout / end of vblank."
1566 * \return Flags, or'ed together as follows:
1568 * DRM_SCANOUTPOS_VALID = Query successful.
1569 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1570 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1571 * this flag means that returned position may be offset by a constant but
1572 * unknown small number of scanlines wrt. real scanout position.
1575 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1576 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1578 u32 stat_crtc = 0, vbl = 0, position = 0;
1579 int vbl_start, vbl_end, vtotal, ret = 0;
1582 struct radeon_device *rdev = dev->dev_private;
1584 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1586 /* Get optional system timestamp before query. */
1588 *stime = ktime_get();
1590 if (ASIC_IS_DCE4(rdev)) {
1592 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1593 EVERGREEN_CRTC0_REGISTER_OFFSET);
1594 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1595 EVERGREEN_CRTC0_REGISTER_OFFSET);
1596 ret |= DRM_SCANOUTPOS_VALID;
1599 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1600 EVERGREEN_CRTC1_REGISTER_OFFSET);
1601 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1602 EVERGREEN_CRTC1_REGISTER_OFFSET);
1603 ret |= DRM_SCANOUTPOS_VALID;
1606 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1607 EVERGREEN_CRTC2_REGISTER_OFFSET);
1608 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1609 EVERGREEN_CRTC2_REGISTER_OFFSET);
1610 ret |= DRM_SCANOUTPOS_VALID;
1613 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1614 EVERGREEN_CRTC3_REGISTER_OFFSET);
1615 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1616 EVERGREEN_CRTC3_REGISTER_OFFSET);
1617 ret |= DRM_SCANOUTPOS_VALID;
1620 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1621 EVERGREEN_CRTC4_REGISTER_OFFSET);
1622 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1623 EVERGREEN_CRTC4_REGISTER_OFFSET);
1624 ret |= DRM_SCANOUTPOS_VALID;
1627 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1628 EVERGREEN_CRTC5_REGISTER_OFFSET);
1629 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1630 EVERGREEN_CRTC5_REGISTER_OFFSET);
1631 ret |= DRM_SCANOUTPOS_VALID;
1633 } else if (ASIC_IS_AVIVO(rdev)) {
1635 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1636 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1637 ret |= DRM_SCANOUTPOS_VALID;
1640 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1641 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1642 ret |= DRM_SCANOUTPOS_VALID;
1645 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1647 /* Assume vbl_end == 0, get vbl_start from
1650 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1651 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1652 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1653 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1654 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1655 if (!(stat_crtc & 1))
1658 ret |= DRM_SCANOUTPOS_VALID;
1661 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1662 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1663 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1664 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1665 if (!(stat_crtc & 1))
1668 ret |= DRM_SCANOUTPOS_VALID;
1672 /* Get optional system timestamp after query. */
1674 *etime = ktime_get();
1676 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1678 /* Decode into vertical and horizontal scanout position. */
1679 *vpos = position & 0x1fff;
1680 *hpos = (position >> 16) & 0x1fff;
1682 /* Valid vblank area boundaries from gpu retrieved? */
1685 ret |= DRM_SCANOUTPOS_ACCURATE;
1686 vbl_start = vbl & 0x1fff;
1687 vbl_end = (vbl >> 16) & 0x1fff;
1690 /* No: Fake something reasonable which gives at least ok results. */
1691 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1695 /* Test scanout position against vblank region. */
1696 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1699 /* Check if inside vblank area and apply corrective offsets:
1700 * vpos will then be >=0 in video scanout area, but negative
1701 * within vblank area, counting down the number of lines until
1705 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1706 if (in_vbl && (*vpos >= vbl_start)) {
1707 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1708 *vpos = *vpos - vtotal;
1711 /* Correct for shifted end of vbl at vbl_end. */
1712 *vpos = *vpos - vbl_end;
1716 ret |= DRM_SCANOUTPOS_INVBL;
1718 /* Is vpos outside nominal vblank area, but less than
1719 * 1/100 of a frame height away from start of vblank?
1720 * If so, assume this isn't a massively delayed vblank
1721 * interrupt, but a vblank interrupt that fired a few
1722 * microseconds before true start of vblank. Compensate
1723 * by adding a full frame duration to the final timestamp.
1724 * Happens, e.g., on ATI R500, R600.
1726 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1728 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1729 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1730 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1732 if (vbl_start - *vpos < vtotal / 100) {
1735 /* Signal this correction as "applied". */