2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
27 * Kernel port Author: Dave Airlie
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drm_dp_helper.h>
36 #include <drm/drm_fixed.h>
37 #include <drm/drm_crtc_helper.h>
42 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
43 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
44 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
45 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
47 enum radeon_rmx_type {
66 enum radeon_underscan_type {
79 RADEON_HPD_NONE = 0xff,
82 #define RADEON_MAX_I2C_BUS 16
84 /* radeon gpio-based i2c
85 * 1. "mask" reg and bits
86 * grabs the gpio pins for software use
91 * 3. "en" reg and bits
92 * sets the pin direction
98 struct radeon_i2c_bus_rec {
100 /* id used by atom */
102 /* id used by atom */
103 enum radeon_hpd_id hpd;
104 /* can be used with hw i2c engine */
106 /* uses multi-media i2c engine */
109 uint32_t mask_clk_reg;
110 uint32_t mask_data_reg;
114 uint32_t en_data_reg;
117 uint32_t mask_clk_mask;
118 uint32_t mask_data_mask;
120 uint32_t a_data_mask;
121 uint32_t en_clk_mask;
122 uint32_t en_data_mask;
124 uint32_t y_data_mask;
127 struct radeon_tmds_pll {
132 #define RADEON_MAX_BIOS_CONNECTOR 16
135 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
136 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
137 #define RADEON_PLL_USE_REF_DIV (1 << 2)
138 #define RADEON_PLL_LEGACY (1 << 3)
139 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
140 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
141 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
142 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
143 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
144 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
145 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
146 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
147 #define RADEON_PLL_USE_POST_DIV (1 << 12)
148 #define RADEON_PLL_IS_LCD (1 << 13)
149 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
152 /* reference frequency */
153 uint32_t reference_freq;
156 uint32_t reference_div;
159 /* pll in/out limits */
162 uint32_t pll_out_min;
163 uint32_t pll_out_max;
164 uint32_t lcd_pll_out_min;
165 uint32_t lcd_pll_out_max;
169 uint32_t min_ref_div;
170 uint32_t max_ref_div;
171 uint32_t min_post_div;
172 uint32_t max_post_div;
173 uint32_t min_feedback_div;
174 uint32_t max_feedback_div;
175 uint32_t min_frac_feedback_div;
176 uint32_t max_frac_feedback_div;
178 /* flags for the current clock */
185 struct radeon_i2c_chan {
188 struct drm_device *dev;
189 struct radeon_i2c_bus_rec rec;
193 /* mostly for macs, but really any system without connector tables */
194 enum radeon_connector_table {
198 CT_POWERBOOK_EXTERNAL,
199 CT_POWERBOOK_INTERNAL,
212 enum radeon_dvo_chip {
222 bool last_buffer_filled_status;
224 struct r600_audio_pin *pin;
227 struct radeon_mode_info {
228 struct atom_context *atom_context;
229 struct card_info *atom_card_info;
230 enum radeon_connector_table connector_table;
231 bool mode_config_initialized;
232 struct radeon_crtc *crtcs[6];
233 struct radeon_afmt *afmt[7];
234 /* DVI-I properties */
235 struct drm_property *coherent_mode_property;
236 /* DAC enable load detect */
237 struct drm_property *load_detect_property;
239 struct drm_property *tv_std_property;
240 /* legacy TMDS PLL detect */
241 struct drm_property *tmds_pll_property;
243 struct drm_property *underscan_property;
244 struct drm_property *underscan_hborder_property;
245 struct drm_property *underscan_vborder_property;
247 struct drm_property *audio_property;
248 /* hardcoded DFP edid from BIOS */
249 struct edid *bios_hardcoded_edid;
250 int bios_hardcoded_edid_size;
252 /* pointer to fbdev info structure */
253 struct radeon_fbdev *rfbdev;
256 /* pointer to backlight encoder */
257 struct radeon_encoder *bl_encoder;
260 #define RADEON_MAX_BL_LEVEL 0xFF
262 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
264 struct radeon_backlight_privdata {
265 struct radeon_encoder *encoder;
271 #define MAX_H_CODE_TIMING_LEN 32
272 #define MAX_V_CODE_TIMING_LEN 32
274 /* need to store these as reading
275 back code tables is excessive */
276 struct radeon_tv_regs {
278 uint32_t timing_cntl;
282 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
283 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
286 struct radeon_atom_ss {
299 struct drm_crtc base;
301 u16 lut_r[256], lut_g[256], lut_b[256];
304 uint32_t crtc_offset;
305 struct drm_gem_object *cursor_bo;
306 uint64_t cursor_addr;
309 int max_cursor_width;
310 int max_cursor_height;
311 uint32_t legacy_display_base_addr;
312 uint32_t legacy_cursor_offset;
313 enum radeon_rmx_type rmx_type;
318 struct drm_display_mode native_mode;
321 struct radeon_unpin_work *unpin_work;
322 int deferred_flip_completion;
324 struct radeon_atom_ss ss;
328 u32 pll_reference_div;
331 struct drm_encoder *encoder;
332 struct drm_connector *connector;
337 struct drm_display_mode hw_mode;
340 struct radeon_encoder_primary_dac {
341 /* legacy primary dac */
342 uint32_t ps2_pdac_adj;
345 struct radeon_encoder_lvds {
347 uint16_t panel_vcc_delay;
348 uint8_t panel_pwr_delay;
349 uint8_t panel_digon_delay;
350 uint8_t panel_blon_delay;
351 uint16_t panel_ref_divider;
352 uint8_t panel_post_divider;
353 uint16_t panel_fb_divider;
354 bool use_bios_dividers;
355 uint32_t lvds_gen_cntl;
357 struct drm_display_mode native_mode;
358 struct backlight_device *bl_dev;
360 uint8_t backlight_level;
363 struct radeon_encoder_tv_dac {
365 uint32_t ps2_tvdac_adj;
366 uint32_t ntsc_tvdac_adj;
367 uint32_t pal_tvdac_adj;
372 int supported_tv_stds;
374 enum radeon_tv_std tv_std;
375 struct radeon_tv_regs tv;
378 struct radeon_encoder_int_tmds {
379 /* legacy int tmds */
380 struct radeon_tmds_pll tmds_pll[4];
383 struct radeon_encoder_ext_tmds {
385 struct radeon_i2c_chan *i2c_bus;
387 enum radeon_dvo_chip dvo_chip;
390 /* spread spectrum */
391 struct radeon_encoder_atom_dig {
395 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
398 uint16_t panel_pwr_delay;
401 struct drm_display_mode native_mode;
402 struct backlight_device *bl_dev;
404 uint8_t backlight_level;
406 struct radeon_afmt *afmt;
409 struct radeon_encoder_atom_dac {
410 enum radeon_tv_std tv_std;
413 struct radeon_encoder {
414 struct drm_encoder base;
415 uint32_t encoder_enum;
418 uint32_t active_device;
420 uint32_t pixel_clock;
421 enum radeon_rmx_type rmx_type;
422 enum radeon_underscan_type underscan_type;
423 uint32_t underscan_hborder;
424 uint32_t underscan_vborder;
425 struct drm_display_mode native_mode;
427 int audio_polling_active;
432 struct radeon_connector_atom_dig {
433 uint32_t igp_lane_info;
435 struct radeon_i2c_chan *dp_i2c_bus;
436 u8 dpcd[DP_RECEIVER_CAP_SIZE];
443 struct radeon_gpio_rec {
451 enum radeon_hpd_id hpd;
453 struct radeon_gpio_rec gpio;
456 struct radeon_router {
458 struct radeon_i2c_bus_rec i2c_info;
463 u8 ddc_mux_control_pin;
468 u8 cd_mux_control_pin;
472 enum radeon_connector_audio {
473 RADEON_AUDIO_DISABLE = 0,
474 RADEON_AUDIO_ENABLE = 1,
475 RADEON_AUDIO_AUTO = 2
478 struct radeon_connector {
479 struct drm_connector base;
480 uint32_t connector_id;
482 struct radeon_i2c_chan *ddc_bus;
483 /* some systems have an hdmi and vga port with a shared ddc line */
486 /* we need to mind the EDID between detect
487 and get modes due to analog/digital/tvencoder */
490 bool dac_load_detect;
491 bool detected_by_load; /* if the connection status was determined by load */
492 uint16_t connector_object_id;
493 struct radeon_hpd hpd;
494 struct radeon_router router;
495 struct radeon_i2c_chan *router_bus;
496 enum radeon_connector_audio audio;
499 struct radeon_framebuffer {
500 struct drm_framebuffer base;
501 struct drm_gem_object *obj;
504 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
505 ((em) == ATOM_ENCODER_MODE_DP_MST))
507 struct atom_clock_dividers {
513 u32 whole_fb_div : 12;
514 u32 frac_fb_div : 14;
516 u32 frac_fb_div : 14;
517 u32 whole_fb_div : 12;
524 bool enable_post_div;
533 struct atom_mpll_param {
557 #define MEM_TYPE_GDDR5 0x50
558 #define MEM_TYPE_GDDR4 0x40
559 #define MEM_TYPE_GDDR3 0x30
560 #define MEM_TYPE_DDR2 0x20
561 #define MEM_TYPE_GDDR1 0x10
562 #define MEM_TYPE_DDR3 0xb0
563 #define MEM_TYPE_MASK 0xf0
565 struct atom_memory_info {
570 #define MAX_AC_TIMING_ENTRIES 16
572 struct atom_memory_clock_range_table
576 u32 mclk[MAX_AC_TIMING_ENTRIES];
579 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32
580 #define VBIOS_MAX_AC_TIMING_ENTRIES 20
582 struct atom_mc_reg_entry {
584 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
587 struct atom_mc_register_address {
592 struct atom_mc_reg_table {
595 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
596 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
599 #define MAX_VOLTAGE_ENTRIES 32
601 struct atom_voltage_table_entry
607 struct atom_voltage_table
612 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
615 extern enum radeon_tv_std
616 radeon_combios_get_tv_info(struct radeon_device *rdev);
617 extern enum radeon_tv_std
618 radeon_atombios_get_tv_info(struct radeon_device *rdev);
619 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
620 u16 *vddc, u16 *vddci, u16 *mvdd);
622 extern struct drm_connector *
623 radeon_get_connector_for_encoder(struct drm_encoder *encoder);
624 extern struct drm_connector *
625 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
626 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
629 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
630 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
631 extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
632 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
633 extern int radeon_get_monitor_bpc(struct drm_connector *connector);
635 extern void radeon_connector_hotplug(struct drm_connector *connector);
636 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
637 struct drm_display_mode *mode);
638 extern void radeon_dp_set_link_config(struct drm_connector *connector,
639 const struct drm_display_mode *mode);
640 extern void radeon_dp_link_train(struct drm_encoder *encoder,
641 struct drm_connector *connector);
642 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
643 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
644 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
645 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
646 struct drm_connector *connector);
647 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
648 extern void radeon_atom_encoder_init(struct radeon_device *rdev);
649 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
650 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
651 int action, uint8_t lane_num,
653 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
654 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
655 extern int radeon_dp_i2c_aux_ch(device_t dev, int mode,
656 u8 write_byte, u8 *read_byte);
658 extern void radeon_i2c_init(struct radeon_device *rdev);
659 extern void radeon_i2c_fini(struct radeon_device *rdev);
660 extern void radeon_combios_i2c_init(struct radeon_device *rdev);
661 extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
662 extern void radeon_i2c_add(struct radeon_device *rdev,
663 struct radeon_i2c_bus_rec *rec,
665 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
666 struct radeon_i2c_bus_rec *i2c_bus);
667 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
668 struct radeon_i2c_bus_rec *rec,
670 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
671 struct radeon_i2c_bus_rec *rec,
673 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
674 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
678 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
682 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
683 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
684 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
685 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
687 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
689 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
690 struct radeon_atom_ss *ss,
692 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
693 struct radeon_atom_ss *ss,
696 extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
698 uint32_t *dot_clock_p,
700 uint32_t *frac_fb_div_p,
702 uint32_t *post_div_p);
704 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
712 extern void radeon_setup_encoder_clones(struct drm_device *dev);
714 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
715 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
716 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
717 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
718 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
719 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
720 extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
721 extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
722 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
723 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
725 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
726 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
727 struct drm_framebuffer *old_fb);
728 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
729 struct drm_framebuffer *fb,
731 enum mode_set_atomic state);
732 extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
733 struct drm_display_mode *mode,
734 struct drm_display_mode *adjusted_mode,
736 struct drm_framebuffer *old_fb);
737 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
739 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
740 struct drm_framebuffer *old_fb);
741 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
742 struct drm_framebuffer *fb,
744 enum mode_set_atomic state);
745 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
746 struct drm_framebuffer *fb,
747 int x, int y, int atomic);
748 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
749 struct drm_file *file_priv,
753 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
756 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
758 int *vpos, int *hpos, ktime_t *stime,
761 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
763 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
764 extern bool radeon_atom_get_clock_info(struct drm_device *dev);
765 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
766 extern struct radeon_encoder_atom_dig *
767 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
768 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
769 struct radeon_encoder_int_tmds *tmds);
770 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
771 struct radeon_encoder_int_tmds *tmds);
772 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
773 struct radeon_encoder_int_tmds *tmds);
774 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
775 struct radeon_encoder_ext_tmds *tmds);
776 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
777 struct radeon_encoder_ext_tmds *tmds);
778 extern struct radeon_encoder_primary_dac *
779 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
780 extern struct radeon_encoder_tv_dac *
781 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
782 extern struct radeon_encoder_lvds *
783 radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
784 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
785 extern struct radeon_encoder_tv_dac *
786 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
787 extern struct radeon_encoder_primary_dac *
788 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
789 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
790 extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
791 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
792 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
793 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
794 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
795 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
796 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
798 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
800 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
802 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
804 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
805 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
806 u16 blue, int regno);
807 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
808 u16 *blue, int regno);
809 int radeon_framebuffer_init(struct drm_device *dev,
810 struct radeon_framebuffer *rfb,
811 struct drm_mode_fb_cmd2 *mode_cmd,
812 struct drm_gem_object *obj);
814 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
815 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
816 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
817 void radeon_atombios_init_crtc(struct drm_device *dev,
818 struct radeon_crtc *radeon_crtc);
819 void radeon_legacy_init_crtc(struct drm_device *dev,
820 struct radeon_crtc *radeon_crtc);
822 void radeon_get_clock_info(struct drm_device *dev);
824 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
825 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
827 void radeon_enc_destroy(struct drm_encoder *encoder);
828 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
829 void radeon_combios_asic_init(struct drm_device *dev);
830 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
831 const struct drm_display_mode *mode,
832 struct drm_display_mode *adjusted_mode);
833 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
834 struct drm_display_mode *adjusted_mode);
835 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
838 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
839 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
840 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
841 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
842 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
843 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
844 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
845 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
846 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
847 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
848 struct drm_display_mode *mode,
849 struct drm_display_mode *adjusted_mode);
852 int radeon_fbdev_init(struct radeon_device *rdev);
853 void radeon_fbdev_fini(struct radeon_device *rdev);
854 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
855 int radeon_fbdev_total_size(struct radeon_device *rdev);
856 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
858 void radeon_fb_output_poll_changed(struct radeon_device *rdev);
860 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
862 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);