2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_ring.c 254885 2013-08-25 19:37:15Z dumbbell $
31 #include <uapi_drm/radeon_drm.h>
32 #include "radeon_reg.h"
39 * IBs (Indirect Buffers) and areas of GPU accessible memory where
40 * commands are stored. You can put a pointer to the IB in the
41 * command ring and the hw will fetch the commands from the IB
42 * and execute them. Generally userspace acceleration drivers
43 * produce command buffers which are send to the kernel and
44 * put in IBs for execution by the requested ring.
46 static int radeon_debugfs_sa_init(struct radeon_device *rdev);
47 #endif /* DUMBBELL_WIP */
50 * radeon_ib_get - request an IB (Indirect Buffer)
52 * @rdev: radeon_device pointer
53 * @ring: ring index the IB is associated with
54 * @ib: IB object returned
55 * @size: requested IB size
57 * Request an IB (all asics). IBs are allocated using the
59 * Returns 0 on success, error on failure.
61 int radeon_ib_get(struct radeon_device *rdev, int ring,
62 struct radeon_ib *ib, struct radeon_vm *vm,
67 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true);
69 dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
73 r = radeon_semaphore_create(rdev, &ib->semaphore);
80 ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
83 /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
84 * space and soffset is the offset inside the pool bo
86 ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
88 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
90 ib->is_const_ib = false;
91 for (i = 0; i < RADEON_NUM_RINGS; ++i)
92 ib->sync_to[i] = NULL;
98 * radeon_ib_free - free an IB (Indirect Buffer)
100 * @rdev: radeon_device pointer
101 * @ib: IB object to free
103 * Free an IB (all asics).
105 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
107 radeon_semaphore_free(rdev, &ib->semaphore, ib->fence);
108 radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
109 radeon_fence_unref(&ib->fence);
113 * radeon_ib_sync_to - sync to fence before executing the IB
115 * @ib: IB object to add fence to
116 * @fence: fence to sync to
118 * Sync to the fence before executing the IB
120 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence)
122 struct radeon_fence *other;
127 other = ib->sync_to[fence->ring];
128 ib->sync_to[fence->ring] = radeon_fence_later(fence, other);
132 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
134 * @rdev: radeon_device pointer
135 * @ib: IB object to schedule
136 * @const_ib: Const IB to schedule (SI only)
138 * Schedule an IB on the associated ring (all asics).
139 * Returns 0 on success, error on failure.
141 * On SI, there are two parallel engines fed from the primary ring,
142 * the CE (Constant Engine) and the DE (Drawing Engine). Since
143 * resource descriptors have moved to memory, the CE allows you to
144 * prime the caches while the DE is updating register state so that
145 * the resource descriptors will be already in cache when the draw is
146 * processed. To accomplish this, the userspace driver submits two
147 * IBs, one for the CE and one for the DE. If there is a CE IB (called
148 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
149 * to SI there was just a DE IB.
151 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
152 struct radeon_ib *const_ib)
154 struct radeon_ring *ring = &rdev->ring[ib->ring];
155 bool need_sync = false;
158 if (!ib->length_dw || !ring->ready) {
159 /* TODO: Nothings in the ib we should report. */
160 dev_err(rdev->dev, "couldn't schedule ib\n");
164 /* 64 dwords should be enough for fence too */
165 r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8);
167 dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
170 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
171 struct radeon_fence *fence = ib->sync_to[i];
172 if (radeon_fence_need_sync(fence, ib->ring)) {
174 radeon_semaphore_sync_rings(rdev, ib->semaphore,
175 fence->ring, ib->ring);
176 radeon_fence_note_sync(fence, ib->ring);
179 /* immediately free semaphore when we don't need to sync */
181 radeon_semaphore_free(rdev, &ib->semaphore, NULL);
183 /* if we can't remember our last VM flush then flush now! */
184 /* XXX figure out why we have to flush for every IB */
185 if (ib->vm /*&& !ib->vm->last_flush*/) {
186 radeon_ring_vm_flush(rdev, ib->ring, ib->vm);
189 radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
190 radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
192 radeon_ring_ib_execute(rdev, ib->ring, ib);
193 r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
195 dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
196 radeon_ring_unlock_undo(rdev, ring);
200 const_ib->fence = radeon_fence_ref(ib->fence);
202 /* we just flushed the VM, remember that */
203 if (ib->vm && !ib->vm->last_flush) {
204 ib->vm->last_flush = radeon_fence_ref(ib->fence);
206 radeon_ring_unlock_commit(rdev, ring);
211 * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
213 * @rdev: radeon_device pointer
215 * Initialize the suballocator to manage a pool of memory
216 * for use as IBs (all asics).
217 * Returns 0 on success, error on failure.
219 int radeon_ib_pool_init(struct radeon_device *rdev)
223 if (rdev->ib_pool_ready) {
226 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
227 RADEON_IB_POOL_SIZE*64*1024,
228 RADEON_GPU_PAGE_SIZE,
229 RADEON_GEM_DOMAIN_GTT);
234 r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
239 rdev->ib_pool_ready = true;
241 if (radeon_debugfs_sa_init(rdev)) {
242 dev_err(rdev->dev, "failed to register debugfs file for SA\n");
244 #endif /* DUMBBELL_WIP */
249 * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
251 * @rdev: radeon_device pointer
253 * Tear down the suballocator managing the pool of memory
254 * for use as IBs (all asics).
256 void radeon_ib_pool_fini(struct radeon_device *rdev)
258 if (rdev->ib_pool_ready) {
259 radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
260 radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
261 rdev->ib_pool_ready = false;
266 * radeon_ib_ring_tests - test IBs on the rings
268 * @rdev: radeon_device pointer
270 * Test an IB (Indirect Buffer) on each ring.
271 * If the test fails, disable the ring.
272 * Returns 0 on success, error if the primary GFX ring
275 int radeon_ib_ring_tests(struct radeon_device *rdev)
280 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
281 struct radeon_ring *ring = &rdev->ring[i];
286 r = radeon_ib_test(rdev, i, ring);
290 if (i == RADEON_RING_TYPE_GFX_INDEX) {
291 /* oh, oh, that's really bad */
292 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
293 rdev->accel_working = false;
297 /* still not good, but we can live with it */
298 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
308 * Most engines on the GPU are fed via ring buffers. Ring
309 * buffers are areas of GPU accessible memory that the host
310 * writes commands into and the GPU reads commands out of.
311 * There is a rptr (read pointer) that determines where the
312 * GPU is currently reading, and a wptr (write pointer)
313 * which determines where the host has written. When the
314 * pointers are equal, the ring is idle. When the host
315 * writes commands to the ring buffer, it increments the
316 * wptr. The GPU then starts fetching commands and executes
317 * them until the pointers are equal again.
319 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
320 #endif /* DUMBBELL_WIP */
322 #if defined(DRM_DEBUG_CODE) && DRM_DEBUG_CODE != 0
324 * radeon_ring_write - write a value to the ring
326 * @ring: radeon_ring structure holding ring information
327 * @v: dword (dw) value to write
329 * Write a value to the requested ring buffer (all asics).
331 void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
334 if (ring->count_dw <= 0) {
335 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
338 ring->ring[ring->wptr++] = v;
339 ring->wptr &= ring->ptr_mask;
341 ring->ring_free_dw--;
346 * radeon_ring_supports_scratch_reg - check if the ring supports
347 * writing to scratch registers
349 * @rdev: radeon_device pointer
350 * @ring: radeon_ring structure holding ring information
352 * Check if a specific ring supports writing to scratch registers (all asics).
353 * Returns true if the ring supports writing to scratch regs, false if not.
355 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
356 struct radeon_ring *ring)
359 case RADEON_RING_TYPE_GFX_INDEX:
360 case CAYMAN_RING_TYPE_CP1_INDEX:
361 case CAYMAN_RING_TYPE_CP2_INDEX:
368 u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
369 struct radeon_ring *ring)
373 if (rdev->wb.enabled)
374 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
376 rptr = RREG32(ring->rptr_reg);
381 u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
382 struct radeon_ring *ring)
386 wptr = RREG32(ring->wptr_reg);
391 void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
392 struct radeon_ring *ring)
394 WREG32(ring->wptr_reg, ring->wptr);
395 (void)RREG32(ring->wptr_reg);
399 * radeon_ring_free_size - update the free size
401 * @rdev: radeon_device pointer
402 * @ring: radeon_ring structure holding ring information
404 * Update the free dw slots in the ring buffer (all asics).
406 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
408 ring->rptr = radeon_ring_get_rptr(rdev, ring);
409 /* This works because ring_size is a power of 2 */
410 ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
411 ring->ring_free_dw -= ring->wptr;
412 ring->ring_free_dw &= ring->ptr_mask;
413 if (!ring->ring_free_dw) {
414 ring->ring_free_dw = ring->ring_size / 4;
419 * radeon_ring_alloc - allocate space on the ring buffer
421 * @rdev: radeon_device pointer
422 * @ring: radeon_ring structure holding ring information
423 * @ndw: number of dwords to allocate in the ring buffer
425 * Allocate @ndw dwords in the ring buffer (all asics).
426 * Returns 0 on success, error on failure.
428 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
432 /* make sure we aren't trying to allocate more space than there is on the ring */
433 if (ndw > (ring->ring_size / 4))
435 /* Align requested size with padding so unlock_commit can
437 radeon_ring_free_size(rdev, ring);
438 if (ring->ring_free_dw == (ring->ring_size / 4)) {
439 /* This is an empty ring update lockup info to avoid
442 radeon_ring_lockup_update(ring);
444 ndw = (ndw + ring->align_mask) & ~ring->align_mask;
445 while (ndw > (ring->ring_free_dw - 1)) {
446 radeon_ring_free_size(rdev, ring);
447 if (ndw < ring->ring_free_dw) {
450 r = radeon_fence_wait_next_locked(rdev, ring->idx);
454 ring->count_dw = ndw;
455 ring->wptr_old = ring->wptr;
460 * radeon_ring_lock - lock the ring and allocate space on it
462 * @rdev: radeon_device pointer
463 * @ring: radeon_ring structure holding ring information
464 * @ndw: number of dwords to allocate in the ring buffer
466 * Lock the ring and allocate @ndw dwords in the ring buffer
468 * Returns 0 on success, error on failure.
470 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
474 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
475 r = radeon_ring_alloc(rdev, ring, ndw);
477 lockmgr(&rdev->ring_lock, LK_RELEASE);
484 * radeon_ring_commit - tell the GPU to execute the new
485 * commands on the ring buffer
487 * @rdev: radeon_device pointer
488 * @ring: radeon_ring structure holding ring information
490 * Update the wptr (write pointer) to tell the GPU to
491 * execute new commands on the ring buffer (all asics).
493 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
495 /* We pad to match fetch size */
496 while (ring->wptr & ring->align_mask) {
497 radeon_ring_write(ring, ring->nop);
500 radeon_ring_set_wptr(rdev, ring);
504 * radeon_ring_unlock_commit - tell the GPU to execute the new
505 * commands on the ring buffer and unlock it
507 * @rdev: radeon_device pointer
508 * @ring: radeon_ring structure holding ring information
510 * Call radeon_ring_commit() then unlock the ring (all asics).
512 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
514 radeon_ring_commit(rdev, ring);
515 lockmgr(&rdev->ring_lock, LK_RELEASE);
519 * radeon_ring_undo - reset the wptr
521 * @ring: radeon_ring structure holding ring information
523 * Reset the driver's copy of the wptr (all asics).
525 void radeon_ring_undo(struct radeon_ring *ring)
527 ring->wptr = ring->wptr_old;
531 * radeon_ring_unlock_undo - reset the wptr and unlock the ring
533 * @ring: radeon_ring structure holding ring information
535 * Call radeon_ring_undo() then unlock the ring (all asics).
537 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
539 radeon_ring_undo(ring);
540 lockmgr(&rdev->ring_lock, LK_RELEASE);
544 * radeon_ring_force_activity - add some nop packets to the ring
546 * @rdev: radeon_device pointer
547 * @ring: radeon_ring structure holding ring information
549 * Add some nop packets to the ring to force activity (all asics).
550 * Used for lockup detection to see if the rptr is advancing.
552 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring)
556 radeon_ring_free_size(rdev, ring);
557 if (ring->rptr == ring->wptr) {
558 r = radeon_ring_alloc(rdev, ring, 1);
560 radeon_ring_write(ring, ring->nop);
561 radeon_ring_commit(rdev, ring);
567 * radeon_ring_lockup_update - update lockup variables
569 * @ring: radeon_ring structure holding ring information
571 * Update the last rptr value and timestamp (all asics).
573 void radeon_ring_lockup_update(struct radeon_ring *ring)
575 ring->last_rptr = ring->rptr;
576 ring->last_activity = jiffies;
580 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
581 * @rdev: radeon device structure
582 * @ring: radeon_ring structure holding ring information
584 * We don't need to initialize the lockup tracking information as we will either
585 * have CP rptr to a different value of jiffies wrap around which will force
586 * initialization of the lockup tracking informations.
588 * A possible false positivie is if we get call after while and last_cp_rptr ==
589 * the current CP rptr, even if it's unlikely it might happen. To avoid this
590 * if the elapsed time since last call is bigger than 2 second than we return
591 * false and update the tracking information. Due to this the caller must call
592 * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported
593 * the fencing code should be cautious about that.
595 * Caller should write to the ring to force CP to do something so we don't get
596 * false positive when CP is just gived nothing to do.
599 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
601 unsigned long cjiffies, elapsed;
604 if (!time_after(cjiffies, ring->last_activity)) {
605 /* likely a wrap around */
606 radeon_ring_lockup_update(ring);
609 ring->rptr = radeon_ring_get_rptr(rdev, ring);
610 if (ring->rptr != ring->last_rptr) {
611 /* CP is still working no lockup */
612 radeon_ring_lockup_update(ring);
615 elapsed = jiffies_to_msecs(cjiffies - ring->last_activity);
616 if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
617 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
620 /* give a chance to the GPU ... */
625 * radeon_ring_backup - Back up the content of a ring
627 * @rdev: radeon_device pointer
628 * @ring: the ring we want to back up
630 * Saves all unprocessed commits from a ring, returns the number of dwords saved.
632 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
635 unsigned size, ptr, i;
637 /* just in case lock the ring */
638 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
641 if (ring->ring_obj == NULL) {
642 lockmgr(&rdev->ring_lock, LK_RELEASE);
646 /* it doesn't make sense to save anything if all fences are signaled */
647 if (!radeon_fence_count_emitted(rdev, ring->idx)) {
648 lockmgr(&rdev->ring_lock, LK_RELEASE);
652 /* calculate the number of dw on the ring */
653 if (ring->rptr_save_reg)
654 ptr = RREG32(ring->rptr_save_reg);
655 else if (rdev->wb.enabled)
656 ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
658 /* no way to read back the next rptr */
659 lockmgr(&rdev->ring_lock, LK_RELEASE);
663 size = ring->wptr + (ring->ring_size / 4);
665 size &= ring->ptr_mask;
667 lockmgr(&rdev->ring_lock, LK_RELEASE);
671 /* and then save the content of the ring */
672 *data = kmalloc(size * sizeof(uint32_t), M_DRM, M_WAITOK);
674 lockmgr(&rdev->ring_lock, LK_RELEASE);
677 for (i = 0; i < size; ++i) {
678 (*data)[i] = ring->ring[ptr++];
679 ptr &= ring->ptr_mask;
682 lockmgr(&rdev->ring_lock, LK_RELEASE);
687 * radeon_ring_restore - append saved commands to the ring again
689 * @rdev: radeon_device pointer
690 * @ring: ring to append commands to
691 * @size: number of dwords we want to write
692 * @data: saved commands
694 * Allocates space on the ring and restore the previously saved commands.
696 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
697 unsigned size, uint32_t *data)
704 /* restore the saved ring content */
705 r = radeon_ring_lock(rdev, ring, size);
709 for (i = 0; i < size; ++i) {
710 radeon_ring_write(ring, data[i]);
713 radeon_ring_unlock_commit(rdev, ring);
719 * radeon_ring_init - init driver ring struct.
721 * @rdev: radeon_device pointer
722 * @ring: radeon_ring structure holding ring information
723 * @ring_size: size of the ring
724 * @rptr_offs: offset of the rptr writeback location in the WB buffer
725 * @rptr_reg: MMIO offset of the rptr register
726 * @wptr_reg: MMIO offset of the wptr register
727 * @nop: nop packet for this ring
729 * Initialize the driver information for the selected ring (all asics).
730 * Returns 0 on success, error on failure.
732 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
733 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop)
738 ring->ring_size = ring_size;
739 ring->rptr_offs = rptr_offs;
740 ring->rptr_reg = rptr_reg;
741 ring->wptr_reg = wptr_reg;
743 /* Allocate ring buffer */
744 if (ring->ring_obj == NULL) {
745 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
746 RADEON_GEM_DOMAIN_GTT,
747 NULL, &ring->ring_obj);
749 dev_err(rdev->dev, "(%d) ring create failed\n", r);
752 r = radeon_bo_reserve(ring->ring_obj, false);
753 if (unlikely(r != 0)) {
754 radeon_bo_unref(&ring->ring_obj);
757 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
760 radeon_bo_unreserve(ring->ring_obj);
761 radeon_bo_unref(&ring->ring_obj);
762 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
765 ring_ptr = &ring->ring;
766 r = radeon_bo_kmap(ring->ring_obj,
768 radeon_bo_unreserve(ring->ring_obj);
770 dev_err(rdev->dev, "(%d) ring map failed\n", r);
771 radeon_bo_unref(&ring->ring_obj);
775 ring->ptr_mask = (ring->ring_size / 4) - 1;
776 ring->ring_free_dw = ring->ring_size / 4;
777 if (rdev->wb.enabled) {
778 u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
779 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
780 ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
783 if (radeon_debugfs_ring_init(rdev, ring)) {
784 DRM_ERROR("Failed to register debugfs file for rings !\n");
786 #endif /* DUMBBELL_WIP */
787 radeon_ring_lockup_update(ring);
792 * radeon_ring_fini - tear down the driver ring struct.
794 * @rdev: radeon_device pointer
795 * @ring: radeon_ring structure holding ring information
797 * Tear down the driver information for the selected ring (all asics).
799 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
802 struct radeon_bo *ring_obj;
804 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
805 ring_obj = ring->ring_obj;
808 ring->ring_obj = NULL;
809 lockmgr(&rdev->ring_lock, LK_RELEASE);
812 r = radeon_bo_reserve(ring_obj, false);
813 if (likely(r == 0)) {
814 radeon_bo_kunmap(ring_obj);
815 radeon_bo_unpin(ring_obj);
816 radeon_bo_unreserve(ring_obj);
818 radeon_bo_unref(&ring_obj);
825 #if defined(CONFIG_DEBUG_FS)
827 static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
829 struct drm_info_node *node = (struct drm_info_node *) m->private;
830 struct drm_device *dev = node->minor->dev;
831 struct radeon_device *rdev = dev->dev_private;
832 int ridx = *(int*)node->info_ent->data;
833 struct radeon_ring *ring = &rdev->ring[ridx];
834 unsigned count, i, j;
837 radeon_ring_free_size(rdev, ring);
838 count = (ring->ring_size / 4) - ring->ring_free_dw;
839 tmp = radeon_ring_get_wptr(rdev, ring);
840 seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp);
841 tmp = radeon_ring_get_rptr(rdev, ring);
842 seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp);
843 if (ring->rptr_save_reg) {
844 seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg,
845 RREG32(ring->rptr_save_reg));
847 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr);
848 seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr);
849 seq_printf(m, "last semaphore signal addr : 0x%016llx\n", ring->last_semaphore_signal_addr);
850 seq_printf(m, "last semaphore wait addr : 0x%016llx\n", ring->last_semaphore_wait_addr);
851 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
852 seq_printf(m, "%u dwords in ring\n", count);
853 /* print 8 dw before current rptr as often it's the last executed
854 * packet that is the root issue
856 i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
858 for (j = 0; j <= (count + 32); j++) {
859 seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]);
860 i = (i + 1) & ring->ptr_mask;
866 static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
867 static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
868 static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
869 static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
870 static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
871 static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
873 static struct drm_info_list radeon_debugfs_ring_info_list[] = {
874 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
875 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index},
876 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index},
877 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
878 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
879 {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
882 static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
884 struct drm_info_node *node = (struct drm_info_node *) m->private;
885 struct drm_device *dev = node->minor->dev;
886 struct radeon_device *rdev = dev->dev_private;
888 radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
894 static struct drm_info_list radeon_debugfs_sa_list[] = {
895 {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
901 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
903 #if defined(CONFIG_DEBUG_FS)
905 for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
906 struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
907 int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
910 if (&rdev->ring[ridx] != ring)
913 r = radeon_debugfs_add_files(rdev, info, 1);
921 static int radeon_debugfs_sa_init(struct radeon_device *rdev)
923 #if defined(CONFIG_DEBUG_FS)
924 return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
929 #endif /* DUMBBELL_WIP */