2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon_asic.h"
29 #include "trinity_dpm.h"
30 #include <linux/seq_file.h>
32 #define TRINITY_MAX_DEEPSLEEP_DIVIDER_ID 5
33 #define TRINITY_MINIMUM_ENGINE_CLOCK 800
34 #define SCLK_MIN_DIV_INTV_SHIFT 12
35 #define TRINITY_DISPCLK_BYPASS_THRESHOLD 10000
37 #ifndef TRINITY_MGCG_SEQUENCE
38 #define TRINITY_MGCG_SEQUENCE 100
40 static const u32 trinity_mgcg_shls_default[] =
42 /* Register, Value, Mask */
43 0x0000802c, 0xc0000000, 0xffffffff,
44 0x00003fc4, 0xc0000000, 0xffffffff,
45 0x00005448, 0x00000100, 0xffffffff,
46 0x000055e4, 0x00000100, 0xffffffff,
47 0x0000160c, 0x00000100, 0xffffffff,
48 0x00008984, 0x06000100, 0xffffffff,
49 0x0000c164, 0x00000100, 0xffffffff,
50 0x00008a18, 0x00000100, 0xffffffff,
51 0x0000897c, 0x06000100, 0xffffffff,
52 0x00008b28, 0x00000100, 0xffffffff,
53 0x00009144, 0x00800200, 0xffffffff,
54 0x00009a60, 0x00000100, 0xffffffff,
55 0x00009868, 0x00000100, 0xffffffff,
56 0x00008d58, 0x00000100, 0xffffffff,
57 0x00009510, 0x00000100, 0xffffffff,
58 0x0000949c, 0x00000100, 0xffffffff,
59 0x00009654, 0x00000100, 0xffffffff,
60 0x00009030, 0x00000100, 0xffffffff,
61 0x00009034, 0x00000100, 0xffffffff,
62 0x00009038, 0x00000100, 0xffffffff,
63 0x0000903c, 0x00000100, 0xffffffff,
64 0x00009040, 0x00000100, 0xffffffff,
65 0x0000a200, 0x00000100, 0xffffffff,
66 0x0000a204, 0x00000100, 0xffffffff,
67 0x0000a208, 0x00000100, 0xffffffff,
68 0x0000a20c, 0x00000100, 0xffffffff,
69 0x00009744, 0x00000100, 0xffffffff,
70 0x00003f80, 0x00000100, 0xffffffff,
71 0x0000a210, 0x00000100, 0xffffffff,
72 0x0000a214, 0x00000100, 0xffffffff,
73 0x000004d8, 0x00000100, 0xffffffff,
74 0x00009664, 0x00000100, 0xffffffff,
75 0x00009698, 0x00000100, 0xffffffff,
76 0x000004d4, 0x00000200, 0xffffffff,
77 0x000004d0, 0x00000000, 0xffffffff,
78 0x000030cc, 0x00000104, 0xffffffff,
79 0x0000d0c0, 0x00000100, 0xffffffff,
80 0x0000d8c0, 0x00000100, 0xffffffff,
81 0x0000951c, 0x00010000, 0xffffffff,
82 0x00009160, 0x00030002, 0xffffffff,
83 0x00009164, 0x00050004, 0xffffffff,
84 0x00009168, 0x00070006, 0xffffffff,
85 0x00009178, 0x00070000, 0xffffffff,
86 0x0000917c, 0x00030002, 0xffffffff,
87 0x00009180, 0x00050004, 0xffffffff,
88 0x0000918c, 0x00010006, 0xffffffff,
89 0x00009190, 0x00090008, 0xffffffff,
90 0x00009194, 0x00070000, 0xffffffff,
91 0x00009198, 0x00030002, 0xffffffff,
92 0x0000919c, 0x00050004, 0xffffffff,
93 0x000091a8, 0x00010006, 0xffffffff,
94 0x000091ac, 0x00090008, 0xffffffff,
95 0x000091b0, 0x00070000, 0xffffffff,
96 0x000091b4, 0x00030002, 0xffffffff,
97 0x000091b8, 0x00050004, 0xffffffff,
98 0x000091c4, 0x00010006, 0xffffffff,
99 0x000091c8, 0x00090008, 0xffffffff,
100 0x000091cc, 0x00070000, 0xffffffff,
101 0x000091d0, 0x00030002, 0xffffffff,
102 0x000091d4, 0x00050004, 0xffffffff,
103 0x000091e0, 0x00010006, 0xffffffff,
104 0x000091e4, 0x00090008, 0xffffffff,
105 0x000091e8, 0x00000000, 0xffffffff,
106 0x000091ec, 0x00070000, 0xffffffff,
107 0x000091f0, 0x00030002, 0xffffffff,
108 0x000091f4, 0x00050004, 0xffffffff,
109 0x00009200, 0x00010006, 0xffffffff,
110 0x00009204, 0x00090008, 0xffffffff,
111 0x00009208, 0x00070000, 0xffffffff,
112 0x0000920c, 0x00030002, 0xffffffff,
113 0x00009210, 0x00050004, 0xffffffff,
114 0x0000921c, 0x00010006, 0xffffffff,
115 0x00009220, 0x00090008, 0xffffffff,
116 0x00009294, 0x00000000, 0xffffffff
119 static const u32 trinity_mgcg_shls_enable[] =
121 /* Register, Value, Mask */
122 0x0000802c, 0xc0000000, 0xffffffff,
123 0x000008f8, 0x00000000, 0xffffffff,
124 0x000008fc, 0x00000000, 0x000133FF,
125 0x000008f8, 0x00000001, 0xffffffff,
126 0x000008fc, 0x00000000, 0xE00B03FC,
127 0x00009150, 0x96944200, 0xffffffff
130 static const u32 trinity_mgcg_shls_disable[] =
132 /* Register, Value, Mask */
133 0x0000802c, 0xc0000000, 0xffffffff,
134 0x00009150, 0x00600000, 0xffffffff,
135 0x000008f8, 0x00000000, 0xffffffff,
136 0x000008fc, 0xffffffff, 0x000133FF,
137 0x000008f8, 0x00000001, 0xffffffff,
138 0x000008fc, 0xffffffff, 0xE00B03FC
142 #ifndef TRINITY_SYSLS_SEQUENCE
143 #define TRINITY_SYSLS_SEQUENCE 100
145 static const u32 trinity_sysls_default[] =
147 /* Register, Value, Mask */
148 0x000055e8, 0x00000000, 0xffffffff,
149 0x0000d0bc, 0x00000000, 0xffffffff,
150 0x0000d8bc, 0x00000000, 0xffffffff,
151 0x000015c0, 0x000c1401, 0xffffffff,
152 0x0000264c, 0x000c0400, 0xffffffff,
153 0x00002648, 0x000c0400, 0xffffffff,
154 0x00002650, 0x000c0400, 0xffffffff,
155 0x000020b8, 0x000c0400, 0xffffffff,
156 0x000020bc, 0x000c0400, 0xffffffff,
157 0x000020c0, 0x000c0c80, 0xffffffff,
158 0x0000f4a0, 0x000000c0, 0xffffffff,
159 0x0000f4a4, 0x00680fff, 0xffffffff,
160 0x00002f50, 0x00000404, 0xffffffff,
161 0x000004c8, 0x00000001, 0xffffffff,
162 0x0000641c, 0x00000000, 0xffffffff,
163 0x00000c7c, 0x00000000, 0xffffffff,
164 0x00006dfc, 0x00000000, 0xffffffff
167 static const u32 trinity_sysls_disable[] =
169 /* Register, Value, Mask */
170 0x0000d0c0, 0x00000000, 0xffffffff,
171 0x0000d8c0, 0x00000000, 0xffffffff,
172 0x000055e8, 0x00000000, 0xffffffff,
173 0x0000d0bc, 0x00000000, 0xffffffff,
174 0x0000d8bc, 0x00000000, 0xffffffff,
175 0x000015c0, 0x00041401, 0xffffffff,
176 0x0000264c, 0x00040400, 0xffffffff,
177 0x00002648, 0x00040400, 0xffffffff,
178 0x00002650, 0x00040400, 0xffffffff,
179 0x000020b8, 0x00040400, 0xffffffff,
180 0x000020bc, 0x00040400, 0xffffffff,
181 0x000020c0, 0x00040c80, 0xffffffff,
182 0x0000f4a0, 0x000000c0, 0xffffffff,
183 0x0000f4a4, 0x00680000, 0xffffffff,
184 0x00002f50, 0x00000404, 0xffffffff,
185 0x000004c8, 0x00000001, 0xffffffff,
186 0x0000641c, 0x00007ffd, 0xffffffff,
187 0x00000c7c, 0x0000ff00, 0xffffffff,
188 0x00006dfc, 0x0000007f, 0xffffffff
191 static const u32 trinity_sysls_enable[] =
193 /* Register, Value, Mask */
194 0x000055e8, 0x00000001, 0xffffffff,
195 0x0000d0bc, 0x00000100, 0xffffffff,
196 0x0000d8bc, 0x00000100, 0xffffffff,
197 0x000015c0, 0x000c1401, 0xffffffff,
198 0x0000264c, 0x000c0400, 0xffffffff,
199 0x00002648, 0x000c0400, 0xffffffff,
200 0x00002650, 0x000c0400, 0xffffffff,
201 0x000020b8, 0x000c0400, 0xffffffff,
202 0x000020bc, 0x000c0400, 0xffffffff,
203 0x000020c0, 0x000c0c80, 0xffffffff,
204 0x0000f4a0, 0x000000c0, 0xffffffff,
205 0x0000f4a4, 0x00680fff, 0xffffffff,
206 0x00002f50, 0x00000903, 0xffffffff,
207 0x000004c8, 0x00000000, 0xffffffff,
208 0x0000641c, 0x00000000, 0xffffffff,
209 0x00000c7c, 0x00000000, 0xffffffff,
210 0x00006dfc, 0x00000000, 0xffffffff
214 static const u32 trinity_override_mgpg_sequences[] =
216 /* Register, Value */
217 0x00000200, 0xE030032C,
218 0x00000204, 0x00000FFF,
219 0x00000200, 0xE0300058,
220 0x00000204, 0x00030301,
221 0x00000200, 0xE0300054,
222 0x00000204, 0x500010FF,
223 0x00000200, 0xE0300074,
224 0x00000204, 0x00030301,
225 0x00000200, 0xE0300070,
226 0x00000204, 0x500010FF,
227 0x00000200, 0xE0300090,
228 0x00000204, 0x00030301,
229 0x00000200, 0xE030008C,
230 0x00000204, 0x500010FF,
231 0x00000200, 0xE03000AC,
232 0x00000204, 0x00030301,
233 0x00000200, 0xE03000A8,
234 0x00000204, 0x500010FF,
235 0x00000200, 0xE03000C8,
236 0x00000204, 0x00030301,
237 0x00000200, 0xE03000C4,
238 0x00000204, 0x500010FF,
239 0x00000200, 0xE03000E4,
240 0x00000204, 0x00030301,
241 0x00000200, 0xE03000E0,
242 0x00000204, 0x500010FF,
243 0x00000200, 0xE0300100,
244 0x00000204, 0x00030301,
245 0x00000200, 0xE03000FC,
246 0x00000204, 0x500010FF,
247 0x00000200, 0xE0300058,
248 0x00000204, 0x00030303,
249 0x00000200, 0xE0300054,
250 0x00000204, 0x600010FF,
251 0x00000200, 0xE0300074,
252 0x00000204, 0x00030303,
253 0x00000200, 0xE0300070,
254 0x00000204, 0x600010FF,
255 0x00000200, 0xE0300090,
256 0x00000204, 0x00030303,
257 0x00000200, 0xE030008C,
258 0x00000204, 0x600010FF,
259 0x00000200, 0xE03000AC,
260 0x00000204, 0x00030303,
261 0x00000200, 0xE03000A8,
262 0x00000204, 0x600010FF,
263 0x00000200, 0xE03000C8,
264 0x00000204, 0x00030303,
265 0x00000200, 0xE03000C4,
266 0x00000204, 0x600010FF,
267 0x00000200, 0xE03000E4,
268 0x00000204, 0x00030303,
269 0x00000200, 0xE03000E0,
270 0x00000204, 0x600010FF,
271 0x00000200, 0xE0300100,
272 0x00000204, 0x00030303,
273 0x00000200, 0xE03000FC,
274 0x00000204, 0x600010FF,
275 0x00000200, 0xE0300058,
276 0x00000204, 0x00030303,
277 0x00000200, 0xE0300054,
278 0x00000204, 0x700010FF,
279 0x00000200, 0xE0300074,
280 0x00000204, 0x00030303,
281 0x00000200, 0xE0300070,
282 0x00000204, 0x700010FF,
283 0x00000200, 0xE0300090,
284 0x00000204, 0x00030303,
285 0x00000200, 0xE030008C,
286 0x00000204, 0x700010FF,
287 0x00000200, 0xE03000AC,
288 0x00000204, 0x00030303,
289 0x00000200, 0xE03000A8,
290 0x00000204, 0x700010FF,
291 0x00000200, 0xE03000C8,
292 0x00000204, 0x00030303,
293 0x00000200, 0xE03000C4,
294 0x00000204, 0x700010FF,
295 0x00000200, 0xE03000E4,
296 0x00000204, 0x00030303,
297 0x00000200, 0xE03000E0,
298 0x00000204, 0x700010FF,
299 0x00000200, 0xE0300100,
300 0x00000204, 0x00030303,
301 0x00000200, 0xE03000FC,
302 0x00000204, 0x700010FF,
303 0x00000200, 0xE0300058,
304 0x00000204, 0x00010303,
305 0x00000200, 0xE0300054,
306 0x00000204, 0x800010FF,
307 0x00000200, 0xE0300074,
308 0x00000204, 0x00010303,
309 0x00000200, 0xE0300070,
310 0x00000204, 0x800010FF,
311 0x00000200, 0xE0300090,
312 0x00000204, 0x00010303,
313 0x00000200, 0xE030008C,
314 0x00000204, 0x800010FF,
315 0x00000200, 0xE03000AC,
316 0x00000204, 0x00010303,
317 0x00000200, 0xE03000A8,
318 0x00000204, 0x800010FF,
319 0x00000200, 0xE03000C4,
320 0x00000204, 0x800010FF,
321 0x00000200, 0xE03000C8,
322 0x00000204, 0x00010303,
323 0x00000200, 0xE03000E4,
324 0x00000204, 0x00010303,
325 0x00000200, 0xE03000E0,
326 0x00000204, 0x800010FF,
327 0x00000200, 0xE0300100,
328 0x00000204, 0x00010303,
329 0x00000200, 0xE03000FC,
330 0x00000204, 0x800010FF,
331 0x00000200, 0x0001f198,
332 0x00000204, 0x0003ffff,
333 0x00000200, 0x0001f19C,
334 0x00000204, 0x3fffffff,
335 0x00000200, 0xE030032C,
336 0x00000204, 0x00000000,
339 static void trinity_program_clk_gating_hw_sequence(struct radeon_device *rdev,
340 const u32 *seq, u32 count);
341 static void trinity_override_dynamic_mg_powergating(struct radeon_device *rdev);
342 static void trinity_apply_state_adjust_rules(struct radeon_device *rdev,
343 struct radeon_ps *new_rps,
344 struct radeon_ps *old_rps);
345 struct trinity_ps *trinity_get_ps(struct radeon_ps *rps);
346 struct trinity_power_info *trinity_get_pi(struct radeon_device *rdev);
347 void trinity_dpm_reset_asic(struct radeon_device *rdev);
349 struct trinity_ps *trinity_get_ps(struct radeon_ps *rps)
351 struct trinity_ps *ps = rps->ps_priv;
356 struct trinity_power_info *trinity_get_pi(struct radeon_device *rdev)
358 struct trinity_power_info *pi = rdev->pm.dpm.priv;
363 static void trinity_gfx_powergating_initialize(struct radeon_device *rdev)
365 struct trinity_power_info *pi = trinity_get_pi(rdev);
368 struct atom_clock_dividers dividers;
369 u32 xclk = radeon_get_xclk(rdev);
372 u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
374 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
375 25000, false, ÷rs);
379 value = RREG32_SMC(GFX_POWER_GATING_CNTL);
380 value &= ~(SSSD_MASK | PDS_DIV_MASK);
383 value |= PDS_DIV(dividers.post_div);
384 WREG32_SMC(GFX_POWER_GATING_CNTL, value);
386 r600_calculate_u_and_p(500, xclk, 16, &p, &u);
388 WREG32(CG_PG_CTRL, SP(p) | SU(u));
390 WREG32_P(CG_GIPOTS, CG_GIPOT(p), ~CG_GIPOT_MASK);
392 /* XXX double check hw_rev */
393 if (pi->override_dynamic_mgpg && (hw_rev == 0))
394 trinity_override_dynamic_mg_powergating(rdev);
398 #define CGCG_CGTT_LOCAL0_MASK 0xFFFF33FF
399 #define CGCG_CGTT_LOCAL1_MASK 0xFFFB0FFE
400 #define CGTS_SM_CTRL_REG_DISABLE 0x00600000
401 #define CGTS_SM_CTRL_REG_ENABLE 0x96944200
403 static void trinity_mg_clockgating_enable(struct radeon_device *rdev,
410 local0 = RREG32_CG(CG_CGTT_LOCAL_0);
411 local1 = RREG32_CG(CG_CGTT_LOCAL_1);
413 WREG32_CG(CG_CGTT_LOCAL_0,
414 (0x00380000 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
415 WREG32_CG(CG_CGTT_LOCAL_1,
416 (0x0E000000 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
418 WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_ENABLE);
420 WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_DISABLE);
422 local0 = RREG32_CG(CG_CGTT_LOCAL_0);
423 local1 = RREG32_CG(CG_CGTT_LOCAL_1);
425 WREG32_CG(CG_CGTT_LOCAL_0,
426 CGCG_CGTT_LOCAL0_MASK | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
427 WREG32_CG(CG_CGTT_LOCAL_1,
428 CGCG_CGTT_LOCAL1_MASK | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
432 static void trinity_mg_clockgating_initialize(struct radeon_device *rdev)
435 const u32 *seq = NULL;
437 seq = &trinity_mgcg_shls_default[0];
438 count = sizeof(trinity_mgcg_shls_default) / (3 * sizeof(u32));
440 trinity_program_clk_gating_hw_sequence(rdev, seq, count);
443 static void trinity_gfx_clockgating_enable(struct radeon_device *rdev,
447 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
449 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
450 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
451 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
452 RREG32(GB_ADDR_CONFIG);
456 static void trinity_program_clk_gating_hw_sequence(struct radeon_device *rdev,
457 const u32 *seq, u32 count)
459 u32 i, length = count * 3;
461 for (i = 0; i < length; i += 3)
462 WREG32_P(seq[i], seq[i+1], ~seq[i+2]);
465 static void trinity_program_override_mgpg_sequences(struct radeon_device *rdev,
466 const u32 *seq, u32 count)
468 u32 i, length = count * 2;
470 for (i = 0; i < length; i += 2)
471 WREG32(seq[i], seq[i+1]);
475 static void trinity_override_dynamic_mg_powergating(struct radeon_device *rdev)
478 const u32 *seq = NULL;
480 seq = &trinity_override_mgpg_sequences[0];
481 count = sizeof(trinity_override_mgpg_sequences) / (2 * sizeof(u32));
483 trinity_program_override_mgpg_sequences(rdev, seq, count);
486 static void trinity_ls_clockgating_enable(struct radeon_device *rdev,
490 const u32 *seq = NULL;
493 seq = &trinity_sysls_enable[0];
494 count = sizeof(trinity_sysls_enable) / (3 * sizeof(u32));
496 seq = &trinity_sysls_disable[0];
497 count = sizeof(trinity_sysls_disable) / (3 * sizeof(u32));
500 trinity_program_clk_gating_hw_sequence(rdev, seq, count);
503 static void trinity_gfx_powergating_enable(struct radeon_device *rdev,
507 if (RREG32_SMC(CC_SMU_TST_EFUSE1_MISC) & RB_BACKEND_DISABLE_MASK)
508 WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01));
510 WREG32_P(SCLK_PWRMGT_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
512 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_PWR_DOWN_EN);
513 RREG32(GB_ADDR_CONFIG);
517 static void trinity_gfx_dynamic_mgpg_enable(struct radeon_device *rdev,
523 value = RREG32_SMC(PM_I_CNTL_1);
524 value &= ~DS_PG_CNTL_MASK;
525 value |= DS_PG_CNTL(1);
526 WREG32_SMC(PM_I_CNTL_1, value);
528 value = RREG32_SMC(SMU_S_PG_CNTL);
529 value &= ~DS_PG_EN_MASK;
530 value |= DS_PG_EN(1);
531 WREG32_SMC(SMU_S_PG_CNTL, value);
533 value = RREG32_SMC(SMU_S_PG_CNTL);
534 value &= ~DS_PG_EN_MASK;
535 WREG32_SMC(SMU_S_PG_CNTL, value);
537 value = RREG32_SMC(PM_I_CNTL_1);
538 value &= ~DS_PG_CNTL_MASK;
539 WREG32_SMC(PM_I_CNTL_1, value);
542 trinity_gfx_dynamic_mgpg_config(rdev);
546 static void trinity_enable_clock_power_gating(struct radeon_device *rdev)
548 struct trinity_power_info *pi = trinity_get_pi(rdev);
550 if (pi->enable_gfx_clock_gating)
551 sumo_gfx_clockgating_initialize(rdev);
552 if (pi->enable_mg_clock_gating)
553 trinity_mg_clockgating_initialize(rdev);
554 if (pi->enable_gfx_power_gating)
555 trinity_gfx_powergating_initialize(rdev);
556 if (pi->enable_mg_clock_gating) {
557 trinity_ls_clockgating_enable(rdev, true);
558 trinity_mg_clockgating_enable(rdev, true);
560 if (pi->enable_gfx_clock_gating)
561 trinity_gfx_clockgating_enable(rdev, true);
562 if (pi->enable_gfx_dynamic_mgpg)
563 trinity_gfx_dynamic_mgpg_enable(rdev, true);
564 if (pi->enable_gfx_power_gating)
565 trinity_gfx_powergating_enable(rdev, true);
568 static void trinity_disable_clock_power_gating(struct radeon_device *rdev)
570 struct trinity_power_info *pi = trinity_get_pi(rdev);
572 if (pi->enable_gfx_power_gating)
573 trinity_gfx_powergating_enable(rdev, false);
574 if (pi->enable_gfx_dynamic_mgpg)
575 trinity_gfx_dynamic_mgpg_enable(rdev, false);
576 if (pi->enable_gfx_clock_gating)
577 trinity_gfx_clockgating_enable(rdev, false);
578 if (pi->enable_mg_clock_gating) {
579 trinity_mg_clockgating_enable(rdev, false);
580 trinity_ls_clockgating_enable(rdev, false);
584 static void trinity_set_divider_value(struct radeon_device *rdev,
587 struct atom_clock_dividers dividers;
590 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
592 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
593 sclk, false, ÷rs);
597 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
598 value &= ~CLK_DIVIDER_MASK;
599 value |= CLK_DIVIDER(dividers.post_div);
600 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
602 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
603 sclk/2, false, ÷rs);
607 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix);
608 value &= ~PD_SCLK_DIVIDER_MASK;
609 value |= PD_SCLK_DIVIDER(dividers.post_div);
610 WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value);
613 static void trinity_set_ds_dividers(struct radeon_device *rdev,
614 u32 index, u32 divider)
617 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
619 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
620 value &= ~DS_DIV_MASK;
621 value |= DS_DIV(divider);
622 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
625 static void trinity_set_ss_dividers(struct radeon_device *rdev,
626 u32 index, u32 divider)
629 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
631 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
632 value &= ~DS_SH_DIV_MASK;
633 value |= DS_SH_DIV(divider);
634 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
637 static void trinity_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
639 struct trinity_power_info *pi = trinity_get_pi(rdev);
640 u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid);
642 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
644 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
646 value |= VID(vid_7bit);
647 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
649 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
652 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
655 static void trinity_set_allos_gnb_slow(struct radeon_device *rdev,
656 u32 index, u32 gnb_slow)
659 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
661 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);
662 value &= ~GNB_SLOW_MASK;
663 value |= GNB_SLOW(gnb_slow);
664 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);
667 static void trinity_set_force_nbp_state(struct radeon_device *rdev,
668 u32 index, u32 force_nbp_state)
671 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
673 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);
674 value &= ~FORCE_NBPS1_MASK;
675 value |= FORCE_NBPS1(force_nbp_state);
676 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);
679 static void trinity_set_display_wm(struct radeon_device *rdev,
683 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
685 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
686 value &= ~DISPLAY_WM_MASK;
687 value |= DISPLAY_WM(wm);
688 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
691 static void trinity_set_vce_wm(struct radeon_device *rdev,
695 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
697 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
698 value &= ~VCE_WM_MASK;
700 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
703 static void trinity_set_at(struct radeon_device *rdev,
707 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
709 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix);
712 WREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix, value);
715 static void trinity_program_power_level(struct radeon_device *rdev,
716 struct trinity_pl *pl, u32 index)
718 struct trinity_power_info *pi = trinity_get_pi(rdev);
720 if (index >= SUMO_MAX_HARDWARE_POWERLEVELS)
723 trinity_set_divider_value(rdev, index, pl->sclk);
724 trinity_set_vid(rdev, index, pl->vddc_index);
725 trinity_set_ss_dividers(rdev, index, pl->ss_divider_index);
726 trinity_set_ds_dividers(rdev, index, pl->ds_divider_index);
727 trinity_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
728 trinity_set_force_nbp_state(rdev, index, pl->force_nbp_state);
729 trinity_set_display_wm(rdev, index, pl->display_wm);
730 trinity_set_vce_wm(rdev, index, pl->vce_wm);
731 trinity_set_at(rdev, index, pi->at[index]);
734 static void trinity_power_level_enable_disable(struct radeon_device *rdev,
735 u32 index, bool enable)
738 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
740 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
741 value &= ~STATE_VALID_MASK;
743 value |= STATE_VALID(1);
744 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
747 static bool trinity_dpm_enabled(struct radeon_device *rdev)
749 if (RREG32_SMC(SMU_SCLK_DPM_CNTL) & SCLK_DPM_EN(1))
755 static void trinity_start_dpm(struct radeon_device *rdev)
757 u32 value = RREG32_SMC(SMU_SCLK_DPM_CNTL);
759 value &= ~(SCLK_DPM_EN_MASK | SCLK_DPM_BOOT_STATE_MASK | VOLTAGE_CHG_EN_MASK);
760 value |= SCLK_DPM_EN(1) | SCLK_DPM_BOOT_STATE(0) | VOLTAGE_CHG_EN(1);
761 WREG32_SMC(SMU_SCLK_DPM_CNTL, value);
763 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
764 WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~EN);
766 trinity_dpm_config(rdev, true);
769 static void trinity_wait_for_dpm_enabled(struct radeon_device *rdev)
773 for (i = 0; i < rdev->usec_timeout; i++) {
774 if (RREG32(SCLK_PWRMGT_CNTL) & DYNAMIC_PM_EN)
778 for (i = 0; i < rdev->usec_timeout; i++) {
779 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_STATE_MASK) == 0)
783 for (i = 0; i < rdev->usec_timeout; i++) {
784 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0)
790 static void trinity_stop_dpm(struct radeon_device *rdev)
794 WREG32_P(CG_CG_VOLTAGE_CNTL, EN, ~EN);
796 sclk_dpm_cntl = RREG32_SMC(SMU_SCLK_DPM_CNTL);
797 sclk_dpm_cntl &= ~(SCLK_DPM_EN_MASK | VOLTAGE_CHG_EN_MASK);
798 WREG32_SMC(SMU_SCLK_DPM_CNTL, sclk_dpm_cntl);
800 trinity_dpm_config(rdev, false);
803 static void trinity_start_am(struct radeon_device *rdev)
805 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~(RESET_SCLK_CNT | RESET_BUSY_CNT));
808 static void trinity_reset_am(struct radeon_device *rdev)
810 WREG32_P(SCLK_PWRMGT_CNTL, RESET_SCLK_CNT | RESET_BUSY_CNT,
811 ~(RESET_SCLK_CNT | RESET_BUSY_CNT));
814 static void trinity_wait_for_level_0(struct radeon_device *rdev)
818 for (i = 0; i < rdev->usec_timeout; i++) {
819 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0)
825 static void trinity_enable_power_level_0(struct radeon_device *rdev)
827 trinity_power_level_enable_disable(rdev, 0, true);
830 static void trinity_force_level_0(struct radeon_device *rdev)
832 trinity_dpm_force_state(rdev, 0);
835 static void trinity_unforce_levels(struct radeon_device *rdev)
837 trinity_dpm_no_forced_level(rdev);
840 static void trinity_program_power_levels_0_to_n(struct radeon_device *rdev,
841 struct radeon_ps *new_rps,
842 struct radeon_ps *old_rps)
844 struct trinity_ps *new_ps = trinity_get_ps(new_rps);
845 struct trinity_ps *old_ps = trinity_get_ps(old_rps);
847 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;
849 for (i = 0; i < new_ps->num_levels; i++) {
850 trinity_program_power_level(rdev, &new_ps->levels[i], i);
851 trinity_power_level_enable_disable(rdev, i, true);
854 for (i = new_ps->num_levels; i < n_current_state_levels; i++)
855 trinity_power_level_enable_disable(rdev, i, false);
858 static void trinity_program_bootup_state(struct radeon_device *rdev)
860 struct trinity_power_info *pi = trinity_get_pi(rdev);
863 trinity_program_power_level(rdev, &pi->boot_pl, 0);
864 trinity_power_level_enable_disable(rdev, 0, true);
866 for (i = 1; i < 8; i++)
867 trinity_power_level_enable_disable(rdev, i, false);
870 static void trinity_setup_uvd_clock_table(struct radeon_device *rdev,
871 struct radeon_ps *rps)
873 struct trinity_ps *ps = trinity_get_ps(rps);
874 u32 uvdstates = (ps->vclk_low_divider |
875 ps->vclk_high_divider << 8 |
876 ps->dclk_low_divider << 16 |
877 ps->dclk_high_divider << 24);
879 WREG32_SMC(SMU_UVD_DPM_STATES, uvdstates);
882 static void trinity_setup_uvd_dpm_interval(struct radeon_device *rdev,
886 u32 tp = RREG32_SMC(PM_TP);
888 u32 xclk = radeon_get_xclk(rdev);
890 r600_calculate_u_and_p(interval, xclk, 16, &p, &u);
892 val = (p + tp - 1) / tp;
894 WREG32_SMC(SMU_UVD_DPM_CNTL, val);
897 static bool trinity_uvd_clocks_zero(struct radeon_ps *rps)
899 if ((rps->vclk == 0) && (rps->dclk == 0))
905 static bool trinity_uvd_clocks_equal(struct radeon_ps *rps1,
906 struct radeon_ps *rps2)
908 struct trinity_ps *ps1 = trinity_get_ps(rps1);
909 struct trinity_ps *ps2 = trinity_get_ps(rps2);
911 if ((rps1->vclk == rps2->vclk) &&
912 (rps1->dclk == rps2->dclk) &&
913 (ps1->vclk_low_divider == ps2->vclk_low_divider) &&
914 (ps1->vclk_high_divider == ps2->vclk_high_divider) &&
915 (ps1->dclk_low_divider == ps2->dclk_low_divider) &&
916 (ps1->dclk_high_divider == ps2->dclk_high_divider))
922 static void trinity_setup_uvd_clocks(struct radeon_device *rdev,
923 struct radeon_ps *new_rps,
924 struct radeon_ps *old_rps)
926 struct trinity_power_info *pi = trinity_get_pi(rdev);
928 if (pi->enable_gfx_power_gating) {
929 trinity_gfx_powergating_enable(rdev, false);
933 if (trinity_uvd_clocks_zero(new_rps) &&
934 !trinity_uvd_clocks_zero(old_rps)) {
935 trinity_setup_uvd_dpm_interval(rdev, 0);
936 } else if (!trinity_uvd_clocks_zero(new_rps)) {
937 trinity_setup_uvd_clock_table(rdev, new_rps);
939 if (trinity_uvd_clocks_zero(old_rps)) {
940 u32 tmp = RREG32(CG_MISC_REG);
942 WREG32(CG_MISC_REG, tmp);
944 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
946 trinity_setup_uvd_dpm_interval(rdev, 3000);
949 trinity_uvd_dpm_config(rdev);
951 if (trinity_uvd_clocks_zero(new_rps) ||
952 trinity_uvd_clocks_equal(new_rps, old_rps))
955 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
958 if (pi->enable_gfx_power_gating) {
959 trinity_gfx_powergating_enable(rdev, true);
963 static void trinity_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
964 struct radeon_ps *new_rps,
965 struct radeon_ps *old_rps)
967 struct trinity_ps *new_ps = trinity_get_ps(new_rps);
968 struct trinity_ps *current_ps = trinity_get_ps(new_rps);
970 if (new_ps->levels[new_ps->num_levels - 1].sclk >=
971 current_ps->levels[current_ps->num_levels - 1].sclk)
974 trinity_setup_uvd_clocks(rdev, new_rps, old_rps);
977 static void trinity_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
978 struct radeon_ps *new_rps,
979 struct radeon_ps *old_rps)
981 struct trinity_ps *new_ps = trinity_get_ps(new_rps);
982 struct trinity_ps *current_ps = trinity_get_ps(old_rps);
984 if (new_ps->levels[new_ps->num_levels - 1].sclk <
985 current_ps->levels[current_ps->num_levels - 1].sclk)
988 trinity_setup_uvd_clocks(rdev, new_rps, old_rps);
991 static void trinity_program_ttt(struct radeon_device *rdev)
993 struct trinity_power_info *pi = trinity_get_pi(rdev);
994 u32 value = RREG32_SMC(SMU_SCLK_DPM_TTT);
996 value &= ~(HT_MASK | LT_MASK);
997 value |= HT((pi->thermal_auto_throttling + 49) * 8);
998 value |= LT((pi->thermal_auto_throttling + 49 - pi->sys_info.htc_hyst_lmt) * 8);
999 WREG32_SMC(SMU_SCLK_DPM_TTT, value);
1002 static void trinity_enable_att(struct radeon_device *rdev)
1004 u32 value = RREG32_SMC(SMU_SCLK_DPM_TT_CNTL);
1006 value &= ~SCLK_TT_EN_MASK;
1007 value |= SCLK_TT_EN(1);
1008 WREG32_SMC(SMU_SCLK_DPM_TT_CNTL, value);
1011 static void trinity_program_sclk_dpm(struct radeon_device *rdev)
1014 u32 tp = RREG32_SMC(PM_TP);
1016 u32 xclk = radeon_get_xclk(rdev);
1019 r600_calculate_u_and_p(400, xclk, 16, &p, &u);
1021 ni = (p + tp - 1) / tp;
1023 value = RREG32_SMC(PM_I_CNTL_1);
1024 value &= ~SCLK_DPM_MASK;
1025 value |= SCLK_DPM(ni);
1026 WREG32_SMC(PM_I_CNTL_1, value);
1029 static int trinity_set_thermal_temperature_range(struct radeon_device *rdev,
1030 int min_temp, int max_temp)
1032 int low_temp = 0 * 1000;
1033 int high_temp = 255 * 1000;
1035 if (low_temp < min_temp)
1036 low_temp = min_temp;
1037 if (high_temp > max_temp)
1038 high_temp = max_temp;
1039 if (high_temp < low_temp) {
1040 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1044 WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);
1045 WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);
1047 rdev->pm.dpm.thermal.min_temp = low_temp;
1048 rdev->pm.dpm.thermal.max_temp = high_temp;
1053 static void trinity_update_current_ps(struct radeon_device *rdev,
1054 struct radeon_ps *rps)
1056 struct trinity_ps *new_ps = trinity_get_ps(rps);
1057 struct trinity_power_info *pi = trinity_get_pi(rdev);
1059 pi->current_rps = *rps;
1060 pi->current_ps = *new_ps;
1061 pi->current_rps.ps_priv = &pi->current_ps;
1064 static void trinity_update_requested_ps(struct radeon_device *rdev,
1065 struct radeon_ps *rps)
1067 struct trinity_ps *new_ps = trinity_get_ps(rps);
1068 struct trinity_power_info *pi = trinity_get_pi(rdev);
1070 pi->requested_rps = *rps;
1071 pi->requested_ps = *new_ps;
1072 pi->requested_rps.ps_priv = &pi->requested_ps;
1075 void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
1077 struct trinity_power_info *pi = trinity_get_pi(rdev);
1079 if (pi->enable_bapm) {
1080 trinity_acquire_mutex(rdev);
1081 trinity_dpm_bapm_enable(rdev, enable);
1082 trinity_release_mutex(rdev);
1086 int trinity_dpm_enable(struct radeon_device *rdev)
1088 struct trinity_power_info *pi = trinity_get_pi(rdev);
1091 trinity_acquire_mutex(rdev);
1093 if (trinity_dpm_enabled(rdev)) {
1094 trinity_release_mutex(rdev);
1098 trinity_enable_clock_power_gating(rdev);
1099 trinity_program_bootup_state(rdev);
1100 sumo_program_vc(rdev, 0x00C00033);
1101 trinity_start_am(rdev);
1102 if (pi->enable_auto_thermal_throttling) {
1103 trinity_program_ttt(rdev);
1104 trinity_enable_att(rdev);
1106 trinity_program_sclk_dpm(rdev);
1107 trinity_start_dpm(rdev);
1108 trinity_wait_for_dpm_enabled(rdev);
1109 trinity_dpm_bapm_enable(rdev, false);
1110 trinity_release_mutex(rdev);
1112 if (rdev->irq.installed &&
1113 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1114 ret = trinity_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1116 trinity_release_mutex(rdev);
1119 rdev->irq.dpm_thermal = true;
1120 radeon_irq_set(rdev);
1123 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1128 void trinity_dpm_disable(struct radeon_device *rdev)
1130 trinity_acquire_mutex(rdev);
1131 if (!trinity_dpm_enabled(rdev)) {
1132 trinity_release_mutex(rdev);
1135 trinity_dpm_bapm_enable(rdev, false);
1136 trinity_disable_clock_power_gating(rdev);
1137 sumo_clear_vc(rdev);
1138 trinity_wait_for_level_0(rdev);
1139 trinity_stop_dpm(rdev);
1140 trinity_reset_am(rdev);
1141 trinity_release_mutex(rdev);
1143 if (rdev->irq.installed &&
1144 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1145 rdev->irq.dpm_thermal = false;
1146 radeon_irq_set(rdev);
1149 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1152 static void trinity_get_min_sclk_divider(struct radeon_device *rdev)
1154 struct trinity_power_info *pi = trinity_get_pi(rdev);
1157 (RREG32_SMC(CC_SMU_MISC_FUSES) & MinSClkDid_MASK) >> MinSClkDid_SHIFT;
1160 static void trinity_setup_nbp_sim(struct radeon_device *rdev,
1161 struct radeon_ps *rps)
1163 struct trinity_power_info *pi = trinity_get_pi(rdev);
1164 struct trinity_ps *new_ps = trinity_get_ps(rps);
1167 if (pi->sys_info.nb_dpm_enable) {
1168 nbpsconfig = RREG32_SMC(NB_PSTATE_CONFIG);
1169 nbpsconfig &= ~(Dpm0PgNbPsLo_MASK | Dpm0PgNbPsHi_MASK | DpmXNbPsLo_MASK | DpmXNbPsHi_MASK);
1170 nbpsconfig |= (Dpm0PgNbPsLo(new_ps->Dpm0PgNbPsLo) |
1171 Dpm0PgNbPsHi(new_ps->Dpm0PgNbPsHi) |
1172 DpmXNbPsLo(new_ps->DpmXNbPsLo) |
1173 DpmXNbPsHi(new_ps->DpmXNbPsHi));
1174 WREG32_SMC(NB_PSTATE_CONFIG, nbpsconfig);
1178 int trinity_dpm_force_performance_level(struct radeon_device *rdev,
1179 enum radeon_dpm_forced_level level)
1181 struct trinity_power_info *pi = trinity_get_pi(rdev);
1182 struct radeon_ps *rps = &pi->current_rps;
1183 struct trinity_ps *ps = trinity_get_ps(rps);
1186 if (ps->num_levels <= 1)
1189 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1190 /* not supported by the hw */
1192 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1193 ret = trinity_dpm_n_levels_disabled(rdev, ps->num_levels - 1);
1197 for (i = 0; i < ps->num_levels; i++) {
1198 ret = trinity_dpm_n_levels_disabled(rdev, 0);
1204 rdev->pm.dpm.forced_level = level;
1209 int trinity_dpm_pre_set_power_state(struct radeon_device *rdev)
1211 struct trinity_power_info *pi = trinity_get_pi(rdev);
1212 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1213 struct radeon_ps *new_ps = &requested_ps;
1215 trinity_update_requested_ps(rdev, new_ps);
1217 trinity_apply_state_adjust_rules(rdev,
1224 int trinity_dpm_set_power_state(struct radeon_device *rdev)
1226 struct trinity_power_info *pi = trinity_get_pi(rdev);
1227 struct radeon_ps *new_ps = &pi->requested_rps;
1228 struct radeon_ps *old_ps = &pi->current_rps;
1230 trinity_acquire_mutex(rdev);
1231 if (pi->enable_dpm) {
1232 if (pi->enable_bapm)
1233 trinity_dpm_bapm_enable(rdev, rdev->pm.dpm.ac_power);
1234 trinity_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1235 trinity_enable_power_level_0(rdev);
1236 trinity_force_level_0(rdev);
1237 trinity_wait_for_level_0(rdev);
1238 trinity_setup_nbp_sim(rdev, new_ps);
1239 trinity_program_power_levels_0_to_n(rdev, new_ps, old_ps);
1240 trinity_force_level_0(rdev);
1241 trinity_unforce_levels(rdev);
1242 trinity_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1244 trinity_release_mutex(rdev);
1249 void trinity_dpm_post_set_power_state(struct radeon_device *rdev)
1251 struct trinity_power_info *pi = trinity_get_pi(rdev);
1252 struct radeon_ps *new_ps = &pi->requested_rps;
1254 trinity_update_current_ps(rdev, new_ps);
1257 void trinity_dpm_setup_asic(struct radeon_device *rdev)
1259 trinity_acquire_mutex(rdev);
1260 sumo_program_sstp(rdev);
1261 sumo_take_smu_control(rdev, true);
1262 trinity_get_min_sclk_divider(rdev);
1263 trinity_release_mutex(rdev);
1266 void trinity_dpm_reset_asic(struct radeon_device *rdev)
1268 struct trinity_power_info *pi = trinity_get_pi(rdev);
1270 trinity_acquire_mutex(rdev);
1271 if (pi->enable_dpm) {
1272 trinity_enable_power_level_0(rdev);
1273 trinity_force_level_0(rdev);
1274 trinity_wait_for_level_0(rdev);
1275 trinity_program_bootup_state(rdev);
1276 trinity_force_level_0(rdev);
1277 trinity_unforce_levels(rdev);
1279 trinity_release_mutex(rdev);
1282 static u16 trinity_convert_voltage_index_to_value(struct radeon_device *rdev,
1285 struct trinity_power_info *pi = trinity_get_pi(rdev);
1286 u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);
1287 u32 svi_mode = (RREG32_SMC(PM_CONFIG) & SVI_Mode) ? 1 : 0;
1288 u32 step = (svi_mode == 0) ? 1250 : 625;
1289 u32 delta = vid_7bit * step + 50;
1294 return (155000 - delta) / 100;
1297 static void trinity_patch_boot_state(struct radeon_device *rdev,
1298 struct trinity_ps *ps)
1300 struct trinity_power_info *pi = trinity_get_pi(rdev);
1305 ps->levels[0] = pi->boot_pl;
1308 static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk)
1315 static void trinity_construct_boot_state(struct radeon_device *rdev)
1317 struct trinity_power_info *pi = trinity_get_pi(rdev);
1319 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1320 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1321 pi->boot_pl.ds_divider_index = 0;
1322 pi->boot_pl.ss_divider_index = 0;
1323 pi->boot_pl.allow_gnb_slow = 1;
1324 pi->boot_pl.force_nbp_state = 0;
1325 pi->boot_pl.display_wm = 0;
1326 pi->boot_pl.vce_wm = 0;
1327 pi->current_ps.num_levels = 1;
1328 pi->current_ps.levels[0] = pi->boot_pl;
1331 static u8 trinity_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1332 u32 sclk, u32 min_sclk_in_sr)
1334 struct trinity_power_info *pi = trinity_get_pi(rdev);
1337 u32 min = (min_sclk_in_sr > TRINITY_MINIMUM_ENGINE_CLOCK) ?
1338 min_sclk_in_sr : TRINITY_MINIMUM_ENGINE_CLOCK;
1343 if (!pi->enable_sclk_ds)
1346 for (i = TRINITY_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
1347 temp = sclk / sumo_get_sleep_divider_from_id(i);
1348 if (temp >= min || i == 0)
1355 static u32 trinity_get_valid_engine_clock(struct radeon_device *rdev,
1358 struct trinity_power_info *pi = trinity_get_pi(rdev);
1361 for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) {
1362 if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit)
1363 return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency;
1366 if (i == pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries)
1367 DRM_ERROR("engine clock out of range!");
1372 static void trinity_patch_thermal_state(struct radeon_device *rdev,
1373 struct trinity_ps *ps,
1374 struct trinity_ps *current_ps)
1376 struct trinity_power_info *pi = trinity_get_pi(rdev);
1377 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1380 u32 current_index = 0;
1383 current_vddc = current_ps->levels[current_index].vddc_index;
1384 current_sclk = current_ps->levels[current_index].sclk;
1386 current_vddc = pi->boot_pl.vddc_index;
1387 current_sclk = pi->boot_pl.sclk;
1390 ps->levels[0].vddc_index = current_vddc;
1392 if (ps->levels[0].sclk > current_sclk)
1393 ps->levels[0].sclk = current_sclk;
1395 ps->levels[0].ds_divider_index =
1396 trinity_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
1397 ps->levels[0].ss_divider_index = ps->levels[0].ds_divider_index;
1398 ps->levels[0].allow_gnb_slow = 1;
1399 ps->levels[0].force_nbp_state = 0;
1400 ps->levels[0].display_wm = 0;
1401 ps->levels[0].vce_wm =
1402 trinity_calculate_vce_wm(rdev, ps->levels[0].sclk);
1405 static u8 trinity_calculate_display_wm(struct radeon_device *rdev,
1406 struct trinity_ps *ps, u32 index)
1408 if (ps == NULL || ps->num_levels <= 1)
1410 else if (ps->num_levels == 2) {
1418 else if (ps->levels[index].sclk < 30000)
1425 static u32 trinity_get_uvd_clock_index(struct radeon_device *rdev,
1426 struct radeon_ps *rps)
1428 struct trinity_power_info *pi = trinity_get_pi(rdev);
1431 for (i = 0; i < 4; i++) {
1432 if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) &&
1433 (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk))
1438 DRM_ERROR("UVD clock index not found!\n");
1444 static void trinity_adjust_uvd_state(struct radeon_device *rdev,
1445 struct radeon_ps *rps)
1447 struct trinity_ps *ps = trinity_get_ps(rps);
1448 struct trinity_power_info *pi = trinity_get_pi(rdev);
1452 if (pi->uvd_dpm && r600_is_uvd_state(rps->class, rps->class2)) {
1453 high_index = trinity_get_uvd_clock_index(rdev, rps);
1455 switch(high_index) {
1467 ps->vclk_low_divider =
1468 pi->sys_info.uvd_clock_table_entries[high_index].vclk_did;
1469 ps->dclk_low_divider =
1470 pi->sys_info.uvd_clock_table_entries[high_index].dclk_did;
1471 ps->vclk_high_divider =
1472 pi->sys_info.uvd_clock_table_entries[low_index].vclk_did;
1473 ps->dclk_high_divider =
1474 pi->sys_info.uvd_clock_table_entries[low_index].dclk_did;
1480 static void trinity_apply_state_adjust_rules(struct radeon_device *rdev,
1481 struct radeon_ps *new_rps,
1482 struct radeon_ps *old_rps)
1484 struct trinity_ps *ps = trinity_get_ps(new_rps);
1485 struct trinity_ps *current_ps = trinity_get_ps(old_rps);
1486 struct trinity_power_info *pi = trinity_get_pi(rdev);
1487 u32 min_voltage = 0; /* ??? */
1488 u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */
1489 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1492 u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count;
1494 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1495 return trinity_patch_thermal_state(rdev, ps, current_ps);
1497 trinity_adjust_uvd_state(rdev, new_rps);
1499 for (i = 0; i < ps->num_levels; i++) {
1500 if (ps->levels[i].vddc_index < min_voltage)
1501 ps->levels[i].vddc_index = min_voltage;
1503 if (ps->levels[i].sclk < min_sclk)
1504 ps->levels[i].sclk =
1505 trinity_get_valid_engine_clock(rdev, min_sclk);
1507 ps->levels[i].ds_divider_index =
1508 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
1510 ps->levels[i].ss_divider_index = ps->levels[i].ds_divider_index;
1512 ps->levels[i].allow_gnb_slow = 1;
1513 ps->levels[i].force_nbp_state = 0;
1514 ps->levels[i].display_wm =
1515 trinity_calculate_display_wm(rdev, ps, i);
1516 ps->levels[i].vce_wm =
1517 trinity_calculate_vce_wm(rdev, ps->levels[0].sclk);
1520 if ((new_rps->class & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) ||
1521 ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY))
1522 ps->bapm_flags |= TRINITY_POWERSTATE_FLAGS_BAPM_DISABLE;
1524 if (pi->sys_info.nb_dpm_enable) {
1525 ps->Dpm0PgNbPsLo = 0x1;
1526 ps->Dpm0PgNbPsHi = 0x0;
1527 ps->DpmXNbPsLo = 0x2;
1528 ps->DpmXNbPsHi = 0x1;
1530 if ((new_rps->class & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) ||
1531 ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)) {
1532 force_high = ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) ||
1533 ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) &&
1534 (pi->sys_info.uma_channel_number == 1)));
1535 force_high = (num_active_displays >= 3) || force_high;
1536 ps->Dpm0PgNbPsLo = force_high ? 0x2 : 0x3;
1537 ps->Dpm0PgNbPsHi = 0x1;
1538 ps->DpmXNbPsLo = force_high ? 0x2 : 0x3;
1539 ps->DpmXNbPsHi = 0x2;
1540 ps->levels[ps->num_levels - 1].allow_gnb_slow = 0;
1545 static void trinity_cleanup_asic(struct radeon_device *rdev)
1547 sumo_take_smu_control(rdev, false);
1551 static void trinity_pre_display_configuration_change(struct radeon_device *rdev)
1553 struct trinity_power_info *pi = trinity_get_pi(rdev);
1555 if (pi->voltage_drop_in_dce)
1556 trinity_dce_enable_voltage_adjustment(rdev, false);
1560 static void trinity_add_dccac_value(struct radeon_device *rdev)
1562 u32 gpu_cac_avrg_cntl_window_size;
1563 u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count;
1564 u64 disp_clk = rdev->clock.default_dispclk / 100;
1567 gpu_cac_avrg_cntl_window_size =
1568 (RREG32_SMC(GPU_CAC_AVRG_CNTL) & WINDOW_SIZE_MASK) >> WINDOW_SIZE_SHIFT;
1570 dc_cac_value = (u32)((14213 * disp_clk * disp_clk * (u64)num_active_displays) >>
1571 (32 - gpu_cac_avrg_cntl_window_size));
1573 WREG32_SMC(DC_CAC_VALUE, dc_cac_value);
1576 void trinity_dpm_display_configuration_changed(struct radeon_device *rdev)
1578 struct trinity_power_info *pi = trinity_get_pi(rdev);
1580 if (pi->voltage_drop_in_dce)
1581 trinity_dce_enable_voltage_adjustment(rdev, true);
1582 trinity_add_dccac_value(rdev);
1586 struct _ATOM_POWERPLAY_INFO info;
1587 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1588 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1589 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1590 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1591 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1594 union pplib_clock_info {
1595 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1596 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1597 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1598 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1601 union pplib_power_state {
1602 struct _ATOM_PPLIB_STATE v1;
1603 struct _ATOM_PPLIB_STATE_V2 v2;
1606 static void trinity_parse_pplib_non_clock_info(struct radeon_device *rdev,
1607 struct radeon_ps *rps,
1608 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
1611 struct trinity_ps *ps = trinity_get_ps(rps);
1613 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1614 rps->class = le16_to_cpu(non_clock_info->usClassification);
1615 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
1617 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
1618 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
1619 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1625 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1626 rdev->pm.dpm.boot_ps = rps;
1627 trinity_patch_boot_state(rdev, ps);
1629 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
1630 rdev->pm.dpm.uvd_ps = rps;
1633 static void trinity_parse_pplib_clock_info(struct radeon_device *rdev,
1634 struct radeon_ps *rps, int index,
1635 union pplib_clock_info *clock_info)
1637 struct trinity_power_info *pi = trinity_get_pi(rdev);
1638 struct trinity_ps *ps = trinity_get_ps(rps);
1639 struct trinity_pl *pl = &ps->levels[index];
1642 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
1643 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
1645 pl->vddc_index = clock_info->sumo.vddcIndex;
1647 ps->num_levels = index + 1;
1649 if (pi->enable_sclk_ds) {
1650 pl->ds_divider_index = 5;
1651 pl->ss_divider_index = 5;
1655 static int trinity_parse_power_table(struct radeon_device *rdev)
1657 struct radeon_mode_info *mode_info = &rdev->mode_info;
1658 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1659 union pplib_power_state *power_state;
1660 int i, j, k, non_clock_array_index, clock_array_index;
1661 union pplib_clock_info *clock_info;
1662 struct _StateArray *state_array;
1663 struct _ClockInfoArray *clock_info_array;
1664 struct _NonClockInfoArray *non_clock_info_array;
1665 union power_info *power_info;
1666 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1669 u8 *power_state_offset;
1672 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1673 &frev, &crev, &data_offset))
1675 power_info = (union power_info *)((uint8_t*)mode_info->atom_context->bios + data_offset);
1677 state_array = (struct _StateArray *)
1678 ((uint8_t*)mode_info->atom_context->bios + data_offset +
1679 le16_to_cpu(power_info->pplib.usStateArrayOffset));
1680 clock_info_array = (struct _ClockInfoArray *)
1681 ((uint8_t*)mode_info->atom_context->bios + data_offset +
1682 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
1683 non_clock_info_array = (struct _NonClockInfoArray *)
1684 ((uint8_t*)mode_info->atom_context->bios + data_offset +
1685 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
1687 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
1688 state_array->ucNumEntries, GFP_KERNEL);
1689 if (!rdev->pm.dpm.ps)
1691 power_state_offset = (u8 *)state_array->states;
1692 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
1693 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
1694 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
1695 for (i = 0; i < state_array->ucNumEntries; i++) {
1697 power_state = (union pplib_power_state *)power_state_offset;
1698 non_clock_array_index = power_state->v2.nonClockInfoIndex;
1699 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1700 &non_clock_info_array->nonClockInfo[non_clock_array_index];
1701 if (!rdev->pm.power_state[i].clock_info)
1703 ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);
1705 kfree(rdev->pm.dpm.ps);
1708 rdev->pm.dpm.ps[i].ps_priv = ps;
1710 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
1711 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
1712 clock_array_index = idx[j];
1713 if (clock_array_index >= clock_info_array->ucNumEntries)
1715 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
1717 clock_info = (union pplib_clock_info *)
1718 ((u8 *)&clock_info_array->clockInfo[0] +
1719 (clock_array_index * clock_info_array->ucEntrySize));
1720 trinity_parse_pplib_clock_info(rdev,
1721 &rdev->pm.dpm.ps[i], k,
1725 trinity_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1727 non_clock_info_array->ucEntrySize);
1728 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
1730 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
1735 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1736 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1737 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
1738 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1739 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1742 static u32 trinity_convert_did_to_freq(struct radeon_device *rdev, u8 did)
1744 struct trinity_power_info *pi = trinity_get_pi(rdev);
1747 if (did >= 8 && did <= 0x3f)
1749 else if (did > 0x3f && did <= 0x5f)
1750 divider = (did - 64) * 50 + 1600;
1751 else if (did > 0x5f && did <= 0x7e)
1752 divider = (did - 96) * 100 + 3200;
1753 else if (did == 0x7f)
1754 divider = 128 * 100;
1758 return ((pi->sys_info.dentist_vco_freq * 100) + (divider - 1)) / divider;
1761 static int trinity_parse_sys_info_table(struct radeon_device *rdev)
1763 struct trinity_power_info *pi = trinity_get_pi(rdev);
1764 struct radeon_mode_info *mode_info = &rdev->mode_info;
1765 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1766 union igp_info *igp_info;
1771 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1772 &frev, &crev, &data_offset)) {
1773 igp_info = (union igp_info *)((uint8_t*)mode_info->atom_context->bios +
1777 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1780 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_7.ulBootUpEngineClock);
1781 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_7.ulMinEngineClock);
1782 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_7.ulBootUpUMAClock);
1783 pi->sys_info.dentist_vco_freq = le32_to_cpu(igp_info->info_7.ulDentistVCOFreq);
1784 pi->sys_info.bootup_nb_voltage_index =
1785 le16_to_cpu(igp_info->info_7.usBootUpNBVoltage);
1786 if (igp_info->info_7.ucHtcTmpLmt == 0)
1787 pi->sys_info.htc_tmp_lmt = 203;
1789 pi->sys_info.htc_tmp_lmt = igp_info->info_7.ucHtcTmpLmt;
1790 if (igp_info->info_7.ucHtcHystLmt == 0)
1791 pi->sys_info.htc_hyst_lmt = 5;
1793 pi->sys_info.htc_hyst_lmt = igp_info->info_7.ucHtcHystLmt;
1794 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
1795 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
1798 if (pi->enable_nbps_policy)
1799 pi->sys_info.nb_dpm_enable = igp_info->info_7.ucNBDPMEnable;
1801 pi->sys_info.nb_dpm_enable = 0;
1803 for (i = 0; i < TRINITY_NUM_NBPSTATES; i++) {
1804 pi->sys_info.nbp_mclk[i] = le32_to_cpu(igp_info->info_7.ulNbpStateMemclkFreq[i]);
1805 pi->sys_info.nbp_nclk[i] = le32_to_cpu(igp_info->info_7.ulNbpStateNClkFreq[i]);
1808 pi->sys_info.nbp_voltage_index[0] = le16_to_cpu(igp_info->info_7.usNBP0Voltage);
1809 pi->sys_info.nbp_voltage_index[1] = le16_to_cpu(igp_info->info_7.usNBP1Voltage);
1810 pi->sys_info.nbp_voltage_index[2] = le16_to_cpu(igp_info->info_7.usNBP2Voltage);
1811 pi->sys_info.nbp_voltage_index[3] = le16_to_cpu(igp_info->info_7.usNBP3Voltage);
1813 if (!pi->sys_info.nb_dpm_enable) {
1814 for (i = 1; i < TRINITY_NUM_NBPSTATES; i++) {
1815 pi->sys_info.nbp_mclk[i] = pi->sys_info.nbp_mclk[0];
1816 pi->sys_info.nbp_nclk[i] = pi->sys_info.nbp_nclk[0];
1817 pi->sys_info.nbp_voltage_index[i] = pi->sys_info.nbp_voltage_index[0];
1821 pi->sys_info.uma_channel_number = igp_info->info_7.ucUMAChannelNumber;
1823 sumo_construct_sclk_voltage_mapping_table(rdev,
1824 &pi->sys_info.sclk_voltage_mapping_table,
1825 igp_info->info_7.sAvail_SCLK);
1826 sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,
1827 igp_info->info_7.sAvail_SCLK);
1829 pi->sys_info.uvd_clock_table_entries[0].vclk_did =
1830 igp_info->info_7.ucDPMState0VclkFid;
1831 pi->sys_info.uvd_clock_table_entries[1].vclk_did =
1832 igp_info->info_7.ucDPMState1VclkFid;
1833 pi->sys_info.uvd_clock_table_entries[2].vclk_did =
1834 igp_info->info_7.ucDPMState2VclkFid;
1835 pi->sys_info.uvd_clock_table_entries[3].vclk_did =
1836 igp_info->info_7.ucDPMState3VclkFid;
1838 pi->sys_info.uvd_clock_table_entries[0].dclk_did =
1839 igp_info->info_7.ucDPMState0DclkFid;
1840 pi->sys_info.uvd_clock_table_entries[1].dclk_did =
1841 igp_info->info_7.ucDPMState1DclkFid;
1842 pi->sys_info.uvd_clock_table_entries[2].dclk_did =
1843 igp_info->info_7.ucDPMState2DclkFid;
1844 pi->sys_info.uvd_clock_table_entries[3].dclk_did =
1845 igp_info->info_7.ucDPMState3DclkFid;
1847 for (i = 0; i < 4; i++) {
1848 pi->sys_info.uvd_clock_table_entries[i].vclk =
1849 trinity_convert_did_to_freq(rdev,
1850 pi->sys_info.uvd_clock_table_entries[i].vclk_did);
1851 pi->sys_info.uvd_clock_table_entries[i].dclk =
1852 trinity_convert_did_to_freq(rdev,
1853 pi->sys_info.uvd_clock_table_entries[i].dclk_did);
1862 int trinity_dpm_init(struct radeon_device *rdev)
1864 struct trinity_power_info *pi;
1867 pi = kzalloc(sizeof(struct trinity_power_info), GFP_KERNEL);
1870 rdev->pm.dpm.priv = pi;
1872 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
1873 pi->at[i] = TRINITY_AT_DFLT;
1875 pi->enable_bapm = false;
1876 pi->enable_nbps_policy = true;
1877 pi->enable_sclk_ds = true;
1878 pi->enable_gfx_power_gating = true;
1879 pi->enable_gfx_clock_gating = true;
1880 pi->enable_mg_clock_gating = true;
1881 pi->enable_gfx_dynamic_mgpg = true; /* ??? */
1882 pi->override_dynamic_mgpg = true;
1883 pi->enable_auto_thermal_throttling = true;
1884 pi->voltage_drop_in_dce = false; /* need to restructure dpm/modeset interaction */
1885 pi->uvd_dpm = true; /* ??? */
1887 ret = trinity_parse_sys_info_table(rdev);
1891 trinity_construct_boot_state(rdev);
1893 ret = trinity_parse_power_table(rdev);
1897 pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt;
1898 pi->enable_dpm = true;
1903 void trinity_dpm_print_power_state(struct radeon_device *rdev,
1904 struct radeon_ps *rps)
1907 struct trinity_ps *ps = trinity_get_ps(rps);
1909 r600_dpm_print_class_info(rps->class, rps->class2);
1910 r600_dpm_print_cap_info(rps->caps);
1911 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1912 for (i = 0; i < ps->num_levels; i++) {
1913 struct trinity_pl *pl = &ps->levels[i];
1914 printk("\t\tpower level %d sclk: %u vddc: %u\n",
1916 trinity_convert_voltage_index_to_value(rdev, pl->vddc_index));
1918 r600_dpm_print_ps_status(rdev, rps);
1921 void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
1924 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
1925 struct trinity_ps *ps = trinity_get_ps(rps);
1926 struct trinity_pl *pl;
1928 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) >>
1929 CURRENT_STATE_SHIFT;
1931 if (current_index >= ps->num_levels) {
1932 seq_printf(m, "invalid dpm profile %d\n", current_index);
1934 pl = &ps->levels[current_index];
1935 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1936 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
1937 current_index, pl->sclk,
1938 trinity_convert_voltage_index_to_value(rdev, pl->vddc_index));
1942 void trinity_dpm_fini(struct radeon_device *rdev)
1946 trinity_cleanup_asic(rdev); /* ??? */
1948 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1949 kfree(rdev->pm.dpm.ps[i].ps_priv);
1951 kfree(rdev->pm.dpm.ps);
1952 kfree(rdev->pm.dpm.priv);
1955 u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low)
1957 struct trinity_power_info *pi = trinity_get_pi(rdev);
1958 struct trinity_ps *requested_state = trinity_get_ps(&pi->requested_rps);
1961 return requested_state->levels[0].sclk;
1963 return requested_state->levels[requested_state->num_levels - 1].sclk;
1966 u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low)
1968 struct trinity_power_info *pi = trinity_get_pi(rdev);
1970 return pi->sys_info.bootup_uma_clk;