2 * Copyright (c) 2003 Dag-Erling Coïdan Smørgrav
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer
10 * in this position and unchanged.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/sound/pci/au88x0.c,v 1.10 2005/03/01 08:58:05 imp Exp $
31 #include <dev/sound/pcm/sound.h>
32 #include <dev/sound/pcm/ac97.h>
33 #include <dev/sound/pci/au88x0.h>
37 #include <bus/pci/pcireg.h>
38 #include <bus/pci/pcivar.h>
41 /***************************************************************************\
43 * SUPPORTED CHIPSETS *
45 \***************************************************************************/
47 static struct au88x0_chipset au88x0_chipsets[] = {
49 .auc_name = "Aureal Vortex (8820)",
50 .auc_pci_id = 0x000112eb,
52 .auc_control = 0x1280c,
54 .auc_irq_source = 0x12800,
55 .auc_irq_mask = 0x12804,
56 .auc_irq_control = 0x12808,
57 .auc_irq_status = 0x1199c,
59 .auc_dma_control = 0x1060c,
61 .auc_fifo_size = 0x20,
63 .auc_wt_fifo_base = 0x0e800,
64 .auc_wt_fifo_ctl = 0x0f800,
65 .auc_wt_dma_ctl = 0x10500,
67 .auc_adb_fifo_base = 0x0e000,
68 .auc_adb_fifo_ctl = 0x0f840,
69 .auc_adb_dma_ctl = 0x10580,
71 .auc_adb_route_base = 0x10800,
72 .auc_adb_route_bits = 7,
73 .auc_adb_codec_in = 0x48,
74 .auc_adb_codec_out = 0x58,
77 .auc_name = "Aureal Vortex 2 (8830)",
78 .auc_pci_id = 0x000212eb,
80 .auc_control = 0x2a00c,
82 .auc_irq_source = 0x2a000,
83 .auc_irq_mask = 0x2a004,
84 .auc_irq_control = 0x2a008,
85 .auc_irq_status = 0x2919c,
87 .auc_dma_control = 0x27ae8,
89 .auc_fifo_size = 0x40,
91 .auc_wt_fifo_base = 0x10000,
92 .auc_wt_fifo_ctl = 0x16000,
93 .auc_wt_dma_ctl = 0x27900,
95 .auc_adb_fifo_base = 0x14000,
96 .auc_adb_fifo_ctl = 0x16100,
97 .auc_adb_dma_ctl = 0x27a00,
99 .auc_adb_route_base = 0x28000,
100 .auc_adb_route_bits = 8,
101 .auc_adb_codec_in = 0x70,
102 .auc_adb_codec_out = 0x88,
105 .auc_name = "Aureal Vortex Advantage (8810)",
106 .auc_pci_id = 0x000312eb,
108 .auc_control = 0x2a00c,
110 .auc_irq_source = 0x2a000,
111 .auc_irq_mask = 0x2a004,
112 .auc_irq_control = 0x2a008,
113 .auc_irq_status = 0x2919c,
115 .auc_dma_control = 0x27ae8,
117 .auc_fifo_size = 0x20,
119 .auc_wt_fifo_base = 0x10000,
120 .auc_wt_fifo_ctl = 0x16000,
121 .auc_wt_dma_ctl = 0x27fd8,
123 .auc_adb_fifo_base = 0x14000,
124 .auc_adb_fifo_ctl = 0x16100,
125 .auc_adb_dma_ctl = 0x27180,
127 .auc_adb_route_base = 0x28000,
128 .auc_adb_route_bits = 8,
129 .auc_adb_codec_in = 0x70,
130 .auc_adb_codec_out = 0x88,
138 /***************************************************************************\
140 * FORMATS AND CAPABILITIES *
142 \***************************************************************************/
144 static u_int32_t au88x0_formats[] = {
146 AFMT_STEREO | AFMT_U8,
148 AFMT_STEREO | AFMT_S16_LE,
152 static struct pcmchan_caps au88x0_capabilities = {
153 4000, /* minimum sample rate */
154 48000, /* maximum sample rate */
155 au88x0_formats, /* supported formats */
156 0 /* no particular capabilities */
160 /***************************************************************************\
164 \***************************************************************************/
167 * Read from the au88x0 register space
170 /* all our writes are 32-bit */
171 #define au88x0_read(aui, reg, n) \
172 bus_space_read_4((aui)->aui_spct, (aui)->aui_spch, (reg))
173 #define au88x0_write(aui, reg, data, n) \
174 bus_space_write_4((aui)->aui_spct, (aui)->aui_spch, (reg), (data))
177 au88x0_read(struct au88x0_info *aui, int reg, int size)
183 data = bus_space_read_1(aui->aui_spct, aui->aui_spch, reg);
186 data = bus_space_read_2(aui->aui_spct, aui->aui_spch, reg);
189 data = bus_space_read_4(aui->aui_spct, aui->aui_spch, reg);
192 panic("unsupported read size %d", size);
198 * Write to the au88x0 register space
201 au88x0_write(struct au88x0_info *aui, int reg, uint32_t data, int size)
206 bus_space_write_1(aui->aui_spct, aui->aui_spch, reg, data);
209 bus_space_write_2(aui->aui_spct, aui->aui_spch, reg, data);
212 bus_space_write_4(aui->aui_spct, aui->aui_spch, reg, data);
215 panic("unsupported write size %d", size);
221 * Reset and initialize the codec
224 au88x0_codec_init(struct au88x0_info *aui)
229 /* wave that chicken */
230 au88x0_write(aui, AU88X0_CODEC_CONTROL, 0x8068, 4);
231 DELAY(AU88X0_SETTLE_DELAY);
232 au88x0_write(aui, AU88X0_CODEC_CONTROL, 0x00e8, 4);
234 for (i = 0; i < 32; ++i) {
235 au88x0_write(aui, AU88X0_CODEC_CHANNEL + i * 4, 0, 4);
236 DELAY(AU88X0_SETTLE_DELAY);
238 au88x0_write(aui, AU88X0_CODEC_CONTROL, 0x00e8, 4);
239 DELAY(AU88X0_SETTLE_DELAY);
241 /* enable both codec channels */
242 data = au88x0_read(aui, AU88X0_CODEC_ENABLE, 4);
243 data |= (1 << (8 + 0)) | (1 << (8 + 1));
244 au88x0_write(aui, AU88X0_CODEC_ENABLE, data, 4);
245 DELAY(AU88X0_SETTLE_DELAY);
249 * Wait for the codec to get ready to accept a register write
250 * Should be called at spltty
253 au88x0_codec_wait(struct au88x0_info *aui)
258 for (i = 0; i < AU88X0_RETRY_COUNT; ++i) {
259 data = au88x0_read(aui, AU88X0_CODEC_CONTROL, 4);
260 if (data & AU88X0_CDCTL_WROK)
262 DELAY(AU88X0_SETTLE_DELAY);
264 device_printf(aui->aui_dev, "timeout while waiting for codec\n");
269 * Read from the ac97 codec
272 au88x0_codec_read(kobj_t obj, void *arg, int reg)
274 struct au88x0_info *aui = arg;
279 au88x0_codec_wait(aui);
280 au88x0_write(aui, AU88X0_CODEC_IO, AU88X0_CDIO_READ(reg), 4);
282 data = au88x0_read(aui, AU88X0_CODEC_IO, 4);
284 data &= AU88X0_CDIO_DATA_MASK;
285 data >>= AU88X0_CDIO_DATA_SHIFT;
290 * Write to the ac97 codec
293 au88x0_codec_write(kobj_t obj, void *arg, int reg, uint32_t data)
295 struct au88x0_info *aui = arg;
299 au88x0_codec_wait(aui);
300 au88x0_write(aui, AU88X0_CODEC_IO, AU88X0_CDIO_WRITE(reg, data), 4);
306 * Codec interface glue
308 static kobj_method_t au88x0_ac97_methods[] = {
309 KOBJMETHOD(ac97_read, au88x0_codec_read),
310 KOBJMETHOD(ac97_write, au88x0_codec_write),
313 AC97_DECLARE(au88x0_ac97);
315 #define au88x0_channel(aui, dir) \
316 &(aui)->aui_chan[((dir) == PCMDIR_PLAY) ? 0 : 1]
319 /***************************************************************************\
321 * CHANNEL INTERFACE *
323 \***************************************************************************/
326 * Initialize a PCM channel
329 au88x0_chan_init(kobj_t obj, void *arg,
330 struct snd_dbuf *buf, struct pcm_channel *chan, int dir)
332 struct au88x0_info *aui = arg;
333 struct au88x0_chan_info *auci = au88x0_channel(aui, dir);
335 if (sndbuf_alloc(buf, aui->aui_dmat, aui->aui_bufsize) != 0)
337 auci->auci_aui = aui;
338 auci->auci_pcmchan = chan;
339 auci->auci_buf = buf;
340 auci->auci_dir = dir;
345 * Set the data format for a PCM channel
348 au88x0_chan_setformat(kobj_t obj, void *arg, u_int32_t format)
356 * Set the sample rate for a PCM channel
359 au88x0_chan_setspeed(kobj_t obj, void *arg, u_int32_t speed)
367 * Set the block size for a PCM channel
370 au88x0_chan_setblocksize(kobj_t obj, void *arg, u_int32_t blocksize)
378 * Initiate a data transfer
381 au88x0_chan_trigger(kobj_t obj, void *arg, int trigger)
383 struct au88x0_chan_info *auci = arg;
400 au88x0_chan_getptr(kobj_t obj, void *arg)
408 * Return the capabilities of a PCM channel
410 static struct pcmchan_caps *
411 au88x0_chan_getcaps(kobj_t obj, void *arg)
414 return (&au88x0_capabilities);
418 * Channel interface glue
420 static kobj_method_t au88x0_chan_methods[] = {
421 KOBJMETHOD(channel_init, au88x0_chan_init),
422 KOBJMETHOD(channel_setformat, au88x0_chan_setformat),
423 KOBJMETHOD(channel_setspeed, au88x0_chan_setspeed),
424 KOBJMETHOD(channel_setblocksize, au88x0_chan_setblocksize),
425 KOBJMETHOD(channel_trigger, au88x0_chan_trigger),
426 KOBJMETHOD(channel_getptr, au88x0_chan_getptr),
427 KOBJMETHOD(channel_getcaps, au88x0_chan_getcaps),
430 CHANNEL_DECLARE(au88x0_chan);
433 /***************************************************************************\
435 * INTERRUPT HANDLER *
437 \***************************************************************************/
440 au88x0_intr(void *arg)
442 struct au88x0_info *aui = arg;
443 struct au88x0_chipset *auc = aui->aui_chipset;
446 pending = au88x0_read(aui, auc->auc_irq_control, 4);
447 if ((pending & AU88X0_IRQ_PENDING_BIT) == 0)
449 source = au88x0_read(aui, auc->auc_irq_source, 4);
450 if (source & AU88X0_IRQ_FATAL_ERR)
451 device_printf(aui->aui_dev,
452 "fatal error interrupt received\n");
453 if (source & AU88X0_IRQ_PARITY_ERR)
454 device_printf(aui->aui_dev,
455 "parity error interrupt received\n");
456 /* XXX handle the others... */
458 /* acknowledge the interrupts we just handled */
459 au88x0_write(aui, auc->auc_irq_source, source, 4);
460 au88x0_read(aui, auc->auc_irq_source, 4);
464 /***************************************************************************\
468 \***************************************************************************/
471 * Reset and initialize the ADB and WT FIFOs
473 * - need to find out what the magic values 0x42000 and 0x2000 mean.
476 au88x0_fifo_init(struct au88x0_info *aui)
478 struct au88x0_chipset *auc = aui->aui_chipset;
481 /* reset, then clear the ADB FIFOs */
482 for (i = 0; i < auc->auc_adb_fifos; ++i)
483 au88x0_write(aui, auc->auc_adb_fifo_ctl + i * 4, 0x42000, 4);
484 for (i = 0; i < auc->auc_adb_fifos * auc->auc_fifo_size; ++i)
485 au88x0_write(aui, auc->auc_adb_fifo_base + i * 4, 0, 4);
487 /* reset, then clear the WT FIFOs */
488 for (i = 0; i < auc->auc_wt_fifos; ++i)
489 au88x0_write(aui, auc->auc_wt_fifo_ctl + i * 4, 0x42000, 4);
490 for (i = 0; i < auc->auc_wt_fifos * auc->auc_fifo_size; ++i)
491 au88x0_write(aui, auc->auc_wt_fifo_base + i * 4, 0, 4);
495 * Hardware initialization
498 au88x0_init(struct au88x0_info *aui)
500 struct au88x0_chipset *auc = aui->aui_chipset;
503 au88x0_write(aui, auc->auc_control, 0xffffffff, 4);
506 /* clear all interrupts */
507 au88x0_write(aui, auc->auc_irq_source, 0xffffffff, 4);
508 au88x0_read(aui, auc->auc_irq_source, 4);
509 au88x0_read(aui, auc->auc_irq_status, 4);
511 /* initialize the codec */
512 au88x0_codec_init(aui);
514 /* initialize the fifos */
515 au88x0_fifo_init(aui);
517 /* initialize the DMA engine */
518 /* XXX chicken-waving! */
519 au88x0_write(aui, auc->auc_dma_control, 0x1380000, 4);
523 * Construct and set status string
526 au88x0_set_status(device_t dev)
528 char status[SND_STATUSLEN];
529 struct au88x0_info *aui;
531 aui = pcm_getdevinfo(dev);
532 snprintf(status, sizeof status, "at %s 0x%lx irq %ld %s",
533 (aui->aui_regtype == SYS_RES_IOPORT)? "io" : "memory",
534 rman_get_start(aui->aui_reg), rman_get_start(aui->aui_irq),PCM_KLDSTRING(snd_au88x0));
535 pcm_setstatus(dev, status);
539 /***************************************************************************\
543 \***************************************************************************/
549 au88x0_pci_probe(device_t dev)
551 struct au88x0_chipset *auc;
554 pci_id = pci_get_devid(dev);
555 for (auc = au88x0_chipsets; auc->auc_pci_id; ++auc) {
556 if (auc->auc_pci_id == pci_id) {
557 device_set_desc(dev, auc->auc_name);
558 return BUS_PROBE_DEFAULT;
568 au88x0_pci_attach(device_t dev)
570 struct au88x0_chipset *auc;
571 struct au88x0_info *aui = NULL;
575 aui = kmalloc(sizeof *aui, M_DEVBUF, M_WAITOK | M_ZERO);
578 /* Model-specific parameters */
579 aui->aui_model = pci_get_devid(dev);
580 for (auc = au88x0_chipsets; auc->auc_pci_id; ++auc)
581 if (auc->auc_pci_id == aui->aui_model)
582 aui->aui_chipset = auc;
583 if (aui->aui_chipset == NULL)
584 panic("%s() called for non-au88x0 device", __func__);
586 /* enable pio, mmio, bus-mastering dma */
587 config = pci_read_config(dev, PCIR_COMMAND, 2);
588 config |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
589 pci_write_config(dev, PCIR_COMMAND, config, 2);
591 /* register mapping */
592 config = pci_read_config(dev, PCIR_COMMAND, 2);
593 if (config & PCIM_CMD_MEMEN) {
594 /* try memory-mapped I/O */
595 aui->aui_regid = PCIR_BAR(0);
596 aui->aui_regtype = SYS_RES_MEMORY;
597 aui->aui_reg = bus_alloc_resource_any(dev, aui->aui_regtype,
598 &aui->aui_regid, RF_ACTIVE);
600 if (aui->aui_reg == NULL && (config & PCIM_CMD_PORTEN)) {
601 /* fall back on port I/O */
602 aui->aui_regid = PCIR_BAR(0);
603 aui->aui_regtype = SYS_RES_IOPORT;
604 aui->aui_reg = bus_alloc_resource_any(dev, aui->aui_regtype,
605 &aui->aui_regid, RF_ACTIVE);
607 if (aui->aui_reg == NULL) {
608 /* both mmio and pio failed... */
609 device_printf(dev, "failed to map registers\n");
612 aui->aui_spct = rman_get_bustag(aui->aui_reg);
613 aui->aui_spch = rman_get_bushandle(aui->aui_reg);
617 aui->aui_irqtype = SYS_RES_IRQ;
618 aui->aui_irq = bus_alloc_resource_any(dev, aui->aui_irqtype,
619 &aui->aui_irqid, RF_ACTIVE | RF_SHAREABLE);
620 if (aui->aui_irq == 0) {
621 device_printf(dev, "failed to map IRQ\n");
625 /* install interrupt handler */
626 error = snd_setup_intr(dev, aui->aui_irq, 0, au88x0_intr,
627 aui, &aui->aui_irqh);
629 device_printf(dev, "failed to install interrupt handler\n");
634 aui->aui_bufsize = pcm_getbuffersize(dev, AU88X0_BUFSIZE_MIN,
635 AU88X0_BUFSIZE_DFLT, AU88X0_BUFSIZE_MAX);
636 error = bus_dma_tag_create(NULL,
637 2, 0, /* 16-bit alignment, no boundary */
638 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, /* restrict to 4GB */
639 NULL, NULL, /* no filter */
640 aui->aui_bufsize, 1, aui->aui_bufsize,
641 0, busdma_lock_mutex, &Giant, &aui->aui_dmat);
643 device_printf(dev, "failed to create DMA tag\n");
647 /* initialize the hardware */
650 /* initialize the ac97 codec and mixer */
651 if ((aui->aui_ac97i = AC97_CREATE(dev, aui, au88x0_ac97)) == NULL) {
652 device_printf(dev, "failed to initialize ac97 codec\n");
655 if (mixer_init(dev, ac97_getmixerclass(), aui->aui_ac97i) != 0) {
656 device_printf(dev, "failed to initialize ac97 mixer\n");
660 /* register with the pcm driver */
661 if (pcm_register(dev, aui, 0, 0))
663 pcm_addchan(dev, PCMDIR_PLAY, &au88x0_chan_class, aui);
665 pcm_addchan(dev, PCMDIR_REC, &au88x0_chan_class, aui);
667 au88x0_set_status(dev);
671 if (aui->aui_ac97i != NULL)
672 ac97_destroy(aui->aui_ac97i);
674 bus_dma_tag_destroy(aui->aui_dmat);
675 if (aui->aui_irqh != NULL)
676 bus_teardown_intr(dev, aui->aui_irq, aui->aui_irqh);
678 bus_release_resource(dev, aui->aui_irqtype,
679 aui->aui_irqid, aui->aui_irq);
681 bus_release_resource(dev, aui->aui_regtype,
682 aui->aui_regid, aui->aui_reg);
683 kfree(aui, M_DEVBUF);
691 au88x0_pci_detach(device_t dev)
693 struct au88x0_info *aui;
696 aui = pcm_getdevinfo(dev);
697 if ((error = pcm_unregister(dev)) != 0)
700 /* release resources in reverse order */
701 bus_dma_tag_destroy(aui->aui_dmat);
702 bus_teardown_intr(dev, aui->aui_irq, aui->aui_irqh);
703 bus_release_resource(dev, aui->aui_irqtype,
704 aui->aui_irqid, aui->aui_irq);
705 bus_release_resource(dev, aui->aui_regtype,
706 aui->aui_regid, aui->aui_reg);
707 kfree(aui, M_DEVBUF);
715 static device_method_t au88x0_methods[] = {
716 DEVMETHOD(device_probe, au88x0_pci_probe),
717 DEVMETHOD(device_attach, au88x0_pci_attach),
718 DEVMETHOD(device_detach, au88x0_pci_detach),
722 static driver_t au88x0_driver = {
728 DRIVER_MODULE(snd_au88x0, pci, au88x0_driver, pcm_devclass, NULL, NULL);
729 MODULE_DEPEND(snd_au88x0, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
730 MODULE_VERSION(snd_au88x0, 1);