sys/dev/netif/bnx/if_bnx.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 #include "opt_bnx.h"
  37 #include "opt_ifpoll.h"
  38
  39 #include <sys/param.h>
  40 #include <sys/bus.h>
  41 #include <sys/endian.h>
  42 #include <sys/kernel.h>
  43 #include <sys/interrupt.h>
  44 #include <sys/mbuf.h>
  45 #include <sys/malloc.h>
  46 #include <sys/queue.h>
  47 #include <sys/rman.h>
  48 #include <sys/serialize.h>
  49 #include <sys/socket.h>
  50 #include <sys/sockio.h>
  51 #include <sys/sysctl.h>
  52
  53 #include <netinet/ip.h>
  54 #include <netinet/tcp.h>
  55
  56 #include <net/bpf.h>
  57 #include <net/ethernet.h>
  58 #include <net/if.h>
  59 #include <net/if_arp.h>
  60 #include <net/if_dl.h>
  61 #include <net/if_media.h>
  62 #include <net/if_poll.h>
  63 #include <net/if_types.h>
  64 #include <net/ifq_var.h>
  65 #include <net/vlan/if_vlan_var.h>
  66 #include <net/vlan/if_vlan_ether.h>
  67
  68 #include <dev/netif/mii_layer/mii.h>
  69 #include <dev/netif/mii_layer/miivar.h>
  70 #include <dev/netif/mii_layer/brgphyreg.h>
  71
  72 #include <bus/pci/pcidevs.h>
  73 #include <bus/pci/pcireg.h>
  74 #include <bus/pci/pcivar.h>
  75
  76 #include <dev/netif/bge/if_bgereg.h>
  77 #include <dev/netif/bnx/if_bnxvar.h>
  78
  79 /* "device miibus" required.  See GENERIC if you get errors here. */
  80 #include "miibus_if.h"
  81
  82 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  83
  84 #define BNX_INTR_CKINTVL        ((10 * hz) / 1000)      /* 10ms */
  85
  86 static const struct bnx_type {
  87         uint16_t                bnx_vid;
  88         uint16_t                bnx_did;
  89         char                    *bnx_name;
  90 } bnx_devs[] = {
  91         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
  92                 "Broadcom BCM5717 Gigabit Ethernet" },
  93         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C,
  94                 "Broadcom BCM5717C Gigabit Ethernet" },
  95         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
  96                 "Broadcom BCM5718 Gigabit Ethernet" },
  97         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
  98                 "Broadcom BCM5719 Gigabit Ethernet" },
  99         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
 100                 "Broadcom BCM5720 Gigabit Ethernet" },
 101
 102         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725,
 103                 "Broadcom BCM5725 Gigabit Ethernet" },
 104         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727,
 105                 "Broadcom BCM5727 Gigabit Ethernet" },
 106         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762,
 107                 "Broadcom BCM5762 Gigabit Ethernet" },
 108
 109         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
 110                 "Broadcom BCM57761 Gigabit Ethernet" },
 111         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
 112                 "Broadcom BCM57762 Gigabit Ethernet" },
 113         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
 114                 "Broadcom BCM57765 Gigabit Ethernet" },
 115         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
 116                 "Broadcom BCM57766 Gigabit Ethernet" },
 117         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
 118                 "Broadcom BCM57781 Gigabit Ethernet" },
 119         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
 120                 "Broadcom BCM57782 Gigabit Ethernet" },
 121         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
 122                 "Broadcom BCM57785 Gigabit Ethernet" },
 123         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
 124                 "Broadcom BCM57786 Gigabit Ethernet" },
 125         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
 126                 "Broadcom BCM57791 Fast Ethernet" },
 127         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
 128                 "Broadcom BCM57795 Fast Ethernet" },
 129
 130         { 0, 0, NULL }
 131 };
 132
 133 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
 134 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
 135 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
 136 #define BNX_IS_57765_FAMILY(sc)  \
 137         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
 138
 139 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
 140
 141 static int      bnx_probe(device_t);
 142 static int      bnx_attach(device_t);
 143 static int      bnx_detach(device_t);
 144 static void     bnx_shutdown(device_t);
 145 static int      bnx_suspend(device_t);
 146 static int      bnx_resume(device_t);
 147 static int      bnx_miibus_readreg(device_t, int, int);
 148 static int      bnx_miibus_writereg(device_t, int, int, int);
 149 static void     bnx_miibus_statchg(device_t);
 150
 151 #ifdef IFPOLL_ENABLE
 152 static void     bnx_npoll(struct ifnet *, struct ifpoll_info *);
 153 static void     bnx_npoll_rx(struct ifnet *, void *, int);
 154 static void     bnx_npoll_tx(struct ifnet *, void *, int);
 155 static void     bnx_npoll_status(struct ifnet *);
 156 #endif
 157 static void     bnx_intr_legacy(void *);
 158 static void     bnx_msi(void *);
 159 static void     bnx_msi_oneshot(void *);
 160 static void     bnx_intr(struct bnx_softc *);
 161 static void     bnx_enable_intr(struct bnx_softc *);
 162 static void     bnx_disable_intr(struct bnx_softc *);
 163 static void     bnx_txeof(struct bnx_tx_ring *, uint16_t);
 164 static void     bnx_rxeof(struct bnx_rx_ret_ring *, uint16_t, int);
 165 static int      bnx_alloc_intr(struct bnx_softc *);
 166 static int      bnx_setup_intr(struct bnx_softc *);
 167 static void     bnx_free_intr(struct bnx_softc *);
 168 static void     bnx_teardown_intr(struct bnx_softc *, int);
 169 static void     bnx_check_intr(void *);
 170
 171 static void     bnx_start(struct ifnet *, struct ifaltq_subque *);
 172 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 173 static void     bnx_init(void *);
 174 static void     bnx_stop(struct bnx_softc *);
 175 static void     bnx_watchdog(struct ifaltq_subque *);
 176 static int      bnx_ifmedia_upd(struct ifnet *);
 177 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 178 static void     bnx_tick(void *);
 179 static void     bnx_serialize(struct ifnet *, enum ifnet_serialize);
 180 static void     bnx_deserialize(struct ifnet *, enum ifnet_serialize);
 181 static int      bnx_tryserialize(struct ifnet *, enum ifnet_serialize);
 182 #ifdef INVARIANTS
 183 static void     bnx_serialize_assert(struct ifnet *, enum ifnet_serialize,
 184                     boolean_t);
 185 #endif
 186
 187 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
 188 static void     bnx_free_jumbo_mem(struct bnx_softc *);
 189 static struct bnx_jslot
 190                 *bnx_jalloc(struct bnx_softc *);
 191 static void     bnx_jfree(void *);
 192 static void     bnx_jref(void *);
 193 static int      bnx_newbuf_std(struct bnx_rx_ret_ring *, int, int);
 194 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
 195 static void     bnx_setup_rxdesc_std(struct bnx_rx_std_ring *, int);
 196 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
 197 static int      bnx_init_rx_ring_std(struct bnx_rx_std_ring *);
 198 static void     bnx_free_rx_ring_std(struct bnx_rx_std_ring *);
 199 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
 200 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
 201 static void     bnx_free_tx_ring(struct bnx_tx_ring *);
 202 static int      bnx_init_tx_ring(struct bnx_tx_ring *);
 203 static int      bnx_create_tx_ring(struct bnx_tx_ring *);
 204 static void     bnx_destroy_tx_ring(struct bnx_tx_ring *);
 205 static int      bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *);
 206 static void     bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *);
 207 static int      bnx_dma_alloc(device_t);
 208 static void     bnx_dma_free(struct bnx_softc *);
 209 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
 210                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
 211 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 212 static struct mbuf *
 213                 bnx_defrag_shortdma(struct mbuf *);
 214 static int      bnx_encap(struct bnx_tx_ring *, struct mbuf **,
 215                     uint32_t *, int *);
 216 static int      bnx_setup_tso(struct bnx_tx_ring *, struct mbuf **,
 217                     uint16_t *, uint16_t *);
 218 static void     bnx_setup_serialize(struct bnx_softc *);
 219
 220 static void     bnx_reset(struct bnx_softc *);
 221 static int      bnx_chipinit(struct bnx_softc *);
 222 static int      bnx_blockinit(struct bnx_softc *);
 223 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
 224 static void     bnx_enable_msi(struct bnx_softc *sc);
 225 static void     bnx_setmulti(struct bnx_softc *);
 226 static void     bnx_setpromisc(struct bnx_softc *);
 227 static void     bnx_stats_update_regs(struct bnx_softc *);
 228 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
 229
 230 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
 231 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
 232 #ifdef notdef
 233 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
 234 #endif
 235 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
 236 static void     bnx_writembx(struct bnx_softc *, int, int);
 237 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
 238 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
 239 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
 240
 241 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
 242 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
 243 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
 244 static void     bnx_link_poll(struct bnx_softc *);
 245
 246 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
 247 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
 248 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
 249 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
 250
 251 static void     bnx_coal_change(struct bnx_softc *);
 252 static int      bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS);
 253 static int      bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS);
 254 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 255 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 256 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
 257 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
 258 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 259 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 260 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
 261                     int, int, uint32_t);
 262 #ifdef IFPOLL_ENABLE
 263 static int      bnx_sysctl_npoll_offset(SYSCTL_HANDLER_ARGS);
 264 static int      bnx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
 265 static int      bnx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
 266 #endif
 267
 268 static int      bnx_msi_enable = 1;
 269 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
 270
 271 static device_method_t bnx_methods[] = {
 272         /* Device interface */
 273         DEVMETHOD(device_probe,         bnx_probe),
 274         DEVMETHOD(device_attach,        bnx_attach),
 275         DEVMETHOD(device_detach,        bnx_detach),
 276         DEVMETHOD(device_shutdown,      bnx_shutdown),
 277         DEVMETHOD(device_suspend,       bnx_suspend),
 278         DEVMETHOD(device_resume,        bnx_resume),
 279
 280         /* bus interface */
 281         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 282         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 283
 284         /* MII interface */
 285         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
 286         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
 287         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
 288
 289         DEVMETHOD_END
 290 };
 291
 292 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
 293 static devclass_t bnx_devclass;
 294
 295 DECLARE_DUMMY_MODULE(if_bnx);
 296 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
 297 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
 298
 299 static uint32_t
 300 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
 301 {
 302         device_t dev = sc->bnx_dev;
 303         uint32_t val;
 304
 305         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 306         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 307         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 308         return (val);
 309 }
 310
 311 static void
 312 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 313 {
 314         device_t dev = sc->bnx_dev;
 315
 316         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 317         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 318         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 319 }
 320
 321 static void
 322 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
 323 {
 324         CSR_WRITE_4(sc, off, val);
 325 }
 326
 327 static void
 328 bnx_writembx(struct bnx_softc *sc, int off, int val)
 329 {
 330         CSR_WRITE_4(sc, off, val);
 331 }
 332
 333 /*
 334  * Read a sequence of bytes from NVRAM.
 335  */
 336 static int
 337 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
 338 {
 339         return (1);
 340 }
 341
 342 /*
 343  * Read a byte of data stored in the EEPROM at address 'addr.' The
 344  * BCM570x supports both the traditional bitbang interface and an
 345  * auto access interface for reading the EEPROM. We use the auto
 346  * access method.
 347  */
 348 static uint8_t
 349 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
 350 {
 351         int i;
 352         uint32_t byte = 0;
 353
 354         /*
 355          * Enable use of auto EEPROM access so we can avoid
 356          * having to use the bitbang method.
 357          */
 358         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 359
 360         /* Reset the EEPROM, load the clock period. */
 361         CSR_WRITE_4(sc, BGE_EE_ADDR,
 362             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 363         DELAY(20);
 364
 365         /* Issue the read EEPROM command. */
 366         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 367
 368         /* Wait for completion */
 369         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
 370                 DELAY(10);
 371                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 372                         break;
 373         }
 374
 375         if (i == BNX_TIMEOUT) {
 376                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 377                 return(1);
 378         }
 379
 380         /* Get result. */
 381         byte = CSR_READ_4(sc, BGE_EE_DATA);
 382
 383         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 384
 385         return(0);
 386 }
 387
 388 /*
 389  * Read a sequence of bytes from the EEPROM.
 390  */
 391 static int
 392 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
 393 {
 394         size_t i;
 395         int err;
 396         uint8_t byte;
 397
 398         for (byte = 0, err = 0, i = 0; i < len; i++) {
 399                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
 400                 if (err)
 401                         break;
 402                 *(dest + i) = byte;
 403         }
 404
 405         return(err ? 1 : 0);
 406 }
 407
 408 static int
 409 bnx_miibus_readreg(device_t dev, int phy, int reg)
 410 {
 411         struct bnx_softc *sc = device_get_softc(dev);
 412         uint32_t val;
 413         int i;
 414
 415         KASSERT(phy == sc->bnx_phyno,
 416             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 417
 418         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 419         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 420                 CSR_WRITE_4(sc, BGE_MI_MODE,
 421                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 422                 DELAY(80);
 423         }
 424
 425         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 426             BGE_MIPHY(phy) | BGE_MIREG(reg));
 427
 428         /* Poll for the PHY register access to complete. */
 429         for (i = 0; i < BNX_TIMEOUT; i++) {
 430                 DELAY(10);
 431                 val = CSR_READ_4(sc, BGE_MI_COMM);
 432                 if ((val & BGE_MICOMM_BUSY) == 0) {
 433                         DELAY(5);
 434                         val = CSR_READ_4(sc, BGE_MI_COMM);
 435                         break;
 436                 }
 437         }
 438         if (i == BNX_TIMEOUT) {
 439                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 440                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 441                 val = 0;
 442         }
 443
 444         /* Restore the autopoll bit if necessary. */
 445         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 446                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 447                 DELAY(80);
 448         }
 449
 450         if (val & BGE_MICOMM_READFAIL)
 451                 return 0;
 452
 453         return (val & 0xFFFF);
 454 }
 455
 456 static int
 457 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
 458 {
 459         struct bnx_softc *sc = device_get_softc(dev);
 460         int i;
 461
 462         KASSERT(phy == sc->bnx_phyno,
 463             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 464
 465         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 466         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 467                 CSR_WRITE_4(sc, BGE_MI_MODE,
 468                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 469                 DELAY(80);
 470         }
 471
 472         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 473             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 474
 475         for (i = 0; i < BNX_TIMEOUT; i++) {
 476                 DELAY(10);
 477                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 478                         DELAY(5);
 479                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 480                         break;
 481                 }
 482         }
 483         if (i == BNX_TIMEOUT) {
 484                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 485                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 486         }
 487
 488         /* Restore the autopoll bit if necessary. */
 489         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 490                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 491                 DELAY(80);
 492         }
 493
 494         return 0;
 495 }
 496
 497 static void
 498 bnx_miibus_statchg(device_t dev)
 499 {
 500         struct bnx_softc *sc;
 501         struct mii_data *mii;
 502
 503         sc = device_get_softc(dev);
 504         mii = device_get_softc(sc->bnx_miibus);
 505
 506         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 507             (IFM_ACTIVE | IFM_AVALID)) {
 508                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 509                 case IFM_10_T:
 510                 case IFM_100_TX:
 511                         sc->bnx_link = 1;
 512                         break;
 513                 case IFM_1000_T:
 514                 case IFM_1000_SX:
 515                 case IFM_2500_SX:
 516                         sc->bnx_link = 1;
 517                         break;
 518                 default:
 519                         sc->bnx_link = 0;
 520                         break;
 521                 }
 522         } else {
 523                 sc->bnx_link = 0;
 524         }
 525         if (sc->bnx_link == 0)
 526                 return;
 527
 528         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 529         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 530             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 531                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 532         } else {
 533                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 534         }
 535
 536         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 537                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 538         } else {
 539                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 540         }
 541 }
 542
 543 /*
 544  * Memory management for jumbo frames.
 545  */
 546 static int
 547 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
 548 {
 549         struct ifnet *ifp = &sc->arpcom.ac_if;
 550         struct bnx_jslot *entry;
 551         uint8_t *ptr;
 552         bus_addr_t paddr;
 553         int i, error;
 554
 555         /*
 556          * Create tag for jumbo mbufs.
 557          * This is really a bit of a kludge. We allocate a special
 558          * jumbo buffer pool which (thanks to the way our DMA
 559          * memory allocation works) will consist of contiguous
 560          * pages. This means that even though a jumbo buffer might
 561          * be larger than a page size, we don't really need to
 562          * map it into more than one DMA segment. However, the
 563          * default mbuf tag will result in multi-segment mappings,
 564          * so we have to create a special jumbo mbuf tag that
 565          * lets us get away with mapping the jumbo buffers as
 566          * a single segment. I think eventually the driver should
 567          * be changed so that it uses ordinary mbufs and cluster
 568          * buffers, i.e. jumbo frames can span multiple DMA
 569          * descriptors. But that's a project for another day.
 570          */
 571
 572         /*
 573          * Create DMA stuffs for jumbo RX ring.
 574          */
 575         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 576                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 577                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 578                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
 579                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
 580         if (error) {
 581                 if_printf(ifp, "could not create jumbo RX ring\n");
 582                 return error;
 583         }
 584
 585         /*
 586          * Create DMA stuffs for jumbo buffer block.
 587          */
 588         error = bnx_dma_block_alloc(sc, BNX_JMEM,
 589                                     &sc->bnx_cdata.bnx_jumbo_tag,
 590                                     &sc->bnx_cdata.bnx_jumbo_map,
 591                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
 592                                     &paddr);
 593         if (error) {
 594                 if_printf(ifp, "could not create jumbo buffer\n");
 595                 return error;
 596         }
 597
 598         SLIST_INIT(&sc->bnx_jfree_listhead);
 599
 600         /*
 601          * Now divide it up into 9K pieces and save the addresses
 602          * in an array. Note that we play an evil trick here by using
 603          * the first few bytes in the buffer to hold the the address
 604          * of the softc structure for this interface. This is because
 605          * bnx_jfree() needs it, but it is called by the mbuf management
 606          * code which will not pass it to us explicitly.
 607          */
 608         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
 609                 entry = &sc->bnx_cdata.bnx_jslots[i];
 610                 entry->bnx_sc = sc;
 611                 entry->bnx_buf = ptr;
 612                 entry->bnx_paddr = paddr;
 613                 entry->bnx_inuse = 0;
 614                 entry->bnx_slot = i;
 615                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
 616
 617                 ptr += BNX_JLEN;
 618                 paddr += BNX_JLEN;
 619         }
 620         return 0;
 621 }
 622
 623 static void
 624 bnx_free_jumbo_mem(struct bnx_softc *sc)
 625 {
 626         /* Destroy jumbo RX ring. */
 627         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 628                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 629                            sc->bnx_ldata.bnx_rx_jumbo_ring);
 630
 631         /* Destroy jumbo buffer block. */
 632         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
 633                            sc->bnx_cdata.bnx_jumbo_map,
 634                            sc->bnx_ldata.bnx_jumbo_buf);
 635 }
 636
 637 /*
 638  * Allocate a jumbo buffer.
 639  */
 640 static struct bnx_jslot *
 641 bnx_jalloc(struct bnx_softc *sc)
 642 {
 643         struct bnx_jslot *entry;
 644
 645         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 646         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
 647         if (entry) {
 648                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
 649                 entry->bnx_inuse = 1;
 650         } else {
 651                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 652         }
 653         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 654         return(entry);
 655 }
 656
 657 /*
 658  * Adjust usage count on a jumbo buffer.
 659  */
 660 static void
 661 bnx_jref(void *arg)
 662 {
 663         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 664         struct bnx_softc *sc = entry->bnx_sc;
 665
 666         if (sc == NULL)
 667                 panic("bnx_jref: can't find softc pointer!");
 668
 669         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 670                 panic("bnx_jref: asked to reference buffer "
 671                     "that we don't manage!");
 672         } else if (entry->bnx_inuse == 0) {
 673                 panic("bnx_jref: buffer already free!");
 674         } else {
 675                 atomic_add_int(&entry->bnx_inuse, 1);
 676         }
 677 }
 678
 679 /*
 680  * Release a jumbo buffer.
 681  */
 682 static void
 683 bnx_jfree(void *arg)
 684 {
 685         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 686         struct bnx_softc *sc = entry->bnx_sc;
 687
 688         if (sc == NULL)
 689                 panic("bnx_jfree: can't find softc pointer!");
 690
 691         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 692                 panic("bnx_jfree: asked to free buffer that we don't manage!");
 693         } else if (entry->bnx_inuse == 0) {
 694                 panic("bnx_jfree: buffer already free!");
 695         } else {
 696                 /*
 697                  * Possible MP race to 0, use the serializer.  The atomic insn
 698                  * is still needed for races against bnx_jref().
 699                  */
 700                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 701                 atomic_subtract_int(&entry->bnx_inuse, 1);
 702                 if (entry->bnx_inuse == 0) {
 703                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead,
 704                                           entry, jslot_link);
 705                 }
 706                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 707         }
 708 }
 709
 710
 711 /*
 712  * Intialize a standard receive ring descriptor.
 713  */
 714 static int
 715 bnx_newbuf_std(struct bnx_rx_ret_ring *ret, int i, int init)
 716 {
 717         struct mbuf *m_new = NULL;
 718         bus_dma_segment_t seg;
 719         bus_dmamap_t map;
 720         int error, nsegs;
 721         struct bnx_rx_buf *rb;
 722
 723         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 724         if (m_new == NULL)
 725                 return ENOBUFS;
 726         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 727         m_adj(m_new, ETHER_ALIGN);
 728
 729         error = bus_dmamap_load_mbuf_segment(ret->bnx_rx_mtag,
 730             ret->bnx_rx_tmpmap, m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 731         if (error) {
 732                 m_freem(m_new);
 733                 return error;
 734         }
 735
 736         rb = &ret->bnx_std->bnx_rx_std_buf[i];
 737
 738         if (!init) {
 739                 bus_dmamap_sync(ret->bnx_rx_mtag, rb->bnx_rx_dmamap,
 740                     BUS_DMASYNC_POSTREAD);
 741                 bus_dmamap_unload(ret->bnx_rx_mtag, rb->bnx_rx_dmamap);
 742         }
 743
 744         map = ret->bnx_rx_tmpmap;
 745         ret->bnx_rx_tmpmap = rb->bnx_rx_dmamap;
 746         rb->bnx_rx_dmamap = map;
 747
 748         rb->bnx_rx_mbuf = m_new;
 749         rb->bnx_rx_paddr = seg.ds_addr;
 750
 751         bnx_setup_rxdesc_std(ret->bnx_std, i);
 752         return 0;
 753 }
 754
 755 static void
 756 bnx_setup_rxdesc_std(struct bnx_rx_std_ring *std, int i)
 757 {
 758         const struct bnx_rx_buf *rb;
 759         struct bge_rx_bd *r;
 760
 761         rb = &std->bnx_rx_std_buf[i];
 762         r = &std->bnx_rx_std_ring[i];
 763
 764         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rb->bnx_rx_paddr);
 765         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rb->bnx_rx_paddr);
 766         r->bge_len = rb->bnx_rx_mbuf->m_len;
 767         r->bge_idx = i;
 768         r->bge_flags = BGE_RXBDFLAG_END;
 769 }
 770
 771 /*
 772  * Initialize a jumbo receive ring descriptor. This allocates
 773  * a jumbo buffer from the pool managed internally by the driver.
 774  */
 775 static int
 776 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
 777 {
 778         struct mbuf *m_new = NULL;
 779         struct bnx_jslot *buf;
 780         bus_addr_t paddr;
 781
 782         /* Allocate the mbuf. */
 783         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 784         if (m_new == NULL)
 785                 return ENOBUFS;
 786
 787         /* Allocate the jumbo buffer */
 788         buf = bnx_jalloc(sc);
 789         if (buf == NULL) {
 790                 m_freem(m_new);
 791                 return ENOBUFS;
 792         }
 793
 794         /* Attach the buffer to the mbuf. */
 795         m_new->m_ext.ext_arg = buf;
 796         m_new->m_ext.ext_buf = buf->bnx_buf;
 797         m_new->m_ext.ext_free = bnx_jfree;
 798         m_new->m_ext.ext_ref = bnx_jref;
 799         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
 800
 801         m_new->m_flags |= M_EXT;
 802
 803         m_new->m_data = m_new->m_ext.ext_buf;
 804         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 805
 806         paddr = buf->bnx_paddr;
 807         m_adj(m_new, ETHER_ALIGN);
 808         paddr += ETHER_ALIGN;
 809
 810         /* Save necessary information */
 811         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_mbuf = m_new;
 812         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_paddr = paddr;
 813
 814         /* Set up the descriptor. */
 815         bnx_setup_rxdesc_jumbo(sc, i);
 816         return 0;
 817 }
 818
 819 static void
 820 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
 821 {
 822         struct bge_rx_bd *r;
 823         struct bnx_rx_buf *rc;
 824
 825         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
 826         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 827
 828         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_rx_paddr);
 829         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_rx_paddr);
 830         r->bge_len = rc->bnx_rx_mbuf->m_len;
 831         r->bge_idx = i;
 832         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 833 }
 834
 835 static int
 836 bnx_init_rx_ring_std(struct bnx_rx_std_ring *std)
 837 {
 838         int i, error;
 839
 840         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 841                 /* Use the first RX return ring's tmp RX mbuf DMA map */
 842                 error = bnx_newbuf_std(&std->bnx_sc->bnx_rx_ret_ring[0], i, 1);
 843                 if (error)
 844                         return error;
 845         }
 846
 847         std->bnx_rx_std = BGE_STD_RX_RING_CNT - 1;
 848         bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO, std->bnx_rx_std);
 849
 850         return(0);
 851 }
 852
 853 static void
 854 bnx_free_rx_ring_std(struct bnx_rx_std_ring *std)
 855 {
 856         int i;
 857
 858         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 859                 struct bnx_rx_buf *rb = &std->bnx_rx_std_buf[i];
 860
 861                 if (rb->bnx_rx_mbuf != NULL) {
 862                         bus_dmamap_unload(std->bnx_rx_mtag, rb->bnx_rx_dmamap);
 863                         m_freem(rb->bnx_rx_mbuf);
 864                         rb->bnx_rx_mbuf = NULL;
 865                 }
 866                 bzero(&std->bnx_rx_std_ring[i], sizeof(struct bge_rx_bd));
 867         }
 868 }
 869
 870 static int
 871 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
 872 {
 873         struct bge_rcb *rcb;
 874         int i, error;
 875
 876         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 877                 error = bnx_newbuf_jumbo(sc, i, 1);
 878                 if (error)
 879                         return error;
 880         }
 881
 882         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
 883
 884         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
 885         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 886         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 887
 888         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
 889
 890         return(0);
 891 }
 892
 893 static void
 894 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
 895 {
 896         int i;
 897
 898         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 899                 struct bnx_rx_buf *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 900
 901                 if (rc->bnx_rx_mbuf != NULL) {
 902                         m_freem(rc->bnx_rx_mbuf);
 903                         rc->bnx_rx_mbuf = NULL;
 904                 }
 905                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
 906                     sizeof(struct bge_rx_bd));
 907         }
 908 }
 909
 910 static void
 911 bnx_free_tx_ring(struct bnx_tx_ring *txr)
 912 {
 913         int i;
 914
 915         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 916                 struct bnx_tx_buf *buf = &txr->bnx_tx_buf[i];
 917
 918                 if (buf->bnx_tx_mbuf != NULL) {
 919                         bus_dmamap_unload(txr->bnx_tx_mtag,
 920                             buf->bnx_tx_dmamap);
 921                         m_freem(buf->bnx_tx_mbuf);
 922                         buf->bnx_tx_mbuf = NULL;
 923                 }
 924                 bzero(&txr->bnx_tx_ring[i], sizeof(struct bge_tx_bd));
 925         }
 926         txr->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
 927 }
 928
 929 static int
 930 bnx_init_tx_ring(struct bnx_tx_ring *txr)
 931 {
 932         txr->bnx_tx_cnt = 0;
 933         txr->bnx_tx_saved_considx = 0;
 934         txr->bnx_tx_prodidx = 0;
 935
 936         /* Initialize transmit producer index for host-memory send ring. */
 937         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, txr->bnx_tx_prodidx);
 938
 939         return(0);
 940 }
 941
 942 static void
 943 bnx_setmulti(struct bnx_softc *sc)
 944 {
 945         struct ifnet *ifp;
 946         struct ifmultiaddr *ifma;
 947         uint32_t hashes[4] = { 0, 0, 0, 0 };
 948         int h, i;
 949
 950         ifp = &sc->arpcom.ac_if;
 951
 952         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 953                 for (i = 0; i < 4; i++)
 954                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
 955                 return;
 956         }
 957
 958         /* First, zot all the existing filters. */
 959         for (i = 0; i < 4; i++)
 960                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
 961
 962         /* Now program new ones. */
 963         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 964                 if (ifma->ifma_addr->sa_family != AF_LINK)
 965                         continue;
 966                 h = ether_crc32_le(
 967                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 968                     ETHER_ADDR_LEN) & 0x7f;
 969                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
 970         }
 971
 972         for (i = 0; i < 4; i++)
 973                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
 974 }
 975
 976 /*
 977  * Do endian, PCI and DMA initialization. Also check the on-board ROM
 978  * self-test results.
 979  */
 980 static int
 981 bnx_chipinit(struct bnx_softc *sc)
 982 {
 983         uint32_t dma_rw_ctl, mode_ctl;
 984         int i;
 985
 986         /* Set endian type before we access any non-PCI registers. */
 987         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
 988             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
 989
 990         /* Clear the MAC control register */
 991         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
 992
 993         /*
 994          * Clear the MAC statistics block in the NIC's
 995          * internal memory.
 996          */
 997         for (i = BGE_STATS_BLOCK;
 998             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
 999                 BNX_MEMWIN_WRITE(sc, i, 0);
1000
1001         for (i = BGE_STATUS_BLOCK;
1002             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1003                 BNX_MEMWIN_WRITE(sc, i, 0);
1004
1005         if (BNX_IS_57765_FAMILY(sc)) {
1006                 uint32_t val;
1007
1008                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
1009                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1010                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1011
1012                         /* Access the lower 1K of PL PCI-E block registers. */
1013                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1014                             val | BGE_MODECTL_PCIE_PL_SEL);
1015
1016                         val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
1017                         val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
1018                         CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
1019
1020                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1021                 }
1022                 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1023                         /* Fix transmit hangs */
1024                         val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
1025                         val |= BGE_CPMU_PADRNG_CTL_RDIV2;
1026                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val);
1027
1028                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1029                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1030
1031                         /* Access the lower 1K of DL PCI-E block registers. */
1032                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1033                             val | BGE_MODECTL_PCIE_DL_SEL);
1034
1035                         val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1036                         val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1037                         val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1038                         CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1039
1040                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1041                 }
1042
1043                 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1044                 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1045                 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1046                 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1047         }
1048
1049         /*
1050          * Set up the PCI DMA control register.
1051          */
1052         dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1053         /*
1054          * Disable 32bytes cache alignment for DMA write to host memory
1055          *
1056          * NOTE:
1057          * 64bytes cache alignment for DMA write to host memory is still
1058          * enabled.
1059          */
1060         dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1061         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1062                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1063         /*
1064          * Enable HW workaround for controllers that misinterpret
1065          * a status tag update and leave interrupts permanently
1066          * disabled.
1067          */
1068         if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1069             sc->bnx_asicrev != BGE_ASICREV_BCM5762 &&
1070             !BNX_IS_57765_FAMILY(sc))
1071                 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1072         if (bootverbose) {
1073                 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1074                     dma_rw_ctl);
1075         }
1076         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1077
1078         /*
1079          * Set up general mode register.
1080          */
1081         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1082             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1083         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1084
1085         /*
1086          * Disable memory write invalidate.  Apparently it is not supported
1087          * properly by these devices.  Also ensure that INTx isn't disabled,
1088          * as these chips need it even when using MSI.
1089          */
1090         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1091             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1092
1093         /* Set the timer prescaler (always 66Mhz) */
1094         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1095
1096         return(0);
1097 }
1098
1099 static int
1100 bnx_blockinit(struct bnx_softc *sc)
1101 {
1102         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
1103         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
1104         struct bge_rcb *rcb;
1105         bus_size_t vrcb;
1106         bge_hostaddr taddr;
1107         uint32_t val;
1108         int i, limit;
1109
1110         /*
1111          * Initialize the memory window pointer register so that
1112          * we can access the first 32K of internal NIC RAM. This will
1113          * allow us to set up the TX send ring RCBs and the RX return
1114          * ring RCBs, plus other things which live in NIC memory.
1115          */
1116         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1117
1118         /* Configure mbuf pool watermarks */
1119         if (BNX_IS_57765_PLUS(sc)) {
1120                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1121                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1122                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1123                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1124                 } else {
1125                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1126                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1127                 }
1128         } else {
1129                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1130                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1131                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1132         }
1133
1134         /* Configure DMA resource watermarks */
1135         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1136         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1137
1138         /* Enable buffer manager */
1139         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1140         /*
1141          * Change the arbitration algorithm of TXMBUF read request to
1142          * round-robin instead of priority based for BCM5719.  When
1143          * TXFIFO is almost empty, RDMA will hold its request until
1144          * TXFIFO is not almost empty.
1145          */
1146         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1147                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1148         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1149             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1150             sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1151                 val |= BGE_BMANMODE_LOMBUF_ATTN;
1152         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1153
1154         /* Poll for buffer manager start indication */
1155         for (i = 0; i < BNX_TIMEOUT; i++) {
1156                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1157                         break;
1158                 DELAY(10);
1159         }
1160
1161         if (i == BNX_TIMEOUT) {
1162                 if_printf(&sc->arpcom.ac_if,
1163                           "buffer manager failed to start\n");
1164                 return(ENXIO);
1165         }
1166
1167         /* Enable flow-through queues */
1168         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1169         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1170
1171         /* Wait until queue initialization is complete */
1172         for (i = 0; i < BNX_TIMEOUT; i++) {
1173                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1174                         break;
1175                 DELAY(10);
1176         }
1177
1178         if (i == BNX_TIMEOUT) {
1179                 if_printf(&sc->arpcom.ac_if,
1180                           "flow-through queue init failed\n");
1181                 return(ENXIO);
1182         }
1183
1184         /*
1185          * Summary of rings supported by the controller:
1186          *
1187          * Standard Receive Producer Ring
1188          * - This ring is used to feed receive buffers for "standard"
1189          *   sized frames (typically 1536 bytes) to the controller.
1190          *
1191          * Jumbo Receive Producer Ring
1192          * - This ring is used to feed receive buffers for jumbo sized
1193          *   frames (i.e. anything bigger than the "standard" frames)
1194          *   to the controller.
1195          *
1196          * Mini Receive Producer Ring
1197          * - This ring is used to feed receive buffers for "mini"
1198          *   sized frames to the controller.
1199          * - This feature required external memory for the controller
1200          *   but was never used in a production system.  Should always
1201          *   be disabled.
1202          *
1203          * Receive Return Ring
1204          * - After the controller has placed an incoming frame into a
1205          *   receive buffer that buffer is moved into a receive return
1206          *   ring.  The driver is then responsible to passing the
1207          *   buffer up to the stack.  Many versions of the controller
1208          *   support multiple RR rings.
1209          *
1210          * Send Ring
1211          * - This ring is used for outgoing frames.  Many versions of
1212          *   the controller support multiple send rings.
1213          */
1214
1215         /* Initialize the standard receive producer ring control block. */
1216         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1217         rcb->bge_hostaddr.bge_addr_lo =
1218             BGE_ADDR_LO(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1219         rcb->bge_hostaddr.bge_addr_hi =
1220             BGE_ADDR_HI(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1221         if (BNX_IS_57765_PLUS(sc)) {
1222                 /*
1223                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1224                  * Bits 15-2 : Maximum RX frame size
1225                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1226                  * Bit 0     : Reserved
1227                  */
1228                 rcb->bge_maxlen_flags =
1229                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1230         } else {
1231                 /*
1232                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1233                  * Bits 15-2 : Reserved (should be 0)
1234                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1235                  * Bit 0     : Reserved
1236                  */
1237                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1238         }
1239         if (BNX_IS_5717_PLUS(sc))
1240                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1241         else
1242                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1243         /* Write the standard receive producer ring control block. */
1244         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1245         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1246         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1247         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1248         /* Reset the standard receive producer ring producer index. */
1249         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1250
1251         /*
1252          * Initialize the jumbo RX producer ring control
1253          * block.  We set the 'ring disabled' bit in the
1254          * flags field until we're actually ready to start
1255          * using this ring (i.e. once we set the MTU
1256          * high enough to require it).
1257          */
1258         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1259                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1260                 /* Get the jumbo receive producer ring RCB parameters. */
1261                 rcb->bge_hostaddr.bge_addr_lo =
1262                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1263                 rcb->bge_hostaddr.bge_addr_hi =
1264                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1265                 rcb->bge_maxlen_flags =
1266                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1267                     BGE_RCB_FLAG_RING_DISABLED);
1268                 if (BNX_IS_5717_PLUS(sc))
1269                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1270                 else
1271                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1272                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1273                     rcb->bge_hostaddr.bge_addr_hi);
1274                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1275                     rcb->bge_hostaddr.bge_addr_lo);
1276                 /* Program the jumbo receive producer ring RCB parameters. */
1277                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1278                     rcb->bge_maxlen_flags);
1279                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1280                 /* Reset the jumbo receive producer ring producer index. */
1281                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1282         }
1283
1284         /*
1285          * The BD ring replenish thresholds control how often the
1286          * hardware fetches new BD's from the producer rings in host
1287          * memory.  Setting the value too low on a busy system can
1288          * starve the hardware and recue the throughpout.
1289          *
1290          * Set the BD ring replentish thresholds. The recommended
1291          * values are 1/8th the number of descriptors allocated to
1292          * each ring.
1293          */
1294         val = 8;
1295         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1296         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1297                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1298                     BGE_JUMBO_RX_RING_CNT/8);
1299         }
1300         if (BNX_IS_57765_PLUS(sc)) {
1301                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1302                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1303         }
1304
1305         /*
1306          * Disable all send rings by setting the 'ring disabled' bit
1307          * in the flags field of all the TX send ring control blocks,
1308          * located in NIC memory.
1309          */
1310         if (BNX_IS_5717_PLUS(sc))
1311                 limit = 4;
1312         else if (BNX_IS_57765_FAMILY(sc) ||
1313             sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1314                 limit = 2;
1315         else
1316                 limit = 1;
1317         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1318         for (i = 0; i < limit; i++) {
1319                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1320                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1321                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1322                 vrcb += sizeof(struct bge_rcb);
1323         }
1324
1325         /* Configure send ring RCB 0 (we use only the first ring) */
1326         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1327         BGE_HOSTADDR(taddr, txr->bnx_tx_ring_paddr);
1328         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1329         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1330         if (BNX_IS_5717_PLUS(sc)) {
1331                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1332         } else {
1333                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1334                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1335         }
1336         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1337             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1338
1339         /*
1340          * Disable all receive return rings by setting the
1341          * 'ring disabled' bit in the flags field of all the receive
1342          * return ring control blocks, located in NIC memory.
1343          */
1344         if (BNX_IS_5717_PLUS(sc)) {
1345                 /* Should be 17, use 16 until we get an SRAM map. */
1346                 limit = 16;
1347         } else if (BNX_IS_57765_FAMILY(sc) ||
1348             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1349                 limit = 4;
1350         } else {
1351                 limit = 1;
1352         }
1353         /* Disable all receive return rings. */
1354         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1355         for (i = 0; i < limit; i++) {
1356                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1357                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1358                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1359                     BGE_RCB_FLAG_RING_DISABLED);
1360                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1361                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1362                     (i * (sizeof(uint64_t))), 0);
1363                 vrcb += sizeof(struct bge_rcb);
1364         }
1365
1366         /*
1367          * Set up receive return ring 0.  Note that the NIC address
1368          * for RX return rings is 0x0.  The return rings live entirely
1369          * within the host, so the nicaddr field in the RCB isn't used.
1370          */
1371         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1372         BGE_HOSTADDR(taddr, ret->bnx_rx_ret_ring_paddr);
1373         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1374         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1375         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1376         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1377             BGE_RCB_MAXLEN_FLAGS(BNX_RETURN_RING_CNT, 0));
1378
1379         /* Set random backoff seed for TX */
1380         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1381             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1382             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1383             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1384             BGE_TX_BACKOFF_SEED_MASK);
1385
1386         /* Set inter-packet gap */
1387         val = 0x2620;
1388         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1389             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1390                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1391                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1392         }
1393         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1394
1395         /*
1396          * Specify which ring to use for packets that don't match
1397          * any RX rules.
1398          */
1399         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1400
1401         /*
1402          * Configure number of RX lists. One interrupt distribution
1403          * list, sixteen active lists, one bad frames class.
1404          */
1405         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1406
1407         /* Inialize RX list placement stats mask. */
1408         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1409         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1410
1411         /* Disable host coalescing until we get it set up */
1412         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1413
1414         /* Poll to make sure it's shut down. */
1415         for (i = 0; i < BNX_TIMEOUT; i++) {
1416                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1417                         break;
1418                 DELAY(10);
1419         }
1420
1421         if (i == BNX_TIMEOUT) {
1422                 if_printf(&sc->arpcom.ac_if,
1423                           "host coalescing engine failed to idle\n");
1424                 return(ENXIO);
1425         }
1426
1427         /* Set up host coalescing defaults */
1428         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bnx_rx_coal_ticks);
1429         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bnx_tx_coal_ticks);
1430         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bnx_rx_coal_bds);
1431         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bnx_tx_coal_bds);
1432         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bnx_rx_coal_bds_int);
1433         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bnx_tx_coal_bds_int);
1434
1435         /* Set up address of status block */
1436         bzero(sc->bnx_ldata.bnx_status_block, BGE_STATUS_BLK_SZ);
1437         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1438             BGE_ADDR_HI(sc->bnx_ldata.bnx_status_block_paddr));
1439         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1440             BGE_ADDR_LO(sc->bnx_ldata.bnx_status_block_paddr));
1441
1442         /* Set up status block partail update size. */
1443         val = BGE_STATBLKSZ_32BYTE;
1444 #if 0
1445         /*
1446          * Does not seem to have visible effect in both
1447          * bulk data (1472B UDP datagram) and tiny data
1448          * (18B UDP datagram) TX tests.
1449          */
1450         val |= BGE_HCCMODE_CLRTICK_TX;
1451 #endif
1452         /* Turn on host coalescing state machine */
1453         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1454
1455         /* Turn on RX BD completion state machine and enable attentions */
1456         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1457             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1458
1459         /* Turn on RX list placement state machine */
1460         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1461
1462         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1463             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1464             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1465             BGE_MACMODE_FRMHDR_DMA_ENB;
1466
1467         if (sc->bnx_flags & BNX_FLAG_TBI)
1468                 val |= BGE_PORTMODE_TBI;
1469         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1470                 val |= BGE_PORTMODE_GMII;
1471         else
1472                 val |= BGE_PORTMODE_MII;
1473
1474         /* Turn on DMA, clear stats */
1475         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1476
1477         /* Set misc. local control, enable interrupts on attentions */
1478         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1479
1480 #ifdef notdef
1481         /* Assert GPIO pins for PHY reset */
1482         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1483             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1484         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1485             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1486 #endif
1487
1488         /* Turn on write DMA state machine */
1489         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1490         /* Enable host coalescing bug fix. */
1491         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1492         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1493                 /* Request larger DMA burst size to get better performance. */
1494                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1495         }
1496         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1497         DELAY(40);
1498
1499         if (BNX_IS_57765_PLUS(sc)) {
1500                 uint32_t dmactl, dmactl_reg;
1501
1502                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1503                         dmactl_reg = BGE_RDMA_RSRVCTRL2;
1504                 else
1505                         dmactl_reg = BGE_RDMA_RSRVCTRL;
1506
1507                 dmactl = CSR_READ_4(sc, dmactl_reg);
1508                 /*
1509                  * Adjust tx margin to prevent TX data corruption and
1510                  * fix internal FIFO overflow.
1511                  */
1512                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1513                     sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1514                     sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1515                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1516                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1517                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1518                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1519                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1520                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1521                 }
1522                 /*
1523                  * Enable fix for read DMA FIFO overruns.
1524                  * The fix is to limit the number of RX BDs
1525                  * the hardware would fetch at a fime.
1526                  */
1527                 CSR_WRITE_4(sc, dmactl_reg,
1528                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1529         }
1530
1531         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1532                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1533                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1534                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1535                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1536         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1537             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1538                 uint32_t ctrl_reg;
1539
1540                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1541                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2;
1542                 else
1543                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL;
1544
1545                 /*
1546                  * Allow 4KB burst length reads for non-LSO frames.
1547                  * Enable 512B burst length reads for buffer descriptors.
1548                  */
1549                 CSR_WRITE_4(sc, ctrl_reg,
1550                     CSR_READ_4(sc, ctrl_reg) |
1551                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1552                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1553         }
1554
1555         /* Turn on read DMA state machine */
1556         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1557         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1558                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1559         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1560             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1561             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1562                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1563                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1564                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1565         }
1566         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1567             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1568                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1569                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1570                 /*
1571                  * Allow multiple outstanding read requests from
1572                  * non-LSO read DMA engine.
1573                  */
1574                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1575         }
1576         if (sc->bnx_asicrev == BGE_ASICREV_BCM57766)
1577                 val |= BGE_RDMAMODE_JMB_2K_MMRR;
1578         if (sc->bnx_flags & BNX_FLAG_TSO)
1579                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1580         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1581         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1582         DELAY(40);
1583
1584         /* Turn on RX data completion state machine */
1585         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1586
1587         /* Turn on RX BD initiator state machine */
1588         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1589
1590         /* Turn on RX data and RX BD initiator state machine */
1591         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1592
1593         /* Turn on send BD completion state machine */
1594         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1595
1596         /* Turn on send data completion state machine */
1597         val = BGE_SDCMODE_ENABLE;
1598         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1599                 val |= BGE_SDCMODE_CDELAY;
1600         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1601
1602         /* Turn on send data initiator state machine */
1603         if (sc->bnx_flags & BNX_FLAG_TSO) {
1604                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1605                     BGE_SDIMODE_HW_LSO_PRE_DMA);
1606         } else {
1607                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1608         }
1609
1610         /* Turn on send BD initiator state machine */
1611         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1612
1613         /* Turn on send BD selector state machine */
1614         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1615
1616         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1617         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1618             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1619
1620         /* ack/clear link change events */
1621         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1622             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1623             BGE_MACSTAT_LINK_CHANGED);
1624         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1625
1626         /*
1627          * Enable attention when the link has changed state for
1628          * devices that use auto polling.
1629          */
1630         if (sc->bnx_flags & BNX_FLAG_TBI) {
1631                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1632         } else {
1633                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1634                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1635                         DELAY(80);
1636                 }
1637         }
1638
1639         /*
1640          * Clear any pending link state attention.
1641          * Otherwise some link state change events may be lost until attention
1642          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1643          * It's not necessary on newer BCM chips - perhaps enabling link
1644          * state change attentions implies clearing pending attention.
1645          */
1646         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1647             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1648             BGE_MACSTAT_LINK_CHANGED);
1649
1650         /* Enable link state change attentions. */
1651         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1652
1653         return(0);
1654 }
1655
1656 /*
1657  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1658  * against our list and return its name if we find a match. Note
1659  * that since the Broadcom controller contains VPD support, we
1660  * can get the device name string from the controller itself instead
1661  * of the compiled-in string. This is a little slow, but it guarantees
1662  * we'll always announce the right product name.
1663  */
1664 static int
1665 bnx_probe(device_t dev)
1666 {
1667         const struct bnx_type *t;
1668         uint16_t product, vendor;
1669
1670         if (!pci_is_pcie(dev))
1671                 return ENXIO;
1672
1673         product = pci_get_device(dev);
1674         vendor = pci_get_vendor(dev);
1675
1676         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1677                 if (vendor == t->bnx_vid && product == t->bnx_did)
1678                         break;
1679         }
1680         if (t->bnx_name == NULL)
1681                 return ENXIO;
1682
1683         device_set_desc(dev, t->bnx_name);
1684         return 0;
1685 }
1686
1687 static int
1688 bnx_attach(device_t dev)
1689 {
1690         struct ifnet *ifp;
1691         struct bnx_softc *sc;
1692         uint32_t hwcfg = 0;
1693         int error = 0, rid, capmask, i;
1694         uint8_t ether_addr[ETHER_ADDR_LEN];
1695         uint16_t product;
1696         uintptr_t mii_priv = 0;
1697 #ifdef BNX_TSO_DEBUG
1698         char desc[32];
1699 #endif
1700 #ifdef IFPOLL_ENABLE
1701         int offset, offset_def;
1702 #endif
1703
1704         sc = device_get_softc(dev);
1705         sc->bnx_dev = dev;
1706         callout_init_mp(&sc->bnx_stat_timer);
1707         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1708         lwkt_serialize_init(&sc->bnx_main_serialize);
1709
1710         product = pci_get_device(dev);
1711
1712 #ifndef BURN_BRIDGES
1713         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1714                 uint32_t irq, mem;
1715
1716                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1717                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1718
1719                 device_printf(dev, "chip is in D%d power mode "
1720                     "-- setting to D0\n", pci_get_powerstate(dev));
1721
1722                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1723
1724                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1725                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1726         }
1727 #endif  /* !BURN_BRIDGE */
1728
1729         /*
1730          * Map control/status registers.
1731          */
1732         pci_enable_busmaster(dev);
1733
1734         rid = BGE_PCI_BAR0;
1735         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1736             RF_ACTIVE);
1737
1738         if (sc->bnx_res == NULL) {
1739                 device_printf(dev, "couldn't map memory\n");
1740                 return ENXIO;
1741         }
1742
1743         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1744         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1745
1746         /* Save various chip information */
1747         sc->bnx_chipid =
1748             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1749             BGE_PCIMISCCTL_ASICREV_SHIFT;
1750         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1751                 /* All chips having dedicated ASICREV register have CPMU */
1752                 sc->bnx_flags |= BNX_FLAG_CPMU;
1753
1754                 switch (product) {
1755                 case PCI_PRODUCT_BROADCOM_BCM5717:
1756                 case PCI_PRODUCT_BROADCOM_BCM5717C:
1757                 case PCI_PRODUCT_BROADCOM_BCM5718:
1758                 case PCI_PRODUCT_BROADCOM_BCM5719:
1759                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1760                 case PCI_PRODUCT_BROADCOM_BCM5725:
1761                 case PCI_PRODUCT_BROADCOM_BCM5727:
1762                 case PCI_PRODUCT_BROADCOM_BCM5762:
1763                         sc->bnx_chipid = pci_read_config(dev,
1764                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1765                         break;
1766
1767                 case PCI_PRODUCT_BROADCOM_BCM57761:
1768                 case PCI_PRODUCT_BROADCOM_BCM57762:
1769                 case PCI_PRODUCT_BROADCOM_BCM57765:
1770                 case PCI_PRODUCT_BROADCOM_BCM57766:
1771                 case PCI_PRODUCT_BROADCOM_BCM57781:
1772                 case PCI_PRODUCT_BROADCOM_BCM57782:
1773                 case PCI_PRODUCT_BROADCOM_BCM57785:
1774                 case PCI_PRODUCT_BROADCOM_BCM57786:
1775                 case PCI_PRODUCT_BROADCOM_BCM57791:
1776                 case PCI_PRODUCT_BROADCOM_BCM57795:
1777                         sc->bnx_chipid = pci_read_config(dev,
1778                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1779                         break;
1780
1781                 default:
1782                         sc->bnx_chipid = pci_read_config(dev,
1783                             BGE_PCI_PRODID_ASICREV, 4);
1784                         break;
1785                 }
1786         }
1787         if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0)
1788                 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0;
1789
1790         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1791         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1792
1793         switch (sc->bnx_asicrev) {
1794         case BGE_ASICREV_BCM5717:
1795         case BGE_ASICREV_BCM5719:
1796         case BGE_ASICREV_BCM5720:
1797                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1798                 break;
1799
1800         case BGE_ASICREV_BCM5762:
1801                 sc->bnx_flags |= BNX_FLAG_57765_PLUS;
1802                 break;
1803
1804         case BGE_ASICREV_BCM57765:
1805         case BGE_ASICREV_BCM57766:
1806                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1807                 break;
1808         }
1809
1810         sc->bnx_flags |= BNX_FLAG_TSO;
1811         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1812             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1813                 sc->bnx_flags &= ~BNX_FLAG_TSO;
1814
1815         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1816             BNX_IS_57765_FAMILY(sc)) {
1817                 /*
1818                  * All BCM57785 and BCM5718 families chips have a bug that
1819                  * under certain situation interrupt will not be enabled
1820                  * even if status tag is written to BGE_MBX_IRQ0_LO mailbox.
1821                  *
1822                  * While BCM5719 and BCM5720 have a hardware workaround
1823                  * which could fix the above bug.
1824                  * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1825                  * bnx_chipinit().
1826                  *
1827                  * For the rest of the chips in these two families, we will
1828                  * have to poll the status block at high rate (10ms currently)
1829                  * to check whether the interrupt is hosed or not.
1830                  * See bnx_check_intr() for details.
1831                  */
1832                 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1833         }
1834
1835         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1836         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1837             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1838                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1839         else
1840                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1841         device_printf(dev, "CHIP ID 0x%08x; "
1842                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1843                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1844
1845         /*
1846          * Set various PHY quirk flags.
1847          */
1848
1849         capmask = MII_CAPMASK_DEFAULT;
1850         if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1851             product == PCI_PRODUCT_BROADCOM_BCM57795) {
1852                 /* 10/100 only */
1853                 capmask &= ~BMSR_EXTSTAT;
1854         }
1855
1856         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1857         if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0)
1858                 mii_priv |= BRGPHY_FLAG_5762_A0;
1859
1860         /* Initialize if_name earlier, so if_printf could be used */
1861         ifp = &sc->arpcom.ac_if;
1862         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1863
1864         /* Try to reset the chip. */
1865         bnx_reset(sc);
1866
1867         if (bnx_chipinit(sc)) {
1868                 device_printf(dev, "chip initialization failed\n");
1869                 error = ENXIO;
1870                 goto fail;
1871         }
1872
1873         /*
1874          * Get station address
1875          */
1876         error = bnx_get_eaddr(sc, ether_addr);
1877         if (error) {
1878                 device_printf(dev, "failed to read station address\n");
1879                 goto fail;
1880         }
1881
1882         /* XXX */
1883         sc->bnx_tx_ringcnt = 1;
1884         sc->bnx_rx_retcnt = 1;
1885
1886         if ((sc->bnx_rx_retcnt == 1 && sc->bnx_tx_ringcnt == 1) ||
1887             (sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt > 1)) {
1888                 /*
1889                  * The RX ring and the corresponding TX ring processing
1890                  * should be on the same CPU, since they share the same
1891                  * status block.
1892                  */
1893                 sc->bnx_flags |= BNX_FLAG_RXTX_BUNDLE;
1894                 if (bootverbose)
1895                         device_printf(dev, "RX/TX bundle\n");
1896         } else {
1897                 KKASSERT(sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt == 1);
1898         }
1899
1900         error = bnx_dma_alloc(dev);
1901         if (error)
1902                 goto fail;
1903
1904 #ifdef IFPOLL_ENABLE
1905         if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
1906                 /*
1907                  * NPOLLING RX/TX CPU offset
1908                  */
1909                 if (sc->bnx_rx_retcnt == ncpus2) {
1910                         offset = 0;
1911                 } else {
1912                         offset_def =
1913                         (sc->bnx_rx_retcnt * device_get_unit(dev)) % ncpus2;
1914                         offset = device_getenv_int(dev, "npoll.offset",
1915                             offset_def);
1916                         if (offset >= ncpus2 ||
1917                             offset % sc->bnx_rx_retcnt != 0) {
1918                                 device_printf(dev, "invalid npoll.offset %d, "
1919                                     "use %d\n", offset, offset_def);
1920                                 offset = offset_def;
1921                         }
1922                 }
1923                 sc->bnx_npoll_rxoff = offset;
1924                 sc->bnx_npoll_txoff = offset;
1925         } else {
1926                 /*
1927                  * NPOLLING RX CPU offset
1928                  */
1929                 if (sc->bnx_rx_retcnt == ncpus2) {
1930                         offset = 0;
1931                 } else {
1932                         offset_def =
1933                         (sc->bnx_rx_retcnt * device_get_unit(dev)) % ncpus2;
1934                         offset = device_getenv_int(dev, "npoll.rxoff",
1935                             offset_def);
1936                         if (offset >= ncpus2 ||
1937                             offset % sc->bnx_rx_retcnt != 0) {
1938                                 device_printf(dev, "invalid npoll.rxoff %d, "
1939                                     "use %d\n", offset, offset_def);
1940                                 offset = offset_def;
1941                         }
1942                 }
1943                 sc->bnx_npoll_rxoff = offset;
1944
1945                 /*
1946                  * NPOLLING TX CPU offset
1947                  */
1948                 offset_def = device_get_unit(dev) % ncpus2;
1949                 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
1950                 if (offset >= ncpus2) {
1951                         device_printf(dev, "invalid npoll.txoff %d, use %d\n",
1952                             offset, offset_def);
1953                         offset = offset_def;
1954                 }
1955                 sc->bnx_npoll_txoff = offset;
1956         }
1957 #endif  /* IFPOLL_ENABLE */
1958
1959         /*
1960          * Allocate interrupt
1961          */
1962         error = bnx_alloc_intr(sc);
1963         if (error)
1964                 goto fail;
1965
1966         /* Setup serializers */
1967         bnx_setup_serialize(sc);
1968
1969         /* Set default tuneable values. */
1970         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
1971         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
1972         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
1973         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
1974         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
1975         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
1976
1977         /* Set up ifnet structure */
1978         ifp->if_softc = sc;
1979         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1980         ifp->if_ioctl = bnx_ioctl;
1981         ifp->if_start = bnx_start;
1982 #ifdef IFPOLL_ENABLE
1983         ifp->if_npoll = bnx_npoll;
1984 #endif
1985         ifp->if_init = bnx_init;
1986         ifp->if_serialize = bnx_serialize;
1987         ifp->if_deserialize = bnx_deserialize;
1988         ifp->if_tryserialize = bnx_tryserialize;
1989 #ifdef INVARIANTS
1990         ifp->if_serialize_assert = bnx_serialize_assert;
1991 #endif
1992         ifp->if_mtu = ETHERMTU;
1993         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1994
1995         ifp->if_capabilities |= IFCAP_HWCSUM;
1996         ifp->if_hwassist = BNX_CSUM_FEATURES;
1997         if (sc->bnx_flags & BNX_FLAG_TSO) {
1998                 ifp->if_capabilities |= IFCAP_TSO;
1999                 ifp->if_hwassist |= CSUM_TSO;
2000         }
2001         ifp->if_capenable = ifp->if_capabilities;
2002
2003         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2004         ifq_set_ready(&ifp->if_snd);
2005         ifq_set_subq_cnt(&ifp->if_snd, sc->bnx_tx_ringcnt);
2006
2007         /*
2008          * Figure out what sort of media we have by checking the
2009          * hardware config word in the first 32k of NIC internal memory,
2010          * or fall back to examining the EEPROM if necessary.
2011          * Note: on some BCM5700 cards, this value appears to be unset.
2012          * If that's the case, we have to rely on identifying the NIC
2013          * by its PCI subsystem ID, as we do below for the SysKonnect
2014          * SK-9D41.
2015          */
2016         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2017                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2018         } else {
2019                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2020                                     sizeof(hwcfg))) {
2021                         device_printf(dev, "failed to read EEPROM\n");
2022                         error = ENXIO;
2023                         goto fail;
2024                 }
2025                 hwcfg = ntohl(hwcfg);
2026         }
2027
2028         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2029         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2030             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2031                 sc->bnx_flags |= BNX_FLAG_TBI;
2032
2033         /* Setup MI MODE */
2034         if (sc->bnx_flags & BNX_FLAG_CPMU)
2035                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
2036         else
2037                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
2038
2039         /* Setup link status update stuffs */
2040         if (sc->bnx_flags & BNX_FLAG_TBI) {
2041                 sc->bnx_link_upd = bnx_tbi_link_upd;
2042                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2043         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
2044                 sc->bnx_link_upd = bnx_autopoll_link_upd;
2045                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2046         } else {
2047                 sc->bnx_link_upd = bnx_copper_link_upd;
2048                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2049         }
2050
2051         /* Set default PHY address */
2052         sc->bnx_phyno = 1;
2053
2054         /*
2055          * PHY address mapping for various devices.
2056          *
2057          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2058          * ---------+-------+-------+-------+-------+
2059          * BCM57XX  |   1   |   X   |   X   |   X   |
2060          * BCM5704  |   1   |   X   |   1   |   X   |
2061          * BCM5717  |   1   |   8   |   2   |   9   |
2062          * BCM5719  |   1   |   8   |   2   |   9   |
2063          * BCM5720  |   1   |   8   |   2   |   9   |
2064          *
2065          * Other addresses may respond but they are not
2066          * IEEE compliant PHYs and should be ignored.
2067          */
2068         if (BNX_IS_5717_PLUS(sc)) {
2069                 int f;
2070
2071                 f = pci_get_function(dev);
2072                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
2073                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2074                             BGE_SGDIGSTS_IS_SERDES)
2075                                 sc->bnx_phyno = f + 8;
2076                         else
2077                                 sc->bnx_phyno = f + 1;
2078                 } else {
2079                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2080                             BGE_CPMU_PHY_STRAP_IS_SERDES)
2081                                 sc->bnx_phyno = f + 8;
2082                         else
2083                                 sc->bnx_phyno = f + 1;
2084                 }
2085         }
2086
2087         if (sc->bnx_flags & BNX_FLAG_TBI) {
2088                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
2089                     bnx_ifmedia_upd, bnx_ifmedia_sts);
2090                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2091                 ifmedia_add(&sc->bnx_ifmedia,
2092                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2093                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2094                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2095                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2096         } else {
2097                 struct mii_probe_args mii_args;
2098
2099                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2100                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2101                 mii_args.mii_capmask = capmask;
2102                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2103                 mii_args.mii_priv = mii_priv;
2104
2105                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2106                 if (error) {
2107                         device_printf(dev, "MII without any PHY!\n");
2108                         goto fail;
2109                 }
2110         }
2111
2112         /*
2113          * Create sysctl nodes.
2114          */
2115         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2116         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2117                                               SYSCTL_STATIC_CHILDREN(_hw),
2118                                               OID_AUTO,
2119                                               device_get_nameunit(dev),
2120                                               CTLFLAG_RD, 0, "");
2121         if (sc->bnx_sysctl_tree == NULL) {
2122                 device_printf(dev, "can't add sysctl node\n");
2123                 error = ENXIO;
2124                 goto fail;
2125         }
2126
2127         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2128             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2129             "rx_rings", CTLFLAG_RD, &sc->bnx_rx_retcnt, 0, "# of RX rings");
2130         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2131             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2132             "tx_rings", CTLFLAG_RD, &sc->bnx_tx_ringcnt, 0, "# of TX rings");
2133
2134         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2135                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2136                         OID_AUTO, "rx_coal_ticks",
2137                         CTLTYPE_INT | CTLFLAG_RW,
2138                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2139                         "Receive coalescing ticks (usec).");
2140         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2141                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2142                         OID_AUTO, "tx_coal_ticks",
2143                         CTLTYPE_INT | CTLFLAG_RW,
2144                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2145                         "Transmit coalescing ticks (usec).");
2146         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2147                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2148                         OID_AUTO, "rx_coal_bds",
2149                         CTLTYPE_INT | CTLFLAG_RW,
2150                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2151                         "Receive max coalesced BD count.");
2152         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2153                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2154                         OID_AUTO, "tx_coal_bds",
2155                         CTLTYPE_INT | CTLFLAG_RW,
2156                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2157                         "Transmit max coalesced BD count.");
2158         /*
2159          * A common design characteristic for many Broadcom
2160          * client controllers is that they only support a
2161          * single outstanding DMA read operation on the PCIe
2162          * bus. This means that it will take twice as long to
2163          * fetch a TX frame that is split into header and
2164          * payload buffers as it does to fetch a single,
2165          * contiguous TX frame (2 reads vs. 1 read). For these
2166          * controllers, coalescing buffers to reduce the number
2167          * of memory reads is effective way to get maximum
2168          * performance(about 940Mbps).  Without collapsing TX
2169          * buffers the maximum TCP bulk transfer performance
2170          * is about 850Mbps. However forcing coalescing mbufs
2171          * consumes a lot of CPU cycles, so leave it off by
2172          * default.
2173          */
2174         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2175             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2176             "force_defrag", CTLTYPE_INT | CTLFLAG_RW,
2177             sc, 0, bnx_sysctl_force_defrag, "I",
2178             "Force defragment on TX path");
2179
2180         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2181             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2182             "tx_wreg", CTLTYPE_INT | CTLFLAG_RW,
2183             sc, 0, bnx_sysctl_tx_wreg, "I",
2184             "# of segments before writing to hardware register");
2185
2186         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2187             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2188             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2189             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2190             "Receive max coalesced BD count during interrupt.");
2191         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2192             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2193             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2194             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2195             "Transmit max coalesced BD count during interrupt.");
2196
2197 #ifdef IFPOLL_ENABLE
2198         if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
2199                 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2200                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2201                     "npoll_offset", CTLTYPE_INT | CTLFLAG_RW,
2202                     sc, 0, bnx_sysctl_npoll_offset, "I",
2203                     "NPOLLING cpu offset");
2204         } else {
2205                 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2206                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2207                     "npoll_rxoff", CTLTYPE_INT | CTLFLAG_RW,
2208                     sc, 0, bnx_sysctl_npoll_rxoff, "I",
2209                     "NPOLLING RX cpu offset");
2210                 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2211                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2212                     "npoll_txoff", CTLTYPE_INT | CTLFLAG_RW,
2213                     sc, 0, bnx_sysctl_npoll_txoff, "I",
2214                     "NPOLLING TX cpu offset");
2215         }
2216 #endif
2217
2218 #ifdef BNX_TSO_DEBUG
2219         for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2220                 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2221                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2222                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2223                     desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2224         }
2225 #endif
2226
2227         /*
2228          * Call MI attach routine.
2229          */
2230         ether_ifattach(ifp, ether_addr, NULL);
2231
2232         /* Setup TX rings and subqueues */
2233         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2234                 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
2235                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
2236
2237                 ifsq_set_cpuid(ifsq, txr->bnx_tx_cpuid);
2238                 ifsq_set_hw_serialize(ifsq, &txr->bnx_tx_serialize);
2239                 ifsq_set_priv(ifsq, txr);
2240                 txr->bnx_ifsq = ifsq;
2241
2242                 ifsq_watchdog_init(&txr->bnx_tx_watchdog, ifsq, bnx_watchdog);
2243         }
2244
2245         error = bnx_setup_intr(sc);
2246         if (error) {
2247                 ether_ifdetach(ifp);
2248                 goto fail;
2249         }
2250
2251         sc->bnx_stat_cpuid = sc->bnx_intr_data[0].bnx_intr_cpuid;
2252
2253         return(0);
2254 fail:
2255         bnx_detach(dev);
2256         return(error);
2257 }
2258
2259 static int
2260 bnx_detach(device_t dev)
2261 {
2262         struct bnx_softc *sc = device_get_softc(dev);
2263
2264         if (device_is_attached(dev)) {
2265                 struct ifnet *ifp = &sc->arpcom.ac_if;
2266
2267                 ifnet_serialize_all(ifp);
2268                 bnx_stop(sc);
2269                 bnx_reset(sc);
2270                 bnx_teardown_intr(sc, sc->bnx_intr_cnt);
2271                 ifnet_deserialize_all(ifp);
2272
2273                 ether_ifdetach(ifp);
2274         }
2275
2276         if (sc->bnx_flags & BNX_FLAG_TBI)
2277                 ifmedia_removeall(&sc->bnx_ifmedia);
2278         if (sc->bnx_miibus)
2279                 device_delete_child(dev, sc->bnx_miibus);
2280         bus_generic_detach(dev);
2281
2282         bnx_free_intr(sc);
2283
2284         if (sc->bnx_res != NULL) {
2285                 bus_release_resource(dev, SYS_RES_MEMORY,
2286                     BGE_PCI_BAR0, sc->bnx_res);
2287         }
2288
2289         if (sc->bnx_sysctl_tree != NULL)
2290                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2291
2292         bnx_dma_free(sc);
2293
2294         if (sc->bnx_serialize != NULL)
2295                 kfree(sc->bnx_serialize, M_DEVBUF);
2296
2297         return 0;
2298 }
2299
2300 static void
2301 bnx_reset(struct bnx_softc *sc)
2302 {
2303         device_t dev;
2304         uint32_t cachesize, command, pcistate, reset;
2305         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2306         int i, val = 0;
2307         uint16_t devctl;
2308
2309         dev = sc->bnx_dev;
2310
2311         write_op = bnx_writemem_direct;
2312
2313         /* Save some important PCI state. */
2314         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2315         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2316         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2317
2318         pci_write_config(dev, BGE_PCI_MISC_CTL,
2319             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2320             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2321             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2322
2323         /* Disable fastboot on controllers that support it. */
2324         if (bootverbose)
2325                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2326         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2327
2328         /*
2329          * Write the magic number to SRAM at offset 0xB50.
2330          * When firmware finishes its initialization it will
2331          * write ~BGE_MAGIC_NUMBER to the same location.
2332          */
2333         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2334
2335         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2336
2337         /* XXX: Broadcom Linux driver. */
2338         /* Force PCI-E 1.0a mode */
2339         if (!BNX_IS_57765_PLUS(sc) &&
2340             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2341             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2342              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2343                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2344                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2345         }
2346         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2347                 /* Prevent PCIE link training during global reset */
2348                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2349                 reset |= (1<<29);
2350         }
2351
2352         /*
2353          * Set GPHY Power Down Override to leave GPHY
2354          * powered up in D0 uninitialized.
2355          */
2356         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2357                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2358
2359         /* Issue global reset */
2360         write_op(sc, BGE_MISC_CFG, reset);
2361
2362         DELAY(1000);
2363
2364         /* XXX: Broadcom Linux driver. */
2365         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2366                 uint32_t v;
2367
2368                 DELAY(500000); /* wait for link training to complete */
2369                 v = pci_read_config(dev, 0xc4, 4);
2370                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2371         }
2372
2373         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2374
2375         /* Disable no snoop and disable relaxed ordering. */
2376         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2377
2378         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2379         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2380                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2381                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2382         }
2383
2384         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2385             devctl, 2);
2386
2387         /* Clear error status. */
2388         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2389             PCIEM_DEVSTS_CORR_ERR |
2390             PCIEM_DEVSTS_NFATAL_ERR |
2391             PCIEM_DEVSTS_FATAL_ERR |
2392             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2393
2394         /* Reset some of the PCI state that got zapped by reset */
2395         pci_write_config(dev, BGE_PCI_MISC_CTL,
2396             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2397             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2398             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2399         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2400         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2401         write_op(sc, BGE_MISC_CFG, (65 << 1));
2402
2403         /* Enable memory arbiter */
2404         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2405
2406         /*
2407          * Poll until we see the 1's complement of the magic number.
2408          * This indicates that the firmware initialization is complete.
2409          */
2410         for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2411                 val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2412                 if (val == ~BGE_MAGIC_NUMBER)
2413                         break;
2414                 DELAY(10);
2415         }
2416         if (i == BNX_FIRMWARE_TIMEOUT) {
2417                 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2418                           "timed out, found 0x%08x\n", val);
2419         }
2420
2421         /* BCM57765 A0 needs additional time before accessing. */
2422         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2423                 DELAY(10 * 1000);
2424
2425         /*
2426          * XXX Wait for the value of the PCISTATE register to
2427          * return to its original pre-reset state. This is a
2428          * fairly good indicator of reset completion. If we don't
2429          * wait for the reset to fully complete, trying to read
2430          * from the device's non-PCI registers may yield garbage
2431          * results.
2432          */
2433         for (i = 0; i < BNX_TIMEOUT; i++) {
2434                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2435                         break;
2436                 DELAY(10);
2437         }
2438
2439         /* Fix up byte swapping */
2440         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2441
2442         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2443
2444         /*
2445          * The 5704 in TBI mode apparently needs some special
2446          * adjustment to insure the SERDES drive level is set
2447          * to 1.2V.
2448          */
2449         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2450             (sc->bnx_flags & BNX_FLAG_TBI)) {
2451                 uint32_t serdescfg;
2452
2453                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2454                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2455                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2456         }
2457
2458         CSR_WRITE_4(sc, BGE_MI_MODE,
2459             sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2460         DELAY(80);
2461
2462         /* XXX: Broadcom Linux driver. */
2463         if (!BNX_IS_57765_PLUS(sc)) {
2464                 uint32_t v;
2465
2466                 /* Enable Data FIFO protection. */
2467                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2468                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2469         }
2470
2471         DELAY(10000);
2472
2473         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2474                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2475                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2476         }
2477 }
2478
2479 /*
2480  * Frame reception handling. This is called if there's a frame
2481  * on the receive return list.
2482  *
2483  * Note: we have to be able to handle two possibilities here:
2484  * 1) the frame is from the jumbo recieve ring
2485  * 2) the frame is from the standard receive ring
2486  */
2487
2488 static void
2489 bnx_rxeof(struct bnx_rx_ret_ring *ret, uint16_t rx_prod, int count)
2490 {
2491         struct bnx_softc *sc = ret->bnx_sc;
2492         struct bnx_rx_std_ring *std = ret->bnx_std;
2493         struct ifnet *ifp = &sc->arpcom.ac_if;
2494         int stdcnt = 0, jumbocnt = 0;
2495
2496         while (ret->bnx_rx_saved_considx != rx_prod && count != 0) {
2497                 struct bge_rx_bd        *cur_rx;
2498                 uint32_t                rxidx;
2499                 struct mbuf             *m = NULL;
2500                 uint16_t                vlan_tag = 0;
2501                 int                     have_tag = 0;
2502
2503                 --count;
2504
2505                 cur_rx = &ret->bnx_rx_ret_ring[ret->bnx_rx_saved_considx];
2506
2507                 rxidx = cur_rx->bge_idx;
2508                 BNX_INC(ret->bnx_rx_saved_considx, BNX_RETURN_RING_CNT);
2509
2510                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2511                         have_tag = 1;
2512                         vlan_tag = cur_rx->bge_vlan_tag;
2513                 }
2514
2515                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2516                         BNX_INC(sc->bnx_jumbo, BGE_JUMBO_RX_RING_CNT);
2517                         jumbocnt++;
2518
2519                         if (rxidx != sc->bnx_jumbo) {
2520                                 IFNET_STAT_INC(ifp, ierrors, 1);
2521                                 if_printf(ifp, "sw jumbo index(%d) "
2522                                     "and hw jumbo index(%d) mismatch, drop!\n",
2523                                     sc->bnx_jumbo, rxidx);
2524                                 bnx_setup_rxdesc_jumbo(sc, rxidx);
2525                                 continue;
2526                         }
2527
2528                         m = sc->bnx_cdata.bnx_rx_jumbo_chain[rxidx].bnx_rx_mbuf;
2529                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2530                                 IFNET_STAT_INC(ifp, ierrors, 1);
2531                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2532                                 continue;
2533                         }
2534                         if (bnx_newbuf_jumbo(sc, sc->bnx_jumbo, 0)) {
2535                                 IFNET_STAT_INC(ifp, ierrors, 1);
2536                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2537                                 continue;
2538                         }
2539                 } else {
2540                         BNX_INC(std->bnx_rx_std, BGE_STD_RX_RING_CNT);
2541                         stdcnt++;
2542
2543                         if (rxidx != std->bnx_rx_std) {
2544                                 IFNET_STAT_INC(ifp, ierrors, 1);
2545                                 if_printf(ifp, "sw std index(%d) "
2546                                     "and hw std index(%d) mismatch, drop!\n",
2547                                     std->bnx_rx_std, rxidx);
2548                                 bnx_setup_rxdesc_std(std, rxidx);
2549                                 continue;
2550                         }
2551
2552                         m = std->bnx_rx_std_buf[rxidx].bnx_rx_mbuf;
2553                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2554                                 IFNET_STAT_INC(ifp, ierrors, 1);
2555                                 bnx_setup_rxdesc_std(std, std->bnx_rx_std);
2556                                 continue;
2557                         }
2558                         if (bnx_newbuf_std(ret, std->bnx_rx_std, 0)) {
2559                                 IFNET_STAT_INC(ifp, ierrors, 1);
2560                                 bnx_setup_rxdesc_std(std, std->bnx_rx_std);
2561                                 continue;
2562                         }
2563                 }
2564
2565                 IFNET_STAT_INC(ifp, ipackets, 1);
2566                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2567                 m->m_pkthdr.rcvif = ifp;
2568
2569                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2570                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2571                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2572                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2573                                 if ((cur_rx->bge_error_flag &
2574                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2575                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2576                         }
2577                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2578                                 m->m_pkthdr.csum_data =
2579                                     cur_rx->bge_tcp_udp_csum;
2580                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2581                                     CSUM_PSEUDO_HDR;
2582                         }
2583                 }
2584
2585                 /*
2586                  * If we received a packet with a vlan tag, pass it
2587                  * to vlan_input() instead of ether_input().
2588                  */
2589                 if (have_tag) {
2590                         m->m_flags |= M_VLANTAG;
2591                         m->m_pkthdr.ether_vlantag = vlan_tag;
2592                 }
2593                 ifp->if_input(ifp, m);
2594         }
2595
2596         bnx_writembx(sc, BGE_MBX_RX_CONS0_LO, ret->bnx_rx_saved_considx);
2597         if (stdcnt)
2598                 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, std->bnx_rx_std);
2599         if (jumbocnt)
2600                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
2601 }
2602
2603 static void
2604 bnx_txeof(struct bnx_tx_ring *txr, uint16_t tx_cons)
2605 {
2606         struct ifnet *ifp = &txr->bnx_sc->arpcom.ac_if;
2607
2608         /*
2609          * Go through our tx ring and free mbufs for those
2610          * frames that have been sent.
2611          */
2612         while (txr->bnx_tx_saved_considx != tx_cons) {
2613                 struct bnx_tx_buf *buf;
2614                 uint32_t idx = 0;
2615
2616                 idx = txr->bnx_tx_saved_considx;
2617                 buf = &txr->bnx_tx_buf[idx];
2618                 if (buf->bnx_tx_mbuf != NULL) {
2619                         IFNET_STAT_INC(ifp, opackets, 1);
2620                         bus_dmamap_unload(txr->bnx_tx_mtag,
2621                             buf->bnx_tx_dmamap);
2622                         m_freem(buf->bnx_tx_mbuf);
2623                         buf->bnx_tx_mbuf = NULL;
2624                 }
2625                 txr->bnx_tx_cnt--;
2626                 BNX_INC(txr->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2627         }
2628
2629         if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) >=
2630             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2631                 ifsq_clr_oactive(txr->bnx_ifsq);
2632
2633         if (txr->bnx_tx_cnt == 0)
2634                 txr->bnx_tx_watchdog.wd_timer = 0;
2635
2636         if (!ifsq_is_empty(txr->bnx_ifsq))
2637                 ifsq_devstart(txr->bnx_ifsq);
2638 }
2639
2640 #ifdef IFPOLL_ENABLE
2641
2642 static void
2643 bnx_npoll_rx(struct ifnet *ifp __unused, void *xret, int cycle)
2644 {
2645         struct bnx_rx_ret_ring *ret = xret;
2646         uint16_t rx_prod;
2647
2648         ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
2649
2650         ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
2651         cpu_lfence();
2652
2653         rx_prod = *ret->bnx_rx_considx;
2654         if (ret->bnx_rx_saved_considx != rx_prod)
2655                 bnx_rxeof(ret, rx_prod, cycle);
2656 }
2657
2658 static void
2659 bnx_npoll_tx(struct ifnet *ifp __unused, void *xtxr, int cycle __unused)
2660 {
2661         struct bnx_tx_ring *txr = xtxr;
2662         uint16_t tx_cons;
2663
2664         ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
2665
2666         tx_cons = *txr->bnx_tx_considx;
2667         if (txr->bnx_tx_saved_considx != tx_cons)
2668                 bnx_txeof(txr, tx_cons);
2669 }
2670
2671 static void
2672 bnx_npoll_status(struct ifnet *ifp)
2673 {
2674         struct bnx_softc *sc = ifp->if_softc;
2675         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2676
2677         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
2678
2679         if ((sblk->bge_status & BGE_STATFLAG_LINKSTATE_CHANGED) ||
2680             sc->bnx_link_evt)
2681                 bnx_link_poll(sc);
2682 }
2683
2684 static void
2685 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2686 {
2687         struct bnx_softc *sc = ifp->if_softc;
2688         int i;
2689
2690         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2691
2692         if (info != NULL) {
2693                 /*
2694                  * TODO handle RXTX bundle and non-bundle
2695                  */
2696                 info->ifpi_status.status_func = bnx_npoll_status;
2697                 info->ifpi_status.serializer = &sc->bnx_main_serialize;
2698
2699                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2700                         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
2701                         int idx = i + sc->bnx_npoll_txoff;
2702
2703                         KKASSERT(idx < ncpus2);
2704                         info->ifpi_tx[idx].poll_func = bnx_npoll_tx;
2705                         info->ifpi_tx[idx].arg = txr;
2706                         info->ifpi_tx[idx].serializer = &txr->bnx_tx_serialize;
2707                         ifsq_set_cpuid(txr->bnx_ifsq, idx);
2708                 }
2709
2710                 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
2711                         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
2712                         int idx = i + sc->bnx_npoll_rxoff;
2713
2714                         KKASSERT(idx < ncpus2);
2715                         info->ifpi_rx[idx].poll_func = bnx_npoll_rx;
2716                         info->ifpi_rx[idx].arg = ret;
2717                         info->ifpi_rx[idx].serializer =
2718                             &ret->bnx_rx_ret_serialize;
2719                 }
2720
2721                 if (ifp->if_flags & IFF_RUNNING)
2722                         bnx_disable_intr(sc);
2723         } else {
2724                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2725                         ifsq_set_cpuid(sc->bnx_tx_ring[i].bnx_ifsq,
2726                             sc->bnx_tx_ring[i].bnx_tx_cpuid);
2727                 }
2728                 if (ifp->if_flags & IFF_RUNNING)
2729                         bnx_enable_intr(sc);
2730         }
2731 }
2732
2733 #endif  /* IFPOLL_ENABLE */
2734
2735 static void
2736 bnx_intr_legacy(void *xsc)
2737 {
2738         struct bnx_softc *sc = xsc;
2739         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
2740
2741         if (ret->bnx_saved_status_tag == *ret->bnx_hw_status_tag) {
2742                 uint32_t val;
2743
2744                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
2745                 if (val & BGE_PCISTAT_INTR_NOTACT)
2746                         return;
2747         }
2748
2749         /*
2750          * NOTE:
2751          * Interrupt will have to be disabled if tagged status
2752          * is used, else interrupt will always be asserted on
2753          * certain chips (at least on BCM5750 AX/BX).
2754          */
2755         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2756
2757         bnx_intr(sc);
2758 }
2759
2760 static void
2761 bnx_msi(void *xsc)
2762 {
2763         struct bnx_softc *sc = xsc;
2764
2765         /* Disable interrupt first */
2766         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2767         bnx_intr(sc);
2768 }
2769
2770 static void
2771 bnx_msi_oneshot(void *xsc)
2772 {
2773         bnx_intr(xsc);
2774 }
2775
2776 static void
2777 bnx_intr(struct bnx_softc *sc)
2778 {
2779         struct ifnet *ifp = &sc->arpcom.ac_if;
2780         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
2781         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2782         uint32_t status;
2783
2784         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
2785
2786         ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
2787         /*
2788          * Use a load fence to ensure that status_tag is saved
2789          * before rx_prod, tx_cons and status.
2790          */
2791         cpu_lfence();
2792
2793         status = sblk->bge_status;
2794
2795         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2796                 bnx_link_poll(sc);
2797
2798         if (ifp->if_flags & IFF_RUNNING) {
2799                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
2800                 uint16_t rx_prod, tx_cons;
2801
2802                 lwkt_serialize_enter(&ret->bnx_rx_ret_serialize);
2803                 rx_prod = *ret->bnx_rx_considx;
2804                 if (ret->bnx_rx_saved_considx != rx_prod)
2805                         bnx_rxeof(ret, rx_prod, -1);
2806                 lwkt_serialize_exit(&ret->bnx_rx_ret_serialize);
2807
2808                 lwkt_serialize_enter(&txr->bnx_tx_serialize);
2809                 tx_cons = *txr->bnx_tx_considx;
2810                 if (txr->bnx_tx_saved_considx != tx_cons)
2811                         bnx_txeof(txr, tx_cons);
2812                 lwkt_serialize_exit(&txr->bnx_tx_serialize);
2813         }
2814
2815         bnx_writembx(sc, BGE_MBX_IRQ0_LO, ret->bnx_saved_status_tag << 24);
2816 }
2817
2818 static void
2819 bnx_tick(void *xsc)
2820 {
2821         struct bnx_softc *sc = xsc;
2822
2823         lwkt_serialize_enter(&sc->bnx_main_serialize);
2824
2825         KKASSERT(mycpuid == sc->bnx_stat_cpuid);
2826
2827         bnx_stats_update_regs(sc);
2828
2829         if (sc->bnx_flags & BNX_FLAG_TBI) {
2830                 /*
2831                  * Since in TBI mode auto-polling can't be used we should poll
2832                  * link status manually. Here we register pending link event
2833                  * and trigger interrupt.
2834                  */
2835                 sc->bnx_link_evt++;
2836                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2837         } else if (!sc->bnx_link) {
2838                 mii_tick(device_get_softc(sc->bnx_miibus));
2839         }
2840
2841         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
2842
2843         lwkt_serialize_exit(&sc->bnx_main_serialize);
2844 }
2845
2846 static void
2847 bnx_stats_update_regs(struct bnx_softc *sc)
2848 {
2849         struct ifnet *ifp = &sc->arpcom.ac_if;
2850         struct bge_mac_stats_regs stats;
2851         uint32_t *s;
2852         int i;
2853
2854         s = (uint32_t *)&stats;
2855         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2856                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2857                 s++;
2858         }
2859
2860         IFNET_STAT_SET(ifp, collisions,
2861            (stats.dot3StatsSingleCollisionFrames +
2862            stats.dot3StatsMultipleCollisionFrames +
2863            stats.dot3StatsExcessiveCollisions +
2864            stats.dot3StatsLateCollisions));
2865 }
2866
2867 /*
2868  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2869  * pointers to descriptors.
2870  */
2871 static int
2872 bnx_encap(struct bnx_tx_ring *txr, struct mbuf **m_head0, uint32_t *txidx,
2873     int *segs_used)
2874 {
2875         struct bge_tx_bd *d = NULL;
2876         uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
2877         bus_dma_segment_t segs[BNX_NSEG_NEW];
2878         bus_dmamap_t map;
2879         int error, maxsegs, nsegs, idx, i;
2880         struct mbuf *m_head = *m_head0, *m_new;
2881
2882         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2883 #ifdef BNX_TSO_DEBUG
2884                 int tso_nsegs;
2885 #endif
2886
2887                 error = bnx_setup_tso(txr, m_head0, &mss, &csum_flags);
2888                 if (error)
2889                         return error;
2890                 m_head = *m_head0;
2891
2892 #ifdef BNX_TSO_DEBUG
2893                 tso_nsegs = (m_head->m_pkthdr.len /
2894                     m_head->m_pkthdr.tso_segsz) - 1;
2895                 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
2896                         tso_nsegs = BNX_TSO_NSTATS - 1;
2897                 else if (tso_nsegs < 0)
2898                         tso_nsegs = 0;
2899                 txr->bnx_sc->bnx_tsosegs[tso_nsegs]++;
2900 #endif
2901         } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
2902                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2903                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2904                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2905                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2906                 if (m_head->m_flags & M_LASTFRAG)
2907                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2908                 else if (m_head->m_flags & M_FRAG)
2909                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2910         }
2911         if (m_head->m_flags & M_VLANTAG) {
2912                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
2913                 vlan_tag = m_head->m_pkthdr.ether_vlantag;
2914         }
2915
2916         idx = *txidx;
2917         map = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
2918
2919         maxsegs = (BGE_TX_RING_CNT - txr->bnx_tx_cnt) - BNX_NSEG_RSVD;
2920         KASSERT(maxsegs >= BNX_NSEG_SPARE,
2921                 ("not enough segments %d", maxsegs));
2922
2923         if (maxsegs > BNX_NSEG_NEW)
2924                 maxsegs = BNX_NSEG_NEW;
2925
2926         /*
2927          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
2928          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
2929          * but when such padded frames employ the bge IP/TCP checksum
2930          * offload, the hardware checksum assist gives incorrect results
2931          * (possibly from incorporating its own padding into the UDP/TCP
2932          * checksum; who knows).  If we pad such runts with zeros, the
2933          * onboard checksum comes out correct.
2934          */
2935         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2936             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
2937                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
2938                 if (error)
2939                         goto back;
2940         }
2941
2942         if ((txr->bnx_tx_flags & BNX_TX_FLAG_SHORTDMA) &&
2943             m_head->m_next != NULL) {
2944                 m_new = bnx_defrag_shortdma(m_head);
2945                 if (m_new == NULL) {
2946                         error = ENOBUFS;
2947                         goto back;
2948                 }
2949                 *m_head0 = m_head = m_new;
2950         }
2951         if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
2952             (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG) &&
2953             m_head->m_next != NULL) {
2954                 /*
2955                  * Forcefully defragment mbuf chain to overcome hardware
2956                  * limitation which only support a single outstanding
2957                  * DMA read operation.  If it fails, keep moving on using
2958                  * the original mbuf chain.
2959                  */
2960                 m_new = m_defrag(m_head, MB_DONTWAIT);
2961                 if (m_new != NULL)
2962                         *m_head0 = m_head = m_new;
2963         }
2964
2965         error = bus_dmamap_load_mbuf_defrag(txr->bnx_tx_mtag, map,
2966             m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2967         if (error)
2968                 goto back;
2969         *segs_used += nsegs;
2970
2971         m_head = *m_head0;
2972         bus_dmamap_sync(txr->bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2973
2974         for (i = 0; ; i++) {
2975                 d = &txr->bnx_tx_ring[idx];
2976
2977                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2978                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2979                 d->bge_len = segs[i].ds_len;
2980                 d->bge_flags = csum_flags;
2981                 d->bge_vlan_tag = vlan_tag;
2982                 d->bge_mss = mss;
2983
2984                 if (i == nsegs - 1)
2985                         break;
2986                 BNX_INC(idx, BGE_TX_RING_CNT);
2987         }
2988         /* Mark the last segment as end of packet... */
2989         d->bge_flags |= BGE_TXBDFLAG_END;
2990
2991         /*
2992          * Insure that the map for this transmission is placed at
2993          * the array index of the last descriptor in this chain.
2994          */
2995         txr->bnx_tx_buf[*txidx].bnx_tx_dmamap = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
2996         txr->bnx_tx_buf[idx].bnx_tx_dmamap = map;
2997         txr->bnx_tx_buf[idx].bnx_tx_mbuf = m_head;
2998         txr->bnx_tx_cnt += nsegs;
2999
3000         BNX_INC(idx, BGE_TX_RING_CNT);
3001         *txidx = idx;
3002 back:
3003         if (error) {
3004                 m_freem(*m_head0);
3005                 *m_head0 = NULL;
3006         }
3007         return error;
3008 }
3009
3010 /*
3011  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3012  * to the mbuf data regions directly in the transmit descriptors.
3013  */
3014 static void
3015 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3016 {
3017         struct bnx_tx_ring *txr = ifsq_get_priv(ifsq);
3018         struct mbuf *m_head = NULL;
3019         uint32_t prodidx;
3020         int nsegs = 0;
3021
3022         KKASSERT(txr->bnx_ifsq == ifsq);
3023         ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
3024
3025         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3026                 return;
3027
3028         prodidx = txr->bnx_tx_prodidx;
3029
3030         while (txr->bnx_tx_buf[prodidx].bnx_tx_mbuf == NULL) {
3031                 /*
3032                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3033                  * descriptors of the end of the ring.  Also make
3034                  * sure there are BGE_NSEG_SPARE descriptors for
3035                  * jumbo buffers' or TSO segments' defragmentation.
3036                  */
3037                 if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) <
3038                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
3039                         ifsq_set_oactive(ifsq);
3040                         break;
3041                 }
3042
3043                 m_head = ifsq_dequeue(ifsq, NULL);
3044                 if (m_head == NULL)
3045                         break;
3046
3047                 /*
3048                  * Pack the data into the transmit ring. If we
3049                  * don't have room, set the OACTIVE flag and wait
3050                  * for the NIC to drain the ring.
3051                  */
3052                 if (bnx_encap(txr, &m_head, &prodidx, &nsegs)) {
3053                         ifsq_set_oactive(ifsq);
3054                         IFNET_STAT_INC(ifp, oerrors, 1);
3055                         break;
3056                 }
3057
3058                 if (nsegs >= txr->bnx_tx_wreg) {
3059                         /* Transmit */
3060                         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
3061                         nsegs = 0;
3062                 }
3063
3064                 ETHER_BPF_MTAP(ifp, m_head);
3065
3066                 /*
3067                  * Set a timeout in case the chip goes out to lunch.
3068                  */
3069                 txr->bnx_tx_watchdog.wd_timer = 5;
3070         }
3071
3072         if (nsegs > 0) {
3073                 /* Transmit */
3074                 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
3075         }
3076         txr->bnx_tx_prodidx = prodidx;
3077 }
3078
3079 static void
3080 bnx_init(void *xsc)
3081 {
3082         struct bnx_softc *sc = xsc;
3083         struct ifnet *ifp = &sc->arpcom.ac_if;
3084         uint16_t *m;
3085         uint32_t mode;
3086         int i;
3087
3088         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3089
3090         /* Cancel pending I/O and flush buffers. */
3091         bnx_stop(sc);
3092         bnx_reset(sc);
3093         bnx_chipinit(sc);
3094
3095         /*
3096          * Init the various state machines, ring
3097          * control blocks and firmware.
3098          */
3099         if (bnx_blockinit(sc)) {
3100                 if_printf(ifp, "initialization failure\n");
3101                 bnx_stop(sc);
3102                 return;
3103         }
3104
3105         /* Specify MTU. */
3106         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3107             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3108
3109         /* Load our MAC address. */
3110         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3111         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3112         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3113
3114         /* Enable or disable promiscuous mode as needed. */
3115         bnx_setpromisc(sc);
3116
3117         /* Program multicast filter. */
3118         bnx_setmulti(sc);
3119
3120         /* Init RX ring. */
3121         if (bnx_init_rx_ring_std(&sc->bnx_rx_std_ring)) {
3122                 if_printf(ifp, "RX ring initialization failed\n");
3123                 bnx_stop(sc);
3124                 return;
3125         }
3126
3127         /* Init jumbo RX ring. */
3128         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3129                 if (bnx_init_rx_ring_jumbo(sc)) {
3130                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3131                         bnx_stop(sc);
3132                         return;
3133                 }
3134         }
3135
3136         /* Init our RX return ring index */
3137         for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3138                 sc->bnx_rx_ret_ring[i].bnx_rx_saved_considx = 0;
3139
3140         /* Init TX ring. */
3141         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3142                 bnx_init_tx_ring(&sc->bnx_tx_ring[i]);
3143
3144         /* Enable TX MAC state machine lockup fix. */
3145         mode = CSR_READ_4(sc, BGE_TX_MODE);
3146         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3147         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
3148             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
3149                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3150                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3151                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3152         }
3153         /* Turn on transmitter */
3154         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3155
3156         /* Turn on receiver */
3157         BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3158
3159         /*
3160          * Set the number of good frames to receive after RX MBUF
3161          * Low Watermark has been reached.  After the RX MAC receives
3162          * this number of frames, it will drop subsequent incoming
3163          * frames until the MBUF High Watermark is reached.
3164          */
3165         if (BNX_IS_57765_FAMILY(sc))
3166                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3167         else
3168                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3169
3170         if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI) {
3171                 if (bootverbose) {
3172                         if_printf(ifp, "MSI_MODE: %#x\n",
3173                             CSR_READ_4(sc, BGE_MSI_MODE));
3174                 }
3175         }
3176
3177         /* Tell firmware we're alive. */
3178         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3179
3180         /* Enable host interrupts if polling(4) is not enabled. */
3181         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3182 #ifdef IFPOLL_ENABLE
3183         if (ifp->if_flags & IFF_NPOLLING)
3184                 bnx_disable_intr(sc);
3185         else
3186 #endif
3187         bnx_enable_intr(sc);
3188
3189         bnx_ifmedia_upd(ifp);
3190
3191         ifp->if_flags |= IFF_RUNNING;
3192         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3193                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3194
3195                 ifsq_clr_oactive(txr->bnx_ifsq);
3196                 ifsq_watchdog_start(&txr->bnx_tx_watchdog);
3197         }
3198
3199         callout_reset_bycpu(&sc->bnx_stat_timer, hz, bnx_tick, sc,
3200             sc->bnx_stat_cpuid);
3201 }
3202
3203 /*
3204  * Set media options.
3205  */
3206 static int
3207 bnx_ifmedia_upd(struct ifnet *ifp)
3208 {
3209         struct bnx_softc *sc = ifp->if_softc;
3210
3211         /* If this is a 1000baseX NIC, enable the TBI port. */
3212         if (sc->bnx_flags & BNX_FLAG_TBI) {
3213                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3214
3215                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3216                         return(EINVAL);
3217
3218                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3219                 case IFM_AUTO:
3220                         break;
3221
3222                 case IFM_1000_SX:
3223                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3224                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3225                                     BGE_MACMODE_HALF_DUPLEX);
3226                         } else {
3227                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3228                                     BGE_MACMODE_HALF_DUPLEX);
3229                         }
3230                         break;
3231                 default:
3232                         return(EINVAL);
3233                 }
3234         } else {
3235                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3236
3237                 sc->bnx_link_evt++;
3238                 sc->bnx_link = 0;
3239                 if (mii->mii_instance) {
3240                         struct mii_softc *miisc;
3241
3242                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3243                                 mii_phy_reset(miisc);
3244                 }
3245                 mii_mediachg(mii);
3246
3247                 /*
3248                  * Force an interrupt so that we will call bnx_link_upd
3249                  * if needed and clear any pending link state attention.
3250                  * Without this we are not getting any further interrupts
3251                  * for link state changes and thus will not UP the link and
3252                  * not be able to send in bnx_start.  The only way to get
3253                  * things working was to receive a packet and get an RX
3254                  * intr.
3255                  *
3256                  * bnx_tick should help for fiber cards and we might not
3257                  * need to do this here if BNX_FLAG_TBI is set but as
3258                  * we poll for fiber anyway it should not harm.
3259                  */
3260                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3261         }
3262         return(0);
3263 }
3264
3265 /*
3266  * Report current media status.
3267  */
3268 static void
3269 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3270 {
3271         struct bnx_softc *sc = ifp->if_softc;
3272
3273         if (sc->bnx_flags & BNX_FLAG_TBI) {
3274                 ifmr->ifm_status = IFM_AVALID;
3275                 ifmr->ifm_active = IFM_ETHER;
3276                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3277                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3278                         ifmr->ifm_status |= IFM_ACTIVE;
3279                 } else {
3280                         ifmr->ifm_active |= IFM_NONE;
3281                         return;
3282                 }
3283
3284                 ifmr->ifm_active |= IFM_1000_SX;
3285                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3286                         ifmr->ifm_active |= IFM_HDX;
3287                 else
3288                         ifmr->ifm_active |= IFM_FDX;
3289         } else {
3290                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3291
3292                 mii_pollstat(mii);
3293                 ifmr->ifm_active = mii->mii_media_active;
3294                 ifmr->ifm_status = mii->mii_media_status;
3295         }
3296 }
3297
3298 static int
3299 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3300 {
3301         struct bnx_softc *sc = ifp->if_softc;
3302         struct ifreq *ifr = (struct ifreq *)data;
3303         int mask, error = 0;
3304
3305         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3306
3307         switch (command) {
3308         case SIOCSIFMTU:
3309                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3310                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3311                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3312                         error = EINVAL;
3313                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3314                         ifp->if_mtu = ifr->ifr_mtu;
3315                         if (ifp->if_flags & IFF_RUNNING)
3316                                 bnx_init(sc);
3317                 }
3318                 break;
3319         case SIOCSIFFLAGS:
3320                 if (ifp->if_flags & IFF_UP) {
3321                         if (ifp->if_flags & IFF_RUNNING) {
3322                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3323
3324                                 /*
3325                                  * If only the state of the PROMISC flag
3326                                  * changed, then just use the 'set promisc
3327                                  * mode' command instead of reinitializing
3328                                  * the entire NIC. Doing a full re-init
3329                                  * means reloading the firmware and waiting
3330                                  * for it to start up, which may take a
3331                                  * second or two.  Similarly for ALLMULTI.
3332                                  */
3333                                 if (mask & IFF_PROMISC)
3334                                         bnx_setpromisc(sc);
3335                                 if (mask & IFF_ALLMULTI)
3336                                         bnx_setmulti(sc);
3337                         } else {
3338                                 bnx_init(sc);
3339                         }
3340                 } else if (ifp->if_flags & IFF_RUNNING) {
3341                         bnx_stop(sc);
3342                 }
3343                 sc->bnx_if_flags = ifp->if_flags;
3344                 break;
3345         case SIOCADDMULTI:
3346         case SIOCDELMULTI:
3347                 if (ifp->if_flags & IFF_RUNNING)
3348                         bnx_setmulti(sc);
3349                 break;
3350         case SIOCSIFMEDIA:
3351         case SIOCGIFMEDIA:
3352                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3353                         error = ifmedia_ioctl(ifp, ifr,
3354                             &sc->bnx_ifmedia, command);
3355                 } else {
3356                         struct mii_data *mii;
3357
3358                         mii = device_get_softc(sc->bnx_miibus);
3359                         error = ifmedia_ioctl(ifp, ifr,
3360                                               &mii->mii_media, command);
3361                 }
3362                 break;
3363         case SIOCSIFCAP:
3364                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3365                 if (mask & IFCAP_HWCSUM) {
3366                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3367                         if (ifp->if_capenable & IFCAP_TXCSUM)
3368                                 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3369                         else
3370                                 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3371                 }
3372                 if (mask & IFCAP_TSO) {
3373                         ifp->if_capenable ^= (mask & IFCAP_TSO);
3374                         if (ifp->if_capenable & IFCAP_TSO)
3375                                 ifp->if_hwassist |= CSUM_TSO;
3376                         else
3377                                 ifp->if_hwassist &= ~CSUM_TSO;
3378                 }
3379                 break;
3380         default:
3381                 error = ether_ioctl(ifp, command, data);
3382                 break;
3383         }
3384         return error;
3385 }
3386
3387 static void
3388 bnx_watchdog(struct ifaltq_subque *ifsq)
3389 {
3390         struct ifnet *ifp = ifsq_get_ifp(ifsq);
3391         struct bnx_softc *sc = ifp->if_softc;
3392         int i;
3393
3394         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3395
3396         if_printf(ifp, "watchdog timeout -- resetting\n");
3397
3398         bnx_init(sc);
3399
3400         IFNET_STAT_INC(ifp, oerrors, 1);
3401
3402         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3403                 ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq);
3404 }
3405
3406 /*
3407  * Stop the adapter and free any mbufs allocated to the
3408  * RX and TX lists.
3409  */
3410 static void
3411 bnx_stop(struct bnx_softc *sc)
3412 {
3413         struct ifnet *ifp = &sc->arpcom.ac_if;
3414         int i;
3415
3416         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3417
3418         callout_stop(&sc->bnx_stat_timer);
3419
3420         /*
3421          * Disable all of the receiver blocks
3422          */
3423         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3424         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3425         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3426         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3427         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3428         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3429
3430         /*
3431          * Disable all of the transmit blocks
3432          */
3433         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3434         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3435         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3436         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3437         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3438         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3439
3440         /*
3441          * Shut down all of the memory managers and related
3442          * state machines.
3443          */
3444         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3445         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3446         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3447         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3448
3449         /* Disable host interrupts. */
3450         bnx_disable_intr(sc);
3451
3452         /*
3453          * Tell firmware we're shutting down.
3454          */
3455         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3456
3457         /* Free the RX lists. */
3458         bnx_free_rx_ring_std(&sc->bnx_rx_std_ring);
3459
3460         /* Free jumbo RX list. */
3461         if (BNX_IS_JUMBO_CAPABLE(sc))
3462                 bnx_free_rx_ring_jumbo(sc);
3463
3464         /* Free TX buffers. */
3465         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3466                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3467
3468                 txr->bnx_saved_status_tag = 0;
3469                 bnx_free_tx_ring(txr);
3470         }
3471
3472         /* Clear saved status tag */
3473         for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3474                 sc->bnx_rx_ret_ring[i].bnx_saved_status_tag = 0;
3475
3476         sc->bnx_link = 0;
3477         sc->bnx_coal_chg = 0;
3478
3479         ifp->if_flags &= ~IFF_RUNNING;
3480         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3481                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3482
3483                 ifsq_clr_oactive(txr->bnx_ifsq);
3484                 ifsq_watchdog_stop(&txr->bnx_tx_watchdog);
3485         }
3486 }
3487
3488 /*
3489  * Stop all chip I/O so that the kernel's probe routines don't
3490  * get confused by errant DMAs when rebooting.
3491  */
3492 static void
3493 bnx_shutdown(device_t dev)
3494 {
3495         struct bnx_softc *sc = device_get_softc(dev);
3496         struct ifnet *ifp = &sc->arpcom.ac_if;
3497
3498         ifnet_serialize_all(ifp);
3499         bnx_stop(sc);
3500         bnx_reset(sc);
3501         ifnet_deserialize_all(ifp);
3502 }
3503
3504 static int
3505 bnx_suspend(device_t dev)
3506 {
3507         struct bnx_softc *sc = device_get_softc(dev);
3508         struct ifnet *ifp = &sc->arpcom.ac_if;
3509
3510         ifnet_serialize_all(ifp);
3511         bnx_stop(sc);
3512         ifnet_deserialize_all(ifp);
3513
3514         return 0;
3515 }
3516
3517 static int
3518 bnx_resume(device_t dev)
3519 {
3520         struct bnx_softc *sc = device_get_softc(dev);
3521         struct ifnet *ifp = &sc->arpcom.ac_if;
3522
3523         ifnet_serialize_all(ifp);
3524
3525         if (ifp->if_flags & IFF_UP) {
3526                 int i;
3527
3528                 bnx_init(sc);
3529                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3530                         ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq);
3531         }
3532
3533         ifnet_deserialize_all(ifp);
3534
3535         return 0;
3536 }
3537
3538 static void
3539 bnx_setpromisc(struct bnx_softc *sc)
3540 {
3541         struct ifnet *ifp = &sc->arpcom.ac_if;
3542
3543         if (ifp->if_flags & IFF_PROMISC)
3544                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3545         else
3546                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3547 }
3548
3549 static void
3550 bnx_dma_free(struct bnx_softc *sc)
3551 {
3552         struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
3553         int i;
3554
3555         /* Destroy RX return rings */
3556         if (sc->bnx_rx_ret_ring != NULL) {
3557                 for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3558                         bnx_destroy_rx_ret_ring(&sc->bnx_rx_ret_ring[i]);
3559                 kfree(sc->bnx_rx_ret_ring, M_DEVBUF);
3560         }
3561
3562         /* Destroy RX mbuf DMA stuffs. */
3563         if (std->bnx_rx_mtag != NULL) {
3564                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3565                         KKASSERT(std->bnx_rx_std_buf[i].bnx_rx_mbuf == NULL);
3566                         bus_dmamap_destroy(std->bnx_rx_mtag,
3567                             std->bnx_rx_std_buf[i].bnx_rx_dmamap);
3568                 }
3569                 bus_dma_tag_destroy(std->bnx_rx_mtag);
3570         }
3571
3572         /* Destroy standard RX ring */
3573         bnx_dma_block_free(std->bnx_rx_std_ring_tag,
3574             std->bnx_rx_std_ring_map, std->bnx_rx_std_ring);
3575
3576         /* Destroy TX rings */
3577         if (sc->bnx_tx_ring != NULL) {
3578                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3579                         bnx_destroy_tx_ring(&sc->bnx_tx_ring[i]);
3580                 kfree(sc->bnx_tx_ring, M_DEVBUF);
3581         }
3582
3583         if (BNX_IS_JUMBO_CAPABLE(sc))
3584                 bnx_free_jumbo_mem(sc);
3585
3586         /* Destroy status block */
3587         bnx_dma_block_free(sc->bnx_cdata.bnx_status_tag,
3588             sc->bnx_cdata.bnx_status_map,
3589             sc->bnx_ldata.bnx_status_block);
3590
3591         /* Destroy the parent tag */
3592         if (sc->bnx_cdata.bnx_parent_tag != NULL)
3593                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3594 }
3595
3596 static int
3597 bnx_dma_alloc(device_t dev)
3598 {
3599         struct bnx_softc *sc = device_get_softc(dev);
3600         struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
3601         int i, error, mbx;
3602
3603         /*
3604          * Allocate the parent bus DMA tag appropriate for PCI.
3605          *
3606          * All of the NetExtreme/NetLink controllers have 4GB boundary
3607          * DMA bug.
3608          * Whenever an address crosses a multiple of the 4GB boundary
3609          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3610          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3611          * state machine will lockup and cause the device to hang.
3612          */
3613         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3614             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3615             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3616             0, &sc->bnx_cdata.bnx_parent_tag);
3617         if (error) {
3618                 device_printf(dev, "could not create parent DMA tag\n");
3619                 return error;
3620         }
3621
3622         /*
3623          * Create DMA stuffs for status block.
3624          */
3625         error = bnx_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3626             &sc->bnx_cdata.bnx_status_tag,
3627             &sc->bnx_cdata.bnx_status_map,
3628             (void *)&sc->bnx_ldata.bnx_status_block,
3629             &sc->bnx_ldata.bnx_status_block_paddr);
3630         if (error) {
3631                 device_printf(dev, "could not create status block\n");
3632                 return error;
3633         }
3634
3635         /*
3636          * Create DMA tag and maps for RX mbufs.
3637          */
3638         std->bnx_sc = sc;
3639         lwkt_serialize_init(&std->bnx_rx_std_serialize);
3640         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3641             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3642             NULL, NULL, MCLBYTES, 1, MCLBYTES,
3643             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, &std->bnx_rx_mtag);
3644         if (error) {
3645                 device_printf(dev, "could not create RX mbuf DMA tag\n");
3646                 return error;
3647         }
3648
3649         for (i = 0; i < BGE_STD_RX_RING_CNT; ++i) {
3650                 error = bus_dmamap_create(std->bnx_rx_mtag, BUS_DMA_WAITOK,
3651                     &std->bnx_rx_std_buf[i].bnx_rx_dmamap);
3652                 if (error) {
3653                         int j;
3654
3655                         for (j = 0; j < i; ++j) {
3656                                 bus_dmamap_destroy(std->bnx_rx_mtag,
3657                                     std->bnx_rx_std_buf[j].bnx_rx_dmamap);
3658                         }
3659                         bus_dma_tag_destroy(std->bnx_rx_mtag);
3660                         std->bnx_rx_mtag = NULL;
3661
3662                         device_printf(dev,
3663                             "could not create %dth RX mbuf DMA map\n", i);
3664                         return error;
3665                 }
3666         }
3667
3668         /*
3669          * Create DMA stuffs for standard RX ring.
3670          */
3671         error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3672             &std->bnx_rx_std_ring_tag,
3673             &std->bnx_rx_std_ring_map,
3674             (void *)&std->bnx_rx_std_ring,
3675             &std->bnx_rx_std_ring_paddr);
3676         if (error) {
3677                 device_printf(dev, "could not create std RX ring\n");
3678                 return error;
3679         }
3680
3681         /*
3682          * Create RX return rings
3683          */
3684         sc->bnx_rx_ret_ring = kmalloc_cachealign(
3685             sizeof(struct bnx_rx_ret_ring) * sc->bnx_rx_retcnt, M_DEVBUF,
3686             M_WAITOK | M_ZERO);
3687         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
3688                 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
3689
3690                 ret->bnx_sc = sc;
3691                 ret->bnx_std = std;
3692
3693                 /* XXX */
3694                 ret->bnx_rx_considx =
3695                 &sc->bnx_ldata.bnx_status_block->bge_idx[0].bge_rx_prod_idx;
3696                 ret->bnx_hw_status_tag =
3697                 &sc->bnx_ldata.bnx_status_block->bge_status_tag;
3698
3699                 error = bnx_create_rx_ret_ring(ret);
3700                 if (error) {
3701                         device_printf(dev,
3702                             "could not create %dth RX ret ring\n", i);
3703                         return error;
3704                 }
3705         }
3706
3707         /*
3708          * Create TX rings
3709          */
3710         mbx = BGE_MBX_TX_HOST_PROD0_LO;
3711         sc->bnx_tx_ring = kmalloc_cachealign(
3712             sizeof(struct bnx_tx_ring) * sc->bnx_tx_ringcnt, M_DEVBUF,
3713             M_WAITOK | M_ZERO);
3714         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3715                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3716
3717                 txr->bnx_sc = sc;
3718                 txr->bnx_tx_mbx = mbx;
3719
3720                 if (mbx & 0x4)
3721                         mbx -= 0x4;
3722                 else
3723                         mbx += 0xc;
3724
3725                 /* XXX */
3726                 txr->bnx_tx_considx =
3727                 &sc->bnx_ldata.bnx_status_block->bge_idx[0].bge_tx_cons_idx;
3728
3729                 error = bnx_create_tx_ring(txr);
3730                 if (error) {
3731                         device_printf(dev,
3732                             "could not create %dth TX ring\n", i);
3733                         return error;
3734                 }
3735         }
3736
3737         /*
3738          * Create jumbo buffer pool.
3739          */
3740         if (BNX_IS_JUMBO_CAPABLE(sc)) {
3741                 error = bnx_alloc_jumbo_mem(sc);
3742                 if (error) {
3743                         device_printf(dev,
3744                             "could not create jumbo buffer pool\n");
3745                         return error;
3746                 }
3747         }
3748
3749         return 0;
3750 }
3751
3752 static int
3753 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3754                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3755 {
3756         bus_dmamem_t dmem;
3757         int error;
3758
3759         error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
3760                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3761                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3762         if (error)
3763                 return error;
3764
3765         *tag = dmem.dmem_tag;
3766         *map = dmem.dmem_map;
3767         *addr = dmem.dmem_addr;
3768         *paddr = dmem.dmem_busaddr;
3769
3770         return 0;
3771 }
3772
3773 static void
3774 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3775 {
3776         if (tag != NULL) {
3777                 bus_dmamap_unload(tag, map);
3778                 bus_dmamem_free(tag, addr, map);
3779                 bus_dma_tag_destroy(tag);
3780         }
3781 }
3782
3783 static void
3784 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
3785 {
3786         struct ifnet *ifp = &sc->arpcom.ac_if;
3787
3788 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3789
3790         /*
3791          * Sometimes PCS encoding errors are detected in
3792          * TBI mode (on fiber NICs), and for some reason
3793          * the chip will signal them as link changes.
3794          * If we get a link change event, but the 'PCS
3795          * encoding error' bit in the MAC status register
3796          * is set, don't bother doing a link check.
3797          * This avoids spurious "gigabit link up" messages
3798          * that sometimes appear on fiber NICs during
3799          * periods of heavy traffic.
3800          */
3801         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3802                 if (!sc->bnx_link) {
3803                         sc->bnx_link++;
3804                         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
3805                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3806                                     BGE_MACMODE_TBI_SEND_CFGS);
3807                         }
3808                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3809
3810                         if (bootverbose)
3811                                 if_printf(ifp, "link UP\n");
3812
3813                         ifp->if_link_state = LINK_STATE_UP;
3814                         if_link_state_change(ifp);
3815                 }
3816         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3817                 if (sc->bnx_link) {
3818                         sc->bnx_link = 0;
3819
3820                         if (bootverbose)
3821                                 if_printf(ifp, "link DOWN\n");
3822
3823                         ifp->if_link_state = LINK_STATE_DOWN;
3824                         if_link_state_change(ifp);
3825                 }
3826         }
3827
3828 #undef PCS_ENCODE_ERR
3829
3830         /* Clear the attention. */
3831         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3832             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3833             BGE_MACSTAT_LINK_CHANGED);
3834 }
3835
3836 static void
3837 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3838 {
3839         struct ifnet *ifp = &sc->arpcom.ac_if;
3840         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3841
3842         mii_pollstat(mii);
3843         bnx_miibus_statchg(sc->bnx_dev);
3844
3845         if (bootverbose) {
3846                 if (sc->bnx_link)
3847                         if_printf(ifp, "link UP\n");
3848                 else
3849                         if_printf(ifp, "link DOWN\n");
3850         }
3851
3852         /* Clear the attention. */
3853         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3854             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3855             BGE_MACSTAT_LINK_CHANGED);
3856 }
3857
3858 static void
3859 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3860 {
3861         struct ifnet *ifp = &sc->arpcom.ac_if;
3862         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3863
3864         mii_pollstat(mii);
3865
3866         if (!sc->bnx_link &&
3867             (mii->mii_media_status & IFM_ACTIVE) &&
3868             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3869                 sc->bnx_link++;
3870                 if (bootverbose)
3871                         if_printf(ifp, "link UP\n");
3872         } else if (sc->bnx_link &&
3873             (!(mii->mii_media_status & IFM_ACTIVE) ||
3874             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3875                 sc->bnx_link = 0;
3876                 if (bootverbose)
3877                         if_printf(ifp, "link DOWN\n");
3878         }
3879
3880         /* Clear the attention. */
3881         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3882             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3883             BGE_MACSTAT_LINK_CHANGED);
3884 }
3885
3886 static int
3887 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3888 {
3889         struct bnx_softc *sc = arg1;
3890
3891         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3892             &sc->bnx_rx_coal_ticks,
3893             BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
3894             BNX_RX_COAL_TICKS_CHG);
3895 }
3896
3897 static int
3898 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3899 {
3900         struct bnx_softc *sc = arg1;
3901
3902         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3903             &sc->bnx_tx_coal_ticks,
3904             BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
3905             BNX_TX_COAL_TICKS_CHG);
3906 }
3907
3908 static int
3909 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
3910 {
3911         struct bnx_softc *sc = arg1;
3912
3913         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3914             &sc->bnx_rx_coal_bds,
3915             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3916             BNX_RX_COAL_BDS_CHG);
3917 }
3918
3919 static int
3920 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
3921 {
3922         struct bnx_softc *sc = arg1;
3923
3924         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3925             &sc->bnx_tx_coal_bds,
3926             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3927             BNX_TX_COAL_BDS_CHG);
3928 }
3929
3930 static int
3931 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3932 {
3933         struct bnx_softc *sc = arg1;
3934
3935         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3936             &sc->bnx_rx_coal_bds_int,
3937             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3938             BNX_RX_COAL_BDS_INT_CHG);
3939 }
3940
3941 static int
3942 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3943 {
3944         struct bnx_softc *sc = arg1;
3945
3946         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3947             &sc->bnx_tx_coal_bds_int,
3948             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3949             BNX_TX_COAL_BDS_INT_CHG);
3950 }
3951
3952 static int
3953 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3954     int coal_min, int coal_max, uint32_t coal_chg_mask)
3955 {
3956         struct bnx_softc *sc = arg1;
3957         struct ifnet *ifp = &sc->arpcom.ac_if;
3958         int error = 0, v;
3959
3960         ifnet_serialize_all(ifp);
3961
3962         v = *coal;
3963         error = sysctl_handle_int(oidp, &v, 0, req);
3964         if (!error && req->newptr != NULL) {
3965                 if (v < coal_min || v > coal_max) {
3966                         error = EINVAL;
3967                 } else {
3968                         *coal = v;
3969                         sc->bnx_coal_chg |= coal_chg_mask;
3970
3971                         /* Commit changes */
3972                         bnx_coal_change(sc);
3973                 }
3974         }
3975
3976         ifnet_deserialize_all(ifp);
3977         return error;
3978 }
3979
3980 static void
3981 bnx_coal_change(struct bnx_softc *sc)
3982 {
3983         struct ifnet *ifp = &sc->arpcom.ac_if;
3984
3985         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3986
3987         if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
3988                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3989                             sc->bnx_rx_coal_ticks);
3990                 DELAY(10);
3991                 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3992
3993                 if (bootverbose) {
3994                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3995                                   sc->bnx_rx_coal_ticks);
3996                 }
3997         }
3998
3999         if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
4000                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
4001                             sc->bnx_tx_coal_ticks);
4002                 DELAY(10);
4003                 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
4004
4005                 if (bootverbose) {
4006                         if_printf(ifp, "tx_coal_ticks -> %u\n",
4007                                   sc->bnx_tx_coal_ticks);
4008                 }
4009         }
4010
4011         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
4012                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4013                             sc->bnx_rx_coal_bds);
4014                 DELAY(10);
4015                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
4016
4017                 if (bootverbose) {
4018                         if_printf(ifp, "rx_coal_bds -> %u\n",
4019                                   sc->bnx_rx_coal_bds);
4020                 }
4021         }
4022
4023         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
4024                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
4025                             sc->bnx_tx_coal_bds);
4026                 DELAY(10);
4027                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
4028
4029                 if (bootverbose) {
4030                         if_printf(ifp, "tx_coal_bds -> %u\n",
4031                                   sc->bnx_tx_coal_bds);
4032                 }
4033         }
4034
4035         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
4036                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
4037                     sc->bnx_rx_coal_bds_int);
4038                 DELAY(10);
4039                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
4040
4041                 if (bootverbose) {
4042                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
4043                             sc->bnx_rx_coal_bds_int);
4044                 }
4045         }
4046
4047         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
4048                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
4049                     sc->bnx_tx_coal_bds_int);
4050                 DELAY(10);
4051                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
4052
4053                 if (bootverbose) {
4054                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
4055                             sc->bnx_tx_coal_bds_int);
4056                 }
4057         }
4058
4059         sc->bnx_coal_chg = 0;
4060 }
4061
4062 static void
4063 bnx_check_intr(void *xintr)
4064 {
4065         struct bnx_intr_data *intr = xintr;
4066         struct bnx_rx_ret_ring *ret;
4067         struct bnx_tx_ring *txr;
4068         struct ifnet *ifp;
4069
4070         lwkt_serialize_enter(intr->bnx_intr_serialize);
4071
4072         KKASSERT(mycpuid == intr->bnx_intr_cpuid);
4073
4074         ifp = &intr->bnx_sc->arpcom.ac_if;
4075         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4076                 lwkt_serialize_exit(intr->bnx_intr_serialize);
4077                 return;
4078         }
4079
4080         txr = intr->bnx_txr;
4081         ret = intr->bnx_ret;
4082
4083         if (*ret->bnx_rx_considx != ret->bnx_rx_saved_considx ||
4084             *txr->bnx_tx_considx != txr->bnx_tx_saved_considx) {
4085                 if (intr->bnx_rx_check_considx == ret->bnx_rx_saved_considx &&
4086                     intr->bnx_tx_check_considx == txr->bnx_tx_saved_considx) {
4087                         if (!intr->bnx_intr_maylose) {
4088                                 intr->bnx_intr_maylose = TRUE;
4089                                 goto done;
4090                         }
4091                         if (bootverbose)
4092                                 if_printf(ifp, "lost interrupt\n");
4093                         intr->bnx_intr_func(intr->bnx_intr_arg);
4094                 }
4095         }
4096         intr->bnx_intr_maylose = FALSE;
4097         intr->bnx_rx_check_considx = ret->bnx_rx_saved_considx;
4098         intr->bnx_tx_check_considx = txr->bnx_tx_saved_considx;
4099
4100 done:
4101         callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL,
4102             intr->bnx_intr_check, intr);
4103         lwkt_serialize_exit(intr->bnx_intr_serialize);
4104 }
4105
4106 static void
4107 bnx_enable_intr(struct bnx_softc *sc)
4108 {
4109         struct ifnet *ifp = &sc->arpcom.ac_if;
4110         struct bnx_intr_data *intr;
4111         int i;
4112
4113         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4114                 lwkt_serialize_handler_enable(
4115                     sc->bnx_intr_data[i].bnx_intr_serialize);
4116         }
4117
4118         /*
4119          * Enable interrupt.
4120          */
4121         intr = &sc->bnx_intr_data[0]; /* XXX */
4122         bnx_writembx(sc, BGE_MBX_IRQ0_LO, (*intr->bnx_saved_status_tag) << 24);
4123         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4124                 /* XXX Linux driver */
4125                 bnx_writembx(sc, BGE_MBX_IRQ0_LO,
4126                     (*intr->bnx_saved_status_tag) << 24);
4127         }
4128
4129         /*
4130          * Unmask the interrupt when we stop polling.
4131          */
4132         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4133             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4134
4135         /*
4136          * Trigger another interrupt, since above writing
4137          * to interrupt mailbox0 may acknowledge pending
4138          * interrupt.
4139          */
4140         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4141
4142         if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) {
4143                 if (bootverbose)
4144                         if_printf(ifp, "status tag bug workaround\n");
4145
4146                 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4147                         intr = &sc->bnx_intr_data[i];
4148                         intr->bnx_intr_maylose = FALSE;
4149                         intr->bnx_rx_check_considx = 0;
4150                         intr->bnx_tx_check_considx = 0;
4151                         callout_reset_bycpu(&intr->bnx_intr_timer,
4152                             BNX_INTR_CKINTVL, intr->bnx_intr_check, intr,
4153                             intr->bnx_intr_cpuid);
4154                 }
4155         }
4156 }
4157
4158 static void
4159 bnx_disable_intr(struct bnx_softc *sc)
4160 {
4161         int i;
4162
4163         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4164                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4165
4166                 callout_stop(&intr->bnx_intr_timer);
4167                 intr->bnx_intr_maylose = FALSE;
4168                 intr->bnx_rx_check_considx = 0;
4169                 intr->bnx_tx_check_considx = 0;
4170         }
4171
4172         /*
4173          * Mask the interrupt when we start polling.
4174          */
4175         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4176             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4177
4178         /*
4179          * Acknowledge possible asserted interrupt.
4180          */
4181         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4182
4183         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4184                 lwkt_serialize_handler_disable(
4185                     sc->bnx_intr_data[i].bnx_intr_serialize);
4186         }
4187 }
4188
4189 static int
4190 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
4191 {
4192         uint32_t mac_addr;
4193         int ret = 1;
4194
4195         mac_addr = bnx_readmem_ind(sc, 0x0c14);
4196         if ((mac_addr >> 16) == 0x484b) {
4197                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4198                 ether_addr[1] = (uint8_t)mac_addr;
4199                 mac_addr = bnx_readmem_ind(sc, 0x0c18);
4200                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4201                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4202                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4203                 ether_addr[5] = (uint8_t)mac_addr;
4204                 ret = 0;
4205         }
4206         return ret;
4207 }
4208
4209 static int
4210 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
4211 {
4212         int mac_offset = BGE_EE_MAC_OFFSET;
4213
4214         if (BNX_IS_5717_PLUS(sc)) {
4215                 int f;
4216
4217                 f = pci_get_function(sc->bnx_dev);
4218                 if (f & 1)
4219                         mac_offset = BGE_EE_MAC_OFFSET_5717;
4220                 if (f > 1)
4221                         mac_offset += BGE_EE_MAC_OFFSET_5717_OFF;
4222         }
4223
4224         return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4225 }
4226
4227 static int
4228 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[])
4229 {
4230         if (sc->bnx_flags & BNX_FLAG_NO_EEPROM)
4231                 return 1;
4232
4233         return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4234                                ETHER_ADDR_LEN);
4235 }
4236
4237 static int
4238 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[])
4239 {
4240         static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = {
4241                 /* NOTE: Order is critical */
4242                 bnx_get_eaddr_mem,
4243                 bnx_get_eaddr_nvram,
4244                 bnx_get_eaddr_eeprom,
4245                 NULL
4246         };
4247         const bnx_eaddr_fcn_t *func;
4248
4249         for (func = bnx_eaddr_funcs; *func != NULL; ++func) {
4250                 if ((*func)(sc, eaddr) == 0)
4251                         break;
4252         }
4253         return (*func == NULL ? ENXIO : 0);
4254 }
4255
4256 /*
4257  * NOTE: 'm' is not freed upon failure
4258  */
4259 struct mbuf *
4260 bnx_defrag_shortdma(struct mbuf *m)
4261 {
4262         struct mbuf *n;
4263         int found;
4264
4265         /*
4266          * If device receive two back-to-back send BDs with less than
4267          * or equal to 8 total bytes then the device may hang.  The two
4268          * back-to-back send BDs must in the same frame for this failure
4269          * to occur.  Scan mbuf chains and see whether two back-to-back
4270          * send BDs are there.  If this is the case, allocate new mbuf
4271          * and copy the frame to workaround the silicon bug.
4272          */
4273         for (n = m, found = 0; n != NULL; n = n->m_next) {
4274                 if (n->m_len < 8) {
4275                         found++;
4276                         if (found > 1)
4277                                 break;
4278                         continue;
4279                 }
4280                 found = 0;
4281         }
4282
4283         if (found > 1)
4284                 n = m_defrag(m, MB_DONTWAIT);
4285         else
4286                 n = m;
4287         return n;
4288 }
4289
4290 static void
4291 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)
4292 {
4293         int i;
4294
4295         BNX_CLRBIT(sc, reg, bit);
4296         for (i = 0; i < BNX_TIMEOUT; i++) {
4297                 if ((CSR_READ_4(sc, reg) & bit) == 0)
4298                         return;
4299                 DELAY(100);
4300         }
4301 }
4302
4303 static void
4304 bnx_link_poll(struct bnx_softc *sc)
4305 {
4306         uint32_t status;
4307
4308         status = CSR_READ_4(sc, BGE_MAC_STS);
4309         if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) {
4310                 sc->bnx_link_evt = 0;
4311                 sc->bnx_link_upd(sc, status);
4312         }
4313 }
4314
4315 static void
4316 bnx_enable_msi(struct bnx_softc *sc)
4317 {
4318         uint32_t msi_mode;
4319
4320         msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4321         msi_mode |= BGE_MSIMODE_ENABLE;
4322         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4323                 /*
4324                  * NOTE:
4325                  * 5718-PG105-R says that "one shot" mode
4326                  * does not work if MSI is used, however,
4327                  * it obviously works.
4328                  */
4329                 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4330         }
4331         CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4332 }
4333
4334 static uint32_t
4335 bnx_dma_swap_options(struct bnx_softc *sc)
4336 {
4337         uint32_t dma_options;
4338
4339         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
4340             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
4341 #if BYTE_ORDER == BIG_ENDIAN
4342         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
4343 #endif
4344         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
4345             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
4346                 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
4347                     BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
4348                     BGE_MODECTL_HTX2B_ENABLE;
4349         }
4350         return dma_options;
4351 }
4352
4353 static int
4354 bnx_setup_tso(struct bnx_tx_ring *txr, struct mbuf **mp,
4355     uint16_t *mss0, uint16_t *flags0)
4356 {
4357         struct mbuf *m;
4358         struct ip *ip;
4359         struct tcphdr *th;
4360         int thoff, iphlen, hoff, hlen;
4361         uint16_t flags, mss;
4362
4363         m = *mp;
4364         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4365
4366         hoff = m->m_pkthdr.csum_lhlen;
4367         iphlen = m->m_pkthdr.csum_iphlen;
4368         thoff = m->m_pkthdr.csum_thlen;
4369
4370         KASSERT(hoff > 0, ("invalid ether header len"));
4371         KASSERT(iphlen > 0, ("invalid ip header len"));
4372         KASSERT(thoff > 0, ("invalid tcp header len"));
4373
4374         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4375                 m = m_pullup(m, hoff + iphlen + thoff);
4376                 if (m == NULL) {
4377                         *mp = NULL;
4378                         return ENOBUFS;
4379                 }
4380                 *mp = m;
4381         }
4382         ip = mtodoff(m, struct ip *, hoff);
4383         th = mtodoff(m, struct tcphdr *, hoff + iphlen);
4384
4385         mss = m->m_pkthdr.tso_segsz;
4386         flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
4387
4388         ip->ip_len = htons(mss + iphlen + thoff);
4389         th->th_sum = 0;
4390
4391         hlen = (iphlen + thoff) >> 2;
4392         mss |= ((hlen & 0x3) << 14);
4393         flags |= ((hlen & 0xf8) << 7) | ((hlen & 0x4) << 2);
4394
4395         *mss0 = mss;
4396         *flags0 = flags;
4397
4398         return 0;
4399 }
4400
4401 static int
4402 bnx_create_tx_ring(struct bnx_tx_ring *txr)
4403 {
4404         bus_size_t txmaxsz, txmaxsegsz;
4405         int i, error;
4406
4407         lwkt_serialize_init(&txr->bnx_tx_serialize);
4408
4409         /*
4410          * Create DMA tag and maps for TX mbufs.
4411          */
4412         if (txr->bnx_sc->bnx_flags & BNX_FLAG_TSO)
4413                 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
4414         else
4415                 txmaxsz = BNX_JUMBO_FRAMELEN;
4416         if (txr->bnx_sc->bnx_asicrev == BGE_ASICREV_BCM57766)
4417                 txmaxsegsz = MCLBYTES;
4418         else
4419                 txmaxsegsz = PAGE_SIZE;
4420         error = bus_dma_tag_create(txr->bnx_sc->bnx_cdata.bnx_parent_tag,
4421             1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
4422             txmaxsz, BNX_NSEG_NEW, txmaxsegsz,
4423             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
4424             &txr->bnx_tx_mtag);
4425         if (error) {
4426                 device_printf(txr->bnx_sc->bnx_dev,
4427                     "could not create TX mbuf DMA tag\n");
4428                 return error;
4429         }
4430
4431         for (i = 0; i < BGE_TX_RING_CNT; i++) {
4432                 error = bus_dmamap_create(txr->bnx_tx_mtag,
4433                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
4434                     &txr->bnx_tx_buf[i].bnx_tx_dmamap);
4435                 if (error) {
4436                         int j;
4437
4438                         for (j = 0; j < i; ++j) {
4439                                 bus_dmamap_destroy(txr->bnx_tx_mtag,
4440                                     txr->bnx_tx_buf[j].bnx_tx_dmamap);
4441                         }
4442                         bus_dma_tag_destroy(txr->bnx_tx_mtag);
4443                         txr->bnx_tx_mtag = NULL;
4444
4445                         device_printf(txr->bnx_sc->bnx_dev,
4446                             "could not create TX mbuf DMA map\n");
4447                         return error;
4448                 }
4449         }
4450
4451         /*
4452          * Create DMA stuffs for TX ring.
4453          */
4454         error = bnx_dma_block_alloc(txr->bnx_sc, BGE_TX_RING_SZ,
4455             &txr->bnx_tx_ring_tag,
4456             &txr->bnx_tx_ring_map,
4457             (void *)&txr->bnx_tx_ring,
4458             &txr->bnx_tx_ring_paddr);
4459         if (error) {
4460                 device_printf(txr->bnx_sc->bnx_dev,
4461                     "could not create TX ring\n");
4462                 return error;
4463         }
4464
4465         txr->bnx_tx_flags |= BNX_TX_FLAG_SHORTDMA;
4466         txr->bnx_tx_wreg = BNX_TX_WREG_NSEGS;
4467
4468         return 0;
4469 }
4470
4471 static void
4472 bnx_destroy_tx_ring(struct bnx_tx_ring *txr)
4473 {
4474         /* Destroy TX mbuf DMA stuffs. */
4475         if (txr->bnx_tx_mtag != NULL) {
4476                 int i;
4477
4478                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
4479                         KKASSERT(txr->bnx_tx_buf[i].bnx_tx_mbuf == NULL);
4480                         bus_dmamap_destroy(txr->bnx_tx_mtag,
4481                             txr->bnx_tx_buf[i].bnx_tx_dmamap);
4482                 }
4483                 bus_dma_tag_destroy(txr->bnx_tx_mtag);
4484         }
4485
4486         /* Destroy TX ring */
4487         bnx_dma_block_free(txr->bnx_tx_ring_tag,
4488             txr->bnx_tx_ring_map, txr->bnx_tx_ring);
4489 }
4490
4491 static int
4492 bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS)
4493 {
4494         struct bnx_softc *sc = (void *)arg1;
4495         struct ifnet *ifp = &sc->arpcom.ac_if;
4496         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
4497         int error, defrag, i;
4498
4499         if (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG)
4500                 defrag = 1;
4501         else
4502                 defrag = 0;
4503
4504         error = sysctl_handle_int(oidp, &defrag, 0, req);
4505         if (error || req->newptr == NULL)
4506                 return error;
4507
4508         ifnet_serialize_all(ifp);
4509         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4510                 txr = &sc->bnx_tx_ring[i];
4511                 if (defrag)
4512                         txr->bnx_tx_flags |= BNX_TX_FLAG_FORCE_DEFRAG;
4513                 else
4514                         txr->bnx_tx_flags &= ~BNX_TX_FLAG_FORCE_DEFRAG;
4515         }
4516         ifnet_deserialize_all(ifp);
4517
4518         return 0;
4519 }
4520
4521 static int
4522 bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS)
4523 {
4524         struct bnx_softc *sc = (void *)arg1;
4525         struct ifnet *ifp = &sc->arpcom.ac_if;
4526         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
4527         int error, tx_wreg, i;
4528
4529         tx_wreg = txr->bnx_tx_wreg;
4530         error = sysctl_handle_int(oidp, &tx_wreg, 0, req);
4531         if (error || req->newptr == NULL)
4532                 return error;
4533
4534         ifnet_serialize_all(ifp);
4535         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
4536                 sc->bnx_tx_ring[i].bnx_tx_wreg = tx_wreg;
4537         ifnet_deserialize_all(ifp);
4538
4539         return 0;
4540 }
4541
4542 static int
4543 bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *ret)
4544 {
4545         int error;
4546
4547         lwkt_serialize_init(&ret->bnx_rx_ret_serialize);
4548
4549         /*
4550          * Create DMA stuffs for RX return ring.
4551          */
4552         error = bnx_dma_block_alloc(ret->bnx_sc,
4553             BGE_RX_RTN_RING_SZ(BNX_RETURN_RING_CNT),
4554             &ret->bnx_rx_ret_ring_tag,
4555             &ret->bnx_rx_ret_ring_map,
4556             (void *)&ret->bnx_rx_ret_ring,
4557             &ret->bnx_rx_ret_ring_paddr);
4558         if (error) {
4559                 device_printf(ret->bnx_sc->bnx_dev,
4560                     "could not create RX ret ring\n");
4561                 return error;
4562         }
4563
4564         /* Shadow standard ring's RX mbuf DMA tag */
4565         ret->bnx_rx_mtag = ret->bnx_std->bnx_rx_mtag;
4566
4567         /*
4568          * Create tmp DMA map for RX mbufs.
4569          */
4570         error = bus_dmamap_create(ret->bnx_rx_mtag, BUS_DMA_WAITOK,
4571             &ret->bnx_rx_tmpmap);
4572         if (error) {
4573                 device_printf(ret->bnx_sc->bnx_dev,
4574                     "could not create tmp RX mbuf DMA map\n");
4575                 ret->bnx_rx_mtag = NULL;
4576                 return error;
4577         }
4578         return 0;
4579 }
4580
4581 static void
4582 bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *ret)
4583 {
4584         /* Destroy tmp RX mbuf DMA map */
4585         if (ret->bnx_rx_mtag != NULL)
4586                 bus_dmamap_destroy(ret->bnx_rx_mtag, ret->bnx_rx_tmpmap);
4587
4588         /* Destroy RX return ring */
4589         bnx_dma_block_free(ret->bnx_rx_ret_ring_tag,
4590             ret->bnx_rx_ret_ring_map, ret->bnx_rx_ret_ring);
4591 }
4592
4593 static int
4594 bnx_alloc_intr(struct bnx_softc *sc)
4595 {
4596         struct bnx_intr_data *intr;
4597         u_int intr_flags;
4598
4599         sc->bnx_intr_cnt = 1;
4600
4601         intr = &sc->bnx_intr_data[0];
4602         intr->bnx_sc = sc;
4603         intr->bnx_ret = &sc->bnx_rx_ret_ring[0];
4604         intr->bnx_txr = &sc->bnx_tx_ring[0];
4605         intr->bnx_intr_serialize = &sc->bnx_main_serialize;
4606         callout_init_mp(&intr->bnx_intr_timer);
4607         intr->bnx_intr_check = bnx_check_intr;
4608         intr->bnx_saved_status_tag = &intr->bnx_ret->bnx_saved_status_tag;
4609
4610         sc->bnx_intr_type = pci_alloc_1intr(sc->bnx_dev, bnx_msi_enable,
4611             &intr->bnx_intr_rid, &intr_flags);
4612
4613         intr->bnx_intr_res = bus_alloc_resource_any(sc->bnx_dev, SYS_RES_IRQ,
4614             &intr->bnx_intr_rid, intr_flags);
4615         if (intr->bnx_intr_res == NULL) {
4616                 device_printf(sc->bnx_dev, "could not alloc interrupt\n");
4617                 return ENXIO;
4618         }
4619
4620         if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI) {
4621                 sc->bnx_flags |= BNX_FLAG_ONESHOT_MSI;
4622                 bnx_enable_msi(sc);
4623
4624                 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4625                         intr->bnx_intr_func = bnx_msi_oneshot;
4626                         if (bootverbose)
4627                                 device_printf(sc->bnx_dev, "oneshot MSI\n");
4628                 } else {
4629                         intr->bnx_intr_func = bnx_msi;
4630                 }
4631         } else {
4632                 intr->bnx_intr_func = bnx_intr_legacy;
4633         }
4634         intr->bnx_intr_arg = sc;
4635         intr->bnx_intr_cpuid = rman_get_cpuid(intr->bnx_intr_res);
4636
4637         intr->bnx_txr->bnx_tx_cpuid = intr->bnx_intr_cpuid;
4638
4639         return 0;
4640 }
4641
4642 static int
4643 bnx_setup_intr(struct bnx_softc *sc)
4644 {
4645         int error, i;
4646
4647         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4648                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4649
4650                 error = bus_setup_intr_descr(sc->bnx_dev, intr->bnx_intr_res,
4651                     INTR_MPSAFE, intr->bnx_intr_func, intr->bnx_intr_arg,
4652                     &intr->bnx_intr_hand, intr->bnx_intr_serialize,
4653                     intr->bnx_intr_desc);
4654                 if (error) {
4655                         device_printf(sc->bnx_dev,
4656                             "could not set up %dth intr\n", i);
4657                         bnx_teardown_intr(sc, i);
4658                         return error;
4659                 }
4660         }
4661         return 0;
4662 }
4663
4664 static void
4665 bnx_teardown_intr(struct bnx_softc *sc, int cnt)
4666 {
4667         int i;
4668
4669         for (i = 0; i < cnt; ++i) {
4670                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4671
4672                 bus_teardown_intr(sc->bnx_dev, intr->bnx_intr_res,
4673                     intr->bnx_intr_hand);
4674         }
4675 }
4676
4677 static void
4678 bnx_free_intr(struct bnx_softc *sc)
4679 {
4680         struct bnx_intr_data *intr;
4681
4682         KKASSERT(sc->bnx_intr_cnt <= 1);
4683         intr = &sc->bnx_intr_data[0];
4684
4685         if (intr->bnx_intr_res != NULL) {
4686                 bus_release_resource(sc->bnx_dev, SYS_RES_IRQ,
4687                     intr->bnx_intr_rid, intr->bnx_intr_res);
4688         }
4689         if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI)
4690                 pci_release_msi(sc->bnx_dev);
4691 }
4692
4693 static void
4694 bnx_setup_serialize(struct bnx_softc *sc)
4695 {
4696         int i, j;
4697
4698         /*
4699          * Allocate serializer array
4700          */
4701
4702         /* Main + RX STD + TX + RX RET */
4703         sc->bnx_serialize_cnt = 1 + 1 + sc->bnx_tx_ringcnt + sc->bnx_rx_retcnt;
4704
4705         sc->bnx_serialize =
4706             kmalloc(sc->bnx_serialize_cnt * sizeof(struct lwkt_serialize *),
4707                 M_DEVBUF, M_WAITOK | M_ZERO);
4708
4709         /*
4710          * Setup serializers
4711          *
4712          * NOTE: Order is critical
4713          */
4714
4715         i = 0;
4716
4717         KKASSERT(i < sc->bnx_serialize_cnt);
4718         sc->bnx_serialize[i++] = &sc->bnx_main_serialize;
4719
4720         KKASSERT(i < sc->bnx_serialize_cnt);
4721         sc->bnx_serialize[i++] = &sc->bnx_rx_std_ring.bnx_rx_std_serialize;
4722
4723         for (j = 0; j < sc->bnx_rx_retcnt; ++j) {
4724                 KKASSERT(i < sc->bnx_serialize_cnt);
4725                 sc->bnx_serialize[i++] =
4726                     &sc->bnx_rx_ret_ring[j].bnx_rx_ret_serialize;
4727         }
4728
4729         for (j = 0; j < sc->bnx_tx_ringcnt; ++j) {
4730                 KKASSERT(i < sc->bnx_serialize_cnt);
4731                 sc->bnx_serialize[i++] =
4732                     &sc->bnx_tx_ring[j].bnx_tx_serialize;
4733         }
4734
4735         KKASSERT(i == sc->bnx_serialize_cnt);
4736 }
4737
4738 static void
4739 bnx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
4740 {
4741         struct bnx_softc *sc = ifp->if_softc;
4742
4743         ifnet_serialize_array_enter(sc->bnx_serialize,
4744             sc->bnx_serialize_cnt, slz);
4745 }
4746
4747 static void
4748 bnx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4749 {
4750         struct bnx_softc *sc = ifp->if_softc;
4751
4752         ifnet_serialize_array_exit(sc->bnx_serialize,
4753             sc->bnx_serialize_cnt, slz);
4754 }
4755
4756 static int
4757 bnx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4758 {
4759         struct bnx_softc *sc = ifp->if_softc;
4760
4761         return ifnet_serialize_array_try(sc->bnx_serialize,
4762             sc->bnx_serialize_cnt, slz);
4763 }
4764
4765 #ifdef INVARIANTS
4766
4767 static void
4768 bnx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
4769     boolean_t serialized)
4770 {
4771         struct bnx_softc *sc = ifp->if_softc;
4772
4773         ifnet_serialize_array_assert(sc->bnx_serialize, sc->bnx_serialize_cnt,
4774             slz, serialized);
4775 }
4776
4777 #endif  /* INVARIANTS */
4778
4779 #ifdef IFPOLL_ENABLE
4780
4781 static int
4782 bnx_sysctl_npoll_offset(SYSCTL_HANDLER_ARGS)
4783 {
4784         struct bnx_softc *sc = (void *)arg1;
4785         struct ifnet *ifp = &sc->arpcom.ac_if;
4786         int error, off;
4787
4788         off = sc->bnx_npoll_rxoff;
4789         error = sysctl_handle_int(oidp, &off, 0, req);
4790         if (error || req->newptr == NULL)
4791                 return error;
4792         if (off < 0)
4793                 return EINVAL;
4794
4795         ifnet_serialize_all(ifp);
4796         if (off >= ncpus2 || off % sc->bnx_rx_retcnt != 0) {
4797                 error = EINVAL;
4798         } else {
4799                 error = 0;
4800                 sc->bnx_npoll_txoff = off;
4801                 sc->bnx_npoll_rxoff = off;
4802         }
4803         ifnet_deserialize_all(ifp);
4804
4805         return error;
4806 }
4807
4808 static int
4809 bnx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
4810 {
4811         struct bnx_softc *sc = (void *)arg1;
4812         struct ifnet *ifp = &sc->arpcom.ac_if;
4813         int error, off;
4814
4815         off = sc->bnx_npoll_rxoff;
4816         error = sysctl_handle_int(oidp, &off, 0, req);
4817         if (error || req->newptr == NULL)
4818                 return error;
4819         if (off < 0)
4820                 return EINVAL;
4821
4822         ifnet_serialize_all(ifp);
4823         if (off >= ncpus2 || off % sc->bnx_rx_retcnt != 0) {
4824                 error = EINVAL;
4825         } else {
4826                 error = 0;
4827                 sc->bnx_npoll_rxoff = off;
4828         }
4829         ifnet_deserialize_all(ifp);
4830
4831         return error;
4832 }
4833
4834 static int
4835 bnx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
4836 {
4837         struct bnx_softc *sc = (void *)arg1;
4838         struct ifnet *ifp = &sc->arpcom.ac_if;
4839         int error, off;
4840
4841         off = sc->bnx_npoll_txoff;
4842         error = sysctl_handle_int(oidp, &off, 0, req);
4843         if (error || req->newptr == NULL)
4844                 return error;
4845         if (off < 0)
4846                 return EINVAL;
4847
4848         ifnet_serialize_all(ifp);
4849         if (off >= ncpus2) {
4850                 error = EINVAL;
4851         } else {
4852                 error = 0;
4853                 sc->bnx_npoll_txoff = off;
4854         }
4855         ifnet_deserialize_all(ifp);
4856
4857         return error;
4858 }
4859
4860 #endif  /* IFPOLL_ENABLE */