2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_bios.c 255572 2013-09-14 17:22:34Z dumbbell $
32 #include "radeon_reg.h"
40 /* If you boot an IGP board with a discrete card as the primary,
41 * the IGP rom is not accessible via the rom bar as the IGP rom is
42 * part of the system bios. On boot, the system bios puts a
43 * copy of the igp rom at the start of vram if a discrete card is
46 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
48 drm_local_map_t bios_map;
49 uint8_t __iomem *bios;
50 resource_size_t vram_base;
51 resource_size_t size = 256 * 1024; /* ??? */
53 DRM_INFO("%s: ===> Try IGP's VRAM...\n", __func__);
55 if (!(rdev->flags & RADEON_IS_IGP))
56 if (!radeon_card_posted(rdev)) {
57 DRM_INFO("%s: not POSTed discrete card detected, skipping this method...\n",
63 vram_base = drm_get_resource_start(rdev->ddev, 0);
64 DRM_INFO("%s: VRAM base address: 0x%jx\n", __func__, (uintmax_t)vram_base);
66 bios_map.offset = vram_base;
71 drm_core_ioremap(&bios_map, rdev->ddev);
72 if (bios_map.handle == NULL) {
73 DRM_INFO("%s: failed to ioremap\n", __func__);
76 bios = bios_map.handle;
78 DRM_INFO("%s: Map address: %p (%ju bytes)\n", __func__, bios, (uintmax_t)size);
80 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
82 DRM_INFO("%s: Incorrect BIOS size\n", __func__);
84 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
85 __func__, bios[0], bios[1]);
87 drm_core_ioremapfree(&bios_map, rdev->ddev);
90 rdev->bios = kmalloc(size, M_DRM, M_WAITOK);
91 if (rdev->bios == NULL) {
92 drm_core_ioremapfree(&bios_map, rdev->ddev);
95 memcpy_fromio(rdev->bios, bios, size);
96 drm_core_ioremapfree(&bios_map, rdev->ddev);
100 static bool radeon_read_bios(struct radeon_device *rdev)
103 uint8_t __iomem *bios;
106 DRM_INFO("%s: ===> Try PCI Expansion ROM...\n", __func__);
108 vga_dev = device_get_parent(rdev->dev);
110 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
111 bios = vga_pci_map_bios(vga_dev, &size);
115 DRM_INFO("%s: Map address: %p (%zu bytes)\n", __func__, bios, size);
117 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
119 DRM_INFO("%s: Incorrect BIOS size\n", __func__);
121 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
122 __func__, bios[0], bios[1]);
124 vga_pci_unmap_bios(vga_dev, bios);
127 rdev->bios = kmalloc(size, M_DRM, M_WAITOK);
128 memcpy(rdev->bios, bios, size);
129 vga_pci_unmap_bios(vga_dev, bios);
133 /* ATRM is used to get the BIOS on the discrete cards in
136 /* retrieve the ROM in 4k blocks */
137 #define ATRM_BIOS_PAGE 4096
139 * radeon_atrm_call - fetch a chunk of the vbios
141 * @atrm_handle: acpi ATRM handle
142 * @bios: vbios image pointer
143 * @offset: offset of vbios image data to fetch
144 * @len: length of vbios image data to fetch
146 * Executes ATRM to fetch a chunk of the discrete
147 * vbios image on PX systems (all asics).
148 * Returns the length of the buffer fetched.
150 static int radeon_atrm_call(ACPI_HANDLE atrm_handle, uint8_t *bios,
154 ACPI_OBJECT atrm_arg_elements[2], *obj;
155 ACPI_OBJECT_LIST atrm_arg;
156 ACPI_BUFFER buffer = { ACPI_ALLOCATE_BUFFER, NULL};
159 atrm_arg.Pointer = &atrm_arg_elements[0];
161 atrm_arg_elements[0].Type = ACPI_TYPE_INTEGER;
162 atrm_arg_elements[0].Integer.Value = offset;
164 atrm_arg_elements[1].Type = ACPI_TYPE_INTEGER;
165 atrm_arg_elements[1].Integer.Value = len;
167 status = AcpiEvaluateObject(atrm_handle, NULL, &atrm_arg, &buffer);
168 if (ACPI_FAILURE(status)) {
169 DRM_ERROR("failed to evaluate ATRM got %s\n", AcpiFormatException(status));
173 obj = (ACPI_OBJECT *)buffer.Pointer;
174 memcpy(bios+offset, obj->Buffer.Pointer, obj->Buffer.Length);
175 len = obj->Buffer.Length;
176 AcpiOsFree(buffer.Pointer);
180 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
183 int size = 256 * 1024;
186 ACPI_HANDLE dhandle, atrm_handle;
190 DRM_INFO("%s: ===> Try ATRM...\n", __func__);
192 /* ATRM is for the discrete card only */
193 if (rdev->flags & RADEON_IS_IGP) {
194 DRM_INFO("%s: IGP card detected, skipping this method...\n",
200 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
201 #endif /* DUMBBELL_WIP */
202 if ((dev = pci_find_class(PCIC_DISPLAY, PCIS_DISPLAY_VGA)) != NULL) {
203 DRM_INFO("%s: pci_find_class() found: %d:%d:%d:%d, vendor=%04x, device=%04x\n",
208 pci_get_function(dev),
210 pci_get_device(dev));
211 DRM_INFO("%s: Get ACPI device handle\n", __func__);
212 dhandle = acpi_get_handle(dev);
216 #endif /* DUMBBELL_WIP */
220 DRM_INFO("%s: Get ACPI handle for \"ATRM\"\n", __func__);
221 status = AcpiGetHandle(dhandle, "ATRM", &atrm_handle);
222 if (!ACPI_FAILURE(status)) {
226 #endif /* DUMBBELL_WIP */
228 DRM_INFO("%s: Failed to get \"ATRM\" handle: %s\n",
229 __func__, AcpiFormatException(status));
236 rdev->bios = kmalloc(size, M_DRM, M_WAITOK);
238 DRM_ERROR("Unable to allocate bios\n");
242 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
243 DRM_INFO("%s: Call radeon_atrm_call()\n", __func__);
244 ret = radeon_atrm_call(atrm_handle,
246 (i * ATRM_BIOS_PAGE),
248 if (ret < ATRM_BIOS_PAGE)
252 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
254 DRM_INFO("%s: Incorrect BIOS size\n", __func__);
256 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
257 __func__, rdev->bios[0], rdev->bios[1]);
259 drm_free(rdev->bios, M_DRM);
265 static bool ni_read_disabled_bios(struct radeon_device *rdev)
270 u32 vga_render_control;
274 DRM_INFO("%s: ===> Try disabled BIOS (ni)...\n", __func__);
276 bus_cntl = RREG32(R600_BUS_CNTL);
277 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
278 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
279 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
280 rom_cntl = RREG32(R600_ROM_CNTL);
283 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
284 /* Disable VGA mode */
285 WREG32(AVIVO_D1VGA_CONTROL,
286 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
287 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
288 WREG32(AVIVO_D2VGA_CONTROL,
289 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
290 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
291 WREG32(AVIVO_VGA_RENDER_CONTROL,
292 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
293 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
295 r = radeon_read_bios(rdev);
298 WREG32(R600_BUS_CNTL, bus_cntl);
299 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
300 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
301 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
302 WREG32(R600_ROM_CNTL, rom_cntl);
306 static bool r700_read_disabled_bios(struct radeon_device *rdev)
308 uint32_t viph_control;
310 uint32_t d1vga_control;
311 uint32_t d2vga_control;
312 uint32_t vga_render_control;
314 uint32_t cg_spll_func_cntl = 0;
315 uint32_t cg_spll_status;
318 DRM_INFO("%s: ===> Try disabled BIOS (r700)...\n", __func__);
320 viph_control = RREG32(RADEON_VIPH_CONTROL);
321 bus_cntl = RREG32(R600_BUS_CNTL);
322 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
323 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
324 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
325 rom_cntl = RREG32(R600_ROM_CNTL);
328 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
330 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
331 /* Disable VGA mode */
332 WREG32(AVIVO_D1VGA_CONTROL,
333 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
334 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
335 WREG32(AVIVO_D2VGA_CONTROL,
336 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
337 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
338 WREG32(AVIVO_VGA_RENDER_CONTROL,
339 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
341 if (rdev->family == CHIP_RV730) {
342 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
344 /* enable bypass mode */
345 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
346 R600_SPLL_BYPASS_EN));
348 /* wait for SPLL_CHG_STATUS to change to 1 */
350 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
351 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
353 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
355 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
357 r = radeon_read_bios(rdev);
360 if (rdev->family == CHIP_RV730) {
361 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
363 /* wait for SPLL_CHG_STATUS to change to 1 */
365 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
366 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
368 WREG32(RADEON_VIPH_CONTROL, viph_control);
369 WREG32(R600_BUS_CNTL, bus_cntl);
370 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
371 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
372 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
373 WREG32(R600_ROM_CNTL, rom_cntl);
377 static bool r600_read_disabled_bios(struct radeon_device *rdev)
379 uint32_t viph_control;
381 uint32_t d1vga_control;
382 uint32_t d2vga_control;
383 uint32_t vga_render_control;
385 uint32_t general_pwrmgt;
386 uint32_t low_vid_lower_gpio_cntl;
387 uint32_t medium_vid_lower_gpio_cntl;
388 uint32_t high_vid_lower_gpio_cntl;
389 uint32_t ctxsw_vid_lower_gpio_cntl;
390 uint32_t lower_gpio_enable;
393 DRM_INFO("%s: ===> Try disabled BIOS (r600)...\n", __func__);
395 viph_control = RREG32(RADEON_VIPH_CONTROL);
396 bus_cntl = RREG32(R600_BUS_CNTL);
397 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
398 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
399 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
400 rom_cntl = RREG32(R600_ROM_CNTL);
401 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
402 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
403 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
404 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
405 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
406 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
409 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
411 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
412 /* Disable VGA mode */
413 WREG32(AVIVO_D1VGA_CONTROL,
414 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
415 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
416 WREG32(AVIVO_D2VGA_CONTROL,
417 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
418 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
419 WREG32(AVIVO_VGA_RENDER_CONTROL,
420 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
422 WREG32(R600_ROM_CNTL,
423 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
424 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
425 R600_SCK_OVERWRITE));
427 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
428 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
429 (low_vid_lower_gpio_cntl & ~0x400));
430 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
431 (medium_vid_lower_gpio_cntl & ~0x400));
432 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
433 (high_vid_lower_gpio_cntl & ~0x400));
434 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
435 (ctxsw_vid_lower_gpio_cntl & ~0x400));
436 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
438 r = radeon_read_bios(rdev);
441 WREG32(RADEON_VIPH_CONTROL, viph_control);
442 WREG32(R600_BUS_CNTL, bus_cntl);
443 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
444 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
445 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
446 WREG32(R600_ROM_CNTL, rom_cntl);
447 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
448 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
449 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
450 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
451 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
452 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
456 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
458 uint32_t seprom_cntl1;
459 uint32_t viph_control;
461 uint32_t d1vga_control;
462 uint32_t d2vga_control;
463 uint32_t vga_render_control;
466 uint32_t gpiopad_mask;
469 DRM_INFO("%s: ===> Try disabled BIOS (avivo)...\n", __func__);
471 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
472 viph_control = RREG32(RADEON_VIPH_CONTROL);
473 bus_cntl = RREG32(RV370_BUS_CNTL);
474 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
475 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
476 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
477 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
478 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
479 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
481 WREG32(RADEON_SEPROM_CNTL1,
482 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
483 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
484 WREG32(RADEON_GPIOPAD_A, 0);
485 WREG32(RADEON_GPIOPAD_EN, 0);
486 WREG32(RADEON_GPIOPAD_MASK, 0);
489 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
492 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
494 /* Disable VGA mode */
495 WREG32(AVIVO_D1VGA_CONTROL,
496 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
497 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
498 WREG32(AVIVO_D2VGA_CONTROL,
499 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
500 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
501 WREG32(AVIVO_VGA_RENDER_CONTROL,
502 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
504 r = radeon_read_bios(rdev);
507 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
508 WREG32(RADEON_VIPH_CONTROL, viph_control);
509 WREG32(RV370_BUS_CNTL, bus_cntl);
510 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
511 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
512 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
513 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
514 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
515 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
519 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
521 uint32_t seprom_cntl1;
522 uint32_t viph_control;
524 uint32_t crtc_gen_cntl;
525 uint32_t crtc2_gen_cntl;
526 uint32_t crtc_ext_cntl;
527 uint32_t fp2_gen_cntl;
530 DRM_INFO("%s: ===> Try disabled BIOS (legacy)...\n", __func__);
532 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
533 viph_control = RREG32(RADEON_VIPH_CONTROL);
534 if (rdev->flags & RADEON_IS_PCIE)
535 bus_cntl = RREG32(RV370_BUS_CNTL);
537 bus_cntl = RREG32(RADEON_BUS_CNTL);
538 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
540 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
543 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
545 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
546 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
549 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
550 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
553 WREG32(RADEON_SEPROM_CNTL1,
554 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
555 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
558 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
561 if (rdev->flags & RADEON_IS_PCIE)
562 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
564 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
566 /* Turn off mem requests and CRTC for both controllers */
567 WREG32(RADEON_CRTC_GEN_CNTL,
568 ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
569 (RADEON_CRTC_DISP_REQ_EN_B |
570 RADEON_CRTC_EXT_DISP_EN)));
571 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
572 WREG32(RADEON_CRTC2_GEN_CNTL,
573 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
574 RADEON_CRTC2_DISP_REQ_EN_B));
577 WREG32(RADEON_CRTC_EXT_CNTL,
578 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
579 (RADEON_CRTC_SYNC_TRISTAT |
580 RADEON_CRTC_DISPLAY_DIS)));
582 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
583 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
586 r = radeon_read_bios(rdev);
589 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
590 WREG32(RADEON_VIPH_CONTROL, viph_control);
591 if (rdev->flags & RADEON_IS_PCIE)
592 WREG32(RV370_BUS_CNTL, bus_cntl);
594 WREG32(RADEON_BUS_CNTL, bus_cntl);
595 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
596 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
597 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
599 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
600 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
601 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
606 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
608 if (rdev->flags & RADEON_IS_IGP)
609 return igp_read_bios_from_vram(rdev);
610 else if (rdev->family >= CHIP_BARTS)
611 return ni_read_disabled_bios(rdev);
612 else if (rdev->family >= CHIP_RV770)
613 return r700_read_disabled_bios(rdev);
614 else if (rdev->family >= CHIP_R600)
615 return r600_read_disabled_bios(rdev);
616 else if (rdev->family >= CHIP_RS600)
617 return avivo_read_disabled_bios(rdev);
619 return legacy_read_disabled_bios(rdev);
622 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
625 ACPI_TABLE_HEADER *hdr;
627 UEFI_ACPI_VFCT *vfct;
628 GOP_VBIOS_CONTENT *vbios;
629 VFCT_IMAGE_HEADER *vhdr;
632 DRM_INFO("%s: ===> Try VFCT...\n", __func__);
634 DRM_INFO("%s: Get \"VFCT\" ACPI table\n", __func__);
635 status = AcpiGetTable("VFCT", 1, &hdr);
636 if (!ACPI_SUCCESS(status)) {
637 DRM_INFO("%s: Failed to get \"VFCT\" table: %s\n",
638 __func__, AcpiFormatException(status));
641 tbl_size = hdr->Length;
642 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
643 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
647 vfct = (UEFI_ACPI_VFCT *)hdr;
648 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
649 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
653 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
654 vhdr = &vbios->VbiosHeader;
655 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
656 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
657 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
659 if (vhdr->PCIBus != rdev->ddev->pci_bus ||
660 vhdr->PCIDevice != rdev->ddev->pci_slot ||
661 vhdr->PCIFunction != rdev->ddev->pci_func ||
662 vhdr->VendorID != rdev->ddev->pci_vendor ||
663 vhdr->DeviceID != rdev->ddev->pci_device) {
664 DRM_INFO("ACPI VFCT table is not for this card\n");
668 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
669 DRM_ERROR("ACPI VFCT image truncated\n");
673 rdev->bios = kmalloc(vhdr->ImageLength, M_DRM, M_WAITOK);
674 memcpy(rdev->bios, &vbios->VbiosContent, vhdr->ImageLength);
681 bool radeon_get_bios(struct radeon_device *rdev)
686 r = radeon_atrm_get_bios(rdev);
688 r = radeon_acpi_vfct_bios(rdev);
690 r = igp_read_bios_from_vram(rdev);
692 r = radeon_read_bios(rdev);
694 r = radeon_read_disabled_bios(rdev);
696 if (r == false || rdev->bios == NULL) {
697 DRM_ERROR("Unable to locate a BIOS ROM\n");
701 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
702 DRM_ERROR("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
707 if (RBIOS8(tmp + 0x14) != 0x0) {
708 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
712 rdev->bios_header_start = RBIOS16(0x48);
713 if (!rdev->bios_header_start) {
716 tmp = rdev->bios_header_start + 4;
717 if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
718 !memcmp(rdev->bios + tmp, "MOTA", 4)) {
719 rdev->is_atom_bios = true;
721 rdev->is_atom_bios = false;
724 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
727 drm_free(rdev->bios, M_DRM);