2 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/dev/netif/acx/if_acxvar.h,v 1.1 2006/04/01 02:55:36 sephe Exp $
41 #define DPRINTF(x) if_printf x
43 #define DPRINTF(x) ((void)0)
46 #define ACX_FRAME_HDRLEN sizeof(struct ieee80211_frame)
47 #define ACX_MEMBLOCK_SIZE 256
49 #define ACX_TX_DESC_CNT 16
50 #define ACX_RX_DESC_CNT 16
52 #define ACX_TX_RING_SIZE \
53 (2 * ACX_TX_DESC_CNT * sizeof(struct acx_host_desc))
54 #define ACX_RX_RING_SIZE \
55 (ACX_RX_DESC_CNT * sizeof(struct acx_host_desc))
57 #define CSR_READ_1(sc, reg) \
58 bus_space_read_1((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, \
59 (sc)->chip_ioreg[(reg)])
60 #define CSR_READ_2(sc, reg) \
61 bus_space_read_2((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, \
62 (sc)->chip_ioreg[(reg)])
63 #define CSR_READ_4(sc, reg) \
64 bus_space_read_4((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, \
65 (sc)->chip_ioreg[(reg)])
67 #define CSR_WRITE_2(sc, reg, val) \
68 bus_space_write_2((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, \
69 (sc)->chip_ioreg[(reg)], val)
70 #define CSR_WRITE_4(sc, reg, val) \
71 bus_space_write_4((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, \
72 (sc)->chip_ioreg[(reg)], val)
74 #define CSR_SETB_2(sc, reg, b) \
75 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (b))
76 #define CSR_CLRB_2(sc, reg, b) \
77 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & (~(b)))
79 #define DESC_READ_1(sc, off) \
80 bus_space_read_1((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off))
81 #define DESC_READ_4(sc, off) \
82 bus_space_read_4((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off))
84 #define DESC_WRITE_1(sc, off, val) \
85 bus_space_write_1((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off), (val))
86 #define DESC_WRITE_2(sc, off, val) \
87 bus_space_write_2((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off), (val))
88 #define DESC_WRITE_4(sc, off, val) \
89 bus_space_write_4((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off), (val))
90 #define DESC_WRITE_REGION_1(sc, off, d, dlen) \
91 bus_space_write_region_1((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, \
92 (off), (const uint8_t *)(d), (dlen))
94 #define FW_TXDESC_SETFIELD(sc, mb, field, val, sz) \
95 DESC_WRITE_##sz((sc), (mb)->tb_fwdesc_ofs + \
96 __offsetof(struct acx_fw_txdesc, field), (val))
98 #define FW_TXDESC_GETFIELD(sc, mb, field, sz) \
99 DESC_READ_##sz((sc), (mb)->tb_fwdesc_ofs + \
100 __offsetof(struct acx_fw_txdesc, field))
102 #define FW_TXDESC_SETFIELD_1(sc, mb, field, val) \
103 FW_TXDESC_SETFIELD(sc, mb, field, val, 1)
104 #define FW_TXDESC_SETFIELD_2(sc, mb, field, val) \
105 FW_TXDESC_SETFIELD(sc, mb, field, htole16(val), 2)
106 #define FW_TXDESC_SETFIELD_4(sc, mb, field, val) \
107 FW_TXDESC_SETFIELD(sc, mb, field, htole32(val), 4)
109 #define FW_TXDESC_GETFIELD_1(sc, mb, field) \
110 FW_TXDESC_GETFIELD(sc, mb, field, 1)
111 #define FW_TXDESC_GETFIELD_4(sc, mb, field) \
112 le32toh(FW_TXDESC_GETFIELD(sc, mb, field, 4))
115 * Firmware TX descriptor
116 * Fields are little endian
118 struct acx_fw_txdesc {
119 uint32_t f_tx_next_desc; /* next acx_fw_txdesc phyaddr */
120 uint32_t f_tx_host_desc; /* acx_host_desc phyaddr */
121 uint32_t f_tx_acx_ptr;
124 uint16_t f_tx_reserved;
126 uint32_t f_tx_dev_spec[4];
128 uint8_t f_tx_ctrl; /* see DESC_CTRL_ */
130 uint8_t f_tx_error; /* see DESC_ERR_ */
131 uint8_t f_tx_ack_fail;
132 uint8_t f_tx_rts_fail;
135 /* XXX should be moved to chip specific file */
138 uint8_t rate100; /* acx100 tx rate */
142 uint16_t rate111; /* acx111 tx rate */
145 #define f_tx_rate100 u.r1.rate100
146 #define f_tx_queue_ctrl u.r1.queue_ctrl
147 #define f_tx_rate111 u.r2.rate111
148 uint32_t f_tx_queue_info;
152 * Firmware RX descriptor
153 * Fields are little endian
155 struct acx_fw_rxdesc {
156 uint32_t f_rx_next_desc; /* next acx_fw_rxdesc phyaddr */
157 uint32_t f_rx_host_desc; /* acx_host_desc phyaddr */
158 uint32_t f_rx_acx_ptr;
161 uint16_t f_rx_wep_len;
162 uint32_t f_rx_wep_ofs;
164 uint8_t f_rx_dev_spec[16];
166 uint8_t f_rx_ctrl; /* see DESC_CTRL_ */
169 uint8_t f_rx_snr; /* signal noise ratio */
171 uint8_t f_rx_queue_ctrl;
172 uint16_t f_rx_unknown0;
173 uint32_t f_rx_unknown1;
177 * Host TX/RX descriptor
178 * Fields are little endian
180 struct acx_host_desc {
181 uint32_t h_data_paddr; /* data phyaddr */
184 uint16_t h_ctrl; /* see DESC_CTRL_ */
185 uint16_t h_data_len; /* data length */
186 uint32_t h_next_desc; /* next acx_host_desc phyaddr */
188 uint32_t h_status; /* see DESC_STATUS_ */
191 #define DESC_STATUS_FULL 0x80000000
193 #define DESC_CTRL_SHORT_PREAMBLE 0x01
194 #define DESC_CTRL_FIRST_FRAG 0x02
195 #define DESC_CTRL_AUTODMA 0x04
196 #define DESC_CTRL_RECLAIM 0x08
197 #define DESC_CTRL_HOSTDONE 0x20 /* host finished buf proc */
198 #define DESC_CTRL_ACXDONE 0x40 /* chip finished buf proc */
199 #define DESC_CTRL_HOSTOWN 0x80 /* host controls desc */
201 #define DESC_ERR_OTHER_FRAG 0x01
202 #define DESC_ERR_ABORT 0x02
203 #define DESC_ERR_PARAM 0x04
204 #define DESC_ERR_NO_WEPKEY 0x08
205 #define DESC_ERR_MSDU_TIMEOUT 0x10
206 #define DESC_ERR_EXCESSIVE_RETRY 0x20
207 #define DESC_ERR_BUF_OVERFLOW 0x40
208 #define DESC_ERR_DMA 0x80
211 * Extra header in receiving buffer
212 * Fields are little endian
214 struct acx_rxbuf_hdr {
215 uint16_t rbh_len; /* ACX_RXBUG_LEN_MASK part is len */
216 uint8_t rbh_memblk_cnt;
218 uint8_t rbh_stat_baseband; /* see ACX_RXBUF_STAT_ */
220 uint8_t rbh_level; /* signal level */
221 uint8_t rbh_snr; /* signal noise ratio */
222 uint32_t rbh_time; /* recv timestamp */
225 * XXX may have 4~8 byte here which
226 * depends on firmware version
230 #define ACX_RXBUF_LEN_MASK 0xfff
231 #define ACX_RXBUF_STAT_LNA 0x80 /* low noise amplifier */
233 struct acx_ring_data {
234 struct acx_host_desc *rx_ring;
235 bus_dma_tag_t rx_ring_dma_tag;
236 bus_dmamap_t rx_ring_dmamap;
237 uint32_t rx_ring_paddr;
239 struct acx_host_desc *tx_ring;
240 bus_dma_tag_t tx_ring_dma_tag;
241 bus_dmamap_t tx_ring_dmamap;
242 uint32_t tx_ring_paddr;
246 struct mbuf *tb_mbuf;
247 bus_dmamap_t tb_mbuf_dmamap;
249 struct acx_host_desc *tb_desc1;
250 struct acx_host_desc *tb_desc2;
252 uint32_t tb_fwdesc_ofs;
255 * Used by tx rate updating
257 struct acx_node *tb_node; /* remote node */
258 int tb_rate; /* current tx rate */
262 struct mbuf *rb_mbuf;
263 bus_dmamap_t rb_mbuf_dmamap;
265 struct acx_host_desc *rb_desc;
268 struct acx_buf_data {
269 struct acx_rxbuf rx_buf[ACX_RX_DESC_CNT];
270 struct acx_txbuf tx_buf[ACX_TX_DESC_CNT];
271 bus_dma_tag_t mbuf_dma_tag;
272 bus_dmamap_t mbuf_tmp_dmamap;
282 struct ieee80211_node nd_node; /* MUST be first */
284 struct ieee80211_rateset nd_rates; /* shared rates */
285 int nd_txrate; /* index into nd_rates[] */
287 int nd_txrate_upd_intvl; /* tx rate upd interval */
288 int nd_txrate_upd_time; /* tx rate upd timestamp */
289 int nd_txrate_sample; /* num of samples for specific rate */
292 struct acx_firmware {
301 uint8_t eaddr[IEEE80211_ADDR_LEN];
304 uint8_t cca_mode; /* acx100 */
305 uint8_t ed_thresh; /* acx100 */
309 uint64_t err_oth_frag; /* XXX error in other frag?? */
310 uint64_t err_abort; /* tx abortion */
311 uint64_t err_param; /* tx desc contains invalid param */
312 uint64_t err_no_wepkey; /* no WEP key exists */
313 uint64_t err_msdu_timeout; /* MSDU timed out */
314 uint64_t err_ex_retry; /* excessive tx retry */
315 uint64_t err_buf_oflow; /* buffer overflow */
316 uint64_t err_dma; /* DMA error */
317 uint64_t err_unkn; /* XXX unknown error */
322 * sc_xxx are filled in by common code
323 * chip_xxx are filled in by chip specific code
325 struct ieee80211com sc_ic;
327 struct callout sc_chanscan_timer;
328 uint32_t sc_flags; /* see ACX_FLAG_ */
330 struct acx_firmware sc_firmware;
331 uint32_t sc_firmware_ver;
332 uint32_t sc_hardware_id;
337 struct resource *sc_mem1_res;
338 bus_space_tag_t sc_mem1_bt;
339 bus_space_handle_t sc_mem1_bh;
345 struct resource *sc_mem2_res;
346 bus_space_tag_t sc_mem2_bt;
347 bus_space_handle_t sc_mem2_bh;
350 struct resource *sc_irq_res;
354 uint32_t sc_cmd; /* cmd reg (MMIO 2) */
355 uint32_t sc_cmd_param; /* cmd param reg (MMIO 2) */
356 uint32_t sc_info; /* unused */
357 uint32_t sc_info_param; /* unused */
359 const uint16_t *chip_ioreg; /* reg map (MMIO 1) */
363 * chip_intr_enable is not necessarily same as
366 uint16_t chip_intr_enable;
367 uint16_t chip_intr_disable;
369 uint16_t chip_gpio_pled; /* power led */
370 uint16_t chip_chan_flags; /* see IEEE80211_CHAN_ */
371 uint16_t chip_txdesc1_len;
372 int chip_rxbuf_exhdr; /* based on fw ver */
373 uint32_t chip_ee_eaddr_ofs;
374 enum ieee80211_phymode chip_phymode; /* see IEEE80211_MODE_ */
375 uint8_t chip_fw_txdesc_ctrl;
377 uint8_t sc_eeprom_ver; /* unused */
378 uint8_t sc_form_factor; /* unused */
379 uint8_t sc_radio_type; /* see ACX_RADIO_TYPE_ */
382 struct acx_ring_data sc_ring_data;
383 struct acx_buf_data sc_buf_data;
385 struct acx_stats sc_stats; /* statistics */
387 struct sysctl_ctx_list sc_sysctl_ctx;
388 struct sysctl_oid *sc_sysctl_tree;
391 * Per interface sysctl variables
393 int sc_txrate_upd_intvl_min;
394 int sc_txrate_upd_intvl_max;
395 int sc_txrate_sample_thresh;
396 int sc_long_retry_limit;
397 int sc_short_retry_limit;
398 int sc_msdu_lifetime;
401 (struct ieee80211com *,
402 enum ieee80211_state, int);
404 int (*chip_init) /* non-NULL */
405 (struct acx_softc *);
407 int (*chip_set_wepkey) /* non-NULL */
409 struct ieee80211_wepkey *, int);
411 int (*chip_read_config)
412 (struct acx_softc *, struct acx_config *);
414 int (*chip_write_config)
415 (struct acx_softc *, struct acx_config *);
417 void (*chip_set_fw_txdesc_rate) /* non-NULL */
418 (struct acx_softc *, struct acx_txbuf *, int);
420 void (*chip_set_bss_join_param) /* non-NULL */
421 (struct acx_softc *, void *, int);
423 void (*chip_proc_wep_rxbuf)
424 (struct acx_softc *, struct mbuf *, int *);
427 #define ACX_FLAG_FW_LOADED 0x1
429 #define ACX_RADIO_TYPE_MAXIM 0x0d
430 #define ACX_RADIO_TYPE_RFMD 0x11
431 #define ACX_RADIO_TYPE_RALINK 0x15
432 #define ACX_RADIO_TYPE_RADIA 0x16
433 #define ACX_RADIO_TYPE_UNKN17 0x17
434 #define ACX_RADIO_TYPE_UNKN19 0x19
436 extern const struct ieee80211_rateset acx_rates_11b;
437 extern const struct ieee80211_rateset acx_rates_11g;
438 extern int acx_beacon_intvl;
440 void acx100_set_param(device_t);
441 void acx111_set_param(device_t);
443 int acx_init_tmplt_ordered(struct acx_softc *);
444 void acx_write_phyreg(struct acx_softc *, uint32_t, uint8_t);
446 #endif /* !_IF_ACXVAR_H */