sys/dev/drm/radeon/radeon_cp.c

   1 /*-
   2  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   3  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   4  * Copyright 2007 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  * __FBSDID("$FreeBSD: src/sys/dev/drm/radeon_cp.c,v 1.36 2009/10/30 18:07:22 rnoland Exp $");
  30  */
  31
  32 #include "dev/drm/drmP.h"
  33 #include "dev/drm/drm.h"
  34 #include "dev/drm/drm_sarea.h"
  35 #include "radeon_drm.h"
  36 #include "radeon_drv.h"
  37 #include "r300_reg.h"
  38
  39 #include "radeon_microcode.h"
  40
  41 #define RADEON_FIFO_DEBUG       0
  42
  43 static int radeon_do_cleanup_cp(struct drm_device * dev);
  44 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  45
  46 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
  47 {
  48         u32 val;
  49
  50         if (dev_priv->flags & RADEON_IS_AGP) {
  51                 val = DRM_READ32(dev_priv->ring_rptr, off);
  52         } else {
  53                 val = *(((volatile u32 *)
  54                          dev_priv->ring_rptr->virtual) +
  55                         (off / sizeof(u32)));
  56                 val = le32_to_cpu(val);
  57         }
  58         return val;
  59 }
  60
  61 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
  62 {
  63         if (dev_priv->writeback_works)
  64                 return radeon_read_ring_rptr(dev_priv, 0);
  65         else {
  66                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  67                         return RADEON_READ(R600_CP_RB_RPTR);
  68                 else
  69                         return RADEON_READ(RADEON_CP_RB_RPTR);
  70         }
  71 }
  72
  73 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
  74 {
  75         if (dev_priv->flags & RADEON_IS_AGP)
  76                 DRM_WRITE32(dev_priv->ring_rptr, off, val);
  77         else
  78                 *(((volatile u32 *) dev_priv->ring_rptr->virtual) +
  79                   (off / sizeof(u32))) = cpu_to_le32(val);
  80 }
  81
  82 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
  83 {
  84         radeon_write_ring_rptr(dev_priv, 0, val);
  85 }
  86
  87 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
  88 {
  89         if (dev_priv->writeback_works) {
  90                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  91                         return radeon_read_ring_rptr(dev_priv,
  92                                                      R600_SCRATCHOFF(index));
  93                 else
  94                         return radeon_read_ring_rptr(dev_priv,
  95                                                      RADEON_SCRATCHOFF(index));
  96         } else {
  97                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  98                         return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
  99                 else
 100                         return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
 101         }
 102 }
 103
 104 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
 105 {
 106         u32 ret;
 107
 108         if (addr < 0x10000)
 109                 ret = DRM_READ32(dev_priv->mmio, addr);
 110         else {
 111                 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
 112                 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
 113         }
 114
 115         return ret;
 116 }
 117
 118 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 119 {
 120         u32 ret;
 121         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
 122         ret = RADEON_READ(R520_MC_IND_DATA);
 123         RADEON_WRITE(R520_MC_IND_INDEX, 0);
 124         return ret;
 125 }
 126
 127 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 128 {
 129         u32 ret;
 130         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
 131         ret = RADEON_READ(RS480_NB_MC_DATA);
 132         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
 133         return ret;
 134 }
 135
 136 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 137 {
 138         u32 ret;
 139         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
 140         ret = RADEON_READ(RS690_MC_DATA);
 141         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
 142         return ret;
 143 }
 144
 145 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 146 {
 147         u32 ret;
 148         RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
 149                                       RS600_MC_IND_CITF_ARB0));
 150         ret = RADEON_READ(RS600_MC_DATA);
 151         return ret;
 152 }
 153
 154 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 155 {
 156         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 157             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 158                 return RS690_READ_MCIND(dev_priv, addr);
 159         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 160                 return RS600_READ_MCIND(dev_priv, addr);
 161         else
 162                 return RS480_READ_MCIND(dev_priv, addr);
 163 }
 164
 165 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 166 {
 167
 168         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 169                 return RADEON_READ(R700_MC_VM_FB_LOCATION);
 170         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 171                 return RADEON_READ(R600_MC_VM_FB_LOCATION);
 172         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 173                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 174         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 175                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 176                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 177         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 178                 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
 179         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 180                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 181         else
 182                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 183 }
 184
 185 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 186 {
 187         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 188                 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
 189         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 190                 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
 191         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 192                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 193         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 194                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 195                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 196         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 197                 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
 198         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 199                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 200         else
 201                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 202 }
 203
 204 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 205 {
 206         /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
 207         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
 208                 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 209                 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 210         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
 211                 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 212                 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 213         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 214                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 215         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 216                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 217                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 218         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 219                 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
 220         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 221                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 222         else
 223                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 224 }
 225
 226 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 227 {
 228         u32 agp_base_hi = upper_32_bits(agp_base);
 229         u32 agp_base_lo = agp_base & 0xffffffff;
 230         u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
 231
 232         /* R6xx/R7xx must be aligned to a 4MB boundry */
 233         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 234                 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
 235         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 236                 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
 237         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 238                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 239                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 240         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 241                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 242                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 243                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 244         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 245                 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
 246                 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
 247         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 248                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 249                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 250         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 251                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 252                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 253                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 254         } else {
 255                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 256                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 257                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 258         }
 259 }
 260
 261 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
 262 {
 263         u32 tmp;
 264         /* Turn on bus mastering */
 265         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 266             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 267                 /* rs600/rs690/rs740 */
 268                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 269                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 270         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 271                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 272                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 273                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 274                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 275                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 276                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 277         } /* PCIE cards appears to not need this */
 278 }
 279
 280 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 281 {
 282         drm_radeon_private_t *dev_priv = dev->dev_private;
 283
 284         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 285         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 286 }
 287
 288 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 289 {
 290         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 291         return RADEON_READ(RADEON_PCIE_DATA);
 292 }
 293
 294 #if RADEON_FIFO_DEBUG
 295 static void radeon_status(drm_radeon_private_t * dev_priv)
 296 {
 297         printk("%s:\n", __func__);
 298         printk("RBBM_STATUS = 0x%08x\n",
 299                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 300         printk("CP_RB_RTPR = 0x%08x\n",
 301                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 302         printk("CP_RB_WTPR = 0x%08x\n",
 303                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 304         printk("AIC_CNTL = 0x%08x\n",
 305                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 306         printk("AIC_STAT = 0x%08x\n",
 307                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 308         printk("AIC_PT_BASE = 0x%08x\n",
 309                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 310         printk("TLB_ADDR = 0x%08x\n",
 311                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 312         printk("TLB_DATA = 0x%08x\n",
 313                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 314 }
 315 #endif
 316
 317 /* ================================================================
 318  * Engine, FIFO control
 319  */
 320
 321 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 322 {
 323         u32 tmp;
 324         int i;
 325
 326         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 327
 328         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 329                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 330                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 331                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 332
 333                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 334                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 335                               & RADEON_RB3D_DC_BUSY)) {
 336                                 return 0;
 337                         }
 338                         DRM_UDELAY(1);
 339                 }
 340         } else {
 341                 /* don't flush or purge cache here or lockup */
 342                 return 0;
 343         }
 344
 345 #if RADEON_FIFO_DEBUG
 346         DRM_ERROR("failed!\n");
 347         radeon_status(dev_priv);
 348 #endif
 349         return -EBUSY;
 350 }
 351
 352 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 353 {
 354         int i;
 355
 356         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 357
 358         for (i = 0; i < dev_priv->usec_timeout; i++) {
 359                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 360                              & RADEON_RBBM_FIFOCNT_MASK);
 361                 if (slots >= entries)
 362                         return 0;
 363                 DRM_UDELAY(1);
 364         }
 365         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
 366                  RADEON_READ(RADEON_RBBM_STATUS),
 367                  RADEON_READ(R300_VAP_CNTL_STATUS));
 368
 369 #if RADEON_FIFO_DEBUG
 370         DRM_ERROR("failed!\n");
 371         radeon_status(dev_priv);
 372 #endif
 373         return -EBUSY;
 374 }
 375
 376 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 377 {
 378         int i, ret;
 379
 380         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 381
 382         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 383         if (ret)
 384                 return ret;
 385
 386         for (i = 0; i < dev_priv->usec_timeout; i++) {
 387                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 388                       & RADEON_RBBM_ACTIVE)) {
 389                         radeon_do_pixcache_flush(dev_priv);
 390                         return 0;
 391                 }
 392                 DRM_UDELAY(1);
 393         }
 394         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
 395                  RADEON_READ(RADEON_RBBM_STATUS),
 396                  RADEON_READ(R300_VAP_CNTL_STATUS));
 397
 398 #if RADEON_FIFO_DEBUG
 399         DRM_ERROR("failed!\n");
 400         radeon_status(dev_priv);
 401 #endif
 402         return -EBUSY;
 403 }
 404
 405 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
 406 {
 407         uint32_t gb_tile_config, gb_pipe_sel = 0;
 408
 409         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
 410                 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
 411                 if ((z_pipe_sel & 3) == 3)
 412                         dev_priv->num_z_pipes = 2;
 413                 else
 414                         dev_priv->num_z_pipes = 1;
 415         } else
 416                 dev_priv->num_z_pipes = 1;
 417
 418         /* RS4xx/RS6xx/R4xx/R5xx */
 419         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 420                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 421                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 422         } else {
 423                 /* R3xx */
 424                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 425                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 426                         dev_priv->num_gb_pipes = 2;
 427                 } else {
 428                         /* R3Vxx */
 429                         dev_priv->num_gb_pipes = 1;
 430                 }
 431         }
 432         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 433
 434         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 435
 436         switch (dev_priv->num_gb_pipes) {
 437         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 438         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 439         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 440         default:
 441         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 442         }
 443
 444         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 445                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 446                 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 447         }
 448         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 449         radeon_do_wait_for_idle(dev_priv);
 450         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 451         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 452                                                R300_DC_AUTOFLUSH_ENABLE |
 453                                                R300_DC_DC_DISABLE_IGNORE_PE));
 454
 455
 456 }
 457
 458 /* ================================================================
 459  * CP control, initialization
 460  */
 461
 462 /* Load the microcode for the CP */
 463 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 464 {
 465         const u32 (*cp)[2];
 466         int i;
 467
 468         DRM_DEBUG("\n");
 469
 470         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 471         case CHIP_R100:
 472         case CHIP_RV100:
 473         case CHIP_RV200:
 474         case CHIP_RS100:
 475         case CHIP_RS200:
 476                 DRM_INFO("Loading R100 Microcode\n");
 477                 cp = R100_cp_microcode;
 478                 break;
 479         case CHIP_R200:
 480         case CHIP_RV250:
 481         case CHIP_RV280:
 482         case CHIP_RS300:
 483                 DRM_INFO("Loading R200 Microcode\n");
 484                 cp = R200_cp_microcode;
 485                 break;
 486         case CHIP_R300:
 487         case CHIP_R350:
 488         case CHIP_RV350:
 489         case CHIP_RV380:
 490         case CHIP_RS400:
 491         case CHIP_RS480:
 492                 DRM_INFO("Loading R300 Microcode\n");
 493                 cp = R300_cp_microcode;
 494                 break;
 495         case CHIP_R420:
 496         case CHIP_R423:
 497         case CHIP_RV410:
 498                 DRM_INFO("Loading R400 Microcode\n");
 499                 cp = R420_cp_microcode;
 500                 break;
 501         case CHIP_RS690:
 502         case CHIP_RS740:
 503                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 504                 cp = RS690_cp_microcode;
 505                 break;
 506         case CHIP_RS600:
 507                 DRM_INFO("Loading RS600 Microcode\n");
 508                 cp = RS600_cp_microcode;
 509                 break;
 510         case CHIP_RV515:
 511         case CHIP_R520:
 512         case CHIP_RV530:
 513         case CHIP_R580:
 514         case CHIP_RV560:
 515         case CHIP_RV570:
 516                 DRM_INFO("Loading R500 Microcode\n");
 517                 cp = R520_cp_microcode;
 518                 break;
 519         default:
 520                 return;
 521         }
 522
 523         radeon_do_wait_for_idle(dev_priv);
 524
 525         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 526
 527         for (i = 0; i != 256; i++) {
 528                 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, cp[i][1]);
 529                 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, cp[i][0]);
 530         }
 531 }
 532
 533 /* Flush any pending commands to the CP.  This should only be used just
 534  * prior to a wait for idle, as it informs the engine that the command
 535  * stream is ending.
 536  */
 537 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 538 {
 539         DRM_DEBUG("\n");
 540 #if 0
 541         u32 tmp;
 542
 543         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 544         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 545 #endif
 546 }
 547
 548 /* Wait for the CP to go idle.
 549  */
 550 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 551 {
 552         RING_LOCALS;
 553         DRM_DEBUG("\n");
 554
 555         BEGIN_RING(6);
 556
 557         RADEON_PURGE_CACHE();
 558         RADEON_PURGE_ZCACHE();
 559         RADEON_WAIT_UNTIL_IDLE();
 560
 561         ADVANCE_RING();
 562         COMMIT_RING();
 563
 564         return radeon_do_wait_for_idle(dev_priv);
 565 }
 566
 567 /* Start the Command Processor.
 568  */
 569 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 570 {
 571         RING_LOCALS;
 572         DRM_DEBUG("\n");
 573
 574         radeon_do_wait_for_idle(dev_priv);
 575
 576         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 577
 578         dev_priv->cp_running = 1;
 579
 580         BEGIN_RING(8);
 581         /* isync can only be written through cp on r5xx write it here */
 582         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 583         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 584                  RADEON_ISYNC_ANY3D_IDLE2D |
 585                  RADEON_ISYNC_WAIT_IDLEGUI |
 586                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 587         RADEON_PURGE_CACHE();
 588         RADEON_PURGE_ZCACHE();
 589         RADEON_WAIT_UNTIL_IDLE();
 590         ADVANCE_RING();
 591         COMMIT_RING();
 592
 593         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 594 }
 595
 596 /* Reset the Command Processor.  This will not flush any pending
 597  * commands, so you must wait for the CP command stream to complete
 598  * before calling this routine.
 599  */
 600 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 601 {
 602         u32 cur_read_ptr;
 603         DRM_DEBUG("\n");
 604
 605         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 606         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 607         SET_RING_HEAD(dev_priv, cur_read_ptr);
 608         dev_priv->ring.tail = cur_read_ptr;
 609 }
 610
 611 /* Stop the Command Processor.  This will not flush any pending
 612  * commands, so you must flush the command stream and wait for the CP
 613  * to go idle before calling this routine.
 614  */
 615 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 616 {
 617         DRM_DEBUG("\n");
 618
 619         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 620
 621         dev_priv->cp_running = 0;
 622 }
 623
 624 /* Reset the engine.  This will stop the CP if it is running.
 625  */
 626 static int radeon_do_engine_reset(struct drm_device * dev)
 627 {
 628         drm_radeon_private_t *dev_priv = dev->dev_private;
 629         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 630         DRM_DEBUG("\n");
 631
 632         radeon_do_pixcache_flush(dev_priv);
 633
 634         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 635                 /* may need something similar for newer chips */
 636                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 637                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 638
 639                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 640                                                     RADEON_FORCEON_MCLKA |
 641                                                     RADEON_FORCEON_MCLKB |
 642                                                     RADEON_FORCEON_YCLKA |
 643                                                     RADEON_FORCEON_YCLKB |
 644                                                     RADEON_FORCEON_MC |
 645                                                     RADEON_FORCEON_AIC));
 646         }
 647
 648         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 649
 650         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 651                                               RADEON_SOFT_RESET_CP |
 652                                               RADEON_SOFT_RESET_HI |
 653                                               RADEON_SOFT_RESET_SE |
 654                                               RADEON_SOFT_RESET_RE |
 655                                               RADEON_SOFT_RESET_PP |
 656                                               RADEON_SOFT_RESET_E2 |
 657                                               RADEON_SOFT_RESET_RB));
 658         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 659         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 660                                               ~(RADEON_SOFT_RESET_CP |
 661                                                 RADEON_SOFT_RESET_HI |
 662                                                 RADEON_SOFT_RESET_SE |
 663                                                 RADEON_SOFT_RESET_RE |
 664                                                 RADEON_SOFT_RESET_PP |
 665                                                 RADEON_SOFT_RESET_E2 |
 666                                                 RADEON_SOFT_RESET_RB)));
 667         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 668
 669         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 670                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 671                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 672                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 673         }
 674
 675         /* setup the raster pipes */
 676         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 677             radeon_init_pipes(dev_priv);
 678
 679         /* Reset the CP ring */
 680         radeon_do_cp_reset(dev_priv);
 681
 682         /* The CP is no longer running after an engine reset */
 683         dev_priv->cp_running = 0;
 684
 685         /* Reset any pending vertex, indirect buffers */
 686         radeon_freelist_reset(dev);
 687
 688         return 0;
 689 }
 690
 691 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 692                                        drm_radeon_private_t *dev_priv,
 693                                        struct drm_file *file_priv)
 694 {
 695         u32 ring_start, cur_read_ptr;
 696
 697         /* Initialize the memory controller. With new memory map, the fb location
 698          * is not changed, it should have been properly initialized already. Part
 699          * of the problem is that the code below is bogus, assuming the GART is
 700          * always appended to the fb which is not necessarily the case
 701          */
 702         if (!dev_priv->new_memmap)
 703                 radeon_write_fb_location(dev_priv,
 704                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 705                              | (dev_priv->fb_location >> 16));
 706
 707 #if __OS_HAS_AGP
 708         if (dev_priv->flags & RADEON_IS_AGP) {
 709                 radeon_write_agp_base(dev_priv, dev->agp->base);
 710
 711                 radeon_write_agp_location(dev_priv,
 712                              (((dev_priv->gart_vm_start - 1 +
 713                                 dev_priv->gart_size) & 0xffff0000) |
 714                               (dev_priv->gart_vm_start >> 16)));
 715
 716                 ring_start = (dev_priv->cp_ring->offset
 717                               - dev->agp->base
 718                               + dev_priv->gart_vm_start);
 719         } else
 720 #endif
 721                 ring_start = (dev_priv->cp_ring->offset - dev->sg->vaddr +
 722                     dev_priv->gart_vm_start);
 723
 724         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 725
 726         /* Set the write pointer delay */
 727         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 728
 729         /* Initialize the ring buffer's read and write pointers */
 730         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 731         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 732         SET_RING_HEAD(dev_priv, cur_read_ptr);
 733         dev_priv->ring.tail = cur_read_ptr;
 734
 735 #if __OS_HAS_AGP
 736         if (dev_priv->flags & RADEON_IS_AGP) {
 737                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 738                              dev_priv->ring_rptr->offset
 739                              - dev->agp->base + dev_priv->gart_vm_start);
 740         } else
 741 #endif
 742         {
 743                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 744                     dev_priv->ring_rptr->offset - dev->sg->vaddr +
 745                     dev_priv->gart_vm_start);
 746         }
 747
 748         /* Set ring buffer size */
 749 #ifdef __BIG_ENDIAN
 750         RADEON_WRITE(RADEON_CP_RB_CNTL,
 751                      RADEON_BUF_SWAP_32BIT |
 752                      (dev_priv->ring.fetch_size_l2ow << 18) |
 753                      (dev_priv->ring.rptr_update_l2qw << 8) |
 754                      dev_priv->ring.size_l2qw);
 755 #else
 756         RADEON_WRITE(RADEON_CP_RB_CNTL,
 757                      (dev_priv->ring.fetch_size_l2ow << 18) |
 758                      (dev_priv->ring.rptr_update_l2qw << 8) |
 759                      dev_priv->ring.size_l2qw);
 760 #endif
 761
 762
 763         /* Initialize the scratch register pointer.  This will cause
 764          * the scratch register values to be written out to memory
 765          * whenever they are updated.
 766          *
 767          * We simply put this behind the ring read pointer, this works
 768          * with PCI GART as well as (whatever kind of) AGP GART
 769          */
 770         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 771                      + RADEON_SCRATCH_REG_OFFSET);
 772
 773         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 774
 775         radeon_enable_bm(dev_priv);
 776
 777         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
 778         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 779
 780         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 781         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 782
 783         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
 784         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 785
 786         /* reset sarea copies of these */
 787         if (dev_priv->sarea_priv) {
 788                 dev_priv->sarea_priv->last_frame = 0;
 789                 dev_priv->sarea_priv->last_dispatch = 0;
 790                 dev_priv->sarea_priv->last_clear = 0;
 791         }
 792
 793         radeon_do_wait_for_idle(dev_priv);
 794
 795         /* Sync everything up */
 796         RADEON_WRITE(RADEON_ISYNC_CNTL,
 797                      (RADEON_ISYNC_ANY2D_IDLE3D |
 798                       RADEON_ISYNC_ANY3D_IDLE2D |
 799                       RADEON_ISYNC_WAIT_IDLEGUI |
 800                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 801
 802 }
 803
 804 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 805 {
 806         u32 tmp;
 807
 808         /* Start with assuming that writeback doesn't work */
 809         dev_priv->writeback_works = 0;
 810
 811         /* Writeback doesn't seem to work everywhere, test it here and possibly
 812          * enable it if it appears to work
 813          */
 814         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 815
 816         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 817
 818         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 819                 u32 val;
 820
 821                 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
 822                 if (val == 0xdeadbeef)
 823                         break;
 824                 DRM_UDELAY(1);
 825         }
 826
 827         if (tmp < dev_priv->usec_timeout) {
 828                 dev_priv->writeback_works = 1;
 829                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 830         } else {
 831                 dev_priv->writeback_works = 0;
 832                 DRM_INFO("writeback test failed\n");
 833         }
 834         if (radeon_no_wb == 1) {
 835                 dev_priv->writeback_works = 0;
 836                 DRM_INFO("writeback forced off\n");
 837         }
 838
 839         if (!dev_priv->writeback_works) {
 840                 /* Disable writeback to avoid unnecessary bus master transfer */
 841                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 842                              RADEON_RB_NO_UPDATE);
 843                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 844         }
 845 }
 846
 847 /* Enable or disable IGP GART on the chip */
 848 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 849 {
 850         u32 temp;
 851
 852         if (on) {
 853                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 854                           dev_priv->gart_vm_start,
 855                           (long)dev_priv->gart_info.bus_addr,
 856                           dev_priv->gart_size);
 857
 858                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 859                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 860                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 861                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 862                                                              RS690_BLOCK_GFX_D3_EN));
 863                 else
 864                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 865
 866                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 867                                                                RS480_VA_SIZE_32MB));
 868
 869                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 870                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 871                                                         RS480_TLB_ENABLE |
 872                                                         RS480_GTW_LAC_EN |
 873                                                         RS480_1LEVEL_GART));
 874
 875                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 876                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 877                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 878
 879                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 880                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 881                                                       RS480_REQ_TYPE_SNOOP_DIS));
 882
 883                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 884
 885                 dev_priv->gart_size = 32*1024*1024;
 886                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 887                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 888
 889                 radeon_write_agp_location(dev_priv, temp);
 890
 891                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 892                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 893                                                                RS480_VA_SIZE_32MB));
 894
 895                 do {
 896                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 897                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 898                                 break;
 899                         DRM_UDELAY(1);
 900                 } while (1);
 901
 902                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 903                                 RS480_GART_CACHE_INVALIDATE);
 904
 905                 do {
 906                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 907                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 908                                 break;
 909                         DRM_UDELAY(1);
 910                 } while (1);
 911
 912                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 913         } else {
 914                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 915         }
 916 }
 917
 918 /* Enable or disable IGP GART on the chip */
 919 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
 920 {
 921         u32 temp;
 922         int i;
 923
 924         if (on) {
 925                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 926                          dev_priv->gart_vm_start,
 927                          (long)dev_priv->gart_info.bus_addr,
 928                          dev_priv->gart_size);
 929
 930                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
 931                                                     RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
 932
 933                 for (i = 0; i < 19; i++)
 934                         IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
 935                                         (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
 936                                          RS600_SYSTEM_ACCESS_MODE_IN_SYS |
 937                                          RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
 938                                          RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
 939                                          RS600_ENABLE_FRAGMENT_PROCESSING |
 940                                          RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
 941
 942                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
 943                                                              RS600_PAGE_TABLE_TYPE_FLAT));
 944
 945                 /* disable all other contexts */
 946                 for (i = 1; i < 8; i++)
 947                         IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
 948
 949                 /* setup the page table aperture */
 950                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
 951                                 dev_priv->gart_info.bus_addr);
 952                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
 953                                 dev_priv->gart_vm_start);
 954                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
 955                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
 956                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 957
 958                 /* setup the system aperture */
 959                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
 960                                 dev_priv->gart_vm_start);
 961                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
 962                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
 963
 964                 /* enable page tables */
 965                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 966                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
 967
 968                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
 969                 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
 970
 971                 /* invalidate the cache */
 972                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 973
 974                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
 975                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
 976                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 977
 978                 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
 979                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
 980                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 981
 982                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
 983                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
 984                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 985
 986         } else {
 987                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
 988                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
 989                 temp &= ~RS600_ENABLE_PAGE_TABLES;
 990                 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
 991         }
 992 }
 993
 994 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 995 {
 996         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 997         if (on) {
 998
 999                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1000                           dev_priv->gart_vm_start,
1001                           (long)dev_priv->gart_info.bus_addr,
1002                           dev_priv->gart_size);
1003                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1004                                   dev_priv->gart_vm_start);
1005                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1006                                   dev_priv->gart_info.bus_addr);
1007                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1008                                   dev_priv->gart_vm_start);
1009                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1010                                   dev_priv->gart_vm_start +
1011                                   dev_priv->gart_size - 1);
1012
1013                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1014
1015                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1016                                   RADEON_PCIE_TX_GART_EN);
1017         } else {
1018                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1019                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1020         }
1021 }
1022
1023 /* Enable or disable PCI GART on the chip */
1024 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1025 {
1026         u32 tmp;
1027
1028         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1029             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1030             (dev_priv->flags & RADEON_IS_IGPGART)) {
1031                 radeon_set_igpgart(dev_priv, on);
1032                 return;
1033         }
1034
1035         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1036                 rs600_set_igpgart(dev_priv, on);
1037                 return;
1038         }
1039
1040         if (dev_priv->flags & RADEON_IS_PCIE) {
1041                 radeon_set_pciegart(dev_priv, on);
1042                 return;
1043         }
1044
1045         tmp = RADEON_READ(RADEON_AIC_CNTL);
1046
1047         if (on) {
1048                 RADEON_WRITE(RADEON_AIC_CNTL,
1049                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1050
1051                 /* set PCI GART page-table base address
1052                  */
1053                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1054
1055                 /* set address range for PCI address translate
1056                  */
1057                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1058                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1059                              + dev_priv->gart_size - 1);
1060
1061                 /* Turn off AGP aperture -- is this required for PCI GART?
1062                  */
1063                 radeon_write_agp_location(dev_priv, 0xffffffc0);
1064                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1065         } else {
1066                 RADEON_WRITE(RADEON_AIC_CNTL,
1067                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1068         }
1069 }
1070
1071 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1072 {
1073         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1074         struct radeon_virt_surface *vp;
1075         int i;
1076
1077         for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1078                 if (!dev_priv->virt_surfaces[i].file_priv ||
1079                     dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1080                         break;
1081         }
1082         if (i >= 2 * RADEON_MAX_SURFACES)
1083                 return -ENOMEM;
1084         vp = &dev_priv->virt_surfaces[i];
1085
1086         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1087                 struct radeon_surface *sp = &dev_priv->surfaces[i];
1088                 if (sp->refcount)
1089                         continue;
1090
1091                 vp->surface_index = i;
1092                 vp->lower = gart_info->bus_addr;
1093                 vp->upper = vp->lower + gart_info->table_size;
1094                 vp->flags = 0;
1095                 vp->file_priv = PCIGART_FILE_PRIV;
1096
1097                 sp->refcount = 1;
1098                 sp->lower = vp->lower;
1099                 sp->upper = vp->upper;
1100                 sp->flags = 0;
1101
1102                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1103                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1104                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1105                 return 0;
1106         }
1107
1108         return -ENOMEM;
1109 }
1110
1111 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1112                              struct drm_file *file_priv)
1113 {
1114         drm_radeon_private_t *dev_priv = dev->dev_private;
1115
1116         DRM_DEBUG("\n");
1117
1118         /* if we require new memory map but we don't have it fail */
1119         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1120                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1121                 radeon_do_cleanup_cp(dev);
1122                 return -EINVAL;
1123         }
1124
1125         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1126                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1127                 dev_priv->flags &= ~RADEON_IS_AGP;
1128         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1129                    && !init->is_pci) {
1130                 DRM_DEBUG("Restoring AGP flag\n");
1131                 dev_priv->flags |= RADEON_IS_AGP;
1132         }
1133
1134         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1135                 DRM_ERROR("PCI GART memory not allocated!\n");
1136                 radeon_do_cleanup_cp(dev);
1137                 return -EINVAL;
1138         }
1139
1140         dev_priv->usec_timeout = init->usec_timeout;
1141         if (dev_priv->usec_timeout < 1 ||
1142             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1143                 DRM_DEBUG("TIMEOUT problem!\n");
1144                 radeon_do_cleanup_cp(dev);
1145                 return -EINVAL;
1146         }
1147
1148         /* Enable vblank on CRTC1 for older X servers
1149          */
1150         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1151
1152         switch(init->func) {
1153         case RADEON_INIT_R200_CP:
1154                 dev_priv->microcode_version = UCODE_R200;
1155                 break;
1156         case RADEON_INIT_R300_CP:
1157                 dev_priv->microcode_version = UCODE_R300;
1158                 break;
1159         default:
1160                 dev_priv->microcode_version = UCODE_R100;
1161         }
1162
1163         dev_priv->do_boxes = 0;
1164         dev_priv->cp_mode = init->cp_mode;
1165
1166         /* We don't support anything other than bus-mastering ring mode,
1167          * but the ring can be in either AGP or PCI space for the ring
1168          * read pointer.
1169          */
1170         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1171             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1172                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1173                 radeon_do_cleanup_cp(dev);
1174                 return -EINVAL;
1175         }
1176
1177         switch (init->fb_bpp) {
1178         case 16:
1179                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1180                 break;
1181         case 32:
1182         default:
1183                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1184                 break;
1185         }
1186         dev_priv->front_offset = init->front_offset;
1187         dev_priv->front_pitch = init->front_pitch;
1188         dev_priv->back_offset = init->back_offset;
1189         dev_priv->back_pitch = init->back_pitch;
1190
1191         switch (init->depth_bpp) {
1192         case 16:
1193                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1194                 break;
1195         case 32:
1196         default:
1197                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1198                 break;
1199         }
1200         dev_priv->depth_offset = init->depth_offset;
1201         dev_priv->depth_pitch = init->depth_pitch;
1202
1203         /* Hardware state for depth clears.  Remove this if/when we no
1204          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1205          * all values to prevent unwanted 3D state from slipping through
1206          * and screwing with the clear operation.
1207          */
1208         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1209                                            (dev_priv->color_fmt << 10) |
1210                                            (dev_priv->microcode_version ==
1211                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1212
1213         dev_priv->depth_clear.rb3d_zstencilcntl =
1214             (dev_priv->depth_fmt |
1215              RADEON_Z_TEST_ALWAYS |
1216              RADEON_STENCIL_TEST_ALWAYS |
1217              RADEON_STENCIL_S_FAIL_REPLACE |
1218              RADEON_STENCIL_ZPASS_REPLACE |
1219              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1220
1221         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1222                                          RADEON_BFACE_SOLID |
1223                                          RADEON_FFACE_SOLID |
1224                                          RADEON_FLAT_SHADE_VTX_LAST |
1225                                          RADEON_DIFFUSE_SHADE_FLAT |
1226                                          RADEON_ALPHA_SHADE_FLAT |
1227                                          RADEON_SPECULAR_SHADE_FLAT |
1228                                          RADEON_FOG_SHADE_FLAT |
1229                                          RADEON_VTX_PIX_CENTER_OGL |
1230                                          RADEON_ROUND_MODE_TRUNC |
1231                                          RADEON_ROUND_PREC_8TH_PIX);
1232
1233
1234         dev_priv->ring_offset = init->ring_offset;
1235         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1236         dev_priv->buffers_offset = init->buffers_offset;
1237         dev_priv->gart_textures_offset = init->gart_textures_offset;
1238
1239         dev_priv->sarea = drm_getsarea(dev);
1240         if (!dev_priv->sarea) {
1241                 DRM_ERROR("could not find sarea!\n");
1242                 radeon_do_cleanup_cp(dev);
1243                 return -EINVAL;
1244         }
1245
1246         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1247         if (!dev_priv->cp_ring) {
1248                 DRM_ERROR("could not find cp ring region!\n");
1249                 radeon_do_cleanup_cp(dev);
1250                 return -EINVAL;
1251         }
1252         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1253         if (!dev_priv->ring_rptr) {
1254                 DRM_ERROR("could not find ring read pointer!\n");
1255                 radeon_do_cleanup_cp(dev);
1256                 return -EINVAL;
1257         }
1258         dev->agp_buffer_token = init->buffers_offset;
1259         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1260         if (!dev->agp_buffer_map) {
1261                 DRM_ERROR("could not find dma buffer region!\n");
1262                 radeon_do_cleanup_cp(dev);
1263                 return -EINVAL;
1264         }
1265
1266         if (init->gart_textures_offset) {
1267                 dev_priv->gart_textures =
1268                     drm_core_findmap(dev, init->gart_textures_offset);
1269                 if (!dev_priv->gart_textures) {
1270                         DRM_ERROR("could not find GART texture region!\n");
1271                         radeon_do_cleanup_cp(dev);
1272                         return -EINVAL;
1273                 }
1274         }
1275
1276         dev_priv->sarea_priv =
1277             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->virtual +
1278                                     init->sarea_priv_offset);
1279
1280 #if __OS_HAS_AGP
1281         if (dev_priv->flags & RADEON_IS_AGP) {
1282                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1283                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1284                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1285                 if (!dev_priv->cp_ring->virtual ||
1286                     !dev_priv->ring_rptr->virtual ||
1287                     !dev->agp_buffer_map->virtual) {
1288                         DRM_ERROR("could not find ioremap agp regions!\n");
1289                         radeon_do_cleanup_cp(dev);
1290                         return -EINVAL;
1291                 }
1292         } else
1293 #endif
1294         {
1295                 dev_priv->cp_ring->virtual =
1296                         (void *)(unsigned long)dev_priv->cp_ring->offset;
1297                 dev_priv->ring_rptr->virtual =
1298                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
1299                 dev->agp_buffer_map->virtual =
1300                         (void *)(unsigned long)dev->agp_buffer_map->offset;
1301
1302                 DRM_DEBUG("dev_priv->cp_ring->virtual %p\n",
1303                           dev_priv->cp_ring->virtual);
1304                 DRM_DEBUG("dev_priv->ring_rptr->virtual %p\n",
1305                           dev_priv->ring_rptr->virtual);
1306                 DRM_DEBUG("dev->agp_buffer_map->virtual %p\n",
1307                           dev->agp_buffer_map->virtual);
1308         }
1309
1310         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1311         dev_priv->fb_size =
1312                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1313                 - dev_priv->fb_location;
1314
1315         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1316                                         ((dev_priv->front_offset
1317                                           + dev_priv->fb_location) >> 10));
1318
1319         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1320                                        ((dev_priv->back_offset
1321                                          + dev_priv->fb_location) >> 10));
1322
1323         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1324                                         ((dev_priv->depth_offset
1325                                           + dev_priv->fb_location) >> 10));
1326
1327         dev_priv->gart_size = init->gart_size;
1328
1329         /* New let's set the memory map ... */
1330         if (dev_priv->new_memmap) {
1331                 u32 base = 0;
1332
1333                 DRM_INFO("Setting GART location based on new memory map\n");
1334
1335                 /* If using AGP, try to locate the AGP aperture at the same
1336                  * location in the card and on the bus, though we have to
1337                  * align it down.
1338                  */
1339 #if __OS_HAS_AGP
1340                 if (dev_priv->flags & RADEON_IS_AGP) {
1341                         base = dev->agp->base;
1342                         /* Check if valid */
1343                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1344                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1345                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1346                                          dev->agp->base);
1347                                 base = 0;
1348                         }
1349                 }
1350 #endif
1351                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1352                 if (base == 0) {
1353                         base = dev_priv->fb_location + dev_priv->fb_size;
1354                         if (base < dev_priv->fb_location ||
1355                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1356                                 base = dev_priv->fb_location
1357                                         - dev_priv->gart_size;
1358                 }
1359                 dev_priv->gart_vm_start = base & 0xffc00000u;
1360                 if (dev_priv->gart_vm_start != base)
1361                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1362                                  base, dev_priv->gart_vm_start);
1363         } else {
1364                 DRM_INFO("Setting GART location based on old memory map\n");
1365                 dev_priv->gart_vm_start = dev_priv->fb_location +
1366                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1367         }
1368
1369 #if __OS_HAS_AGP
1370         if (dev_priv->flags & RADEON_IS_AGP)
1371                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1372                                                  - dev->agp->base
1373                                                  + dev_priv->gart_vm_start);
1374         else
1375 #endif
1376                 dev_priv->gart_buffers_offset = dev->agp_buffer_map->offset -
1377                     dev->sg->vaddr + dev_priv->gart_vm_start;
1378
1379         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1380         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1381         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1382                   dev_priv->gart_buffers_offset);
1383
1384         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->virtual;
1385         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->virtual
1386                               + init->ring_size / sizeof(u32));
1387         dev_priv->ring.size = init->ring_size;
1388         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1389
1390         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1391         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1392
1393         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1394         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1395         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1396
1397         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1398
1399 #if __OS_HAS_AGP
1400         if (dev_priv->flags & RADEON_IS_AGP) {
1401                 /* Turn off PCI GART */
1402                 radeon_set_pcigart(dev_priv, 0);
1403         } else
1404 #endif
1405         {
1406                 u32 sctrl;
1407                 int ret;
1408
1409                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1410                 /* if we have an offset set from userspace */
1411                 if (dev_priv->pcigart_offset_set) {
1412                         dev_priv->gart_info.bus_addr =
1413                             dev_priv->pcigart_offset + dev_priv->fb_location;
1414                         dev_priv->gart_info.mapping.offset =
1415                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1416                         dev_priv->gart_info.mapping.size =
1417                             dev_priv->gart_info.table_size;
1418
1419                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1420                         dev_priv->gart_info.addr =
1421                             dev_priv->gart_info.mapping.virtual;
1422
1423                         if (dev_priv->flags & RADEON_IS_PCIE)
1424                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1425                         else
1426                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1427                         dev_priv->gart_info.gart_table_location =
1428                             DRM_ATI_GART_FB;
1429
1430                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1431                                   dev_priv->gart_info.addr,
1432                                   dev_priv->pcigart_offset);
1433                 } else {
1434                         if (dev_priv->flags & RADEON_IS_IGPGART)
1435                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1436                         else
1437                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1438                         dev_priv->gart_info.gart_table_location =
1439                             DRM_ATI_GART_MAIN;
1440                         dev_priv->gart_info.addr = NULL;
1441                         dev_priv->gart_info.bus_addr = 0;
1442                         if (dev_priv->flags & RADEON_IS_PCIE) {
1443                                 DRM_ERROR
1444                                     ("Cannot use PCI Express without GART in FB memory\n");
1445                                 radeon_do_cleanup_cp(dev);
1446                                 return -EINVAL;
1447                         }
1448                 }
1449
1450                 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1451                 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1452                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1453                         ret = r600_page_table_init(dev);
1454                 else
1455                         ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1456                 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1457
1458                 if (!ret) {
1459                         DRM_ERROR("failed to init PCI GART!\n");
1460                         radeon_do_cleanup_cp(dev);
1461                         return -ENOMEM;
1462                 }
1463
1464                 ret = radeon_setup_pcigart_surface(dev_priv);
1465                 if (ret) {
1466                         DRM_ERROR("failed to setup GART surface!\n");
1467                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1468                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1469                         else
1470                                 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1471                         radeon_do_cleanup_cp(dev);
1472                         return ret;
1473                 }
1474
1475                 /* Turn on PCI GART */
1476                 radeon_set_pcigart(dev_priv, 1);
1477         }
1478
1479         radeon_cp_load_microcode(dev_priv);
1480         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1481
1482         dev_priv->last_buf = 0;
1483
1484         radeon_do_engine_reset(dev);
1485         radeon_test_writeback(dev_priv);
1486
1487         return 0;
1488 }
1489
1490 static int radeon_do_cleanup_cp(struct drm_device * dev)
1491 {
1492         drm_radeon_private_t *dev_priv = dev->dev_private;
1493         DRM_DEBUG("\n");
1494
1495         /* Make sure interrupts are disabled here because the uninstall ioctl
1496          * may not have been called from userspace and after dev_private
1497          * is freed, it's too late.
1498          */
1499         if (dev->irq_enabled)
1500                 drm_irq_uninstall(dev);
1501
1502 #if __OS_HAS_AGP
1503         if (dev_priv->flags & RADEON_IS_AGP) {
1504                 if (dev_priv->cp_ring != NULL) {
1505                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1506                         dev_priv->cp_ring = NULL;
1507                 }
1508                 if (dev_priv->ring_rptr != NULL) {
1509                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1510                         dev_priv->ring_rptr = NULL;
1511                 }
1512                 if (dev->agp_buffer_map != NULL) {
1513                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1514                         dev->agp_buffer_map = NULL;
1515                 }
1516         } else
1517 #endif
1518         {
1519
1520                 if (dev_priv->gart_info.bus_addr) {
1521                         /* Turn off PCI GART */
1522                         radeon_set_pcigart(dev_priv, 0);
1523                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1524                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1525                         else {
1526                                 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1527                                         DRM_ERROR("failed to cleanup PCI GART!\n");
1528                         }
1529                 }
1530
1531                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1532                 {
1533                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1534                         dev_priv->gart_info.addr = 0;
1535                 }
1536         }
1537         /* only clear to the start of flags */
1538         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1539
1540         return 0;
1541 }
1542
1543 /* This code will reinit the Radeon CP hardware after a resume from disc.
1544  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1545  * here we make sure that all Radeon hardware initialisation is re-done without
1546  * affecting running applications.
1547  *
1548  * Charl P. Botha <http://cpbotha.net>
1549  */
1550 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1551 {
1552         drm_radeon_private_t *dev_priv = dev->dev_private;
1553
1554         if (!dev_priv) {
1555                 DRM_ERROR("Called with no initialization\n");
1556                 return -EINVAL;
1557         }
1558
1559         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1560
1561 #if __OS_HAS_AGP
1562         if (dev_priv->flags & RADEON_IS_AGP) {
1563                 /* Turn off PCI GART */
1564                 radeon_set_pcigart(dev_priv, 0);
1565         } else
1566 #endif
1567         {
1568                 /* Turn on PCI GART */
1569                 radeon_set_pcigart(dev_priv, 1);
1570         }
1571
1572         radeon_cp_load_microcode(dev_priv);
1573         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1574
1575         radeon_do_engine_reset(dev);
1576         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1577
1578         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1579
1580         return 0;
1581 }
1582
1583 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1584 {
1585         drm_radeon_private_t *dev_priv = dev->dev_private;
1586         drm_radeon_init_t *init = data;
1587
1588         LOCK_TEST_WITH_RETURN(dev, file_priv);
1589
1590         if (init->func == RADEON_INIT_R300_CP)
1591                 r300_init_reg_flags(dev);
1592
1593         switch (init->func) {
1594         case RADEON_INIT_CP:
1595         case RADEON_INIT_R200_CP:
1596         case RADEON_INIT_R300_CP:
1597                 return radeon_do_init_cp(dev, init, file_priv);
1598         case RADEON_INIT_R600_CP:
1599                 return r600_do_init_cp(dev, init, file_priv);
1600         case RADEON_CLEANUP_CP:
1601                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1602                         return r600_do_cleanup_cp(dev);
1603                 else
1604                         return radeon_do_cleanup_cp(dev);
1605         }
1606
1607         return -EINVAL;
1608 }
1609
1610 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1611 {
1612         drm_radeon_private_t *dev_priv = dev->dev_private;
1613         DRM_DEBUG("\n");
1614
1615         LOCK_TEST_WITH_RETURN(dev, file_priv);
1616
1617         if (dev_priv->cp_running) {
1618                 DRM_DEBUG("while CP running\n");
1619                 return 0;
1620         }
1621         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1622                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1623                           dev_priv->cp_mode);
1624                 return 0;
1625         }
1626
1627         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1628                 r600_do_cp_start(dev_priv);
1629         else
1630                 radeon_do_cp_start(dev_priv);
1631
1632         return 0;
1633 }
1634
1635 /* Stop the CP.  The engine must have been idled before calling this
1636  * routine.
1637  */
1638 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1639 {
1640         drm_radeon_private_t *dev_priv = dev->dev_private;
1641         drm_radeon_cp_stop_t *stop = data;
1642         int ret;
1643         DRM_DEBUG("\n");
1644
1645         LOCK_TEST_WITH_RETURN(dev, file_priv);
1646
1647         if (!dev_priv->cp_running)
1648                 return 0;
1649
1650         /* Flush any pending CP commands.  This ensures any outstanding
1651          * commands are exectuted by the engine before we turn it off.
1652          */
1653         if (stop->flush) {
1654                 radeon_do_cp_flush(dev_priv);
1655         }
1656
1657         /* If we fail to make the engine go idle, we return an error
1658          * code so that the DRM ioctl wrapper can try again.
1659          */
1660         if (stop->idle) {
1661                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1662                         ret = r600_do_cp_idle(dev_priv);
1663                 else
1664                         ret = radeon_do_cp_idle(dev_priv);
1665                 if (ret)
1666                         return ret;
1667         }
1668
1669         /* Finally, we can turn off the CP.  If the engine isn't idle,
1670          * we will get some dropped triangles as they won't be fully
1671          * rendered before the CP is shut down.
1672          */
1673         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1674                 r600_do_cp_stop(dev_priv);
1675         else
1676                 radeon_do_cp_stop(dev_priv);
1677
1678         /* Reset the engine */
1679         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1680                 r600_do_engine_reset(dev);
1681         else
1682                 radeon_do_engine_reset(dev);
1683
1684         return 0;
1685 }
1686
1687 void radeon_do_release(struct drm_device * dev)
1688 {
1689         drm_radeon_private_t *dev_priv = dev->dev_private;
1690         int i, ret;
1691
1692         if (dev_priv) {
1693                 if (dev_priv->cp_running) {
1694                         /* Stop the cp */
1695                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1696                                 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1697                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1698                                         tsleep_interlock(&dev->lock.lock_queue,
1699                                                          PCATCH);
1700                                         DRM_UNLOCK(dev);
1701                                         ret = tsleep(&dev->lock.lock_queue,
1702                                                     PCATCH | PINTERLOCKED,
1703                                                     "rdnrel", 0);
1704                                         DRM_LOCK(dev);
1705 /* DragonFly equivalent of
1706  *                                      mtx_sleep(&ret, &dev->dev_lock, 0,
1707  *                                          "rdnrel", 1);
1708  */
1709                                 }
1710                         } else {
1711                                 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1712                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1713                                         tsleep_interlock(&dev->lock.lock_queue,
1714                                                          PCATCH);
1715                                         DRM_UNLOCK(dev);
1716                                         ret = tsleep(&dev->lock.lock_queue,
1717                                                     PCATCH | PINTERLOCKED,
1718                                                     "rdnrel", 0);
1719                                         DRM_LOCK(dev);
1720                                 }
1721                         }
1722                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1723                                 r600_do_cp_stop(dev_priv);
1724                                 r600_do_engine_reset(dev);
1725                         } else {
1726                                 radeon_do_cp_stop(dev_priv);
1727                                 radeon_do_engine_reset(dev);
1728                         }
1729                 }
1730
1731                 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1732                         /* Disable *all* interrupts */
1733                         if (dev_priv->mmio)     /* remove this after permanent addmaps */
1734                                 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1735
1736                         if (dev_priv->mmio) {   /* remove all surfaces */
1737                                 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1738                                         RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1739                                         RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1740                                                      16 * i, 0);
1741                                         RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1742                                                      16 * i, 0);
1743                                 }
1744                         }
1745                 }
1746
1747                 /* Free memory heap structures */
1748                 radeon_mem_takedown(&(dev_priv->gart_heap));
1749                 radeon_mem_takedown(&(dev_priv->fb_heap));
1750
1751                 /* deallocate kernel resources */
1752                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1753                         r600_do_cleanup_cp(dev);
1754                 else
1755                         radeon_do_cleanup_cp(dev);
1756         }
1757 }
1758
1759 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1760  */
1761 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1762 {
1763         drm_radeon_private_t *dev_priv = dev->dev_private;
1764         DRM_DEBUG("\n");
1765
1766         LOCK_TEST_WITH_RETURN(dev, file_priv);
1767
1768         if (!dev_priv) {
1769                 DRM_DEBUG("called before init done\n");
1770                 return -EINVAL;
1771         }
1772
1773         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1774                 r600_do_cp_reset(dev_priv);
1775         else
1776                 radeon_do_cp_reset(dev_priv);
1777
1778         /* The CP is no longer running after an engine reset */
1779         dev_priv->cp_running = 0;
1780
1781         return 0;
1782 }
1783
1784 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1785 {
1786         drm_radeon_private_t *dev_priv = dev->dev_private;
1787         DRM_DEBUG("\n");
1788
1789         LOCK_TEST_WITH_RETURN(dev, file_priv);
1790
1791         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1792                 return r600_do_cp_idle(dev_priv);
1793         else
1794                 return radeon_do_cp_idle(dev_priv);
1795 }
1796
1797 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1798  */
1799 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1800 {
1801         drm_radeon_private_t *dev_priv = dev->dev_private;
1802         DRM_DEBUG("\n");
1803
1804         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1805                 return r600_do_resume_cp(dev, file_priv);
1806         else
1807                 return radeon_do_resume_cp(dev, file_priv);
1808 }
1809
1810 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1811 {
1812         drm_radeon_private_t *dev_priv = dev->dev_private;
1813         DRM_DEBUG("\n");
1814
1815         LOCK_TEST_WITH_RETURN(dev, file_priv);
1816
1817         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1818                 return r600_do_engine_reset(dev);
1819         else
1820                 return radeon_do_engine_reset(dev);
1821 }
1822
1823 /* ================================================================
1824  * Fullscreen mode
1825  */
1826
1827 /* KW: Deprecated to say the least:
1828  */
1829 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1830 {
1831         return 0;
1832 }
1833
1834 /* ================================================================
1835  * Freelist management
1836  */
1837
1838 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1839  *   bufs until freelist code is used.  Note this hides a problem with
1840  *   the scratch register * (used to keep track of last buffer
1841  *   completed) being written to before * the last buffer has actually
1842  *   completed rendering.
1843  *
1844  * KW:  It's also a good way to find free buffers quickly.
1845  *
1846  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1847  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1848  * we essentially have to do this, else old clients will break.
1849  *
1850  * However, it does leave open a potential deadlock where all the
1851  * buffers are held by other clients, which can't release them because
1852  * they can't get the lock.
1853  */
1854
1855 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1856 {
1857         struct drm_device_dma *dma = dev->dma;
1858         drm_radeon_private_t *dev_priv = dev->dev_private;
1859         drm_radeon_buf_priv_t *buf_priv;
1860         struct drm_buf *buf;
1861         int i, t;
1862         int start;
1863
1864         if (++dev_priv->last_buf >= dma->buf_count)
1865                 dev_priv->last_buf = 0;
1866
1867         start = dev_priv->last_buf;
1868
1869         for (t = 0; t < dev_priv->usec_timeout; t++) {
1870                 u32 done_age = GET_SCRATCH(dev_priv, 1);
1871                 DRM_DEBUG("done_age = %d\n", done_age);
1872                 for (i = 0; i < dma->buf_count; i++) {
1873                         buf = dma->buflist[start];
1874                         buf_priv = buf->dev_private;
1875                         if (buf->file_priv == NULL || (buf->pending &&
1876                                                        buf_priv->age <=
1877                                                        done_age)) {
1878                                 dev_priv->stats.requested_bufs++;
1879                                 buf->pending = 0;
1880                                 return buf;
1881                         }
1882                         if (++start >= dma->buf_count)
1883                                 start = 0;
1884                 }
1885
1886                 if (t) {
1887                         DRM_UDELAY(1);
1888                         dev_priv->stats.freelist_loops++;
1889                 }
1890         }
1891
1892         DRM_DEBUG("returning NULL!\n");
1893         return NULL;
1894 }
1895
1896 void radeon_freelist_reset(struct drm_device * dev)
1897 {
1898         struct drm_device_dma *dma = dev->dma;
1899         drm_radeon_private_t *dev_priv = dev->dev_private;
1900         int i;
1901
1902         dev_priv->last_buf = 0;
1903         for (i = 0; i < dma->buf_count; i++) {
1904                 struct drm_buf *buf = dma->buflist[i];
1905                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1906                 buf_priv->age = 0;
1907         }
1908 }
1909
1910 /* ================================================================
1911  * CP command submission
1912  */
1913
1914 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1915 {
1916         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1917         int i;
1918         u32 last_head = GET_RING_HEAD(dev_priv);
1919
1920         for (i = 0; i < dev_priv->usec_timeout; i++) {
1921                 u32 head = GET_RING_HEAD(dev_priv);
1922
1923                 ring->space = (head - ring->tail) * sizeof(u32);
1924                 if (ring->space <= 0)
1925                         ring->space += ring->size;
1926                 if (ring->space > n)
1927                         return 0;
1928
1929                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1930
1931                 if (head != last_head)
1932                         i = 0;
1933                 last_head = head;
1934
1935                 DRM_UDELAY(1);
1936         }
1937
1938         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1939 #if RADEON_FIFO_DEBUG
1940         radeon_status(dev_priv);
1941         DRM_ERROR("failed!\n");
1942 #endif
1943         return -EBUSY;
1944 }
1945
1946 static int radeon_cp_get_buffers(struct drm_device *dev,
1947                                  struct drm_file *file_priv,
1948                                  struct drm_dma * d)
1949 {
1950         int i;
1951         struct drm_buf *buf;
1952
1953         for (i = d->granted_count; i < d->request_count; i++) {
1954                 buf = radeon_freelist_get(dev);
1955                 if (!buf)
1956                         return -EBUSY;  /* NOTE: broken client */
1957
1958                 buf->file_priv = file_priv;
1959
1960                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1961                                      sizeof(buf->idx)))
1962                         return -EFAULT;
1963                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1964                                      sizeof(buf->total)))
1965                         return -EFAULT;
1966
1967                 d->granted_count++;
1968         }
1969         return 0;
1970 }
1971
1972 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1973 {
1974         struct drm_device_dma *dma = dev->dma;
1975         int ret = 0;
1976         struct drm_dma *d = data;
1977
1978         LOCK_TEST_WITH_RETURN(dev, file_priv);
1979
1980         /* Please don't send us buffers.
1981          */
1982         if (d->send_count != 0) {
1983                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1984                           DRM_CURRENTPID, d->send_count);
1985                 return -EINVAL;
1986         }
1987
1988         /* We'll send you buffers.
1989          */
1990         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1991                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1992                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1993                 return -EINVAL;
1994         }
1995
1996         d->granted_count = 0;
1997
1998         if (d->request_count) {
1999                 ret = radeon_cp_get_buffers(dev, file_priv, d);
2000         }
2001
2002         return ret;
2003 }
2004
2005 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2006 {
2007         drm_radeon_private_t *dev_priv;
2008         int ret = 0;
2009
2010         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2011         if (dev_priv == NULL)
2012                 return -ENOMEM;
2013
2014         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2015         dev->dev_private = (void *)dev_priv;
2016         dev_priv->flags = flags;
2017
2018         switch (flags & RADEON_FAMILY_MASK) {
2019         case CHIP_R100:
2020         case CHIP_RV200:
2021         case CHIP_R200:
2022         case CHIP_R300:
2023         case CHIP_R350:
2024         case CHIP_R420:
2025         case CHIP_R423:
2026         case CHIP_RV410:
2027         case CHIP_RV515:
2028         case CHIP_R520:
2029         case CHIP_RV570:
2030         case CHIP_R580:
2031                 dev_priv->flags |= RADEON_HAS_HIERZ;
2032                 break;
2033         default:
2034                 /* all other chips have no hierarchical z buffer */
2035                 break;
2036         }
2037
2038         if (drm_device_is_agp(dev))
2039                 dev_priv->flags |= RADEON_IS_AGP;
2040         else if (drm_device_is_pcie(dev))
2041                 dev_priv->flags |= RADEON_IS_PCIE;
2042         else
2043                 dev_priv->flags |= RADEON_IS_PCI;
2044
2045         lockinit(&dev_priv->cs.cs_mutex, "cs_mtx", 0, LK_EXCLUSIVE);
2046
2047         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2048                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2049                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2050         if (ret != 0)
2051                 goto error;
2052
2053         ret = drm_vblank_init(dev, 2);
2054         if (ret != 0)
2055                 goto error;
2056
2057         dev->max_vblank_count = 0x001fffff;
2058
2059         DRM_DEBUG("%s card detected\n",
2060                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" :
2061                     (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2062
2063         return ret;
2064
2065 error:
2066         radeon_driver_unload(dev);
2067         return ret;
2068 }
2069
2070 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2071  * have to find them.
2072  */
2073 int radeon_driver_firstopen(struct drm_device *dev)
2074 {
2075         int ret;
2076         drm_local_map_t *map;
2077         drm_radeon_private_t *dev_priv = dev->dev_private;
2078
2079         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2080
2081         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2082         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2083                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2084                          _DRM_WRITE_COMBINING, &map);
2085         if (ret != 0)
2086                 return ret;
2087
2088         return 0;
2089 }
2090
2091 int radeon_driver_unload(struct drm_device *dev)
2092 {
2093         drm_radeon_private_t *dev_priv = dev->dev_private;
2094
2095         DRM_DEBUG("\n");
2096
2097         drm_rmmap(dev, dev_priv->mmio);
2098
2099         lockuninit(&dev_priv->cs.cs_mutex);
2100
2101         drm_free(dev_priv, DRM_MEM_DRIVER);
2102
2103         dev->dev_private = NULL;
2104         return 0;
2105 }
2106
2107 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2108 {
2109         int i;
2110         u32 *ring;
2111         int tail_aligned;
2112
2113         /* check if the ring is padded out to 16-dword alignment */
2114
2115         tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN - 1);
2116         if (tail_aligned) {
2117                 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2118
2119                 ring = dev_priv->ring.start;
2120                 /* pad with some CP_PACKET2 */
2121                 for (i = 0; i < num_p2; i++)
2122                         ring[dev_priv->ring.tail + i] = CP_PACKET2();
2123
2124                 dev_priv->ring.tail += i;
2125
2126                 dev_priv->ring.space -= num_p2 * sizeof(u32);
2127         }
2128
2129         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2130
2131         DRM_MEMORYBARRIER();
2132         GET_RING_HEAD( dev_priv );
2133
2134         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2135                 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2136                 /* read from PCI bus to ensure correct posting */
2137                 RADEON_READ(R600_CP_RB_RPTR);
2138         } else {
2139                 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2140                 /* read from PCI bus to ensure correct posting */
2141                 RADEON_READ(RADEON_CP_RB_RPTR);
2142         }
2143 }