2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
33 * Driver for the Atheros Wireless LAN controller.
35 * This software is derived from work of Atsushi Onoe; his contribution
36 * is greatly appreciated.
42 * This is needed for register operations which are performed
43 * by the driver - eg, calls to ath_hal_gettsf32().
45 * It's also required for any AH_DEBUG checks in here, eg the
46 * module dependencies.
51 #include <sys/param.h>
52 #include <sys/systm.h>
53 #include <sys/sysctl.h>
55 #include <sys/malloc.h>
57 #include <sys/mutex.h>
58 #include <sys/kernel.h>
59 #include <sys/socket.h>
60 #include <sys/sockio.h>
61 #include <sys/errno.h>
62 #include <sys/callout.h>
64 #include <sys/endian.h>
65 #include <sys/kthread.h>
66 #include <sys/taskqueue.h>
68 #include <sys/module.h>
72 #include <net/if_var.h>
73 #include <net/if_dl.h>
74 #include <net/if_media.h>
75 #include <net/if_types.h>
76 #include <net/if_arp.h>
77 #include <net/ethernet.h>
78 #include <net/if_llc.h>
80 #include <netproto/802_11/ieee80211_var.h>
81 #include <netproto/802_11/ieee80211_regdomain.h>
82 #ifdef IEEE80211_SUPPORT_SUPERG
83 #include <netproto/802_11/ieee80211_superg.h>
85 #ifdef IEEE80211_SUPPORT_TDMA
86 #include <netproto/802_11/ieee80211_tdma.h>
92 #include <netinet/in.h>
93 #include <netinet/if_ether.h>
96 #include <dev/netif/ath/ath/if_athvar.h>
97 #include <dev/netif/ath/ath_hal/ah_devid.h> /* XXX for softled */
98 #include <dev/netif/ath/ath_hal/ah_diagcodes.h>
100 #include <dev/netif/ath/ath/if_ath_debug.h>
101 #include <dev/netif/ath/ath/if_ath_misc.h>
102 #include <dev/netif/ath/ath/if_ath_tsf.h>
103 #include <dev/netif/ath/ath/if_ath_tx.h>
104 #include <dev/netif/ath/ath/if_ath_sysctl.h>
105 #include <dev/netif/ath/ath/if_ath_led.h>
106 #include <dev/netif/ath/ath/if_ath_keycache.h>
107 #include <dev/netif/ath/ath/if_ath_rx.h>
108 #include <dev/netif/ath/ath/if_ath_rx_edma.h>
109 #include <dev/netif/ath/ath/if_ath_tx_edma.h>
110 #include <dev/netif/ath/ath/if_ath_beacon.h>
111 #include <dev/netif/ath/ath/if_ath_btcoex.h>
112 #include <dev/netif/ath/ath/if_ath_spectral.h>
113 #include <dev/netif/ath/ath/if_ath_lna_div.h>
114 #include <dev/netif/ath/ath/if_athdfs.h>
117 #include <dev/netif/ath/ath_tx99/ath_tx99.h>
121 #include <dev/netif/ath/ath/if_ath_alq.h>
125 * Only enable this if you're working on PS-POLL support.
130 * ATH_BCBUF determines the number of vap's that can transmit
131 * beacons and also (currently) the number of vap's that can
132 * have unique mac addresses/bssid. When staggering beacons
133 * 4 is probably a good max as otherwise the beacons become
134 * very closely spaced and there is limited time for cab q traffic
135 * to go out. You can burst beacons instead but that is not good
136 * for stations in power save and at some point you really want
137 * another radio (and channel).
139 * The limit on the number of mac addresses is tied to our use of
140 * the U/L bit and tracking addresses in a byte; it would be
141 * worthwhile to allow more for applications like proxy sta.
143 CTASSERT(ATH_BCBUF <= 8);
145 static struct ieee80211vap *ath_vap_create(struct ieee80211com *,
146 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
147 const uint8_t [IEEE80211_ADDR_LEN],
148 const uint8_t [IEEE80211_ADDR_LEN]);
149 static void ath_vap_delete(struct ieee80211vap *);
150 static void ath_init(void *);
151 static void ath_stop_locked(struct ifnet *);
152 static void ath_stop(struct ifnet *);
153 static int ath_reset_vap(struct ieee80211vap *, u_long);
154 static int ath_transmit(struct ifnet *ifp, struct mbuf *m);
155 static void ath_qflush(struct ifnet *ifp);
156 static int ath_media_change(struct ifnet *);
157 static void ath_watchdog(void *);
158 static int ath_ioctl(struct ifnet *, u_long, caddr_t);
159 static void ath_fatal_proc(void *, int);
160 static void ath_bmiss_vap(struct ieee80211vap *);
161 static void ath_bmiss_proc(void *, int);
162 static void ath_key_update_begin(struct ieee80211vap *);
163 static void ath_key_update_end(struct ieee80211vap *);
164 static void ath_update_mcast(struct ifnet *);
165 static void ath_update_promisc(struct ifnet *);
166 static void ath_updateslot(struct ifnet *);
167 static void ath_bstuck_proc(void *, int);
168 static void ath_reset_proc(void *, int);
169 static int ath_desc_alloc(struct ath_softc *);
170 static void ath_desc_free(struct ath_softc *);
171 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *,
172 const uint8_t [IEEE80211_ADDR_LEN]);
173 static void ath_node_cleanup(struct ieee80211_node *);
174 static void ath_node_free(struct ieee80211_node *);
175 static void ath_node_getsignal(const struct ieee80211_node *,
177 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int);
178 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
179 static int ath_tx_setup(struct ath_softc *, int, int);
180 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
181 static void ath_tx_cleanup(struct ath_softc *);
182 static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq,
184 static void ath_tx_proc_q0(void *, int);
185 static void ath_tx_proc_q0123(void *, int);
186 static void ath_tx_proc(void *, int);
187 static void ath_txq_sched_tasklet(void *, int);
188 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
189 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
190 static void ath_scan_start(struct ieee80211com *);
191 static void ath_scan_end(struct ieee80211com *);
192 static void ath_set_channel(struct ieee80211com *);
193 #ifdef ATH_ENABLE_11N
194 static void ath_update_chw(struct ieee80211com *);
195 #endif /* ATH_ENABLE_11N */
196 static void ath_calibrate(void *);
197 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int);
198 static void ath_setup_stationkey(struct ieee80211_node *);
199 static void ath_newassoc(struct ieee80211_node *, int);
200 static int ath_setregdomain(struct ieee80211com *,
201 struct ieee80211_regdomain *, int,
202 struct ieee80211_channel []);
203 static void ath_getradiocaps(struct ieee80211com *, int, int *,
204 struct ieee80211_channel []);
205 static int ath_getchannels(struct ath_softc *);
207 static int ath_rate_setup(struct ath_softc *, u_int mode);
208 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
210 static void ath_announce(struct ath_softc *);
212 static void ath_dfs_tasklet(void *, int);
213 static void ath_node_powersave(struct ieee80211_node *, int);
214 static int ath_node_set_tim(struct ieee80211_node *, int);
215 static void ath_node_recv_pspoll(struct ieee80211_node *, struct mbuf *);
217 #ifdef IEEE80211_SUPPORT_TDMA
218 #include <dev/netif/ath/ath/if_ath_tdma.h>
221 SYSCTL_DECL(_hw_ath);
223 /* XXX validate sysctl values */
224 static int ath_longcalinterval = 30; /* long cals every 30 secs */
225 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval,
226 0, "long chip calibration interval (secs)");
227 static int ath_shortcalinterval = 100; /* short cals every 100 ms */
228 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval,
229 0, "short chip calibration interval (msecs)");
230 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */
231 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval,
232 0, "reset chip calibration results (secs)");
233 static int ath_anicalinterval = 100; /* ANI calibration - 100 msec */
234 SYSCTL_INT(_hw_ath, OID_AUTO, anical, CTLFLAG_RW, &ath_anicalinterval,
235 0, "ANI calibration (msecs)");
237 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
238 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf,
239 0, "rx buffers allocated");
240 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf);
241 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
242 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf,
243 0, "tx buffers allocated");
244 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf);
245 int ath_txbuf_mgmt = ATH_MGMT_TXBUF; /* # mgmt tx buffers to allocate */
246 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf_mgmt, CTLFLAG_RW, &ath_txbuf_mgmt,
247 0, "tx (mgmt) buffers allocated");
248 TUNABLE_INT("hw.ath.txbuf_mgmt", &ath_txbuf_mgmt);
250 int ath_bstuck_threshold = 4; /* max missed beacons */
251 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold,
252 0, "max missed beacon xmits before chip reset");
254 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
257 ath_legacy_attach_comp_func(struct ath_softc *sc)
261 * Special case certain configurations. Note the
262 * CAB queue is handled by these specially so don't
263 * include them when checking the txq setup mask.
265 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
267 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
270 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
273 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
278 #define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20)
279 #define HAL_MODE_HT40 \
280 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS | \
281 HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)
283 ath_attach(u_int16_t devid, struct ath_softc *sc)
286 struct ieee80211com *ic;
287 struct ath_hal *ah = NULL;
291 uint8_t macaddr[IEEE80211_ADDR_LEN];
292 int rx_chainmask, tx_chainmask;
294 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
297 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
299 device_printf(sc->sc_dev, "can not if_alloc()\n");
306 /* set these up early for if_printf use */
307 if_initname(ifp, device_get_name(sc->sc_dev),
308 device_get_unit(sc->sc_dev));
311 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh,
312 sc->sc_eepromdata, &status);
314 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
320 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
322 sc->sc_debug = ath_debug;
326 * Setup the DMA/EDMA functions based on the current
329 * This is required before the descriptors are allocated.
331 if (ath_hal_hasedma(sc->sc_ah)) {
333 ath_recv_setup_edma(sc);
334 ath_xmit_setup_edma(sc);
336 ath_recv_setup_legacy(sc);
337 ath_xmit_setup_legacy(sc);
341 * Check if the MAC has multi-rate retry support.
342 * We do this by trying to setup a fake extended
343 * descriptor. MAC's that don't have support will
344 * return false w/o doing anything. MAC's that do
345 * support it will return true w/o doing anything.
347 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
350 * Check if the device has hardware counters for PHY
351 * errors. If so we need to enable the MIB interrupt
352 * so we can act on stat triggers.
354 if (ath_hal_hwphycounters(ah))
358 * Get the hardware key cache size.
360 sc->sc_keymax = ath_hal_keycachesize(ah);
361 if (sc->sc_keymax > ATH_KEYMAX) {
362 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
363 ATH_KEYMAX, sc->sc_keymax);
364 sc->sc_keymax = ATH_KEYMAX;
367 * Reset the key cache since some parts do not
368 * reset the contents on initial power up.
370 for (i = 0; i < sc->sc_keymax; i++)
371 ath_hal_keyreset(ah, i);
374 * Collect the default channel list.
376 error = ath_getchannels(sc);
381 * Setup rate tables for all potential media types.
383 ath_rate_setup(sc, IEEE80211_MODE_11A);
384 ath_rate_setup(sc, IEEE80211_MODE_11B);
385 ath_rate_setup(sc, IEEE80211_MODE_11G);
386 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
387 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
388 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A);
389 ath_rate_setup(sc, IEEE80211_MODE_11NA);
390 ath_rate_setup(sc, IEEE80211_MODE_11NG);
391 ath_rate_setup(sc, IEEE80211_MODE_HALF);
392 ath_rate_setup(sc, IEEE80211_MODE_QUARTER);
394 /* NB: setup here so ath_rate_update is happy */
395 ath_setcurmode(sc, IEEE80211_MODE_11A);
398 * Allocate TX descriptors and populate the lists.
400 error = ath_desc_alloc(sc);
402 if_printf(ifp, "failed to allocate TX descriptors: %d\n",
406 error = ath_txdma_setup(sc);
408 if_printf(ifp, "failed to allocate TX descriptors: %d\n",
414 * Allocate RX descriptors and populate the lists.
416 error = ath_rxdma_setup(sc);
418 if_printf(ifp, "failed to allocate RX descriptors: %d\n",
423 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0);
424 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0);
426 ATH_TXBUF_LOCK_INIT(sc);
428 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT,
429 taskqueue_thread_enqueue, &sc->sc_tq);
430 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET,
431 "%s taskq", ifp->if_xname);
433 TASK_INIT(&sc->sc_rxtask, 0, sc->sc_rx.recv_tasklet, sc);
434 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
435 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc);
436 TASK_INIT(&sc->sc_resettask,0, ath_reset_proc, sc);
437 TASK_INIT(&sc->sc_txqtask, 0, ath_txq_sched_tasklet, sc);
438 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc);
441 * Allocate hardware transmit queues: one queue for
442 * beacon frames and one data queue for each QoS
443 * priority. Note that the hal handles resetting
444 * these queues at the needed time.
448 sc->sc_bhalq = ath_beaconq_setup(sc);
449 if (sc->sc_bhalq == (u_int) -1) {
450 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
454 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
455 if (sc->sc_cabq == NULL) {
456 if_printf(ifp, "unable to setup CAB xmit queue!\n");
460 /* NB: insure BK queue is the lowest priority h/w queue */
461 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
462 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
463 ieee80211_wme_acnames[WME_AC_BK]);
467 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
468 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
469 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
471 * Not enough hardware tx queues to properly do WME;
472 * just punt and assign them all to the same h/w queue.
473 * We could do a better job of this if, for example,
474 * we allocate queues when we switch from station to
477 if (sc->sc_ac2q[WME_AC_VI] != NULL)
478 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
479 if (sc->sc_ac2q[WME_AC_BE] != NULL)
480 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
481 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
482 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
483 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
487 * Attach the TX completion function.
489 * The non-EDMA chips may have some special case optimisations;
490 * this method gives everyone a chance to attach cleanly.
492 sc->sc_tx.xmit_attach_comp_func(sc);
495 * Setup rate control. Some rate control modules
496 * call back to change the anntena state so expose
497 * the necessary entry points.
498 * XXX maybe belongs in struct ath_ratectrl?
500 sc->sc_setdefantenna = ath_setdefantenna;
501 sc->sc_rc = ath_rate_attach(sc);
502 if (sc->sc_rc == NULL) {
507 /* Attach DFS module */
508 if (! ath_dfs_attach(sc)) {
509 device_printf(sc->sc_dev,
510 "%s: unable to attach DFS\n", __func__);
515 /* Attach spectral module */
516 if (ath_spectral_attach(sc) < 0) {
517 device_printf(sc->sc_dev,
518 "%s: unable to attach spectral\n", __func__);
523 /* Attach bluetooth coexistence module */
524 if (ath_btcoex_attach(sc) < 0) {
525 device_printf(sc->sc_dev,
526 "%s: unable to attach bluetooth coexistence\n", __func__);
531 /* Attach LNA diversity module */
532 if (ath_lna_div_attach(sc) < 0) {
533 device_printf(sc->sc_dev,
534 "%s: unable to attach LNA diversity\n", __func__);
539 /* Start DFS processing tasklet */
540 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc);
542 /* Configure LED state */
545 sc->sc_ledon = 0; /* low true */
546 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
547 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE);
550 * Don't setup hardware-based blinking.
552 * Although some NICs may have this configured in the
553 * default reset register values, the user may wish
554 * to alter which pins have which function.
556 * The reference driver attaches the MAC network LED to GPIO1 and
557 * the MAC power LED to GPIO2. However, the DWA-552 cardbus
558 * NIC has these reversed.
560 sc->sc_hardled = (1 == 0);
561 sc->sc_led_net_pin = -1;
562 sc->sc_led_pwr_pin = -1;
564 * Auto-enable soft led processing for IBM cards and for
565 * 5211 minipci cards. Users can also manually enable/disable
566 * support with a sysctl.
568 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
570 ath_hal_setledstate(ah, HAL_LED_INIT);
573 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
574 ifp->if_transmit = ath_transmit;
575 ifp->if_qflush = ath_qflush;
576 ifp->if_ioctl = ath_ioctl;
577 ifp->if_init = ath_init;
578 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
579 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
580 IFQ_SET_READY(&ifp->if_snd);
583 /* XXX not right but it's not used anywhere important */
584 ic->ic_phytype = IEEE80211_T_OFDM;
585 ic->ic_opmode = IEEE80211_M_STA;
587 IEEE80211_C_STA /* station mode */
588 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
589 | IEEE80211_C_HOSTAP /* hostap mode */
590 | IEEE80211_C_MONITOR /* monitor mode */
591 | IEEE80211_C_AHDEMO /* adhoc demo mode */
592 | IEEE80211_C_WDS /* 4-address traffic works */
593 | IEEE80211_C_MBSS /* mesh point link mode */
594 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
595 | IEEE80211_C_SHSLOT /* short slot time supported */
596 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
597 #ifndef ATH_ENABLE_11N
598 | IEEE80211_C_BGSCAN /* capable of bg scanning */
600 | IEEE80211_C_TXFRAG /* handle tx frags */
601 #ifdef ATH_ENABLE_DFS
602 | IEEE80211_C_DFS /* Enable radar detection */
606 * Query the hal to figure out h/w crypto support.
608 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
609 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP;
610 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
611 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB;
612 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
613 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM;
614 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
615 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP;
616 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
617 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP;
619 * Check if h/w does the MIC and/or whether the
620 * separate key cache entries are required to
621 * handle both tx+rx MIC keys.
623 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
624 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
626 * If the h/w supports storing tx+rx MIC keys
627 * in one cache slot automatically enable use.
629 if (ath_hal_hastkipsplit(ah) ||
630 !ath_hal_settkipsplit(ah, AH_FALSE))
633 * If the h/w can do TKIP MIC together with WME then
634 * we use it; otherwise we force the MIC to be done
635 * in software by the net80211 layer.
637 if (ath_hal_haswmetkipmic(ah))
638 sc->sc_wmetkipmic = 1;
640 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
642 * Check for multicast key search support.
644 if (ath_hal_hasmcastkeysearch(sc->sc_ah) &&
645 !ath_hal_getmcastkeysearch(sc->sc_ah)) {
646 ath_hal_setmcastkeysearch(sc->sc_ah, 1);
648 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
650 * Mark key cache slots associated with global keys
651 * as in use. If we knew TKIP was not to be used we
652 * could leave the +32, +64, and +32+64 slots free.
654 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
655 setbit(sc->sc_keymap, i);
656 setbit(sc->sc_keymap, i+64);
657 if (sc->sc_splitmic) {
658 setbit(sc->sc_keymap, i+32);
659 setbit(sc->sc_keymap, i+32+64);
663 * TPC support can be done either with a global cap or
664 * per-packet support. The latter is not available on
665 * all parts. We're a bit pedantic here as all parts
666 * support a global cap.
668 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
669 ic->ic_caps |= IEEE80211_C_TXPMGT;
672 * Mark WME capability only if we have sufficient
673 * hardware queues to do proper priority scheduling.
675 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
676 ic->ic_caps |= IEEE80211_C_WME;
678 * Check for misc other capabilities.
680 if (ath_hal_hasbursting(ah))
681 ic->ic_caps |= IEEE80211_C_BURST;
682 sc->sc_hasbmask = ath_hal_hasbssidmask(ah);
683 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah);
684 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah);
685 sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah);
686 sc->sc_rxtsf32 = ath_hal_has_long_rxdesc_tsf(ah);
687 sc->sc_hasenforcetxop = ath_hal_hasenforcetxop(ah);
688 sc->sc_rx_lnamixer = ath_hal_hasrxlnamixer(ah);
689 sc->sc_hasdivcomb = ath_hal_hasdivantcomb(ah);
691 if (ath_hal_hasfastframes(ah))
692 ic->ic_caps |= IEEE80211_C_FF;
693 wmodes = ath_hal_getwirelessmodes(ah);
694 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO))
695 ic->ic_caps |= IEEE80211_C_TURBOP;
696 #ifdef IEEE80211_SUPPORT_TDMA
697 if (ath_hal_macversion(ah) > 0x78) {
698 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */
699 ic->ic_tdma_update = ath_tdma_update;
704 * TODO: enforce that at least this many frames are available
705 * in the txbuf list before allowing data frames (raw or
706 * otherwise) to be transmitted.
708 sc->sc_txq_data_minfree = 10;
710 * Leave this as default to maintain legacy behaviour.
711 * Shortening the cabq/mcastq may end up causing some
712 * undesirable behaviour.
714 sc->sc_txq_mcastq_maxdepth = ath_txbuf;
717 * How deep can the node software TX queue get whilst it's asleep.
719 sc->sc_txq_node_psq_maxdepth = 16;
722 * Default the maximum queue depth for a given node
723 * to 1/4'th the TX buffers, or 64, whichever
726 sc->sc_txq_node_maxdepth = MAX(64, ath_txbuf / 4);
728 /* Enable CABQ by default */
729 sc->sc_cabq_enable = 1;
732 * Allow the TX and RX chainmasks to be overridden by
733 * environment variables and/or device.hints.
735 * This must be done early - before the hardware is
736 * calibrated or before the 802.11n stream calculation
739 if (resource_int_value(device_get_name(sc->sc_dev),
740 device_get_unit(sc->sc_dev), "rx_chainmask",
741 &rx_chainmask) == 0) {
742 device_printf(sc->sc_dev, "Setting RX chainmask to 0x%x\n",
744 (void) ath_hal_setrxchainmask(sc->sc_ah, rx_chainmask);
746 if (resource_int_value(device_get_name(sc->sc_dev),
747 device_get_unit(sc->sc_dev), "tx_chainmask",
748 &tx_chainmask) == 0) {
749 device_printf(sc->sc_dev, "Setting TX chainmask to 0x%x\n",
751 (void) ath_hal_settxchainmask(sc->sc_ah, tx_chainmask);
755 * Query the TX/RX chainmask configuration.
757 * This is only relevant for 11n devices.
759 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask);
760 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask);
763 * Disable MRR with protected frames by default.
764 * Only 802.11n series NICs can handle this.
766 sc->sc_mrrprot = 0; /* XXX should be a capability */
769 * Query the enterprise mode information the HAL.
771 if (ath_hal_getcapability(ah, HAL_CAP_ENTERPRISE_MODE, 0,
772 &sc->sc_ent_cfg) == HAL_OK)
775 #ifdef ATH_ENABLE_11N
777 * Query HT capabilities
779 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK &&
780 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) {
783 device_printf(sc->sc_dev, "[HT] enabling HT modes\n");
785 sc->sc_mrrprot = 1; /* XXX should be a capability */
787 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */
788 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */
789 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */
790 | IEEE80211_HTCAP_MAXAMSDU_3839
791 /* max A-MSDU length */
792 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */
796 * Enable short-GI for HT20 only if the hardware
797 * advertises support.
798 * Notably, anything earlier than the AR9287 doesn't.
800 if ((ath_hal_getcapability(ah,
801 HAL_CAP_HT20_SGI, 0, NULL) == HAL_OK) &&
802 (wmodes & HAL_MODE_HT20)) {
803 device_printf(sc->sc_dev,
804 "[HT] enabling short-GI in 20MHz mode\n");
805 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20;
808 if (wmodes & HAL_MODE_HT40)
809 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40
810 | IEEE80211_HTCAP_SHORTGI40;
813 * TX/RX streams need to be taken into account when
814 * negotiating which MCS rates it'll receive and
815 * what MCS rates are available for TX.
817 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &txs);
818 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &rxs);
819 ic->ic_txstream = txs;
820 ic->ic_rxstream = rxs;
823 * Setup TX and RX STBC based on what the HAL allows and
824 * the currently configured chainmask set.
825 * Ie - don't enable STBC TX if only one chain is enabled.
826 * STBC RX is fine on a single RX chain; it just won't
827 * provide any real benefit.
829 if (ath_hal_getcapability(ah, HAL_CAP_RX_STBC, 0,
832 device_printf(sc->sc_dev,
833 "[HT] 1 stream STBC receive enabled\n");
834 ic->ic_htcaps |= IEEE80211_HTCAP_RXSTBC_1STREAM;
836 if (txs > 1 && ath_hal_getcapability(ah, HAL_CAP_TX_STBC, 0,
839 device_printf(sc->sc_dev,
840 "[HT] 1 stream STBC transmit enabled\n");
841 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC;
844 (void) ath_hal_getcapability(ah, HAL_CAP_RTS_AGGR_LIMIT, 1,
845 &sc->sc_rts_aggr_limit);
846 if (sc->sc_rts_aggr_limit != (64 * 1024))
847 device_printf(sc->sc_dev,
848 "[HT] RTS aggregates limited to %d KiB\n",
849 sc->sc_rts_aggr_limit / 1024);
851 device_printf(sc->sc_dev,
852 "[HT] %d RX streams; %d TX streams\n", rxs, txs);
857 * Initial aggregation settings.
859 sc->sc_hwq_limit_aggr = ATH_AGGR_MIN_QDEPTH;
860 sc->sc_hwq_limit_nonaggr = ATH_NONAGGR_MIN_QDEPTH;
861 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW;
862 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH;
863 sc->sc_aggr_limit = ATH_AGGR_MAXSIZE;
864 sc->sc_delim_min_pad = 0;
867 * Check if the hardware requires PCI register serialisation.
868 * Some of the Owl based MACs require this.
871 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR,
872 0, NULL) == HAL_OK) {
873 sc->sc_ah->ah_config.ah_serialise_reg_war = 1;
874 device_printf(sc->sc_dev,
875 "Enabling register serialisation\n");
879 * Initialise the deferred completed RX buffer list.
881 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP]);
882 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP]);
885 * Indicate we need the 802.11 header padded to a
886 * 32-bit boundary for 4-address and QoS frames.
888 ic->ic_flags |= IEEE80211_F_DATAPAD;
891 * Query the hal about antenna support.
893 sc->sc_defant = ath_hal_getdefantenna(ah);
896 * Not all chips have the VEOL support we want to
897 * use with IBSS beacons; check here for it.
899 sc->sc_hasveol = ath_hal_hasveol(ah);
901 /* get mac address from hardware */
902 ath_hal_getmac(ah, macaddr);
904 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask);
906 /* NB: used to size node table key mapping array */
907 ic->ic_max_keyix = sc->sc_keymax;
908 /* call MI attach routine. */
909 ieee80211_ifattach(ic, macaddr);
910 ic->ic_setregdomain = ath_setregdomain;
911 ic->ic_getradiocaps = ath_getradiocaps;
912 sc->sc_opmode = HAL_M_STA;
914 /* override default methods */
915 ic->ic_newassoc = ath_newassoc;
916 ic->ic_updateslot = ath_updateslot;
917 ic->ic_wme.wme_update = ath_wme_update;
918 ic->ic_vap_create = ath_vap_create;
919 ic->ic_vap_delete = ath_vap_delete;
920 ic->ic_raw_xmit = ath_raw_xmit;
921 ic->ic_update_mcast = ath_update_mcast;
922 ic->ic_update_promisc = ath_update_promisc;
923 ic->ic_node_alloc = ath_node_alloc;
924 sc->sc_node_free = ic->ic_node_free;
925 ic->ic_node_free = ath_node_free;
926 sc->sc_node_cleanup = ic->ic_node_cleanup;
927 ic->ic_node_cleanup = ath_node_cleanup;
928 ic->ic_node_getsignal = ath_node_getsignal;
929 ic->ic_scan_start = ath_scan_start;
930 ic->ic_scan_end = ath_scan_end;
931 ic->ic_set_channel = ath_set_channel;
932 #ifdef ATH_ENABLE_11N
933 /* 802.11n specific - but just override anyway */
934 sc->sc_addba_request = ic->ic_addba_request;
935 sc->sc_addba_response = ic->ic_addba_response;
936 sc->sc_addba_stop = ic->ic_addba_stop;
937 sc->sc_bar_response = ic->ic_bar_response;
938 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout;
940 ic->ic_addba_request = ath_addba_request;
941 ic->ic_addba_response = ath_addba_response;
942 ic->ic_addba_response_timeout = ath_addba_response_timeout;
943 ic->ic_addba_stop = ath_addba_stop;
944 ic->ic_bar_response = ath_bar_response;
946 ic->ic_update_chw = ath_update_chw;
947 #endif /* ATH_ENABLE_11N */
949 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
951 * There's one vendor bitmap entry in the RX radiotap
952 * header; make sure that's taken into account.
954 ieee80211_radiotap_attachv(ic,
955 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 0,
956 ATH_TX_RADIOTAP_PRESENT,
957 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1,
958 ATH_RX_RADIOTAP_PRESENT);
961 * No vendor bitmap/extensions are present.
963 ieee80211_radiotap_attach(ic,
964 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
965 ATH_TX_RADIOTAP_PRESENT,
966 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
967 ATH_RX_RADIOTAP_PRESENT);
968 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
971 * Setup the ALQ logging if required
974 if_ath_alq_init(&sc->sc_alq, device_get_nameunit(sc->sc_dev));
975 if_ath_alq_setcfg(&sc->sc_alq,
976 sc->sc_ah->ah_macVersion,
977 sc->sc_ah->ah_macRev,
978 sc->sc_ah->ah_phyRev,
979 sc->sc_ah->ah_magic);
983 * Setup dynamic sysctl's now that country code and
984 * regdomain are available from the hal.
986 ath_sysctlattach(sc);
987 ath_sysctl_stats_attach(sc);
988 ath_sysctl_hal_attach(sc);
991 ieee80211_announce(ic);
997 ath_txdma_teardown(sc);
998 ath_rxdma_teardown(sc);
1004 * To work around scoping issues with CURVNET_SET/CURVNET_RESTORE..
1006 if (ifp != NULL && ifp->if_vnet) {
1007 CURVNET_SET(ifp->if_vnet);
1010 } else if (ifp != NULL)
1017 ath_detach(struct ath_softc *sc)
1019 struct ifnet *ifp = sc->sc_ifp;
1021 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1022 __func__, ifp->if_flags);
1025 * NB: the order of these is important:
1026 * o stop the chip so no more interrupts will fire
1027 * o call the 802.11 layer before detaching the hal to
1028 * insure callbacks into the driver to delete global
1029 * key cache entries can be handled
1030 * o free the taskqueue which drains any pending tasks
1031 * o reclaim the tx queue data structures after calling
1032 * the 802.11 layer as we'll get called back to reclaim
1033 * node state and potentially want to use them
1034 * o to cleanup the tx queues the hal is called, so detach
1036 * Other than that, it's straightforward...
1039 ieee80211_ifdetach(ifp->if_l2com);
1040 taskqueue_free(sc->sc_tq);
1041 #ifdef ATH_TX99_DIAG
1042 if (sc->sc_tx99 != NULL)
1043 sc->sc_tx99->detach(sc->sc_tx99);
1045 ath_rate_detach(sc->sc_rc);
1046 #ifdef ATH_DEBUG_ALQ
1047 if_ath_alq_tidyup(&sc->sc_alq);
1049 ath_lna_div_detach(sc);
1050 ath_btcoex_detach(sc);
1051 ath_spectral_detach(sc);
1054 ath_txdma_teardown(sc);
1055 ath_rxdma_teardown(sc);
1057 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */
1059 CURVNET_SET(ifp->if_vnet);
1067 * MAC address handling for multiple BSS on the same radio.
1068 * The first vap uses the MAC address from the EEPROM. For
1069 * subsequent vap's we set the U/L bit (bit 1) in the MAC
1070 * address and use the next six bits as an index.
1073 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone)
1077 if (clone && sc->sc_hasbmask) {
1078 /* NB: we only do this if h/w supports multiple bssid */
1079 for (i = 0; i < 8; i++)
1080 if ((sc->sc_bssidmask & (1<<i)) == 0)
1083 mac[0] |= (i << 2)|0x2;
1086 sc->sc_bssidmask |= 1<<i;
1087 sc->sc_hwbssidmask[0] &= ~mac[0];
1093 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN])
1095 int i = mac[0] >> 2;
1098 if (i != 0 || --sc->sc_nbssid0 == 0) {
1099 sc->sc_bssidmask &= ~(1<<i);
1100 /* recalculate bssid mask from remaining addresses */
1102 for (i = 1; i < 8; i++)
1103 if (sc->sc_bssidmask & (1<<i))
1104 mask &= ~((i<<2)|0x2);
1105 sc->sc_hwbssidmask[0] |= mask;
1110 * Assign a beacon xmit slot. We try to space out
1111 * assignments so when beacons are staggered the
1112 * traffic coming out of the cab q has maximal time
1113 * to go out before the next beacon is scheduled.
1116 assign_bslot(struct ath_softc *sc)
1121 for (slot = 0; slot < ATH_BCBUF; slot++)
1122 if (sc->sc_bslot[slot] == NULL) {
1123 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL &&
1124 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL)
1127 /* NB: keep looking for a double slot */
1132 static struct ieee80211vap *
1133 ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1134 enum ieee80211_opmode opmode, int flags,
1135 const uint8_t bssid[IEEE80211_ADDR_LEN],
1136 const uint8_t mac0[IEEE80211_ADDR_LEN])
1138 struct ath_softc *sc = ic->ic_ifp->if_softc;
1139 struct ath_vap *avp;
1140 struct ieee80211vap *vap;
1141 uint8_t mac[IEEE80211_ADDR_LEN];
1142 int needbeacon, error;
1143 enum ieee80211_opmode ic_opmode;
1145 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap),
1146 M_80211_VAP, M_WAITOK | M_ZERO);
1148 IEEE80211_ADDR_COPY(mac, mac0);
1151 ic_opmode = opmode; /* default to opmode of new vap */
1153 case IEEE80211_M_STA:
1154 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */
1155 device_printf(sc->sc_dev, "only 1 sta vap supported\n");
1160 * With multiple vaps we must fall back
1161 * to s/w beacon miss handling.
1163 flags |= IEEE80211_CLONE_NOBEACONS;
1165 if (flags & IEEE80211_CLONE_NOBEACONS) {
1167 * Station mode w/o beacons are implemented w/ AP mode.
1169 ic_opmode = IEEE80211_M_HOSTAP;
1172 case IEEE80211_M_IBSS:
1173 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */
1174 device_printf(sc->sc_dev,
1175 "only 1 ibss vap supported\n");
1180 case IEEE80211_M_AHDEMO:
1181 #ifdef IEEE80211_SUPPORT_TDMA
1182 if (flags & IEEE80211_CLONE_TDMA) {
1183 if (sc->sc_nvaps != 0) {
1184 device_printf(sc->sc_dev,
1185 "only 1 tdma vap supported\n");
1189 flags |= IEEE80211_CLONE_NOBEACONS;
1193 case IEEE80211_M_MONITOR:
1194 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) {
1196 * Adopt existing mode. Adding a monitor or ahdemo
1197 * vap to an existing configuration is of dubious
1198 * value but should be ok.
1200 /* XXX not right for monitor mode */
1201 ic_opmode = ic->ic_opmode;
1204 case IEEE80211_M_HOSTAP:
1205 case IEEE80211_M_MBSS:
1208 case IEEE80211_M_WDS:
1209 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) {
1210 device_printf(sc->sc_dev,
1211 "wds not supported in sta mode\n");
1215 * Silently remove any request for a unique
1216 * bssid; WDS vap's always share the local
1219 flags &= ~IEEE80211_CLONE_BSSID;
1220 if (sc->sc_nvaps == 0)
1221 ic_opmode = IEEE80211_M_HOSTAP;
1223 ic_opmode = ic->ic_opmode;
1226 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
1230 * Check that a beacon buffer is available; the code below assumes it.
1232 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) {
1233 device_printf(sc->sc_dev, "no beacon buffer available\n");
1238 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) {
1239 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID);
1240 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1244 /* XXX can't hold mutex across if_alloc */
1246 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags,
1250 device_printf(sc->sc_dev, "%s: error %d creating vap\n",
1255 /* h/w crypto support */
1256 vap->iv_key_alloc = ath_key_alloc;
1257 vap->iv_key_delete = ath_key_delete;
1258 vap->iv_key_set = ath_key_set;
1259 vap->iv_key_update_begin = ath_key_update_begin;
1260 vap->iv_key_update_end = ath_key_update_end;
1262 /* override various methods */
1263 avp->av_recv_mgmt = vap->iv_recv_mgmt;
1264 vap->iv_recv_mgmt = ath_recv_mgmt;
1265 vap->iv_reset = ath_reset_vap;
1266 vap->iv_update_beacon = ath_beacon_update;
1267 avp->av_newstate = vap->iv_newstate;
1268 vap->iv_newstate = ath_newstate;
1269 avp->av_bmiss = vap->iv_bmiss;
1270 vap->iv_bmiss = ath_bmiss_vap;
1272 avp->av_node_ps = vap->iv_node_ps;
1273 vap->iv_node_ps = ath_node_powersave;
1275 avp->av_set_tim = vap->iv_set_tim;
1276 vap->iv_set_tim = ath_node_set_tim;
1278 avp->av_recv_pspoll = vap->iv_recv_pspoll;
1279 vap->iv_recv_pspoll = ath_node_recv_pspoll;
1281 /* Set default parameters */
1284 * Anything earlier than some AR9300 series MACs don't
1285 * support a smaller MPDU density.
1287 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8;
1289 * All NICs can handle the maximum size, however
1290 * AR5416 based MACs can only TX aggregates w/ RTS
1291 * protection when the total aggregate size is <= 8k.
1292 * However, for now that's enforced by the TX path.
1294 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K;
1299 * Allocate beacon state and setup the q for buffered
1300 * multicast frames. We know a beacon buffer is
1301 * available because we checked above.
1303 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf);
1304 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list);
1305 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) {
1307 * Assign the vap to a beacon xmit slot. As above
1308 * this cannot fail to find a free one.
1310 avp->av_bslot = assign_bslot(sc);
1311 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL,
1312 ("beacon slot %u not empty", avp->av_bslot));
1313 sc->sc_bslot[avp->av_bslot] = vap;
1316 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) {
1318 * Multple vaps are to transmit beacons and we
1319 * have h/w support for TSF adjusting; enable
1320 * use of staggered beacons.
1322 sc->sc_stagbeacons = 1;
1324 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ);
1327 ic->ic_opmode = ic_opmode;
1328 if (opmode != IEEE80211_M_WDS) {
1330 if (opmode == IEEE80211_M_STA)
1332 if (opmode == IEEE80211_M_MBSS)
1335 switch (ic_opmode) {
1336 case IEEE80211_M_IBSS:
1337 sc->sc_opmode = HAL_M_IBSS;
1339 case IEEE80211_M_STA:
1340 sc->sc_opmode = HAL_M_STA;
1342 case IEEE80211_M_AHDEMO:
1343 #ifdef IEEE80211_SUPPORT_TDMA
1344 if (vap->iv_caps & IEEE80211_C_TDMA) {
1346 /* NB: disable tsf adjust */
1347 sc->sc_stagbeacons = 0;
1350 * NB: adhoc demo mode is a pseudo mode; to the hal it's
1355 case IEEE80211_M_HOSTAP:
1356 case IEEE80211_M_MBSS:
1357 sc->sc_opmode = HAL_M_HOSTAP;
1359 case IEEE80211_M_MONITOR:
1360 sc->sc_opmode = HAL_M_MONITOR;
1363 /* XXX should not happen */
1366 if (sc->sc_hastsfadd) {
1368 * Configure whether or not TSF adjust should be done.
1370 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons);
1372 if (flags & IEEE80211_CLONE_NOBEACONS) {
1374 * Enable s/w beacon miss handling.
1380 /* complete setup */
1381 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status);
1384 reclaim_address(sc, mac);
1385 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1387 free(avp, M_80211_VAP);
1393 ath_vap_delete(struct ieee80211vap *vap)
1395 struct ieee80211com *ic = vap->iv_ic;
1396 struct ifnet *ifp = ic->ic_ifp;
1397 struct ath_softc *sc = ifp->if_softc;
1398 struct ath_hal *ah = sc->sc_ah;
1399 struct ath_vap *avp = ATH_VAP(vap);
1401 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
1402 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1404 * Quiesce the hardware while we remove the vap. In
1405 * particular we need to reclaim all references to
1406 * the vap state by any frames pending on the tx queues.
1408 ath_hal_intrset(ah, 0); /* disable interrupts */
1409 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */
1410 /* XXX Do all frames from all vaps/nodes need draining here? */
1411 ath_stoprecv(sc, 1); /* stop recv side */
1414 ieee80211_vap_detach(vap);
1417 * XXX Danger Will Robinson! Danger!
1419 * Because ieee80211_vap_detach() can queue a frame (the station
1420 * diassociate message?) after we've drained the TXQ and
1421 * flushed the software TXQ, we will end up with a frame queued
1422 * to a node whose vap is about to be freed.
1424 * To work around this, flush the hardware/software again.
1425 * This may be racy - the ath task may be running and the packet
1426 * may be being scheduled between sw->hw txq. Tsk.
1428 * TODO: figure out why a new node gets allocated somewhere around
1429 * here (after the ath_tx_swq() call; and after an ath_stop_locked()
1433 ath_draintxq(sc, ATH_RESET_DEFAULT);
1437 * Reclaim beacon state. Note this must be done before
1438 * the vap instance is reclaimed as we may have a reference
1439 * to it in the buffer for the beacon frame.
1441 if (avp->av_bcbuf != NULL) {
1442 if (avp->av_bslot != -1) {
1443 sc->sc_bslot[avp->av_bslot] = NULL;
1446 ath_beacon_return(sc, avp->av_bcbuf);
1447 avp->av_bcbuf = NULL;
1448 if (sc->sc_nbcnvaps == 0) {
1449 sc->sc_stagbeacons = 0;
1450 if (sc->sc_hastsfadd)
1451 ath_hal_settsfadjust(sc->sc_ah, 0);
1454 * Reclaim any pending mcast frames for the vap.
1456 ath_tx_draintxq(sc, &avp->av_mcastq);
1459 * Update bookkeeping.
1461 if (vap->iv_opmode == IEEE80211_M_STA) {
1463 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss)
1465 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
1466 vap->iv_opmode == IEEE80211_M_MBSS) {
1467 reclaim_address(sc, vap->iv_myaddr);
1468 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask);
1469 if (vap->iv_opmode == IEEE80211_M_MBSS)
1472 if (vap->iv_opmode != IEEE80211_M_WDS)
1474 #ifdef IEEE80211_SUPPORT_TDMA
1475 /* TDMA operation ceases when the last vap is destroyed */
1476 if (sc->sc_tdma && sc->sc_nvaps == 0) {
1481 free(avp, M_80211_VAP);
1483 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1485 * Restart rx+tx machines if still running (RUNNING will
1486 * be reset if we just destroyed the last vap).
1488 if (ath_startrecv(sc) != 0)
1489 if_printf(ifp, "%s: unable to restart recv logic\n",
1491 if (sc->sc_beacons) { /* restart beacons */
1492 #ifdef IEEE80211_SUPPORT_TDMA
1494 ath_tdma_config(sc, NULL);
1497 ath_beacon_config(sc, NULL);
1499 ath_hal_intrset(ah, sc->sc_imask);
1505 ath_suspend(struct ath_softc *sc)
1507 struct ifnet *ifp = sc->sc_ifp;
1508 struct ieee80211com *ic = ifp->if_l2com;
1510 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1511 __func__, ifp->if_flags);
1513 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0;
1515 ieee80211_suspend_all(ic);
1517 * NB: don't worry about putting the chip in low power
1518 * mode; pci will power off our socket on suspend and
1519 * CardBus detaches the device.
1523 * XXX ensure none of the taskqueues are running
1524 * XXX ensure sc_invalid is 1
1525 * XXX ensure the calibration callout is disabled
1528 /* Disable the PCIe PHY, complete with workarounds */
1529 ath_hal_enablepcie(sc->sc_ah, 1, 1);
1533 * Reset the key cache since some parts do not reset the
1534 * contents on resume. First we clear all entries, then
1535 * re-load keys that the 802.11 layer assumes are setup
1539 ath_reset_keycache(struct ath_softc *sc)
1541 struct ifnet *ifp = sc->sc_ifp;
1542 struct ieee80211com *ic = ifp->if_l2com;
1543 struct ath_hal *ah = sc->sc_ah;
1546 for (i = 0; i < sc->sc_keymax; i++)
1547 ath_hal_keyreset(ah, i);
1548 ieee80211_crypto_reload_keys(ic);
1552 * Fetch the current chainmask configuration based on the current
1553 * operating channel and options.
1556 ath_update_chainmasks(struct ath_softc *sc, struct ieee80211_channel *chan)
1560 * Set TX chainmask to the currently configured chainmask;
1561 * the TX chainmask depends upon the current operating mode.
1563 sc->sc_cur_rxchainmask = sc->sc_rxchainmask;
1564 if (IEEE80211_IS_CHAN_HT(chan)) {
1565 sc->sc_cur_txchainmask = sc->sc_txchainmask;
1567 sc->sc_cur_txchainmask = 1;
1570 DPRINTF(sc, ATH_DEBUG_RESET,
1571 "%s: TX chainmask is now 0x%x, RX is now 0x%x\n",
1573 sc->sc_cur_txchainmask,
1574 sc->sc_cur_rxchainmask);
1578 ath_resume(struct ath_softc *sc)
1580 struct ifnet *ifp = sc->sc_ifp;
1581 struct ieee80211com *ic = ifp->if_l2com;
1582 struct ath_hal *ah = sc->sc_ah;
1585 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1586 __func__, ifp->if_flags);
1588 /* Re-enable PCIe, re-enable the PCIe bus */
1589 ath_hal_enablepcie(ah, 0, 0);
1592 * Must reset the chip before we reload the
1593 * keycache as we were powered down on suspend.
1595 ath_update_chainmasks(sc,
1596 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan);
1597 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
1598 sc->sc_cur_rxchainmask);
1599 ath_hal_reset(ah, sc->sc_opmode,
1600 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan,
1602 ath_reset_keycache(sc);
1604 /* Let DFS at it in case it's a DFS channel */
1605 ath_dfs_radar_enable(sc, ic->ic_curchan);
1607 /* Let spectral at in case spectral is enabled */
1608 ath_spectral_enable(sc, ic->ic_curchan);
1611 * Let bluetooth coexistence at in case it's needed for this channel
1613 ath_btcoex_enable(sc, ic->ic_curchan);
1616 * If we're doing TDMA, enforce the TXOP limitation for chips that
1619 if (sc->sc_hasenforcetxop && sc->sc_tdma)
1620 ath_hal_setenforcetxop(sc->sc_ah, 1);
1622 ath_hal_setenforcetxop(sc->sc_ah, 0);
1624 /* Restore the LED configuration */
1626 ath_hal_setledstate(ah, HAL_LED_INIT);
1628 if (sc->sc_resume_up)
1629 ieee80211_resume_all(ic);
1635 ath_shutdown(struct ath_softc *sc)
1637 struct ifnet *ifp = sc->sc_ifp;
1639 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1640 __func__, ifp->if_flags);
1643 /* NB: no point powering down chip as we're about to reboot */
1647 * Interrupt handler. Most of the actual processing is deferred.
1652 struct ath_softc *sc = arg;
1653 struct ifnet *ifp = sc->sc_ifp;
1654 struct ath_hal *ah = sc->sc_ah;
1659 * If we're inside a reset path, just print a warning and
1660 * clear the ISR. The reset routine will finish it for us.
1663 if (sc->sc_inreset_cnt) {
1665 ath_hal_getisr(ah, &status); /* clear ISR */
1666 ath_hal_intrset(ah, 0); /* disable further intr's */
1667 DPRINTF(sc, ATH_DEBUG_ANY,
1668 "%s: in reset, ignoring: status=0x%x\n",
1674 if (sc->sc_invalid) {
1676 * The hardware is not ready/present, don't touch anything.
1677 * Note this can happen early on if the IRQ is shared.
1679 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
1683 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */
1688 if ((ifp->if_flags & IFF_UP) == 0 ||
1689 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1692 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
1693 __func__, ifp->if_flags);
1694 ath_hal_getisr(ah, &status); /* clear ISR */
1695 ath_hal_intrset(ah, 0); /* disable further intr's */
1701 * Figure out the reason(s) for the interrupt. Note
1702 * that the hal returns a pseudo-ISR that may include
1703 * bits we haven't explicitly enabled so we mask the
1704 * value to insure we only process bits we requested.
1706 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
1707 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
1708 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1, "ath_intr: mask=0x%.8x", status);
1709 #ifdef ATH_DEBUG_ALQ
1710 if_ath_alq_post_intr(&sc->sc_alq, status, ah->ah_intrstate,
1712 #endif /* ATH_DEBUG_ALQ */
1713 #ifdef ATH_KTR_INTR_DEBUG
1714 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 5,
1715 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x",
1716 ah->ah_intrstate[0],
1717 ah->ah_intrstate[1],
1718 ah->ah_intrstate[2],
1719 ah->ah_intrstate[3],
1720 ah->ah_intrstate[6]);
1723 /* Squirrel away SYNC interrupt debugging */
1724 if (ah->ah_syncstate != 0) {
1726 for (i = 0; i < 32; i++)
1727 if (ah->ah_syncstate & (i << i))
1728 sc->sc_intr_stats.sync_intr[i]++;
1731 status &= sc->sc_imask; /* discard unasked for bits */
1733 /* Short-circuit un-handled interrupts */
1734 if (status == 0x0) {
1740 * Take a note that we're inside the interrupt handler, so
1741 * the reset routines know to wait.
1747 * Handle the interrupt. We won't run concurrent with the reset
1748 * or channel change routines as they'll wait for sc_intr_cnt
1749 * to be 0 before continuing.
1751 if (status & HAL_INT_FATAL) {
1752 sc->sc_stats.ast_hardware++;
1753 ath_hal_intrset(ah, 0); /* disable intr's until reset */
1754 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask);
1756 if (status & HAL_INT_SWBA) {
1758 * Software beacon alert--time to send a beacon.
1759 * Handle beacon transmission directly; deferring
1760 * this is too slow to meet timing constraints
1763 #ifdef IEEE80211_SUPPORT_TDMA
1765 if (sc->sc_tdmaswba == 0) {
1766 struct ieee80211com *ic = ifp->if_l2com;
1767 struct ieee80211vap *vap =
1768 TAILQ_FIRST(&ic->ic_vaps);
1769 ath_tdma_beacon_send(sc, vap);
1771 vap->iv_tdma->tdma_bintval;
1777 ath_beacon_proc(sc, 0);
1778 #ifdef IEEE80211_SUPPORT_SUPERG
1780 * Schedule the rx taskq in case there's no
1781 * traffic so any frames held on the staging
1782 * queue are aged and potentially flushed.
1784 sc->sc_rx.recv_sched(sc, 1);
1788 if (status & HAL_INT_RXEOL) {
1790 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXEOL");
1793 * NB: the hardware should re-read the link when
1794 * RXE bit is written, but it doesn't work at
1795 * least on older hardware revs.
1797 sc->sc_stats.ast_rxeol++;
1799 * Disable RXEOL/RXORN - prevent an interrupt
1800 * storm until the PCU logic can be reset.
1801 * In case the interface is reset some other
1802 * way before "sc_kickpcu" is called, don't
1803 * modify sc_imask - that way if it is reset
1804 * by a call to ath_reset() somehow, the
1805 * interrupt mask will be correctly reprogrammed.
1807 imask = sc->sc_imask;
1808 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN);
1809 ath_hal_intrset(ah, imask);
1811 * Only blank sc_rxlink if we've not yet kicked
1814 * This isn't entirely correct - the correct solution
1815 * would be to have a PCU lock and engage that for
1816 * the duration of the PCU fiddling; which would include
1817 * running the RX process. Otherwise we could end up
1818 * messing up the RX descriptor chain and making the
1819 * RX desc list much shorter.
1821 if (! sc->sc_kickpcu)
1822 sc->sc_rxlink = NULL;
1826 * Enqueue an RX proc, to handled whatever
1827 * is in the RX queue.
1828 * This will then kick the PCU.
1830 sc->sc_rx.recv_sched(sc, 1);
1832 if (status & HAL_INT_TXURN) {
1833 sc->sc_stats.ast_txurn++;
1834 /* bump tx trigger level */
1835 ath_hal_updatetxtriglevel(ah, AH_TRUE);
1838 * Handle both the legacy and RX EDMA interrupt bits.
1839 * Note that HAL_INT_RXLP is also HAL_INT_RXDESC.
1841 if (status & (HAL_INT_RX | HAL_INT_RXHP | HAL_INT_RXLP)) {
1842 sc->sc_stats.ast_rx_intr++;
1843 sc->sc_rx.recv_sched(sc, 1);
1845 if (status & HAL_INT_TX) {
1846 sc->sc_stats.ast_tx_intr++;
1848 * Grab all the currently set bits in the HAL txq bitmap
1849 * and blank them. This is the only place we should be
1852 if (! sc->sc_isedma) {
1855 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs);
1856 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 3,
1857 "ath_intr: TX; txqs=0x%08x, txq_active was 0x%08x, now 0x%08x",
1860 sc->sc_txq_active | txqs);
1861 sc->sc_txq_active |= txqs;
1864 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
1866 if (status & HAL_INT_BMISS) {
1867 sc->sc_stats.ast_bmiss++;
1868 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
1870 if (status & HAL_INT_GTT)
1871 sc->sc_stats.ast_tx_timeout++;
1872 if (status & HAL_INT_CST)
1873 sc->sc_stats.ast_tx_cst++;
1874 if (status & HAL_INT_MIB) {
1875 sc->sc_stats.ast_mib++;
1878 * Disable interrupts until we service the MIB
1879 * interrupt; otherwise it will continue to fire.
1881 ath_hal_intrset(ah, 0);
1883 * Let the hal handle the event. We assume it will
1884 * clear whatever condition caused the interrupt.
1886 ath_hal_mibevent(ah, &sc->sc_halstats);
1888 * Don't reset the interrupt if we've just
1889 * kicked the PCU, or we may get a nested
1890 * RXEOL before the rxproc has had a chance
1893 if (sc->sc_kickpcu == 0)
1894 ath_hal_intrset(ah, sc->sc_imask);
1897 if (status & HAL_INT_RXORN) {
1898 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */
1899 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXORN");
1900 sc->sc_stats.ast_rxorn++;
1909 ath_fatal_proc(void *arg, int pending)
1911 struct ath_softc *sc = arg;
1912 struct ifnet *ifp = sc->sc_ifp;
1917 if_printf(ifp, "hardware error; resetting\n");
1919 * Fatal errors are unrecoverable. Typically these
1920 * are caused by DMA errors. Collect h/w state from
1921 * the hal so we can diagnose what's going on.
1923 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) {
1924 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len));
1926 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n",
1927 state[0], state[1] , state[2], state[3],
1928 state[4], state[5]);
1930 ath_reset(ifp, ATH_RESET_NOLOSS);
1934 ath_bmiss_vap(struct ieee80211vap *vap)
1937 * Workaround phantom bmiss interrupts by sanity-checking
1938 * the time of our last rx'd frame. If it is within the
1939 * beacon miss interval then ignore the interrupt. If it's
1940 * truly a bmiss we'll get another interrupt soon and that'll
1941 * be dispatched up for processing. Note this applies only
1942 * for h/w beacon miss events.
1944 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) {
1945 struct ifnet *ifp = vap->iv_ic->ic_ifp;
1946 struct ath_softc *sc = ifp->if_softc;
1947 u_int64_t lastrx = sc->sc_lastrx;
1948 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
1949 /* XXX should take a locked ref to iv_bss */
1950 u_int bmisstimeout =
1951 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024;
1953 DPRINTF(sc, ATH_DEBUG_BEACON,
1954 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
1955 __func__, (unsigned long long) tsf,
1956 (unsigned long long)(tsf - lastrx),
1957 (unsigned long long) lastrx, bmisstimeout);
1959 if (tsf - lastrx <= bmisstimeout) {
1960 sc->sc_stats.ast_bmiss_phantom++;
1964 ATH_VAP(vap)->av_bmiss(vap);
1968 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs)
1973 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize))
1975 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize));
1976 *hangs = *(uint32_t *)sp;
1981 ath_bmiss_proc(void *arg, int pending)
1983 struct ath_softc *sc = arg;
1984 struct ifnet *ifp = sc->sc_ifp;
1987 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
1990 * Do a reset upon any becaon miss event.
1992 * It may be a non-recognised RX clear hang which needs a reset
1995 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) {
1996 ath_reset(ifp, ATH_RESET_NOLOSS);
1997 if_printf(ifp, "bb hang detected (0x%x), resetting\n", hangs);
1999 ath_reset(ifp, ATH_RESET_NOLOSS);
2000 ieee80211_beacon_miss(ifp->if_l2com);
2005 * Handle TKIP MIC setup to deal hardware that doesn't do MIC
2006 * calcs together with WME. If necessary disable the crypto
2007 * hardware and mark the 802.11 state so keys will be setup
2008 * with the MIC work done in software.
2011 ath_settkipmic(struct ath_softc *sc)
2013 struct ifnet *ifp = sc->sc_ifp;
2014 struct ieee80211com *ic = ifp->if_l2com;
2016 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) {
2017 if (ic->ic_flags & IEEE80211_F_WME) {
2018 ath_hal_settkipmic(sc->sc_ah, AH_FALSE);
2019 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC;
2021 ath_hal_settkipmic(sc->sc_ah, AH_TRUE);
2022 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
2030 struct ath_softc *sc = (struct ath_softc *) arg;
2031 struct ifnet *ifp = sc->sc_ifp;
2032 struct ieee80211com *ic = ifp->if_l2com;
2033 struct ath_hal *ah = sc->sc_ah;
2036 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
2037 __func__, ifp->if_flags);
2041 * Stop anything previously setup. This is safe
2042 * whether this is the first time through or not.
2044 ath_stop_locked(ifp);
2047 * The basic interface to setting the hardware in a good
2048 * state is ``reset''. On return the hardware is known to
2049 * be powered up and with interrupts disabled. This must
2050 * be followed by initialization of the appropriate bits
2051 * and then setup of the interrupt mask.
2054 ath_update_chainmasks(sc, ic->ic_curchan);
2055 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2056 sc->sc_cur_rxchainmask);
2057 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) {
2058 if_printf(ifp, "unable to reset hardware; hal status %u\n",
2063 ath_chan_change(sc, ic->ic_curchan);
2065 /* Let DFS at it in case it's a DFS channel */
2066 ath_dfs_radar_enable(sc, ic->ic_curchan);
2068 /* Let spectral at in case spectral is enabled */
2069 ath_spectral_enable(sc, ic->ic_curchan);
2072 * Let bluetooth coexistence at in case it's needed for this channel
2074 ath_btcoex_enable(sc, ic->ic_curchan);
2077 * If we're doing TDMA, enforce the TXOP limitation for chips that
2080 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2081 ath_hal_setenforcetxop(sc->sc_ah, 1);
2083 ath_hal_setenforcetxop(sc->sc_ah, 0);
2086 * Likewise this is set during reset so update
2087 * state cached in the driver.
2089 sc->sc_diversity = ath_hal_getdiversity(ah);
2090 sc->sc_lastlongcal = 0;
2091 sc->sc_resetcal = 1;
2092 sc->sc_lastcalreset = 0;
2094 sc->sc_lastshortcal = 0;
2095 sc->sc_doresetcal = AH_FALSE;
2097 * Beacon timers were cleared here; give ath_newstate()
2098 * a hint that the beacon timers should be poked when
2099 * things transition to the RUN state.
2104 * Setup the hardware after reset: the key cache
2105 * is filled as needed and the receive engine is
2106 * set going. Frame transmit is handled entirely
2107 * in the frame output path; there's nothing to do
2108 * here except setup the interrupt mask.
2110 if (ath_startrecv(sc) != 0) {
2111 if_printf(ifp, "unable to start recv logic\n");
2117 * Enable interrupts.
2119 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
2120 | HAL_INT_RXEOL | HAL_INT_RXORN
2122 | HAL_INT_FATAL | HAL_INT_GLOBAL;
2125 * Enable RX EDMA bits. Note these overlap with
2126 * HAL_INT_RX and HAL_INT_RXDESC respectively.
2129 sc->sc_imask |= (HAL_INT_RXHP | HAL_INT_RXLP);
2132 * Enable MIB interrupts when there are hardware phy counters.
2133 * Note we only do this (at the moment) for station mode.
2135 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
2136 sc->sc_imask |= HAL_INT_MIB;
2138 /* Enable global TX timeout and carrier sense timeout if available */
2139 if (ath_hal_gtxto_supported(ah))
2140 sc->sc_imask |= HAL_INT_GTT;
2142 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n",
2143 __func__, sc->sc_imask);
2145 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2146 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc);
2147 ath_hal_intrset(ah, sc->sc_imask);
2151 #ifdef ATH_TX99_DIAG
2152 if (sc->sc_tx99 != NULL)
2153 sc->sc_tx99->start(sc->sc_tx99);
2156 ieee80211_start_all(ic); /* start all vap's */
2160 ath_stop_locked(struct ifnet *ifp)
2162 struct ath_softc *sc = ifp->if_softc;
2163 struct ath_hal *ah = sc->sc_ah;
2165 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
2166 __func__, sc->sc_invalid, ifp->if_flags);
2168 ATH_LOCK_ASSERT(sc);
2169 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2171 * Shutdown the hardware and driver:
2172 * reset 802.11 state machine
2174 * disable interrupts
2175 * turn off the radio
2176 * clear transmit machinery
2177 * clear receive machinery
2178 * drain and release tx queues
2179 * reclaim beacon resources
2180 * power down hardware
2182 * Note that some of this work is not possible if the
2183 * hardware is gone (invalid).
2185 #ifdef ATH_TX99_DIAG
2186 if (sc->sc_tx99 != NULL)
2187 sc->sc_tx99->stop(sc->sc_tx99);
2189 callout_stop(&sc->sc_wd_ch);
2190 sc->sc_wd_timer = 0;
2191 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2192 if (!sc->sc_invalid) {
2193 if (sc->sc_softled) {
2194 callout_stop(&sc->sc_ledtimer);
2195 ath_hal_gpioset(ah, sc->sc_ledpin,
2197 sc->sc_blinking = 0;
2199 ath_hal_intrset(ah, 0);
2201 ath_draintxq(sc, ATH_RESET_DEFAULT);
2202 if (!sc->sc_invalid) {
2203 ath_stoprecv(sc, 1);
2204 ath_hal_phydisable(ah);
2206 sc->sc_rxlink = NULL;
2207 ath_beacon_free(sc); /* XXX not needed */
2211 #define MAX_TXRX_ITERATIONS 1000
2213 ath_txrx_stop_locked(struct ath_softc *sc)
2215 int i = MAX_TXRX_ITERATIONS;
2217 ATH_UNLOCK_ASSERT(sc);
2218 ATH_PCU_LOCK_ASSERT(sc);
2221 * Sleep until all the pending operations have completed.
2223 * The caller must ensure that reset has been incremented
2224 * or the pending operations may continue being queued.
2226 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt ||
2227 sc->sc_txstart_cnt || sc->sc_intr_cnt) {
2230 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop", 1);
2235 device_printf(sc->sc_dev,
2236 "%s: didn't finish after %d iterations\n",
2237 __func__, MAX_TXRX_ITERATIONS);
2239 #undef MAX_TXRX_ITERATIONS
2243 ath_txrx_stop(struct ath_softc *sc)
2245 ATH_UNLOCK_ASSERT(sc);
2246 ATH_PCU_UNLOCK_ASSERT(sc);
2249 ath_txrx_stop_locked(sc);
2255 ath_txrx_start(struct ath_softc *sc)
2258 taskqueue_unblock(sc->sc_tq);
2262 * Grab the reset lock, and wait around until noone else
2263 * is trying to do anything with it.
2265 * This is totally horrible but we can't hold this lock for
2266 * long enough to do TX/RX or we end up with net80211/ip stack
2267 * LORs and eventual deadlock.
2269 * "dowait" signals whether to spin, waiting for the reset
2270 * lock count to reach 0. This should (for now) only be used
2271 * during the reset path, as the rest of the code may not
2272 * be locking-reentrant enough to behave correctly.
2274 * Another, cleaner way should be found to serialise all of
2277 #define MAX_RESET_ITERATIONS 10
2279 ath_reset_grablock(struct ath_softc *sc, int dowait)
2282 int i = MAX_RESET_ITERATIONS;
2284 ATH_PCU_LOCK_ASSERT(sc);
2286 if (sc->sc_inreset_cnt == 0) {
2295 pause("ath_reset_grablock", 1);
2301 * We always increment the refcounter, regardless
2302 * of whether we succeeded to get it in an exclusive
2305 sc->sc_inreset_cnt++;
2308 device_printf(sc->sc_dev,
2309 "%s: didn't finish after %d iterations\n",
2310 __func__, MAX_RESET_ITERATIONS);
2313 device_printf(sc->sc_dev,
2314 "%s: warning, recursive reset path!\n",
2319 #undef MAX_RESET_ITERATIONS
2322 * XXX TODO: write ath_reset_releaselock
2326 ath_stop(struct ifnet *ifp)
2328 struct ath_softc *sc = ifp->if_softc;
2331 ath_stop_locked(ifp);
2336 * Reset the hardware w/o losing operational state. This is
2337 * basically a more efficient way of doing ath_stop, ath_init,
2338 * followed by state transitions to the current 802.11
2339 * operational state. Used to recover from various errors and
2340 * to reset or reload hardware state.
2343 ath_reset(struct ifnet *ifp, ATH_RESET_TYPE reset_type)
2345 struct ath_softc *sc = ifp->if_softc;
2346 struct ieee80211com *ic = ifp->if_l2com;
2347 struct ath_hal *ah = sc->sc_ah;
2351 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
2353 /* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */
2354 ATH_PCU_UNLOCK_ASSERT(sc);
2355 ATH_UNLOCK_ASSERT(sc);
2357 /* Try to (stop any further TX/RX from occuring */
2358 taskqueue_block(sc->sc_tq);
2363 * Grab the reset lock before TX/RX is stopped.
2365 * This is needed to ensure that when the TX/RX actually does finish,
2366 * no further TX/RX/reset runs in parallel with this.
2368 if (ath_reset_grablock(sc, 1) == 0) {
2369 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
2373 /* disable interrupts */
2374 ath_hal_intrset(ah, 0);
2377 * Now, ensure that any in progress TX/RX completes before we
2380 ath_txrx_stop_locked(sc);
2385 * Should now wait for pending TX/RX to complete
2386 * and block future ones from occuring. This needs to be
2387 * done before the TX queue is drained.
2389 ath_draintxq(sc, reset_type); /* stop xmit side */
2392 * Regardless of whether we're doing a no-loss flush or
2393 * not, stop the PCU and handle what's in the RX queue.
2394 * That way frames aren't dropped which shouldn't be.
2396 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS));
2399 ath_settkipmic(sc); /* configure TKIP MIC handling */
2400 /* NB: indicate channel change so we do a full reset */
2401 ath_update_chainmasks(sc, ic->ic_curchan);
2402 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2403 sc->sc_cur_rxchainmask);
2404 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status))
2405 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
2407 sc->sc_diversity = ath_hal_getdiversity(ah);
2409 /* Let DFS at it in case it's a DFS channel */
2410 ath_dfs_radar_enable(sc, ic->ic_curchan);
2412 /* Let spectral at in case spectral is enabled */
2413 ath_spectral_enable(sc, ic->ic_curchan);
2416 * Let bluetooth coexistence at in case it's needed for this channel
2418 ath_btcoex_enable(sc, ic->ic_curchan);
2421 * If we're doing TDMA, enforce the TXOP limitation for chips that
2424 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2425 ath_hal_setenforcetxop(sc->sc_ah, 1);
2427 ath_hal_setenforcetxop(sc->sc_ah, 0);
2429 if (ath_startrecv(sc) != 0) /* restart recv */
2430 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
2432 * We may be doing a reset in response to an ioctl
2433 * that changes the channel so update any state that
2434 * might change as a result.
2436 ath_chan_change(sc, ic->ic_curchan);
2437 if (sc->sc_beacons) { /* restart beacons */
2438 #ifdef IEEE80211_SUPPORT_TDMA
2440 ath_tdma_config(sc, NULL);
2443 ath_beacon_config(sc, NULL);
2447 * Release the reset lock and re-enable interrupts here.
2448 * If an interrupt was being processed in ath_intr(),
2449 * it would disable interrupts at this point. So we have
2450 * to atomically enable interrupts and decrement the
2451 * reset counter - this way ath_intr() doesn't end up
2452 * disabling interrupts without a corresponding enable
2453 * in the rest or channel change path.
2456 sc->sc_inreset_cnt--;
2457 /* XXX only do this if sc_inreset_cnt == 0? */
2458 ath_hal_intrset(ah, sc->sc_imask);
2462 * TX and RX can be started here. If it were started with
2463 * sc_inreset_cnt > 0, the TX and RX path would abort.
2464 * Thus if this is a nested call through the reset or
2465 * channel change code, TX completion will occur but
2466 * RX completion and ath_start / ath_tx_start will not
2470 /* Restart TX/RX as needed */
2473 /* Restart TX completion and pending TX */
2474 if (reset_type == ATH_RESET_NOLOSS) {
2475 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
2476 if (ATH_TXQ_SETUP(sc, i)) {
2477 ATH_TXQ_LOCK(&sc->sc_txq[i]);
2478 ath_txq_restart_dma(sc, &sc->sc_txq[i]);
2479 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
2482 ath_txq_sched(sc, &sc->sc_txq[i]);
2489 * This may have been set during an ath_start() call which
2490 * set this once it detected a concurrent TX was going on.
2493 IF_LOCK(&ifp->if_snd);
2494 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2495 IF_UNLOCK(&ifp->if_snd);
2497 /* Handle any frames in the TX queue */
2499 * XXX should this be done by the caller, rather than
2502 ath_tx_kick(sc); /* restart xmit */
2507 ath_reset_vap(struct ieee80211vap *vap, u_long cmd)
2509 struct ieee80211com *ic = vap->iv_ic;
2510 struct ifnet *ifp = ic->ic_ifp;
2511 struct ath_softc *sc = ifp->if_softc;
2512 struct ath_hal *ah = sc->sc_ah;
2515 case IEEE80211_IOC_TXPOWER:
2517 * If per-packet TPC is enabled, then we have nothing
2518 * to do; otherwise we need to force the global limit.
2519 * All this can happen directly; no need to reset.
2521 if (!ath_hal_gettpc(ah))
2522 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
2525 /* XXX? Full or NOLOSS? */
2526 return ath_reset(ifp, ATH_RESET_FULL);
2530 _ath_getbuf_locked(struct ath_softc *sc, ath_buf_type_t btype)
2534 ATH_TXBUF_LOCK_ASSERT(sc);
2536 if (btype == ATH_BUFTYPE_MGMT)
2537 bf = TAILQ_FIRST(&sc->sc_txbuf_mgmt);
2539 bf = TAILQ_FIRST(&sc->sc_txbuf);
2542 sc->sc_stats.ast_tx_getnobuf++;
2544 if (bf->bf_flags & ATH_BUF_BUSY) {
2545 sc->sc_stats.ast_tx_getbusybuf++;
2550 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) {
2551 if (btype == ATH_BUFTYPE_MGMT)
2552 TAILQ_REMOVE(&sc->sc_txbuf_mgmt, bf, bf_list);
2554 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list);
2558 * This shuldn't happen; however just to be
2559 * safe print a warning and fudge the txbuf
2562 if (sc->sc_txbuf_cnt < 0) {
2563 device_printf(sc->sc_dev,
2564 "%s: sc_txbuf_cnt < 0?\n",
2566 sc->sc_txbuf_cnt = 0;
2573 /* XXX should check which list, mgmt or otherwise */
2574 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__,
2575 TAILQ_FIRST(&sc->sc_txbuf) == NULL ?
2576 "out of xmit buffers" : "xmit buffer busy");
2580 /* XXX TODO: should do this at buffer list initialisation */
2581 /* XXX (then, ensure the buffer has the right flag set) */
2583 if (btype == ATH_BUFTYPE_MGMT)
2584 bf->bf_flags |= ATH_BUF_MGMT;
2586 bf->bf_flags &= (~ATH_BUF_MGMT);
2588 /* Valid bf here; clear some basic fields */
2589 bf->bf_next = NULL; /* XXX just to be sure */
2590 bf->bf_last = NULL; /* XXX again, just to be sure */
2591 bf->bf_comp = NULL; /* XXX again, just to be sure */
2592 bzero(&bf->bf_state, sizeof(bf->bf_state));
2595 * Track the descriptor ID only if doing EDMA
2597 if (sc->sc_isedma) {
2598 bf->bf_descid = sc->sc_txbuf_descid;
2599 sc->sc_txbuf_descid++;
2606 * When retrying a software frame, buffers marked ATH_BUF_BUSY
2607 * can't be thrown back on the queue as they could still be
2608 * in use by the hardware.
2610 * This duplicates the buffer, or returns NULL.
2612 * The descriptor is also copied but the link pointers and
2613 * the DMA segments aren't copied; this frame should thus
2614 * be again passed through the descriptor setup/chain routines
2615 * so the link is correct.
2617 * The caller must free the buffer using ath_freebuf().
2620 ath_buf_clone(struct ath_softc *sc, struct ath_buf *bf)
2622 struct ath_buf *tbf;
2624 tbf = ath_getbuf(sc,
2625 (bf->bf_flags & ATH_BUF_MGMT) ?
2626 ATH_BUFTYPE_MGMT : ATH_BUFTYPE_NORMAL);
2628 return NULL; /* XXX failure? Why? */
2631 tbf->bf_next = NULL;
2632 tbf->bf_nseg = bf->bf_nseg;
2633 tbf->bf_flags = bf->bf_flags & ATH_BUF_FLAGS_CLONE;
2634 tbf->bf_status = bf->bf_status;
2635 tbf->bf_m = bf->bf_m;
2636 tbf->bf_node = bf->bf_node;
2637 /* will be setup by the chain/setup function */
2638 tbf->bf_lastds = NULL;
2639 /* for now, last == self */
2641 tbf->bf_comp = bf->bf_comp;
2643 /* NOTE: DMA segments will be setup by the setup/chain functions */
2645 /* The caller has to re-init the descriptor + links */
2648 * Free the DMA mapping here, before we NULL the mbuf.
2649 * We must only call bus_dmamap_unload() once per mbuf chain
2650 * or behaviour is undefined.
2652 if (bf->bf_m != NULL) {
2654 * XXX is this POSTWRITE call required?
2656 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2657 BUS_DMASYNC_POSTWRITE);
2658 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2665 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state));
2671 ath_getbuf(struct ath_softc *sc, ath_buf_type_t btype)
2676 bf = _ath_getbuf_locked(sc, btype);
2678 * If a mgmt buffer was requested but we're out of those,
2679 * try requesting a normal one.
2681 if (bf == NULL && btype == ATH_BUFTYPE_MGMT)
2682 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL);
2683 ATH_TXBUF_UNLOCK(sc);
2685 struct ifnet *ifp = sc->sc_ifp;
2687 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__);
2688 sc->sc_stats.ast_tx_qstop++;
2689 IF_LOCK(&ifp->if_snd);
2690 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2691 IF_UNLOCK(&ifp->if_snd);
2697 ath_qflush(struct ifnet *ifp)
2704 * Transmit a single frame.
2706 * net80211 will free the node reference if the transmit
2707 * fails, so don't free the node reference here.
2710 ath_transmit(struct ifnet *ifp, struct mbuf *m)
2712 struct ieee80211com *ic = ifp->if_l2com;
2713 struct ath_softc *sc = ic->ic_ifp->if_softc;
2714 struct ieee80211_node *ni;
2721 * Tell the reset path that we're currently transmitting.
2724 if (sc->sc_inreset_cnt > 0) {
2725 DPRINTF(sc, ATH_DEBUG_XMIT,
2726 "%s: sc_inreset_cnt > 0; bailing\n", __func__);
2728 IF_LOCK(&ifp->if_snd);
2729 sc->sc_stats.ast_tx_qstop++;
2730 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2731 IF_UNLOCK(&ifp->if_snd);
2732 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: OACTIVE, finish");
2733 return (ENOBUFS); /* XXX should be EINVAL or? */
2735 sc->sc_txstart_cnt++;
2738 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: start");
2740 * Grab the TX lock - it's ok to do this here; we haven't
2741 * yet started transmitting.
2746 * Node reference, if there's one.
2748 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
2751 * Enforce how deep a node queue can get.
2753 * XXX it would be nicer if we kept an mbuf queue per
2754 * node and only whacked them into ath_bufs when we
2755 * are ready to schedule some traffic from them.
2756 * .. that may come later.
2758 * XXX we should also track the per-node hardware queue
2759 * depth so it is easy to limit the _SUM_ of the swq and
2760 * hwq frames. Since we only schedule two HWQ frames
2761 * at a time, this should be OK for now.
2763 if ((!(m->m_flags & M_EAPOL)) &&
2764 (ATH_NODE(ni)->an_swq_depth > sc->sc_txq_node_maxdepth)) {
2765 sc->sc_stats.ast_tx_nodeq_overflow++;
2773 * Check how many TX buffers are available.
2775 * If this is for non-EAPOL traffic, just leave some
2776 * space free in order for buffer cloning and raw
2777 * frame transmission to occur.
2779 * If it's for EAPOL traffic, ignore this for now.
2780 * Management traffic will be sent via the raw transmit
2781 * method which bypasses this check.
2783 * This is needed to ensure that EAPOL frames during
2784 * (re) keying have a chance to go out.
2786 * See kern/138379 for more information.
2788 if ((!(m->m_flags & M_EAPOL)) &&
2789 (sc->sc_txbuf_cnt <= sc->sc_txq_data_minfree)) {
2790 sc->sc_stats.ast_tx_nobuf++;
2798 * Grab a TX buffer and associated resources.
2800 * If it's an EAPOL frame, allocate a MGMT ath_buf.
2801 * That way even with temporary buffer exhaustion due to
2802 * the data path doesn't leave us without the ability
2803 * to transmit management frames.
2805 * Otherwise allocate a normal buffer.
2807 if (m->m_flags & M_EAPOL)
2808 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT);
2810 bf = ath_getbuf(sc, ATH_BUFTYPE_NORMAL);
2814 * If we failed to allocate a buffer, fail.
2816 * We shouldn't fail normally, due to the check
2819 sc->sc_stats.ast_tx_nobuf++;
2820 IF_LOCK(&ifp->if_snd);
2821 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2822 IF_UNLOCK(&ifp->if_snd);
2830 * At this point we have a buffer; so we need to free it
2831 * if we hit any error conditions.
2835 * Check for fragmentation. If this frame
2836 * has been broken up verify we have enough
2837 * buffers to send all the fragments so all
2841 if ((m->m_flags & M_FRAG) &&
2842 !ath_txfrag_setup(sc, &frags, m, ni)) {
2843 DPRINTF(sc, ATH_DEBUG_XMIT,
2844 "%s: out of txfrag buffers\n", __func__);
2845 sc->sc_stats.ast_tx_nofrag++;
2852 * At this point if we have any TX fragments, then we will
2853 * have bumped the node reference once for each of those.
2857 * XXX Is there anything actually _enforcing_ that the
2858 * fragments are being transmitted in one hit, rather than
2859 * being interleaved with other transmissions on that
2862 * The ATH TX output lock is the only thing serialising this
2867 * Calculate the "next fragment" length field in ath_buf
2868 * in order to let the transmit path know enough about
2869 * what to next write to the hardware.
2871 if (m->m_flags & M_FRAG) {
2872 struct ath_buf *fbf = bf;
2873 struct ath_buf *n_fbf = NULL;
2874 struct mbuf *fm = m->m_nextpkt;
2877 * We need to walk the list of fragments and set
2878 * the next size to the following buffer.
2879 * However, the first buffer isn't in the frag
2880 * list, so we have to do some gymnastics here.
2882 TAILQ_FOREACH(n_fbf, &frags, bf_list) {
2883 fbf->bf_nextfraglen = fm->m_pkthdr.len;
2890 * Bump the ifp output counter.
2892 * XXX should use atomics?
2897 * Pass the frame to the h/w for transmission.
2898 * Fragmented frames have each frag chained together
2899 * with m_nextpkt. We know there are sufficient ath_buf's
2900 * to send all the frags because of work done by
2901 * ath_txfrag_setup. We leave m_nextpkt set while
2902 * calling ath_tx_start so it can use it to extend the
2903 * the tx duration to cover the subsequent frag and
2904 * so it can reclaim all the mbufs in case of an error;
2905 * ath_tx_start clears m_nextpkt once it commits to
2906 * handing the frame to the hardware.
2908 * Note: if this fails, then the mbufs are freed but
2909 * not the node reference.
2911 next = m->m_nextpkt;
2912 if (ath_tx_start(sc, ni, bf, m)) {
2919 ath_returnbuf_head(sc, bf);
2921 * Free the rest of the node references and
2922 * buffers for the fragment list.
2924 ath_txfrag_cleanup(sc, &frags, ni);
2925 ATH_TXBUF_UNLOCK(sc);
2931 * Check here if the node is in power save state.
2933 ath_tx_update_tim(sc, ni, 1);
2937 * Beware of state changing between frags.
2938 * XXX check sta power-save state?
2940 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) {
2941 DPRINTF(sc, ATH_DEBUG_XMIT,
2942 "%s: flush fragmented packet, state %s\n",
2944 ieee80211_state_name[ni->ni_vap->iv_state]);
2950 bf = TAILQ_FIRST(&frags);
2951 KASSERT(bf != NULL, ("no buf for txfrag"));
2952 TAILQ_REMOVE(&frags, bf, bf_list);
2957 * Bump watchdog timer.
2959 sc->sc_wd_timer = 5;
2965 * Finished transmitting!
2968 sc->sc_txstart_cnt--;
2971 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: finished");
2977 ath_media_change(struct ifnet *ifp)
2979 int error = ieee80211_media_change(ifp);
2980 /* NB: only the fixed rate can change and that doesn't need a reset */
2981 return (error == ENETRESET ? 0 : error);
2985 * Block/unblock tx+rx processing while a key change is done.
2986 * We assume the caller serializes key management operations
2987 * so we only need to worry about synchronization with other
2988 * uses that originate in the driver.
2991 ath_key_update_begin(struct ieee80211vap *vap)
2993 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2994 struct ath_softc *sc = ifp->if_softc;
2996 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2997 taskqueue_block(sc->sc_tq);
2998 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
3002 ath_key_update_end(struct ieee80211vap *vap)
3004 struct ifnet *ifp = vap->iv_ic->ic_ifp;
3005 struct ath_softc *sc = ifp->if_softc;
3007 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
3008 IF_UNLOCK(&ifp->if_snd);
3009 taskqueue_unblock(sc->sc_tq);
3013 ath_update_promisc(struct ifnet *ifp)
3015 struct ath_softc *sc = ifp->if_softc;
3018 /* configure rx filter */
3019 rfilt = ath_calcrxfilter(sc);
3020 ath_hal_setrxfilter(sc->sc_ah, rfilt);
3022 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt);
3026 ath_update_mcast(struct ifnet *ifp)
3028 struct ath_softc *sc = ifp->if_softc;
3031 /* calculate and install multicast filter */
3032 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
3033 struct ifmultiaddr *ifma;
3035 * Merge multicast addresses to form the hardware filter.
3037 mfilt[0] = mfilt[1] = 0;
3038 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */
3039 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3044 /* calculate XOR of eight 6bit values */
3045 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
3046 val = LE_READ_4(dl + 0);
3047 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3048 val = LE_READ_4(dl + 3);
3049 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3051 mfilt[pos / 32] |= (1 << (pos % 32));
3053 if_maddr_runlock(ifp);
3055 mfilt[0] = mfilt[1] = ~0;
3056 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]);
3057 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n",
3058 __func__, mfilt[0], mfilt[1]);
3062 ath_mode_init(struct ath_softc *sc)
3064 struct ifnet *ifp = sc->sc_ifp;
3065 struct ath_hal *ah = sc->sc_ah;
3068 /* configure rx filter */
3069 rfilt = ath_calcrxfilter(sc);
3070 ath_hal_setrxfilter(ah, rfilt);
3072 /* configure operational mode */
3073 ath_hal_setopmode(ah);
3075 DPRINTF(sc, ATH_DEBUG_STATE | ATH_DEBUG_MODE,
3076 "%s: ah=%p, ifp=%p, if_addr=%p\n",
3080 (ifp == NULL) ? NULL : ifp->if_addr);
3082 /* handle any link-level address change */
3083 ath_hal_setmac(ah, IF_LLADDR(ifp));
3085 /* calculate and install multicast filter */
3086 ath_update_mcast(ifp);
3090 * Set the slot time based on the current setting.
3093 ath_setslottime(struct ath_softc *sc)
3095 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3096 struct ath_hal *ah = sc->sc_ah;
3099 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan))
3101 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan))
3103 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
3104 /* honor short/long slot time only in 11g */
3105 /* XXX shouldn't honor on pure g or turbo g channel */
3106 if (ic->ic_flags & IEEE80211_F_SHSLOT)
3107 usec = HAL_SLOT_TIME_9;
3109 usec = HAL_SLOT_TIME_20;
3111 usec = HAL_SLOT_TIME_9;
3113 DPRINTF(sc, ATH_DEBUG_RESET,
3114 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n",
3115 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags,
3116 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec);
3118 ath_hal_setslottime(ah, usec);
3119 sc->sc_updateslot = OK;
3123 * Callback from the 802.11 layer to update the
3124 * slot time based on the current setting.
3127 ath_updateslot(struct ifnet *ifp)
3129 struct ath_softc *sc = ifp->if_softc;
3130 struct ieee80211com *ic = ifp->if_l2com;
3133 * When not coordinating the BSS, change the hardware
3134 * immediately. For other operation we defer the change
3135 * until beacon updates have propagated to the stations.
3137 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3138 ic->ic_opmode == IEEE80211_M_MBSS)
3139 sc->sc_updateslot = UPDATE;
3141 ath_setslottime(sc);
3145 * Append the contents of src to dst; both queues
3146 * are assumed to be locked.
3149 ath_txqmove(struct ath_txq *dst, struct ath_txq *src)
3152 ATH_TXQ_LOCK_ASSERT(src);
3153 ATH_TXQ_LOCK_ASSERT(dst);
3155 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list);
3156 dst->axq_link = src->axq_link;
3157 src->axq_link = NULL;
3158 dst->axq_depth += src->axq_depth;
3159 dst->axq_aggr_depth += src->axq_aggr_depth;
3161 src->axq_aggr_depth = 0;
3165 * Reset the hardware, with no loss.
3167 * This can't be used for a general case reset.
3170 ath_reset_proc(void *arg, int pending)
3172 struct ath_softc *sc = arg;
3173 struct ifnet *ifp = sc->sc_ifp;
3176 if_printf(ifp, "%s: resetting\n", __func__);
3178 ath_reset(ifp, ATH_RESET_NOLOSS);
3182 * Reset the hardware after detecting beacons have stopped.
3185 ath_bstuck_proc(void *arg, int pending)
3187 struct ath_softc *sc = arg;
3188 struct ifnet *ifp = sc->sc_ifp;
3191 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0)
3192 if_printf(ifp, "bb hang detected (0x%x)\n", hangs);
3194 #ifdef ATH_DEBUG_ALQ
3195 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_STUCK_BEACON))
3196 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_STUCK_BEACON, 0, NULL);
3199 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
3201 sc->sc_stats.ast_bstuck++;
3203 * This assumes that there's no simultaneous channel mode change
3206 ath_reset(ifp, ATH_RESET_NOLOSS);
3210 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3212 bus_addr_t *paddr = (bus_addr_t*) arg;
3213 KASSERT(error == 0, ("error %u on bus_dma callback", error));
3214 *paddr = segs->ds_addr;
3218 * Allocate the descriptors and appropriate DMA tag/setup.
3220 * For some situations (eg EDMA TX completion), there isn't a requirement
3221 * for the ath_buf entries to be allocated.
3224 ath_descdma_alloc_desc(struct ath_softc *sc,
3225 struct ath_descdma *dd, ath_bufhead *head,
3226 const char *name, int ds_size, int ndesc)
3228 #define DS2PHYS(_dd, _ds) \
3229 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
3230 #define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \
3231 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0)
3232 struct ifnet *ifp = sc->sc_ifp;
3235 dd->dd_descsize = ds_size;
3237 DPRINTF(sc, ATH_DEBUG_RESET,
3238 "%s: %s DMA: %u desc, %d bytes per descriptor\n",
3239 __func__, name, ndesc, dd->dd_descsize);
3242 dd->dd_desc_len = dd->dd_descsize * ndesc;
3245 * Merlin work-around:
3246 * Descriptors that cross the 4KB boundary can't be used.
3247 * Assume one skipped descriptor per 4KB page.
3249 if (! ath_hal_split4ktrans(sc->sc_ah)) {
3250 int numpages = dd->dd_desc_len / 4096;
3251 dd->dd_desc_len += ds_size * numpages;
3255 * Setup DMA descriptor area.
3257 * BUS_DMA_ALLOCNOW is not used; we never use bounce
3258 * buffers for the descriptors themselves.
3260 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
3261 PAGE_SIZE, 0, /* alignment, bounds */
3262 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3263 BUS_SPACE_MAXADDR, /* highaddr */
3264 NULL, NULL, /* filter, filterarg */
3265 dd->dd_desc_len, /* maxsize */
3267 dd->dd_desc_len, /* maxsegsize */
3269 NULL, /* lockfunc */
3273 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
3277 /* allocate descriptors */
3278 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
3279 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
3282 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
3283 "error %u\n", ndesc, dd->dd_name, error);
3287 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
3288 dd->dd_desc, dd->dd_desc_len,
3289 ath_load_cb, &dd->dd_desc_paddr,
3292 if_printf(ifp, "unable to map %s descriptors, error %u\n",
3293 dd->dd_name, error);
3297 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
3298 __func__, dd->dd_name, (uint8_t *) dd->dd_desc,
3299 (u_long) dd->dd_desc_len, (caddr_t) dd->dd_desc_paddr,
3300 /*XXX*/ (u_long) dd->dd_desc_len);
3305 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3307 bus_dma_tag_destroy(dd->dd_dmat);
3308 memset(dd, 0, sizeof(*dd));
3311 #undef ATH_DESC_4KB_BOUND_CHECK
3315 ath_descdma_setup(struct ath_softc *sc,
3316 struct ath_descdma *dd, ath_bufhead *head,
3317 const char *name, int ds_size, int nbuf, int ndesc)
3319 #define DS2PHYS(_dd, _ds) \
3320 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
3321 #define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \
3322 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0)
3323 struct ifnet *ifp = sc->sc_ifp;
3326 int i, bsize, error;
3328 /* Allocate descriptors */
3329 error = ath_descdma_alloc_desc(sc, dd, head, name, ds_size,
3332 /* Assume any errors during allocation were dealt with */
3337 ds = (uint8_t *) dd->dd_desc;
3339 /* allocate rx buffers */
3340 bsize = sizeof(struct ath_buf) * nbuf;
3341 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
3343 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
3344 dd->dd_name, bsize);
3350 for (i = 0; i < nbuf; i++, bf++, ds += (ndesc * dd->dd_descsize)) {
3351 bf->bf_desc = (struct ath_desc *) ds;
3352 bf->bf_daddr = DS2PHYS(dd, ds);
3353 if (! ath_hal_split4ktrans(sc->sc_ah)) {
3355 * Merlin WAR: Skip descriptor addresses which
3356 * cause 4KB boundary crossing along any point
3357 * in the descriptor.
3359 if (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr,
3361 /* Start at the next page */
3362 ds += 0x1000 - (bf->bf_daddr & 0xFFF);
3363 bf->bf_desc = (struct ath_desc *) ds;
3364 bf->bf_daddr = DS2PHYS(dd, ds);
3367 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
3370 if_printf(ifp, "unable to create dmamap for %s "
3371 "buffer %u, error %u\n", dd->dd_name, i, error);
3372 ath_descdma_cleanup(sc, dd, head);
3375 bf->bf_lastds = bf->bf_desc; /* Just an initial value */
3376 TAILQ_INSERT_TAIL(head, bf, bf_list);
3380 * XXX TODO: ensure that ds doesn't overflow the descriptor
3381 * allocation otherwise weird stuff will occur and crash your
3385 /* XXX this should likely just call ath_descdma_cleanup() */
3387 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3388 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3389 bus_dma_tag_destroy(dd->dd_dmat);
3390 memset(dd, 0, sizeof(*dd));
3393 #undef ATH_DESC_4KB_BOUND_CHECK
3397 * Allocate ath_buf entries but no descriptor contents.
3399 * This is for RX EDMA where the descriptors are the header part of
3403 ath_descdma_setup_rx_edma(struct ath_softc *sc,
3404 struct ath_descdma *dd, ath_bufhead *head,
3405 const char *name, int nbuf, int rx_status_len)
3407 struct ifnet *ifp = sc->sc_ifp;
3409 int i, bsize, error;
3411 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers\n",
3412 __func__, name, nbuf);
3416 * This is (mostly) purely for show. We're not allocating any actual
3417 * descriptors here as EDMA RX has the descriptor be part
3420 * However, dd_desc_len is used by ath_descdma_free() to determine
3421 * whether we have already freed this DMA mapping.
3423 dd->dd_desc_len = rx_status_len * nbuf;
3424 dd->dd_descsize = rx_status_len;
3426 /* allocate rx buffers */
3427 bsize = sizeof(struct ath_buf) * nbuf;
3428 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
3430 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
3431 dd->dd_name, bsize);
3438 for (i = 0; i < nbuf; i++, bf++) {
3441 bf->bf_lastds = NULL; /* Just an initial value */
3443 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
3446 if_printf(ifp, "unable to create dmamap for %s "
3447 "buffer %u, error %u\n", dd->dd_name, i, error);
3448 ath_descdma_cleanup(sc, dd, head);
3451 TAILQ_INSERT_TAIL(head, bf, bf_list);
3455 memset(dd, 0, sizeof(*dd));
3460 ath_descdma_cleanup(struct ath_softc *sc,
3461 struct ath_descdma *dd, ath_bufhead *head)
3464 struct ieee80211_node *ni;
3467 if (dd->dd_dmamap != 0) {
3468 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3469 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3470 bus_dma_tag_destroy(dd->dd_dmat);
3474 TAILQ_FOREACH(bf, head, bf_list) {
3477 * XXX warn if there's buffers here.
3478 * XXX it should have been freed by the
3482 if (do_warning == 0) {
3484 device_printf(sc->sc_dev,
3485 "%s: %s: mbuf should've been"
3486 " unmapped/freed!\n",
3490 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3491 BUS_DMASYNC_POSTREAD);
3492 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3496 if (bf->bf_dmamap != NULL) {
3497 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
3498 bf->bf_dmamap = NULL;
3504 * Reclaim node reference.
3506 ieee80211_free_node(ni);
3514 if (dd->dd_bufptr != NULL)
3515 free(dd->dd_bufptr, M_ATHDEV);
3516 memset(dd, 0, sizeof(*dd));
3520 ath_desc_alloc(struct ath_softc *sc)
3524 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
3525 "tx", sc->sc_tx_desclen, ath_txbuf, ATH_MAX_SCATTER);
3529 sc->sc_txbuf_cnt = ath_txbuf;
3531 error = ath_descdma_setup(sc, &sc->sc_txdma_mgmt, &sc->sc_txbuf_mgmt,
3532 "tx_mgmt", sc->sc_tx_desclen, ath_txbuf_mgmt,
3535 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3540 * XXX mark txbuf_mgmt frames with ATH_BUF_MGMT, so the
3541 * flag doesn't have to be set in ath_getbuf_locked().
3544 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
3545 "beacon", sc->sc_tx_desclen, ATH_BCBUF, 1);
3547 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3548 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
3549 &sc->sc_txbuf_mgmt);
3556 ath_desc_free(struct ath_softc *sc)
3559 if (sc->sc_bdma.dd_desc_len != 0)
3560 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
3561 if (sc->sc_txdma.dd_desc_len != 0)
3562 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3563 if (sc->sc_txdma_mgmt.dd_desc_len != 0)
3564 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
3565 &sc->sc_txbuf_mgmt);
3568 static struct ieee80211_node *
3569 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
3571 struct ieee80211com *ic = vap->iv_ic;
3572 struct ath_softc *sc = ic->ic_ifp->if_softc;
3573 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
3574 struct ath_node *an;
3576 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
3581 ath_rate_node_init(sc, an);
3583 /* Setup the mutex - there's no associd yet so set the name to NULL */
3584 snprintf(an->an_name, sizeof(an->an_name), "%s: node %p",
3585 device_get_nameunit(sc->sc_dev), an);
3586 mtx_init(&an->an_mtx, an->an_name, NULL, MTX_DEF);
3588 /* XXX setup ath_tid */
3589 ath_tx_tid_init(sc, an);
3591 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, mac, ":", an);
3592 return &an->an_node;
3596 ath_node_cleanup(struct ieee80211_node *ni)
3598 struct ieee80211com *ic = ni->ni_ic;
3599 struct ath_softc *sc = ic->ic_ifp->if_softc;
3601 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
3602 ni->ni_macaddr, ":", ATH_NODE(ni));
3604 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */
3605 ath_tx_node_flush(sc, ATH_NODE(ni));
3606 ath_rate_node_cleanup(sc, ATH_NODE(ni));
3607 sc->sc_node_cleanup(ni);
3611 ath_node_free(struct ieee80211_node *ni)
3613 struct ieee80211com *ic = ni->ni_ic;
3614 struct ath_softc *sc = ic->ic_ifp->if_softc;
3616 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
3617 ni->ni_macaddr, ":", ATH_NODE(ni));
3618 mtx_destroy(&ATH_NODE(ni)->an_mtx);
3619 sc->sc_node_free(ni);
3623 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise)
3625 struct ieee80211com *ic = ni->ni_ic;
3626 struct ath_softc *sc = ic->ic_ifp->if_softc;
3627 struct ath_hal *ah = sc->sc_ah;
3629 *rssi = ic->ic_node_getrssi(ni);
3630 if (ni->ni_chan != IEEE80211_CHAN_ANYC)
3631 *noise = ath_hal_getchannoise(ah, ni->ni_chan);
3633 *noise = -95; /* nominally correct */
3637 * Set the default antenna.
3640 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
3642 struct ath_hal *ah = sc->sc_ah;
3644 /* XXX block beacon interrupts */
3645 ath_hal_setdefantenna(ah, antenna);
3646 if (sc->sc_defant != antenna)
3647 sc->sc_stats.ast_ant_defswitch++;
3648 sc->sc_defant = antenna;
3649 sc->sc_rxotherant = 0;
3653 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
3655 txq->axq_qnum = qnum;
3658 txq->axq_aggr_depth = 0;
3659 txq->axq_intrcnt = 0;
3660 txq->axq_link = NULL;
3661 txq->axq_softc = sc;
3662 TAILQ_INIT(&txq->axq_q);
3663 TAILQ_INIT(&txq->axq_tidq);
3664 TAILQ_INIT(&txq->fifo.axq_q);
3665 ATH_TXQ_LOCK_INIT(sc, txq);
3669 * Setup a h/w transmit queue.
3671 static struct ath_txq *
3672 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
3674 #define N(a) (sizeof(a)/sizeof(a[0]))
3675 struct ath_hal *ah = sc->sc_ah;
3679 memset(&qi, 0, sizeof(qi));
3680 qi.tqi_subtype = subtype;
3681 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
3682 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
3683 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
3685 * Enable interrupts only for EOL and DESC conditions.
3686 * We mark tx descriptors to receive a DESC interrupt
3687 * when a tx queue gets deep; otherwise waiting for the
3688 * EOL to reap descriptors. Note that this is done to
3689 * reduce interrupt load and this only defers reaping
3690 * descriptors, never transmitting frames. Aside from
3691 * reducing interrupts this also permits more concurrency.
3692 * The only potential downside is if the tx queue backs
3693 * up in which case the top half of the kernel may backup
3694 * due to a lack of tx descriptors.
3697 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE |
3698 HAL_TXQ_TXOKINT_ENABLE;
3700 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE |
3701 HAL_TXQ_TXDESCINT_ENABLE;
3703 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
3706 * NB: don't print a message, this happens
3707 * normally on parts with too few tx queues
3711 if (qnum >= N(sc->sc_txq)) {
3712 device_printf(sc->sc_dev,
3713 "hal qnum %u out of range, max %zu!\n",
3714 qnum, N(sc->sc_txq));
3715 ath_hal_releasetxqueue(ah, qnum);
3718 if (!ATH_TXQ_SETUP(sc, qnum)) {
3719 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
3720 sc->sc_txqsetup |= 1<<qnum;
3722 return &sc->sc_txq[qnum];
3727 * Setup a hardware data transmit queue for the specified
3728 * access control. The hal may not support all requested
3729 * queues in which case it will return a reference to a
3730 * previously setup queue. We record the mapping from ac's
3731 * to h/w queues for use by ath_tx_start and also track
3732 * the set of h/w queues being used to optimize work in the
3733 * transmit interrupt handler and related routines.
3736 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
3738 #define N(a) (sizeof(a)/sizeof(a[0]))
3739 struct ath_txq *txq;
3741 if (ac >= N(sc->sc_ac2q)) {
3742 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
3743 ac, N(sc->sc_ac2q));
3746 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
3749 sc->sc_ac2q[ac] = txq;
3757 * Update WME parameters for a transmit queue.
3760 ath_txq_update(struct ath_softc *sc, int ac)
3762 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
3763 #define ATH_TXOP_TO_US(v) (v<<5)
3764 struct ifnet *ifp = sc->sc_ifp;
3765 struct ieee80211com *ic = ifp->if_l2com;
3766 struct ath_txq *txq = sc->sc_ac2q[ac];
3767 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
3768 struct ath_hal *ah = sc->sc_ah;
3771 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
3772 #ifdef IEEE80211_SUPPORT_TDMA
3775 * AIFS is zero so there's no pre-transmit wait. The
3776 * burst time defines the slot duration and is configured
3777 * through net80211. The QCU is setup to not do post-xmit
3778 * back off, lockout all lower-priority QCU's, and fire
3779 * off the DMA beacon alert timer which is setup based
3780 * on the slot configuration.
3782 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
3783 | HAL_TXQ_TXERRINT_ENABLE
3784 | HAL_TXQ_TXURNINT_ENABLE
3785 | HAL_TXQ_TXEOLINT_ENABLE
3787 | HAL_TXQ_BACKOFF_DISABLE
3788 | HAL_TXQ_ARB_LOCKOUT_GLOBAL
3792 qi.tqi_readyTime = sc->sc_tdmaslotlen;
3793 qi.tqi_burstTime = qi.tqi_readyTime;
3797 * XXX shouldn't this just use the default flags
3798 * used in the previous queue setup?
3800 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
3801 | HAL_TXQ_TXERRINT_ENABLE
3802 | HAL_TXQ_TXDESCINT_ENABLE
3803 | HAL_TXQ_TXURNINT_ENABLE
3804 | HAL_TXQ_TXEOLINT_ENABLE
3806 qi.tqi_aifs = wmep->wmep_aifsn;
3807 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
3808 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
3809 qi.tqi_readyTime = 0;
3810 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
3811 #ifdef IEEE80211_SUPPORT_TDMA
3815 DPRINTF(sc, ATH_DEBUG_RESET,
3816 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n",
3817 __func__, txq->axq_qnum, qi.tqi_qflags,
3818 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime);
3820 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
3821 if_printf(ifp, "unable to update hardware queue "
3822 "parameters for %s traffic!\n",
3823 ieee80211_wme_acnames[ac]);
3826 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
3829 #undef ATH_TXOP_TO_US
3830 #undef ATH_EXPONENT_TO_VALUE
3834 * Callback from the 802.11 layer to update WME parameters.
3837 ath_wme_update(struct ieee80211com *ic)
3839 struct ath_softc *sc = ic->ic_ifp->if_softc;
3841 return !ath_txq_update(sc, WME_AC_BE) ||
3842 !ath_txq_update(sc, WME_AC_BK) ||
3843 !ath_txq_update(sc, WME_AC_VI) ||
3844 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
3848 * Reclaim resources for a setup queue.
3851 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
3854 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
3855 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
3856 ATH_TXQ_LOCK_DESTROY(txq);
3860 * Reclaim all tx queue resources.
3863 ath_tx_cleanup(struct ath_softc *sc)
3867 ATH_TXBUF_LOCK_DESTROY(sc);
3868 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3869 if (ATH_TXQ_SETUP(sc, i))
3870 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
3874 * Return h/w rate index for an IEEE rate (w/o basic rate bit)
3875 * using the current rates in sc_rixmap.
3878 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate)
3880 int rix = sc->sc_rixmap[rate];
3881 /* NB: return lowest rix for invalid rate */
3882 return (rix == 0xff ? 0 : rix);
3886 ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts,
3889 struct ieee80211_node *ni = bf->bf_node;
3890 struct ifnet *ifp = sc->sc_ifp;
3891 struct ieee80211com *ic = ifp->if_l2com;
3894 if (ts->ts_status == 0) {
3895 u_int8_t txant = ts->ts_antenna;
3896 sc->sc_stats.ast_ant_tx[txant]++;
3897 sc->sc_ant_tx[txant]++;
3898 if (ts->ts_finaltsi != 0)
3899 sc->sc_stats.ast_tx_altrate++;
3900 pri = M_WME_GETAC(bf->bf_m);
3901 if (pri >= WME_AC_VO)
3902 ic->ic_wme.wme_hipri_traffic++;
3903 if ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)
3904 ni->ni_inact = ni->ni_inact_reload;
3906 if (ts->ts_status & HAL_TXERR_XRETRY)
3907 sc->sc_stats.ast_tx_xretries++;
3908 if (ts->ts_status & HAL_TXERR_FIFO)
3909 sc->sc_stats.ast_tx_fifoerr++;
3910 if (ts->ts_status & HAL_TXERR_FILT)
3911 sc->sc_stats.ast_tx_filtered++;
3912 if (ts->ts_status & HAL_TXERR_XTXOP)
3913 sc->sc_stats.ast_tx_xtxop++;
3914 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED)
3915 sc->sc_stats.ast_tx_timerexpired++;
3917 if (bf->bf_m->m_flags & M_FF)
3918 sc->sc_stats.ast_ff_txerr++;
3920 /* XXX when is this valid? */
3921 if (ts->ts_flags & HAL_TX_DESC_CFG_ERR)
3922 sc->sc_stats.ast_tx_desccfgerr++;
3924 * This can be valid for successful frame transmission!
3925 * If there's a TX FIFO underrun during aggregate transmission,
3926 * the MAC will pad the rest of the aggregate with delimiters.
3927 * If a BA is returned, the frame is marked as "OK" and it's up
3928 * to the TX completion code to notice which frames weren't
3929 * successfully transmitted.
3931 if (ts->ts_flags & HAL_TX_DATA_UNDERRUN)
3932 sc->sc_stats.ast_tx_data_underrun++;
3933 if (ts->ts_flags & HAL_TX_DELIM_UNDERRUN)
3934 sc->sc_stats.ast_tx_delim_underrun++;
3936 sr = ts->ts_shortretry;
3937 lr = ts->ts_longretry;
3938 sc->sc_stats.ast_tx_shortretry += sr;
3939 sc->sc_stats.ast_tx_longretry += lr;
3944 * The default completion. If fail is 1, this means
3945 * "please don't retry the frame, and just return -1 status
3946 * to the net80211 stack.
3949 ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
3951 struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
3957 st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ?
3958 ts->ts_status : HAL_TXERR_XRETRY;
3961 if (bf->bf_state.bfs_dobaw)
3962 device_printf(sc->sc_dev,
3963 "%s: bf %p: seqno %d: dobaw should've been cleared!\n",
3966 SEQNO(bf->bf_state.bfs_seqno));
3968 if (bf->bf_next != NULL)
3969 device_printf(sc->sc_dev,
3970 "%s: bf %p: seqno %d: bf_next not NULL!\n",
3973 SEQNO(bf->bf_state.bfs_seqno));
3976 * Check if the node software queue is empty; if so
3977 * then clear the TIM.
3979 * This needs to be done before the buffer is freed as
3980 * otherwise the node reference will have been released
3981 * and the node may not actually exist any longer.
3983 * XXX I don't like this belonging here, but it's cleaner
3984 * to do it here right now then all the other places
3985 * where ath_tx_default_comp() is called.
3987 * XXX TODO: during drain, ensure that the callback is
3988 * being called so we get a chance to update the TIM.
3992 ath_tx_update_tim(sc, bf->bf_node, 0);
3997 * Do any tx complete callback. Note this must
3998 * be done before releasing the node reference.
3999 * This will free the mbuf, release the net80211
4000 * node and recycle the ath_buf.
4002 ath_tx_freebuf(sc, bf, st);
4006 * Update rate control with the given completion status.
4009 ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni,
4010 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen,
4011 int nframes, int nbad)
4013 struct ath_node *an;
4015 /* Only for unicast frames */
4020 ATH_NODE_UNLOCK_ASSERT(an);
4022 if ((ts->ts_status & HAL_TXERR_FILT) == 0) {
4024 ath_rate_tx_complete(sc, an, rc, ts, frmlen, nframes, nbad);
4025 ATH_NODE_UNLOCK(an);
4030 * Process the completion of the given buffer.
4032 * This calls the rate control update and then the buffer completion.
4033 * This will either free the buffer or requeue it. In any case, the
4034 * bf pointer should be treated as invalid after this function is called.
4037 ath_tx_process_buf_completion(struct ath_softc *sc, struct ath_txq *txq,
4038 struct ath_tx_status *ts, struct ath_buf *bf)
4040 struct ieee80211_node *ni = bf->bf_node;
4041 struct ath_node *an = NULL;
4043 ATH_TX_UNLOCK_ASSERT(sc);
4044 ATH_TXQ_UNLOCK_ASSERT(txq);
4046 /* If unicast frame, update general statistics */
4049 /* update statistics */
4050 ath_tx_update_stats(sc, ts, bf);
4054 * Call the completion handler.
4055 * The completion handler is responsible for
4056 * calling the rate control code.
4058 * Frames with no completion handler get the
4059 * rate control code called here.
4061 if (bf->bf_comp == NULL) {
4062 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
4063 (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) {
4065 * XXX assume this isn't an aggregate
4068 ath_tx_update_ratectrl(sc, ni,
4069 bf->bf_state.bfs_rc, ts,
4070 bf->bf_state.bfs_pktlen, 1,
4071 (ts->ts_status == 0 ? 0 : 1));
4073 ath_tx_default_comp(sc, bf, 0);
4075 bf->bf_comp(sc, bf, 0);
4081 * Process completed xmit descriptors from the specified queue.
4082 * Kick the packet scheduler if needed. This can occur from this
4086 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched)
4088 struct ath_hal *ah = sc->sc_ah;
4090 struct ath_desc *ds;
4091 struct ath_tx_status *ts;
4092 struct ieee80211_node *ni;
4093 #ifdef IEEE80211_SUPPORT_SUPERG
4094 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
4095 #endif /* IEEE80211_SUPPORT_SUPERG */
4099 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
4100 __func__, txq->axq_qnum,
4101 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4104 ATH_KTR(sc, ATH_KTR_TXCOMP, 4,
4105 "ath_tx_processq: txq=%u head %p link %p depth %p",
4107 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4114 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
4115 bf = TAILQ_FIRST(&txq->axq_q);
4117 ATH_TXQ_UNLOCK(txq);
4120 ds = bf->bf_lastds; /* XXX must be setup correctly! */
4121 ts = &bf->bf_status.ds_txstat;
4123 status = ath_hal_txprocdesc(ah, ds, ts);
4125 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
4126 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4128 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0))
4129 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4132 #ifdef ATH_DEBUG_ALQ
4133 if (if_ath_alq_checkdebug(&sc->sc_alq,
4134 ATH_ALQ_EDMA_TXSTATUS)) {
4135 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS,
4136 sc->sc_tx_statuslen,
4141 if (status == HAL_EINPROGRESS) {
4142 ATH_KTR(sc, ATH_KTR_TXCOMP, 3,
4143 "ath_tx_processq: txq=%u, bf=%p ds=%p, HAL_EINPROGRESS",
4144 txq->axq_qnum, bf, ds);
4145 ATH_TXQ_UNLOCK(txq);
4148 ATH_TXQ_REMOVE(txq, bf, bf_list);
4153 if (txq->axq_qnum != bf->bf_state.bfs_tx_queue) {
4154 device_printf(sc->sc_dev,
4155 "%s: TXQ=%d: bf=%p, bfs_tx_queue=%d\n",
4159 bf->bf_state.bfs_tx_queue);
4161 if (txq->axq_qnum != bf->bf_last->bf_state.bfs_tx_queue) {
4162 device_printf(sc->sc_dev,
4163 "%s: TXQ=%d: bf_last=%p, bfs_tx_queue=%d\n",
4167 bf->bf_last->bf_state.bfs_tx_queue);
4171 if (txq->axq_depth > 0) {
4173 * More frames follow. Mark the buffer busy
4174 * so it's not re-used while the hardware may
4175 * still re-read the link field in the descriptor.
4177 * Use the last buffer in an aggregate as that
4178 * is where the hardware may be - intermediate
4179 * descriptors won't be "busy".
4181 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
4183 txq->axq_link = NULL;
4185 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
4187 if (bf->bf_state.bfs_aggr)
4188 txq->axq_aggr_depth--;
4192 ATH_KTR(sc, ATH_KTR_TXCOMP, 5,
4193 "ath_tx_processq: txq=%u, bf=%p, ds=%p, ni=%p, ts_status=0x%08x",
4194 txq->axq_qnum, bf, ds, ni, ts->ts_status);
4196 * If unicast frame was ack'd update RSSI,
4197 * including the last rx time used to
4198 * workaround phantom bmiss interrupts.
4200 if (ni != NULL && ts->ts_status == 0 &&
4201 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) {
4203 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
4204 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
4207 ATH_TXQ_UNLOCK(txq);
4210 * Update statistics and call completion
4212 ath_tx_process_buf_completion(sc, txq, ts, bf);
4214 /* XXX at this point, bf and ni may be totally invalid */
4216 #ifdef IEEE80211_SUPPORT_SUPERG
4218 * Flush fast-frame staging queue when traffic slows.
4220 if (txq->axq_depth <= 1)
4221 ieee80211_ff_flush(ic, txq->axq_ac);
4224 /* Kick the software TXQ scheduler */
4227 ath_txq_sched(sc, txq);
4231 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4232 "ath_tx_processq: txq=%u: done",
4238 #define TXQACTIVE(t, q) ( (t) & (1 << (q)))
4241 * Deferred processing of transmit interrupt; special-cased
4242 * for a single hardware transmit queue (e.g. 5210 and 5211).
4245 ath_tx_proc_q0(void *arg, int npending)
4247 struct ath_softc *sc = arg;
4248 struct ifnet *ifp = sc->sc_ifp;
4252 sc->sc_txproc_cnt++;
4253 txqs = sc->sc_txq_active;
4254 sc->sc_txq_active &= ~txqs;
4257 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4258 "ath_tx_proc_q0: txqs=0x%08x", txqs);
4260 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1))
4261 /* XXX why is lastrx updated in tx code? */
4262 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4263 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4264 ath_tx_processq(sc, sc->sc_cabq, 1);
4265 IF_LOCK(&ifp->if_snd);
4266 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4267 IF_UNLOCK(&ifp->if_snd);
4268 sc->sc_wd_timer = 0;
4271 ath_led_event(sc, sc->sc_txrix);
4274 sc->sc_txproc_cnt--;
4281 * Deferred processing of transmit interrupt; special-cased
4282 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
4285 ath_tx_proc_q0123(void *arg, int npending)
4287 struct ath_softc *sc = arg;
4288 struct ifnet *ifp = sc->sc_ifp;
4293 sc->sc_txproc_cnt++;
4294 txqs = sc->sc_txq_active;
4295 sc->sc_txq_active &= ~txqs;
4298 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4299 "ath_tx_proc_q0123: txqs=0x%08x", txqs);
4302 * Process each active queue.
4305 if (TXQACTIVE(txqs, 0))
4306 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1);
4307 if (TXQACTIVE(txqs, 1))
4308 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1);
4309 if (TXQACTIVE(txqs, 2))
4310 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1);
4311 if (TXQACTIVE(txqs, 3))
4312 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1);
4313 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4314 ath_tx_processq(sc, sc->sc_cabq, 1);
4316 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4318 IF_LOCK(&ifp->if_snd);
4319 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4320 IF_UNLOCK(&ifp->if_snd);
4321 sc->sc_wd_timer = 0;
4324 ath_led_event(sc, sc->sc_txrix);
4327 sc->sc_txproc_cnt--;
4334 * Deferred processing of transmit interrupt.
4337 ath_tx_proc(void *arg, int npending)
4339 struct ath_softc *sc = arg;
4340 struct ifnet *ifp = sc->sc_ifp;
4345 sc->sc_txproc_cnt++;
4346 txqs = sc->sc_txq_active;
4347 sc->sc_txq_active &= ~txqs;
4350 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, "ath_tx_proc: txqs=0x%08x", txqs);
4353 * Process each active queue.
4356 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4357 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i))
4358 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1);
4360 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4362 /* XXX check this inside of IF_LOCK? */
4363 IF_LOCK(&ifp->if_snd);
4364 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4365 IF_UNLOCK(&ifp->if_snd);
4366 sc->sc_wd_timer = 0;
4369 ath_led_event(sc, sc->sc_txrix);
4372 sc->sc_txproc_cnt--;
4380 * Deferred processing of TXQ rescheduling.
4383 ath_txq_sched_tasklet(void *arg, int npending)
4385 struct ath_softc *sc = arg;
4388 /* XXX is skipping ok? */
4391 if (sc->sc_inreset_cnt > 0) {
4392 device_printf(sc->sc_dev,
4393 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
4398 sc->sc_txproc_cnt++;
4402 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
4403 if (ATH_TXQ_SETUP(sc, i)) {
4404 ath_txq_sched(sc, &sc->sc_txq[i]);
4410 sc->sc_txproc_cnt--;
4415 ath_returnbuf_tail(struct ath_softc *sc, struct ath_buf *bf)
4418 ATH_TXBUF_LOCK_ASSERT(sc);
4420 if (bf->bf_flags & ATH_BUF_MGMT)
4421 TAILQ_INSERT_TAIL(&sc->sc_txbuf_mgmt, bf, bf_list);
4423 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
4425 if (sc->sc_txbuf_cnt > ath_txbuf) {
4426 device_printf(sc->sc_dev,
4427 "%s: sc_txbuf_cnt > %d?\n",
4430 sc->sc_txbuf_cnt = ath_txbuf;
4436 ath_returnbuf_head(struct ath_softc *sc, struct ath_buf *bf)
4439 ATH_TXBUF_LOCK_ASSERT(sc);
4441 if (bf->bf_flags & ATH_BUF_MGMT)
4442 TAILQ_INSERT_HEAD(&sc->sc_txbuf_mgmt, bf, bf_list);
4444 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
4446 if (sc->sc_txbuf_cnt > ATH_TXBUF) {
4447 device_printf(sc->sc_dev,
4448 "%s: sc_txbuf_cnt > %d?\n",
4451 sc->sc_txbuf_cnt = ATH_TXBUF;
4457 * Free the holding buffer if it exists
4460 ath_txq_freeholdingbuf(struct ath_softc *sc, struct ath_txq *txq)
4462 ATH_TXBUF_UNLOCK_ASSERT(sc);
4463 ATH_TXQ_LOCK_ASSERT(txq);
4465 if (txq->axq_holdingbf == NULL)
4468 txq->axq_holdingbf->bf_flags &= ~ATH_BUF_BUSY;
4471 ath_returnbuf_tail(sc, txq->axq_holdingbf);
4472 ATH_TXBUF_UNLOCK(sc);
4474 txq->axq_holdingbf = NULL;
4478 * Add this buffer to the holding queue, freeing the previous
4482 ath_txq_addholdingbuf(struct ath_softc *sc, struct ath_buf *bf)
4484 struct ath_txq *txq;
4486 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
4488 ATH_TXBUF_UNLOCK_ASSERT(sc);
4489 ATH_TXQ_LOCK_ASSERT(txq);
4491 /* XXX assert ATH_BUF_BUSY is set */
4493 /* XXX assert the tx queue is under the max number */
4494 if (bf->bf_state.bfs_tx_queue > HAL_NUM_TX_QUEUES) {
4495 device_printf(sc->sc_dev, "%s: bf=%p: invalid tx queue (%d)\n",
4498 bf->bf_state.bfs_tx_queue);
4499 bf->bf_flags &= ~ATH_BUF_BUSY;
4500 ath_returnbuf_tail(sc, bf);
4503 ath_txq_freeholdingbuf(sc, txq);
4504 txq->axq_holdingbf = bf;
4508 * Return a buffer to the pool and update the 'busy' flag on the
4509 * previous 'tail' entry.
4511 * This _must_ only be called when the buffer is involved in a completed
4512 * TX. The logic is that if it was part of an active TX, the previous
4513 * buffer on the list is now not involved in a halted TX DMA queue, waiting
4514 * for restart (eg for TDMA.)
4516 * The caller must free the mbuf and recycle the node reference.
4518 * XXX This method of handling busy / holding buffers is insanely stupid.
4519 * It requires bf_state.bfs_tx_queue to be correctly assigned. It would
4520 * be much nicer if buffers in the processq() methods would instead be
4521 * always completed there (pushed onto a txq or ath_bufhead) so we knew
4522 * exactly what hardware queue they came from in the first place.
4525 ath_freebuf(struct ath_softc *sc, struct ath_buf *bf)
4527 struct ath_txq *txq;
4529 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
4531 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__));
4532 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__));
4535 * If this buffer is busy, push it onto the holding queue.
4537 if (bf->bf_flags & ATH_BUF_BUSY) {
4539 ath_txq_addholdingbuf(sc, bf);
4540 ATH_TXQ_UNLOCK(txq);
4545 * Not a busy buffer, so free normally
4548 ath_returnbuf_tail(sc, bf);
4549 ATH_TXBUF_UNLOCK(sc);
4553 * This is currently used by ath_tx_draintxq() and
4554 * ath_tx_tid_free_pkts().
4556 * It recycles a single ath_buf.
4559 ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status)
4561 struct ieee80211_node *ni = bf->bf_node;
4562 struct mbuf *m0 = bf->bf_m;
4565 * Make sure that we only sync/unload if there's an mbuf.
4566 * If not (eg we cloned a buffer), the unload will have already
4569 if (bf->bf_m != NULL) {
4570 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
4571 BUS_DMASYNC_POSTWRITE);
4572 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4578 /* Free the buffer, it's not needed any longer */
4579 ath_freebuf(sc, bf);
4581 /* Pass the buffer back to net80211 - completing it */
4582 ieee80211_tx_complete(ni, m0, status);
4585 static struct ath_buf *
4586 ath_tx_draintxq_get_one(struct ath_softc *sc, struct ath_txq *txq)
4590 ATH_TXQ_LOCK_ASSERT(txq);
4593 * Drain the FIFO queue first, then if it's
4594 * empty, move to the normal frame queue.
4596 bf = TAILQ_FIRST(&txq->fifo.axq_q);
4599 * Is it the last buffer in this set?
4600 * Decrement the FIFO counter.
4602 if (bf->bf_flags & ATH_BUF_FIFOEND) {
4603 if (txq->axq_fifo_depth == 0) {
4604 device_printf(sc->sc_dev,
4605 "%s: Q%d: fifo_depth=0, fifo.axq_depth=%d?\n",
4608 txq->fifo.axq_depth);
4610 txq->axq_fifo_depth--;
4612 ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list);
4619 if (txq->axq_fifo_depth != 0 || txq->fifo.axq_depth != 0) {
4620 device_printf(sc->sc_dev,
4621 "%s: Q%d: fifo_depth=%d, fifo.axq_depth=%d\n",
4624 txq->axq_fifo_depth,
4625 txq->fifo.axq_depth);
4629 * Now drain the pending queue.
4631 bf = TAILQ_FIRST(&txq->axq_q);
4633 txq->axq_link = NULL;
4636 ATH_TXQ_REMOVE(txq, bf, bf_list);
4641 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
4644 struct ath_hal *ah = sc->sc_ah;
4650 * NB: this assumes output has been stopped and
4651 * we do not need to block ath_tx_proc
4653 for (ix = 0;; ix++) {
4655 bf = ath_tx_draintxq_get_one(sc, txq);
4657 ATH_TXQ_UNLOCK(txq);
4660 if (bf->bf_state.bfs_aggr)
4661 txq->axq_aggr_depth--;
4663 if (sc->sc_debug & ATH_DEBUG_RESET) {
4664 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
4668 * EDMA operation has a TX completion FIFO
4669 * separate from the TX descriptor, so this
4670 * method of checking the "completion" status
4673 if (! sc->sc_isedma) {
4674 status = (ath_hal_txprocdesc(ah,
4676 &bf->bf_status.ds_txstat) == HAL_OK);
4678 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, status);
4679 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *),
4680 bf->bf_m->m_len, 0, -1);
4682 #endif /* ATH_DEBUG */
4684 * Since we're now doing magic in the completion
4685 * functions, we -must- call it for aggregation
4686 * destinations or BAW tracking will get upset.
4689 * Clear ATH_BUF_BUSY; the completion handler
4690 * will free the buffer.
4692 ATH_TXQ_UNLOCK(txq);
4693 bf->bf_flags &= ~ATH_BUF_BUSY;
4695 bf->bf_comp(sc, bf, 1);
4697 ath_tx_default_comp(sc, bf, 1);
4701 * Free the holding buffer if it exists
4704 ath_txq_freeholdingbuf(sc, txq);
4705 ATH_TXQ_UNLOCK(txq);
4708 * Drain software queued frames which are on
4711 ath_tx_txq_drain(sc, txq);
4715 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
4717 struct ath_hal *ah = sc->sc_ah;
4719 ATH_TXQ_LOCK_ASSERT(txq);
4721 DPRINTF(sc, ATH_DEBUG_RESET,
4722 "%s: tx queue [%u] %p, active=%d, hwpending=%d, flags 0x%08x, "
4723 "link %p, holdingbf=%p\n",
4726 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
4727 (int) (!! ath_hal_txqenabled(ah, txq->axq_qnum)),
4728 (int) ath_hal_numtxpending(ah, txq->axq_qnum),
4731 txq->axq_holdingbf);
4733 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
4734 /* We've stopped TX DMA, so mark this as stopped. */
4735 txq->axq_flags &= ~ATH_TXQ_PUTRUNNING;
4738 if ((sc->sc_debug & ATH_DEBUG_RESET)
4739 && (txq->axq_holdingbf != NULL)) {
4740 ath_printtxbuf(sc, txq->axq_holdingbf, txq->axq_qnum, 0, 0);
4746 ath_stoptxdma(struct ath_softc *sc)
4748 struct ath_hal *ah = sc->sc_ah;
4751 /* XXX return value */
4755 if (!sc->sc_invalid) {
4756 /* don't touch the hardware if marked invalid */
4757 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
4758 __func__, sc->sc_bhalq,
4759 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq),
4762 /* stop the beacon queue */
4763 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
4765 /* Stop the data queues */
4766 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
4767 if (ATH_TXQ_SETUP(sc, i)) {
4768 ATH_TXQ_LOCK(&sc->sc_txq[i]);
4769 ath_tx_stopdma(sc, &sc->sc_txq[i]);
4770 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
4780 ath_tx_dump(struct ath_softc *sc, struct ath_txq *txq)
4782 struct ath_hal *ah = sc->sc_ah;
4786 if (! (sc->sc_debug & ATH_DEBUG_RESET))
4789 device_printf(sc->sc_dev, "%s: Q%d: begin\n",
4790 __func__, txq->axq_qnum);
4791 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) {
4792 ath_printtxbuf(sc, bf, txq->axq_qnum, i,
4793 ath_hal_txprocdesc(ah, bf->bf_lastds,
4794 &bf->bf_status.ds_txstat) == HAL_OK);
4797 device_printf(sc->sc_dev, "%s: Q%d: end\n",
4798 __func__, txq->axq_qnum);
4800 #endif /* ATH_DEBUG */
4803 * Drain the transmit queues and reclaim resources.
4806 ath_legacy_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
4808 struct ath_hal *ah = sc->sc_ah;
4809 struct ifnet *ifp = sc->sc_ifp;
4811 struct ath_buf *bf_last;
4813 (void) ath_stoptxdma(sc);
4816 * Dump the queue contents
4818 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
4820 * XXX TODO: should we just handle the completed TX frames
4821 * here, whether or not the reset is a full one or not?
4823 if (ATH_TXQ_SETUP(sc, i)) {
4825 if (sc->sc_debug & ATH_DEBUG_RESET)
4826 ath_tx_dump(sc, &sc->sc_txq[i]);
4827 #endif /* ATH_DEBUG */
4828 if (reset_type == ATH_RESET_NOLOSS) {
4829 ath_tx_processq(sc, &sc->sc_txq[i], 0);
4830 ATH_TXQ_LOCK(&sc->sc_txq[i]);
4832 * Free the holding buffer; DMA is now
4835 ath_txq_freeholdingbuf(sc, &sc->sc_txq[i]);
4837 * Setup the link pointer to be the
4838 * _last_ buffer/descriptor in the list.
4839 * If there's nothing in the list, set it
4842 bf_last = ATH_TXQ_LAST(&sc->sc_txq[i],
4844 if (bf_last != NULL) {
4845 ath_hal_gettxdesclinkptr(ah,
4847 &sc->sc_txq[i].axq_link);
4849 sc->sc_txq[i].axq_link = NULL;
4851 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
4853 ath_tx_draintxq(sc, &sc->sc_txq[i]);
4857 if (sc->sc_debug & ATH_DEBUG_RESET) {
4858 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf);
4859 if (bf != NULL && bf->bf_m != NULL) {
4860 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0,
4861 ath_hal_txprocdesc(ah, bf->bf_lastds,
4862 &bf->bf_status.ds_txstat) == HAL_OK);
4863 ieee80211_dump_pkt(ifp->if_l2com,
4864 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len,
4868 #endif /* ATH_DEBUG */
4869 IF_LOCK(&ifp->if_snd);
4870 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4871 IF_UNLOCK(&ifp->if_snd);
4872 sc->sc_wd_timer = 0;
4876 * Update internal state after a channel change.
4879 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
4881 enum ieee80211_phymode mode;
4884 * Change channels and update the h/w rate map
4885 * if we're switching; e.g. 11a to 11b/g.
4887 mode = ieee80211_chan2mode(chan);
4888 if (mode != sc->sc_curmode)
4889 ath_setcurmode(sc, mode);
4890 sc->sc_curchan = chan;
4894 * Set/change channels. If the channel is really being changed,
4895 * it's done by resetting the chip. To accomplish this we must
4896 * first cleanup any pending DMA, then restart stuff after a la
4900 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
4902 struct ifnet *ifp = sc->sc_ifp;
4903 struct ieee80211com *ic = ifp->if_l2com;
4904 struct ath_hal *ah = sc->sc_ah;
4907 /* Treat this as an interface reset */
4908 ATH_PCU_UNLOCK_ASSERT(sc);
4909 ATH_UNLOCK_ASSERT(sc);
4911 /* (Try to) stop TX/RX from occuring */
4912 taskqueue_block(sc->sc_tq);
4916 /* Stop new RX/TX/interrupt completion */
4917 if (ath_reset_grablock(sc, 1) == 0) {
4918 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
4922 ath_hal_intrset(ah, 0);
4924 /* Stop pending RX/TX completion */
4925 ath_txrx_stop_locked(sc);
4929 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n",
4930 __func__, ieee80211_chan2ieee(ic, chan),
4931 chan->ic_freq, chan->ic_flags);
4932 if (chan != sc->sc_curchan) {
4935 * To switch channels clear any pending DMA operations;
4936 * wait long enough for the RX fifo to drain, reset the
4937 * hardware at the new frequency, and then re-enable
4938 * the relevant bits of the h/w.
4941 ath_hal_intrset(ah, 0); /* disable interrupts */
4943 ath_stoprecv(sc, 1); /* turn off frame recv */
4945 * First, handle completed TX/RX frames.
4948 ath_draintxq(sc, ATH_RESET_NOLOSS);
4950 * Next, flush the non-scheduled frames.
4952 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */
4954 ath_update_chainmasks(sc, chan);
4955 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
4956 sc->sc_cur_rxchainmask);
4957 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) {
4958 if_printf(ifp, "%s: unable to reset "
4959 "channel %u (%u MHz, flags 0x%x), hal status %u\n",
4960 __func__, ieee80211_chan2ieee(ic, chan),
4961 chan->ic_freq, chan->ic_flags, status);
4965 sc->sc_diversity = ath_hal_getdiversity(ah);
4967 /* Let DFS at it in case it's a DFS channel */
4968 ath_dfs_radar_enable(sc, chan);
4970 /* Let spectral at in case spectral is enabled */
4971 ath_spectral_enable(sc, chan);
4974 * Let bluetooth coexistence at in case it's needed for this
4977 ath_btcoex_enable(sc, ic->ic_curchan);
4980 * If we're doing TDMA, enforce the TXOP limitation for chips
4983 if (sc->sc_hasenforcetxop && sc->sc_tdma)
4984 ath_hal_setenforcetxop(sc->sc_ah, 1);
4986 ath_hal_setenforcetxop(sc->sc_ah, 0);
4989 * Re-enable rx framework.
4991 if (ath_startrecv(sc) != 0) {
4992 if_printf(ifp, "%s: unable to restart recv logic\n",
4999 * Change channels and update the h/w rate map
5000 * if we're switching; e.g. 11a to 11b/g.
5002 ath_chan_change(sc, chan);
5005 * Reset clears the beacon timers; reset them
5008 if (sc->sc_beacons) { /* restart beacons */
5009 #ifdef IEEE80211_SUPPORT_TDMA
5011 ath_tdma_config(sc, NULL);
5014 ath_beacon_config(sc, NULL);
5018 * Re-enable interrupts.
5021 ath_hal_intrset(ah, sc->sc_imask);
5027 sc->sc_inreset_cnt--;
5028 /* XXX only do this if sc_inreset_cnt == 0? */
5029 ath_hal_intrset(ah, sc->sc_imask);
5032 IF_LOCK(&ifp->if_snd);
5033 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5034 IF_UNLOCK(&ifp->if_snd);
5036 /* XXX ath_start? */
5042 * Periodically recalibrate the PHY to account
5043 * for temperature/environment changes.
5046 ath_calibrate(void *arg)
5048 struct ath_softc *sc = arg;
5049 struct ath_hal *ah = sc->sc_ah;
5050 struct ifnet *ifp = sc->sc_ifp;
5051 struct ieee80211com *ic = ifp->if_l2com;
5052 HAL_BOOL longCal, isCalDone = AH_TRUE;
5053 HAL_BOOL aniCal, shortCal = AH_FALSE;
5056 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */
5058 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz);
5059 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000);
5060 if (sc->sc_doresetcal)
5061 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000);
5063 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal);
5065 sc->sc_stats.ast_ani_cal++;
5066 sc->sc_lastani = ticks;
5067 ath_hal_ani_poll(ah, sc->sc_curchan);
5071 sc->sc_stats.ast_per_cal++;
5072 sc->sc_lastlongcal = ticks;
5073 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
5075 * Rfgain is out of bounds, reset the chip
5076 * to load new gain values.
5078 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5079 "%s: rfgain change\n", __func__);
5080 sc->sc_stats.ast_per_rfgain++;
5081 sc->sc_resetcal = 0;
5082 sc->sc_doresetcal = AH_TRUE;
5083 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
5084 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
5088 * If this long cal is after an idle period, then
5089 * reset the data collection state so we start fresh.
5091 if (sc->sc_resetcal) {
5092 (void) ath_hal_calreset(ah, sc->sc_curchan);
5093 sc->sc_lastcalreset = ticks;
5094 sc->sc_lastshortcal = ticks;
5095 sc->sc_resetcal = 0;
5096 sc->sc_doresetcal = AH_TRUE;
5100 /* Only call if we're doing a short/long cal, not for ANI calibration */
5101 if (shortCal || longCal) {
5102 isCalDone = AH_FALSE;
5103 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) {
5106 * Calibrate noise floor data again in case of change.
5108 ath_hal_process_noisefloor(ah);
5111 DPRINTF(sc, ATH_DEBUG_ANY,
5112 "%s: calibration of channel %u failed\n",
5113 __func__, sc->sc_curchan->ic_freq);
5114 sc->sc_stats.ast_per_calfail++;
5117 sc->sc_lastshortcal = ticks;
5122 * Use a shorter interval to potentially collect multiple
5123 * data samples required to complete calibration. Once
5124 * we're told the work is done we drop back to a longer
5125 * interval between requests. We're more aggressive doing
5126 * work when operating as an AP to improve operation right
5129 sc->sc_lastshortcal = ticks;
5130 nextcal = ath_shortcalinterval*hz/1000;
5131 if (sc->sc_opmode != HAL_M_HOSTAP)
5133 sc->sc_doresetcal = AH_TRUE;
5135 /* nextcal should be the shortest time for next event */
5136 nextcal = ath_longcalinterval*hz;
5137 if (sc->sc_lastcalreset == 0)
5138 sc->sc_lastcalreset = sc->sc_lastlongcal;
5139 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz)
5140 sc->sc_resetcal = 1; /* setup reset next trip */
5141 sc->sc_doresetcal = AH_FALSE;
5143 /* ANI calibration may occur more often than short/long/resetcal */
5144 if (ath_anicalinterval > 0)
5145 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000);
5148 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n",
5149 __func__, nextcal, isCalDone ? "" : "!");
5150 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc);
5152 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n",
5154 /* NB: don't rearm timer */
5159 ath_scan_start(struct ieee80211com *ic)
5161 struct ifnet *ifp = ic->ic_ifp;
5162 struct ath_softc *sc = ifp->if_softc;
5163 struct ath_hal *ah = sc->sc_ah;
5166 /* XXX calibration timer? */
5169 sc->sc_scanning = 1;
5170 sc->sc_syncbeacon = 0;
5171 rfilt = ath_calcrxfilter(sc);
5175 ath_hal_setrxfilter(ah, rfilt);
5176 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0);
5179 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n",
5180 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr));
5184 ath_scan_end(struct ieee80211com *ic)
5186 struct ifnet *ifp = ic->ic_ifp;
5187 struct ath_softc *sc = ifp->if_softc;
5188 struct ath_hal *ah = sc->sc_ah;
5192 sc->sc_scanning = 0;
5193 rfilt = ath_calcrxfilter(sc);
5197 ath_hal_setrxfilter(ah, rfilt);
5198 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5200 ath_hal_process_noisefloor(ah);
5203 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5204 __func__, rfilt, ether_sprintf(sc->sc_curbssid),
5208 #ifdef ATH_ENABLE_11N
5210 * For now, just do a channel change.
5212 * Later, we'll go through the hard slog of suspending tx/rx, changing rate
5213 * control state and resetting the hardware without dropping frames out
5216 * The unfortunate trouble here is making absolutely sure that the
5217 * channel width change has propagated enough so the hardware
5218 * absolutely isn't handed bogus frames for it's current operating
5219 * mode. (Eg, 40MHz frames in 20MHz mode.) Since TX and RX can and
5220 * does occur in parallel, we need to make certain we've blocked
5221 * any further ongoing TX (and RX, that can cause raw TX)
5222 * before we do this.
5225 ath_update_chw(struct ieee80211com *ic)
5227 struct ifnet *ifp = ic->ic_ifp;
5228 struct ath_softc *sc = ifp->if_softc;
5230 DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__);
5231 ath_set_channel(ic);
5233 #endif /* ATH_ENABLE_11N */
5236 ath_set_channel(struct ieee80211com *ic)
5238 struct ifnet *ifp = ic->ic_ifp;
5239 struct ath_softc *sc = ifp->if_softc;
5241 (void) ath_chan_set(sc, ic->ic_curchan);
5243 * If we are returning to our bss channel then mark state
5244 * so the next recv'd beacon's tsf will be used to sync the
5245 * beacon timers. Note that since we only hear beacons in
5246 * sta/ibss mode this has no effect in other operating modes.
5249 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan)
5250 sc->sc_syncbeacon = 1;
5255 * Walk the vap list and check if there any vap's in RUN state.
5258 ath_isanyrunningvaps(struct ieee80211vap *this)
5260 struct ieee80211com *ic = this->iv_ic;
5261 struct ieee80211vap *vap;
5263 IEEE80211_LOCK_ASSERT(ic);
5265 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
5266 if (vap != this && vap->iv_state >= IEEE80211_S_RUN)
5273 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
5275 struct ieee80211com *ic = vap->iv_ic;
5276 struct ath_softc *sc = ic->ic_ifp->if_softc;
5277 struct ath_vap *avp = ATH_VAP(vap);
5278 struct ath_hal *ah = sc->sc_ah;
5279 struct ieee80211_node *ni = NULL;
5280 int i, error, stamode;
5282 int csa_run_transition = 0;
5284 static const HAL_LED_STATE leds[] = {
5285 HAL_LED_INIT, /* IEEE80211_S_INIT */
5286 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
5287 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
5288 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
5289 HAL_LED_RUN, /* IEEE80211_S_CAC */
5290 HAL_LED_RUN, /* IEEE80211_S_RUN */
5291 HAL_LED_RUN, /* IEEE80211_S_CSA */
5292 HAL_LED_RUN, /* IEEE80211_S_SLEEP */
5295 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
5296 ieee80211_state_name[vap->iv_state],
5297 ieee80211_state_name[nstate]);
5300 * net80211 _should_ have the comlock asserted at this point.
5301 * There are some comments around the calls to vap->iv_newstate
5302 * which indicate that it (newstate) may end up dropping the
5303 * lock. This and the subsequent lock assert check after newstate
5304 * are an attempt to catch these and figure out how/why.
5306 IEEE80211_LOCK_ASSERT(ic);
5308 if (vap->iv_state == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN)
5309 csa_run_transition = 1;
5311 callout_drain(&sc->sc_cal_ch);
5312 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
5314 if (nstate == IEEE80211_S_SCAN) {
5316 * Scanning: turn off beacon miss and don't beacon.
5317 * Mark beacon state so when we reach RUN state we'll
5318 * [re]setup beacons. Unblock the task q thread so
5319 * deferred interrupt processing is done.
5322 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
5323 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5325 taskqueue_unblock(sc->sc_tq);
5328 ni = ieee80211_ref_node(vap->iv_bss);
5329 rfilt = ath_calcrxfilter(sc);
5330 stamode = (vap->iv_opmode == IEEE80211_M_STA ||
5331 vap->iv_opmode == IEEE80211_M_AHDEMO ||
5332 vap->iv_opmode == IEEE80211_M_IBSS);
5333 if (stamode && nstate == IEEE80211_S_RUN) {
5334 sc->sc_curaid = ni->ni_associd;
5335 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid);
5336 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5338 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5339 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid);
5340 ath_hal_setrxfilter(ah, rfilt);
5342 /* XXX is this to restore keycache on resume? */
5343 if (vap->iv_opmode != IEEE80211_M_STA &&
5344 (vap->iv_flags & IEEE80211_F_PRIVACY)) {
5345 for (i = 0; i < IEEE80211_WEP_NKID; i++)
5346 if (ath_hal_keyisvalid(ah, i))
5347 ath_hal_keysetmac(ah, i, ni->ni_bssid);
5351 * Invoke the parent method to do net80211 work.
5353 error = avp->av_newstate(vap, nstate, arg);
5358 * See above: ensure av_newstate() doesn't drop the lock
5361 IEEE80211_LOCK_ASSERT(ic);
5363 if (nstate == IEEE80211_S_RUN) {
5364 /* NB: collect bss node again, it may have changed */
5365 ieee80211_free_node(ni);
5366 ni = ieee80211_ref_node(vap->iv_bss);
5368 DPRINTF(sc, ATH_DEBUG_STATE,
5369 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s "
5370 "capinfo 0x%04x chan %d\n", __func__,
5371 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid),
5372 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan));
5374 switch (vap->iv_opmode) {
5375 #ifdef IEEE80211_SUPPORT_TDMA
5376 case IEEE80211_M_AHDEMO:
5377 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0)
5381 case IEEE80211_M_HOSTAP:
5382 case IEEE80211_M_IBSS:
5383 case IEEE80211_M_MBSS:
5385 * Allocate and setup the beacon frame.
5387 * Stop any previous beacon DMA. This may be
5388 * necessary, for example, when an ibss merge
5389 * causes reconfiguration; there will be a state
5390 * transition from RUN->RUN that means we may
5391 * be called with beacon transmission active.
5393 ath_hal_stoptxdma(ah, sc->sc_bhalq);
5395 error = ath_beacon_alloc(sc, ni);
5399 * If joining an adhoc network defer beacon timer
5400 * configuration to the next beacon frame so we
5401 * have a current TSF to use. Otherwise we're
5402 * starting an ibss/bss so there's no need to delay;
5403 * if this is the first vap moving to RUN state, then
5404 * beacon state needs to be [re]configured.
5406 if (vap->iv_opmode == IEEE80211_M_IBSS &&
5407 ni->ni_tstamp.tsf != 0) {
5408 sc->sc_syncbeacon = 1;
5409 } else if (!sc->sc_beacons) {
5410 #ifdef IEEE80211_SUPPORT_TDMA
5411 if (vap->iv_caps & IEEE80211_C_TDMA)
5412 ath_tdma_config(sc, vap);
5415 ath_beacon_config(sc, vap);
5419 case IEEE80211_M_STA:
5421 * Defer beacon timer configuration to the next
5422 * beacon frame so we have a current TSF to use
5423 * (any TSF collected when scanning is likely old).
5424 * However if it's due to a CSA -> RUN transition,
5425 * force a beacon update so we pick up a lack of
5426 * beacons from an AP in CAC and thus force a
5429 * And, there's also corner cases here where
5430 * after a scan, the AP may have disappeared.
5431 * In that case, we may not receive an actual
5432 * beacon to update the beacon timer and thus we
5433 * won't get notified of the missing beacons.
5435 sc->sc_syncbeacon = 1;
5437 if (csa_run_transition)
5439 ath_beacon_config(sc, vap);
5444 * Reconfigure beacons during reset; as otherwise
5445 * we won't get the beacon timers reprogrammed
5446 * after a reset and thus we won't pick up a
5447 * beacon miss interrupt.
5449 * Hopefully we'll see a beacon before the BMISS
5450 * timer fires (too often), leading to a STA
5455 case IEEE80211_M_MONITOR:
5457 * Monitor mode vaps have only INIT->RUN and RUN->RUN
5458 * transitions so we must re-enable interrupts here to
5459 * handle the case of a single monitor mode vap.
5461 ath_hal_intrset(ah, sc->sc_imask);
5463 case IEEE80211_M_WDS:
5469 * Let the hal process statistics collected during a
5470 * scan so it can provide calibrated noise floor data.
5472 ath_hal_process_noisefloor(ah);
5474 * Reset rssi stats; maybe not the best place...
5476 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
5477 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
5478 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
5480 * Finally, start any timers and the task q thread
5481 * (in case we didn't go through SCAN state).
5483 if (ath_longcalinterval != 0) {
5484 /* start periodic recalibration timer */
5485 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
5487 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5488 "%s: calibration disabled\n", __func__);
5490 taskqueue_unblock(sc->sc_tq);
5491 } else if (nstate == IEEE80211_S_INIT) {
5493 * If there are no vaps left in RUN state then
5494 * shutdown host/driver operation:
5495 * o disable interrupts
5496 * o disable the task queue thread
5497 * o mark beacon processing as stopped
5499 if (!ath_isanyrunningvaps(vap)) {
5500 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5501 /* disable interrupts */
5502 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
5503 taskqueue_block(sc->sc_tq);
5506 #ifdef IEEE80211_SUPPORT_TDMA
5507 ath_hal_setcca(ah, AH_TRUE);
5511 ieee80211_free_node(ni);
5516 * Allocate a key cache slot to the station so we can
5517 * setup a mapping from key index to node. The key cache
5518 * slot is needed for managing antenna state and for
5519 * compression when stations do not use crypto. We do
5520 * it uniliaterally here; if crypto is employed this slot
5521 * will be reassigned.
5524 ath_setup_stationkey(struct ieee80211_node *ni)
5526 struct ieee80211vap *vap = ni->ni_vap;
5527 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
5528 ieee80211_keyix keyix, rxkeyix;
5530 /* XXX should take a locked ref to vap->iv_bss */
5531 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
5533 * Key cache is full; we'll fall back to doing
5534 * the more expensive lookup in software. Note
5535 * this also means no h/w compression.
5537 /* XXX msg+statistic */
5540 ni->ni_ucastkey.wk_keyix = keyix;
5541 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
5542 /* NB: must mark device key to get called back on delete */
5543 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY;
5544 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr);
5545 /* NB: this will create a pass-thru key entry */
5546 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss);
5551 * Setup driver-specific state for a newly associated node.
5552 * Note that we're called also on a re-associate, the isnew
5553 * param tells us if this is the first time or not.
5556 ath_newassoc(struct ieee80211_node *ni, int isnew)
5558 struct ath_node *an = ATH_NODE(ni);
5559 struct ieee80211vap *vap = ni->ni_vap;
5560 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
5561 const struct ieee80211_txparam *tp = ni->ni_txparms;
5563 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate);
5564 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate);
5566 ath_rate_newassoc(sc, an, isnew);
5569 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey &&
5570 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
5571 ath_setup_stationkey(ni);
5574 * If we're reassociating, make sure that any paused queues
5577 * Now, we may hvae frames in the hardware queue for this node.
5578 * So if we are reassociating and there are frames in the queue,
5579 * we need to go through the cleanup path to ensure that they're
5580 * marked as non-aggregate.
5583 DPRINTF(sc, ATH_DEBUG_NODE,
5584 "%s: %6D: reassoc; is_powersave=%d\n",
5588 an->an_is_powersave);
5590 /* XXX for now, we can't hold the lock across assoc */
5591 ath_tx_node_reassoc(sc, an);
5593 /* XXX for now, we can't hold the lock across wakeup */
5594 if (an->an_is_powersave)
5595 ath_tx_node_wakeup(sc, an);
5600 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg,
5601 int nchans, struct ieee80211_channel chans[])
5603 struct ath_softc *sc = ic->ic_ifp->if_softc;
5604 struct ath_hal *ah = sc->sc_ah;
5607 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
5608 "%s: rd %u cc %u location %c%s\n",
5609 __func__, reg->regdomain, reg->country, reg->location,
5610 reg->ecm ? " ecm" : "");
5612 status = ath_hal_set_channels(ah, chans, nchans,
5613 reg->country, reg->regdomain);
5614 if (status != HAL_OK) {
5615 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n",
5617 return EINVAL; /* XXX */
5624 ath_getradiocaps(struct ieee80211com *ic,
5625 int maxchans, int *nchans, struct ieee80211_channel chans[])
5627 struct ath_softc *sc = ic->ic_ifp->if_softc;
5628 struct ath_hal *ah = sc->sc_ah;
5630 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n",
5631 __func__, SKU_DEBUG, CTRY_DEFAULT);
5633 /* XXX check return */
5634 (void) ath_hal_getchannels(ah, chans, maxchans, nchans,
5635 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE);
5640 ath_getchannels(struct ath_softc *sc)
5642 struct ifnet *ifp = sc->sc_ifp;
5643 struct ieee80211com *ic = ifp->if_l2com;
5644 struct ath_hal *ah = sc->sc_ah;
5648 * Collect channel set based on EEPROM contents.
5650 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX,
5651 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE);
5652 if (status != HAL_OK) {
5653 if_printf(ifp, "%s: unable to collect channel list from hal, "
5654 "status %d\n", __func__, status);
5657 (void) ath_hal_getregdomain(ah, &sc->sc_eerd);
5658 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */
5659 /* XXX map Atheros sku's to net80211 SKU's */
5660 /* XXX net80211 types too small */
5661 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd;
5662 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc;
5663 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */
5664 ic->ic_regdomain.isocc[1] = ' ';
5666 ic->ic_regdomain.ecm = 1;
5667 ic->ic_regdomain.location = 'I';
5669 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
5670 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n",
5671 __func__, sc->sc_eerd, sc->sc_eecc,
5672 ic->ic_regdomain.regdomain, ic->ic_regdomain.country,
5673 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : "");
5678 ath_rate_setup(struct ath_softc *sc, u_int mode)
5680 struct ath_hal *ah = sc->sc_ah;
5681 const HAL_RATE_TABLE *rt;
5684 case IEEE80211_MODE_11A:
5685 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
5687 case IEEE80211_MODE_HALF:
5688 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE);
5690 case IEEE80211_MODE_QUARTER:
5691 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE);
5693 case IEEE80211_MODE_11B:
5694 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
5696 case IEEE80211_MODE_11G:
5697 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
5699 case IEEE80211_MODE_TURBO_A:
5700 rt = ath_hal_getratetable(ah, HAL_MODE_108A);
5702 case IEEE80211_MODE_TURBO_G:
5703 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
5705 case IEEE80211_MODE_STURBO_A:
5706 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
5708 case IEEE80211_MODE_11NA:
5709 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20);
5711 case IEEE80211_MODE_11NG:
5712 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20);
5715 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
5719 sc->sc_rates[mode] = rt;
5720 return (rt != NULL);
5724 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
5726 #define N(a) (sizeof(a)/sizeof(a[0]))
5727 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
5728 static const struct {
5729 u_int rate; /* tx/rx 802.11 rate */
5730 u_int16_t timeOn; /* LED on time (ms) */
5731 u_int16_t timeOff; /* LED off time (ms) */
5747 /* XXX half/quarter rates */
5749 const HAL_RATE_TABLE *rt;
5752 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
5753 rt = sc->sc_rates[mode];
5754 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
5755 for (i = 0; i < rt->rateCount; i++) {
5756 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
5757 if (rt->info[i].phy != IEEE80211_T_HT)
5758 sc->sc_rixmap[ieeerate] = i;
5760 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i;
5762 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
5763 for (i = 0; i < N(sc->sc_hwmap); i++) {
5764 if (i >= rt->rateCount) {
5765 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
5766 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
5769 sc->sc_hwmap[i].ieeerate =
5770 rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
5771 if (rt->info[i].phy == IEEE80211_T_HT)
5772 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS;
5773 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
5774 if (rt->info[i].shortPreamble ||
5775 rt->info[i].phy == IEEE80211_T_OFDM)
5776 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
5777 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags;
5778 for (j = 0; j < N(blinkrates)-1; j++)
5779 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
5781 /* NB: this uses the last entry if the rate isn't found */
5782 /* XXX beware of overlow */
5783 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
5784 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
5786 sc->sc_currates = rt;
5787 sc->sc_curmode = mode;
5789 * All protection frames are transmited at 2Mb/s for
5790 * 11g, otherwise at 1Mb/s.
5792 if (mode == IEEE80211_MODE_11G)
5793 sc->sc_protrix = ath_tx_findrix(sc, 2*2);
5795 sc->sc_protrix = ath_tx_findrix(sc, 2*1);
5796 /* NB: caller is responsible for resetting rate control state */
5801 ath_watchdog(void *arg)
5803 struct ath_softc *sc = arg;
5806 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) {
5807 struct ifnet *ifp = sc->sc_ifp;
5810 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) &&
5812 if_printf(ifp, "%s hang detected (0x%x)\n",
5813 hangs & 0xff ? "bb" : "mac", hangs);
5815 if_printf(ifp, "device timeout\n");
5818 sc->sc_stats.ast_watchdog++;
5822 * We can't hold the lock across the ath_reset() call.
5824 * And since this routine can't hold a lock and sleep,
5825 * do the reset deferred.
5828 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
5831 callout_schedule(&sc->sc_wd_ch, hz);
5835 * Fetch the rate control statistics for the given node.
5838 ath_ioctl_ratestats(struct ath_softc *sc, struct ath_rateioctl *rs)
5840 struct ath_node *an;
5841 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
5842 struct ieee80211_node *ni;
5845 /* Perform a lookup on the given node */
5846 ni = ieee80211_find_node(&ic->ic_sta, rs->is_u.macaddr);
5852 /* Lock the ath_node */
5856 /* Fetch the rate control stats for this node */
5857 error = ath_rate_fetch_node_stats(sc, an, rs);
5859 /* No matter what happens here, just drop through */
5861 /* Unlock the ath_node */
5862 ATH_NODE_UNLOCK(an);
5864 /* Unref the node */
5865 ieee80211_node_decref(ni);
5873 * Diagnostic interface to the HAL. This is used by various
5874 * tools to do things like retrieve register contents for
5875 * debugging. The mechanism is intentionally opaque so that
5876 * it can change frequently w/o concern for compatiblity.
5879 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
5881 struct ath_hal *ah = sc->sc_ah;
5882 u_int id = ad->ad_id & ATH_DIAG_ID;
5883 void *indata = NULL;
5884 void *outdata = NULL;
5885 u_int32_t insize = ad->ad_in_size;
5886 u_int32_t outsize = ad->ad_out_size;
5889 if (ad->ad_id & ATH_DIAG_IN) {
5893 indata = malloc(insize, M_TEMP, M_NOWAIT);
5894 if (indata == NULL) {
5898 error = copyin(ad->ad_in_data, indata, insize);
5902 if (ad->ad_id & ATH_DIAG_DYN) {
5904 * Allocate a buffer for the results (otherwise the HAL
5905 * returns a pointer to a buffer where we can read the
5906 * results). Note that we depend on the HAL leaving this
5907 * pointer for us to use below in reclaiming the buffer;
5908 * may want to be more defensive.
5910 outdata = malloc(outsize, M_TEMP, M_NOWAIT);
5911 if (outdata == NULL) {
5916 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
5917 if (outsize < ad->ad_out_size)
5918 ad->ad_out_size = outsize;
5919 if (outdata != NULL)
5920 error = copyout(outdata, ad->ad_out_data,
5926 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
5927 free(indata, M_TEMP);
5928 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
5929 free(outdata, M_TEMP);
5932 #endif /* ATH_DIAGAPI */
5935 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
5937 #define IS_RUNNING(ifp) \
5938 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
5939 struct ath_softc *sc = ifp->if_softc;
5940 struct ieee80211com *ic = ifp->if_l2com;
5941 struct ifreq *ifr = (struct ifreq *)data;
5942 const HAL_RATE_TABLE *rt;
5948 if (IS_RUNNING(ifp)) {
5950 * To avoid rescanning another access point,
5951 * do not call ath_init() here. Instead,
5952 * only reflect promisc mode settings.
5955 } else if (ifp->if_flags & IFF_UP) {
5957 * Beware of being called during attach/detach
5958 * to reset promiscuous mode. In that case we
5959 * will still be marked UP but not RUNNING.
5960 * However trying to re-init the interface
5961 * is the wrong thing to do as we've already
5962 * torn down much of our state. There's
5963 * probably a better way to deal with this.
5965 if (!sc->sc_invalid)
5966 ath_init(sc); /* XXX lose error */
5968 ath_stop_locked(ifp);
5970 /* XXX must wakeup in places like ath_vap_delete */
5971 if (!sc->sc_invalid)
5972 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP);
5979 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
5982 /* NB: embed these numbers to get a consistent view */
5983 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
5984 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
5985 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi);
5986 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi);
5987 #ifdef IEEE80211_SUPPORT_TDMA
5988 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap);
5989 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam);
5991 rt = sc->sc_currates;
5992 sc->sc_stats.ast_tx_rate =
5993 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC;
5994 if (rt->info[sc->sc_txrix].phy & IEEE80211_T_HT)
5995 sc->sc_stats.ast_tx_rate |= IEEE80211_RATE_MCS;
5996 return copyout(&sc->sc_stats,
5997 ifr->ifr_data, sizeof (sc->sc_stats));
5998 case SIOCGATHAGSTATS:
5999 return copyout(&sc->sc_aggr_stats,
6000 ifr->ifr_data, sizeof (sc->sc_aggr_stats));
6002 error = priv_check(curthread, PRIV_DRIVER);
6004 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats));
6005 memset(&sc->sc_aggr_stats, 0,
6006 sizeof(sc->sc_aggr_stats));
6007 memset(&sc->sc_intr_stats, 0,
6008 sizeof(sc->sc_intr_stats));
6013 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
6015 case SIOCGATHPHYERR:
6016 error = ath_ioctl_phyerr(sc,(struct ath_diag*) ifr);
6019 case SIOCGATHSPECTRAL:
6020 error = ath_ioctl_spectral(sc,(struct ath_diag*) ifr);
6022 case SIOCGATHNODERATESTATS:
6023 error = ath_ioctl_ratestats(sc, (struct ath_rateioctl *) ifr);
6026 error = ether_ioctl(ifp, cmd, data);
6037 * Announce various information on device/driver attach.
6040 ath_announce(struct ath_softc *sc)
6042 struct ifnet *ifp = sc->sc_ifp;
6043 struct ath_hal *ah = sc->sc_ah;
6045 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n",
6046 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev,
6047 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
6048 if_printf(ifp, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n",
6049 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev);
6052 for (i = 0; i <= WME_AC_VO; i++) {
6053 struct ath_txq *txq = sc->sc_ac2q[i];
6054 if_printf(ifp, "Use hw queue %u for %s traffic\n",
6055 txq->axq_qnum, ieee80211_wme_acnames[i]);
6057 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
6058 sc->sc_cabq->axq_qnum);
6059 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
6061 if (ath_rxbuf != ATH_RXBUF)
6062 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
6063 if (ath_txbuf != ATH_TXBUF)
6064 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
6065 if (sc->sc_mcastkey && bootverbose)
6066 if_printf(ifp, "using multicast key search\n");
6070 ath_dfs_tasklet(void *p, int npending)
6072 struct ath_softc *sc = (struct ath_softc *) p;
6073 struct ifnet *ifp = sc->sc_ifp;
6074 struct ieee80211com *ic = ifp->if_l2com;
6077 * If previous processing has found a radar event,
6078 * signal this to the net80211 layer to begin DFS
6081 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) {
6082 /* DFS event found, initiate channel change */
6084 * XXX doesn't currently tell us whether the event
6085 * XXX was found in the primary or extension
6089 ieee80211_dfs_notify_radar(ic, sc->sc_curchan);
6090 IEEE80211_UNLOCK(ic);
6095 * Enable/disable power save. This must be called with
6096 * no TX driver locks currently held, so it should only
6097 * be called from the RX path (which doesn't hold any
6101 ath_node_powersave(struct ieee80211_node *ni, int enable)
6104 struct ath_node *an = ATH_NODE(ni);
6105 struct ieee80211com *ic = ni->ni_ic;
6106 struct ath_softc *sc = ic->ic_ifp->if_softc;
6107 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6109 /* XXX and no TXQ locks should be held here */
6111 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, "%s: %6D: enable=%d\n",
6117 /* Suspend or resume software queue handling */
6119 ath_tx_node_sleep(sc, an);
6121 ath_tx_node_wakeup(sc, an);
6123 /* Update net80211 state */
6124 avp->av_node_ps(ni, enable);
6126 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6128 /* Update net80211 state */
6129 avp->av_node_ps(ni, enable);
6130 #endif/* ATH_SW_PSQ */
6134 * Notification from net80211 that the powersave queue state has
6137 * Since the software queue also may have some frames:
6139 * + if the node software queue has frames and the TID state
6140 * is 0, we set the TIM;
6141 * + if the node and the stack are both empty, we clear the TIM bit.
6142 * + If the stack tries to set the bit, always set it.
6143 * + If the stack tries to clear the bit, only clear it if the
6144 * software queue in question is also cleared.
6146 * TODO: this is called during node teardown; so let's ensure this
6147 * is all correctly handled and that the TIM bit is cleared.
6148 * It may be that the node flush is called _AFTER_ the net80211
6149 * stack clears the TIM.
6151 * Here is the racy part. Since it's possible >1 concurrent,
6152 * overlapping TXes will appear complete with a TX completion in
6153 * another thread, it's possible that the concurrent TIM calls will
6154 * clash. We can't hold the node lock here because setting the
6155 * TIM grabs the net80211 comlock and this may cause a LOR.
6156 * The solution is either to totally serialise _everything_ at
6157 * this point (ie, all TX, completion and any reset/flush go into
6158 * one taskqueue) or a new "ath TIM lock" needs to be created that
6159 * just wraps the driver state change and this call to avp->av_set_tim().
6161 * The same race exists in the net80211 power save queue handling
6162 * as well. Since multiple transmitting threads may queue frames
6163 * into the driver, as well as ps-poll and the driver transmitting
6164 * frames (and thus clearing the psq), it's quite possible that
6165 * a packet entering the PSQ and a ps-poll being handled will
6166 * race, causing the TIM to be cleared and not re-set.
6169 ath_node_set_tim(struct ieee80211_node *ni, int enable)
6172 struct ieee80211com *ic = ni->ni_ic;
6173 struct ath_softc *sc = ic->ic_ifp->if_softc;
6174 struct ath_node *an = ATH_NODE(ni);
6175 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6179 an->an_stack_psq = enable;
6182 * This will get called for all operating modes,
6183 * even if avp->av_set_tim is unset.
6184 * It's currently set for hostap/ibss modes; but
6185 * the same infrastructure is used for both STA
6186 * and AP/IBSS node power save.
6188 if (avp->av_set_tim == NULL) {
6194 * If setting the bit, always set it here.
6195 * If clearing the bit, only clear it if the
6196 * software queue is also empty.
6198 * If the node has left power save, just clear the TIM
6199 * bit regardless of the state of the power save queue.
6201 * XXX TODO: although atomics are used, it's quite possible
6202 * that a race will occur between this and setting/clearing
6203 * in another thread. TX completion will occur always in
6204 * one thread, however setting/clearing the TIM bit can come
6205 * from a variety of different process contexts!
6207 if (enable && an->an_tim_set == 1) {
6208 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6209 "%s: %6D: enable=%d, tim_set=1, ignoring\n",
6215 } else if (enable) {
6216 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6217 "%s: %6D: enable=%d, enabling TIM\n",
6224 changed = avp->av_set_tim(ni, enable);
6225 } else if (an->an_swq_depth == 0) {
6227 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6228 "%s: %6D: enable=%d, an_swq_depth == 0, disabling\n",
6235 changed = avp->av_set_tim(ni, enable);
6236 } else if (! an->an_is_powersave) {
6238 * disable regardless; the node isn't in powersave now
6240 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6241 "%s: %6D: enable=%d, an_pwrsave=0, disabling\n",
6248 changed = avp->av_set_tim(ni, enable);
6251 * psq disable, node is currently in powersave, node
6252 * software queue isn't empty, so don't clear the TIM bit
6256 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6257 "%s: %6D: enable=%d, an_swq_depth > 0, ignoring\n",
6267 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6270 * Some operating modes don't set av_set_tim(), so don't
6273 if (avp->av_set_tim == NULL)
6276 return (avp->av_set_tim(ni, enable));
6277 #endif /* ATH_SW_PSQ */
6281 * Set or update the TIM from the software queue.
6283 * Check the software queue depth before attempting to do lock
6284 * anything; that avoids trying to obtain the lock. Then,
6285 * re-check afterwards to ensure nothing has changed in the
6288 * set: This is designed to be called from the TX path, after
6289 * a frame has been queued; to see if the swq > 0.
6291 * clear: This is designed to be called from the buffer completion point
6292 * (right now it's ath_tx_default_comp()) where the state of
6293 * a software queue has changed.
6295 * It makes sense to place it at buffer free / completion rather
6296 * than after each software queue operation, as there's no real
6297 * point in churning the TIM bit as the last frames in the software
6298 * queue are transmitted. If they fail and we retry them, we'd
6299 * just be setting the TIM bit again anyway.
6302 ath_tx_update_tim(struct ath_softc *sc, struct ieee80211_node *ni,
6306 struct ath_node *an;
6307 struct ath_vap *avp;
6309 /* Don't do this for broadcast/etc frames */
6314 avp = ATH_VAP(ni->ni_vap);
6317 * And for operating modes without the TIM handler set, let's
6320 if (avp->av_set_tim == NULL)
6323 ATH_TX_LOCK_ASSERT(sc);
6326 if (an->an_is_powersave &&
6327 an->an_tim_set == 0 &&
6328 an->an_swq_depth != 0) {
6329 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6330 "%s: %6D: swq_depth>0, tim_set=0, set!\n",
6335 (void) avp->av_set_tim(ni, 1);
6339 * Don't bother grabbing the lock unless the queue is empty.
6341 if (&an->an_swq_depth != 0)
6344 if (an->an_is_powersave &&
6345 an->an_stack_psq == 0 &&
6346 an->an_tim_set == 1 &&
6347 an->an_swq_depth == 0) {
6348 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6349 "%s: %6D: swq_depth=0, tim_set=1, psq_set=0,"
6355 (void) avp->av_set_tim(ni, 0);
6360 #endif /* ATH_SW_PSQ */
6364 * Received a ps-poll frame from net80211.
6366 * Here we get a chance to serve out a software-queued frame ourselves
6367 * before we punt it to net80211 to transmit us one itself - either
6368 * because there's traffic in the net80211 psq, or a NULL frame to
6369 * indicate there's nothing else.
6372 ath_node_recv_pspoll(struct ieee80211_node *ni, struct mbuf *m)
6375 struct ath_node *an;
6376 struct ath_vap *avp;
6377 struct ieee80211com *ic = ni->ni_ic;
6378 struct ath_softc *sc = ic->ic_ifp->if_softc;
6386 * Unassociated (temporary node) station.
6388 if (ni->ni_associd == 0)
6392 * We do have an active node, so let's begin looking into it.
6395 avp = ATH_VAP(ni->ni_vap);
6398 * For now, we just call the original ps-poll method.
6399 * Once we're ready to flip this on:
6401 * + Set leak to 1, as no matter what we're going to have
6403 * + Check the software queue and if there's something in it,
6404 * schedule the highest TID thas has traffic from this node.
6405 * Then make sure we schedule the software scheduler to
6406 * run so it picks up said frame.
6408 * That way whatever happens, we'll at least send _a_ frame
6409 * to the given node.
6411 * Again, yes, it's crappy QoS if the node has multiple
6412 * TIDs worth of traffic - but let's get it working first
6413 * before we optimise it.
6415 * Also yes, there's definitely latency here - we're not
6416 * direct dispatching to the hardware in this path (and
6417 * we're likely being called from the packet receive path,
6418 * so going back into TX may be a little hairy!) but again
6419 * I'd like to get this working first before optimising
6426 * Legacy - we're called and the node isn't asleep.
6429 if (! an->an_is_powersave) {
6430 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6431 "%s: %6D: not in powersave?\n",
6436 avp->av_recv_pspoll(ni, m);
6441 * We're in powersave.
6445 an->an_leak_count = 1;
6448 * Now, if there's no frames in the node, just punt to
6451 * Don't bother checking if the TIM bit is set, we really
6452 * only care if there are any frames here!
6454 if (an->an_swq_depth == 0) {
6456 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6457 "%s: %6D: SWQ empty; punting to net80211\n",
6461 avp->av_recv_pspoll(ni, m);
6466 * Ok, let's schedule the highest TID that has traffic
6467 * and then schedule something.
6469 for (tid = IEEE80211_TID_SIZE - 1; tid >= 0; tid--) {
6470 struct ath_tid *atid = &an->an_tid[tid];
6474 if (atid->axq_depth == 0)
6476 ath_tx_tid_sched(sc, atid);
6478 * XXX we could do a direct call to the TXQ
6479 * scheduler code here to optimise latency
6480 * at the expense of a REALLY deep callstack.
6483 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask);
6484 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6485 "%s: %6D: leaking frame to TID %d\n",
6496 * XXX nothing in the TIDs at this point? Eek.
6498 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6499 "%s: %6D: TIDs empty, but ath_node showed traffic?!\n",
6503 avp->av_recv_pspoll(ni, m);
6505 avp->av_recv_pspoll(ni, m);
6506 #endif /* ATH_SW_PSQ */
6509 MODULE_VERSION(if_ath, 1);
6510 MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */
6511 #if defined(IEEE80211_ALQ) || defined(AH_DEBUG_ALQ)
6512 MODULE_DEPEND(if_ath, alq, 1, 1, 1);