sys/dev/netif/bnx/if_bnx.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 #include "opt_bnx.h"
  37 #include "opt_ifpoll.h"
  38
  39 #include <sys/param.h>
  40 #include <sys/bus.h>
  41 #include <sys/endian.h>
  42 #include <sys/kernel.h>
  43 #include <sys/interrupt.h>
  44 #include <sys/mbuf.h>
  45 #include <sys/malloc.h>
  46 #include <sys/queue.h>
  47 #include <sys/rman.h>
  48 #include <sys/serialize.h>
  49 #include <sys/socket.h>
  50 #include <sys/sockio.h>
  51 #include <sys/sysctl.h>
  52
  53 #include <netinet/ip.h>
  54 #include <netinet/tcp.h>
  55
  56 #include <net/bpf.h>
  57 #include <net/ethernet.h>
  58 #include <net/if.h>
  59 #include <net/if_arp.h>
  60 #include <net/if_dl.h>
  61 #include <net/if_media.h>
  62 #include <net/if_poll.h>
  63 #include <net/if_types.h>
  64 #include <net/ifq_var.h>
  65 #include <net/toeplitz.h>
  66 #include <net/toeplitz2.h>
  67 #include <net/vlan/if_vlan_var.h>
  68 #include <net/vlan/if_vlan_ether.h>
  69
  70 #include <dev/netif/mii_layer/mii.h>
  71 #include <dev/netif/mii_layer/miivar.h>
  72 #include <dev/netif/mii_layer/brgphyreg.h>
  73
  74 #include <bus/pci/pcidevs.h>
  75 #include <bus/pci/pcireg.h>
  76 #include <bus/pci/pcivar.h>
  77
  78 #include <dev/netif/bge/if_bgereg.h>
  79 #include <dev/netif/bnx/if_bnxvar.h>
  80
  81 /* "device miibus" required.  See GENERIC if you get errors here. */
  82 #include "miibus_if.h"
  83
  84 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  85
  86 #define BNX_INTR_CKINTVL        ((10 * hz) / 1000)      /* 10ms */
  87
  88 #ifdef BNX_RSS_DEBUG
  89 #define BNX_RSS_DPRINTF(sc, lvl, fmt, ...) \
  90 do { \
  91         if (sc->bnx_rss_debug >= lvl) \
  92                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
  93 } while (0)
  94 #else   /* !BNX_RSS_DEBUG */
  95 #define BNX_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  96 #endif  /* BNX_RSS_DEBUG */
  97
  98 static const struct bnx_type {
  99         uint16_t                bnx_vid;
 100         uint16_t                bnx_did;
 101         char                    *bnx_name;
 102 } bnx_devs[] = {
 103         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
 104                 "Broadcom BCM5717 Gigabit Ethernet" },
 105         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C,
 106                 "Broadcom BCM5717C Gigabit Ethernet" },
 107         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
 108                 "Broadcom BCM5718 Gigabit Ethernet" },
 109         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
 110                 "Broadcom BCM5719 Gigabit Ethernet" },
 111         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
 112                 "Broadcom BCM5720 Gigabit Ethernet" },
 113
 114         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725,
 115                 "Broadcom BCM5725 Gigabit Ethernet" },
 116         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727,
 117                 "Broadcom BCM5727 Gigabit Ethernet" },
 118         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762,
 119                 "Broadcom BCM5762 Gigabit Ethernet" },
 120
 121         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
 122                 "Broadcom BCM57761 Gigabit Ethernet" },
 123         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
 124                 "Broadcom BCM57762 Gigabit Ethernet" },
 125         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
 126                 "Broadcom BCM57765 Gigabit Ethernet" },
 127         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
 128                 "Broadcom BCM57766 Gigabit Ethernet" },
 129         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
 130                 "Broadcom BCM57781 Gigabit Ethernet" },
 131         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
 132                 "Broadcom BCM57782 Gigabit Ethernet" },
 133         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
 134                 "Broadcom BCM57785 Gigabit Ethernet" },
 135         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
 136                 "Broadcom BCM57786 Gigabit Ethernet" },
 137         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
 138                 "Broadcom BCM57791 Fast Ethernet" },
 139         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
 140                 "Broadcom BCM57795 Fast Ethernet" },
 141
 142         { 0, 0, NULL }
 143 };
 144
 145 static const int bnx_tx_mailbox[BNX_TX_RING_MAX] = {
 146         BGE_MBX_TX_HOST_PROD0_LO,
 147         BGE_MBX_TX_HOST_PROD0_HI,
 148         BGE_MBX_TX_HOST_PROD1_LO,
 149         BGE_MBX_TX_HOST_PROD1_HI
 150 };
 151
 152 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
 153 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
 154 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
 155 #define BNX_IS_57765_FAMILY(sc)  \
 156         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
 157
 158 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
 159
 160 static int      bnx_probe(device_t);
 161 static int      bnx_attach(device_t);
 162 static int      bnx_detach(device_t);
 163 static void     bnx_shutdown(device_t);
 164 static int      bnx_suspend(device_t);
 165 static int      bnx_resume(device_t);
 166 static int      bnx_miibus_readreg(device_t, int, int);
 167 static int      bnx_miibus_writereg(device_t, int, int, int);
 168 static void     bnx_miibus_statchg(device_t);
 169
 170 static void     bnx_handle_status(struct bnx_softc *);
 171 #ifdef IFPOLL_ENABLE
 172 static void     bnx_npoll(struct ifnet *, struct ifpoll_info *);
 173 static void     bnx_npoll_rx(struct ifnet *, void *, int);
 174 static void     bnx_npoll_tx(struct ifnet *, void *, int);
 175 static void     bnx_npoll_tx_notag(struct ifnet *, void *, int);
 176 static void     bnx_npoll_status(struct ifnet *);
 177 static void     bnx_npoll_status_notag(struct ifnet *);
 178 #endif
 179 static void     bnx_intr_legacy(void *);
 180 static void     bnx_msi(void *);
 181 static void     bnx_intr(struct bnx_softc *);
 182 static void     bnx_msix_status(void *);
 183 static void     bnx_msix_tx_status(void *);
 184 static void     bnx_msix_rx(void *);
 185 static void     bnx_msix_rxtx(void *);
 186 static void     bnx_enable_intr(struct bnx_softc *);
 187 static void     bnx_disable_intr(struct bnx_softc *);
 188 static void     bnx_txeof(struct bnx_tx_ring *, uint16_t);
 189 static void     bnx_rxeof(struct bnx_rx_ret_ring *, uint16_t, int);
 190 static int      bnx_alloc_intr(struct bnx_softc *);
 191 static int      bnx_setup_intr(struct bnx_softc *);
 192 static void     bnx_free_intr(struct bnx_softc *);
 193 static void     bnx_teardown_intr(struct bnx_softc *, int);
 194 static int      bnx_alloc_msix(struct bnx_softc *);
 195 static void     bnx_free_msix(struct bnx_softc *, boolean_t);
 196 static void     bnx_check_intr_rxtx(void *);
 197 static void     bnx_check_intr_rx(void *);
 198 static void     bnx_check_intr_tx(void *);
 199 static void     bnx_rx_std_refill_ithread(void *);
 200 static void     bnx_rx_std_refill(void *, void *);
 201 static void     bnx_rx_std_refill_sched_ipi(void *);
 202 static void     bnx_rx_std_refill_stop(void *);
 203 static void     bnx_rx_std_refill_sched(struct bnx_rx_ret_ring *,
 204                     struct bnx_rx_std_ring *);
 205
 206 static void     bnx_start(struct ifnet *, struct ifaltq_subque *);
 207 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 208 static void     bnx_init(void *);
 209 static void     bnx_stop(struct bnx_softc *);
 210 static void     bnx_watchdog(struct ifaltq_subque *);
 211 static int      bnx_ifmedia_upd(struct ifnet *);
 212 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 213 static void     bnx_tick(void *);
 214 static void     bnx_serialize(struct ifnet *, enum ifnet_serialize);
 215 static void     bnx_deserialize(struct ifnet *, enum ifnet_serialize);
 216 static int      bnx_tryserialize(struct ifnet *, enum ifnet_serialize);
 217 #ifdef INVARIANTS
 218 static void     bnx_serialize_assert(struct ifnet *, enum ifnet_serialize,
 219                     boolean_t);
 220 #endif
 221 static void     bnx_serialize_skipmain(struct bnx_softc *);
 222 static void     bnx_deserialize_skipmain(struct bnx_softc *sc);
 223
 224 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
 225 static void     bnx_free_jumbo_mem(struct bnx_softc *);
 226 static struct bnx_jslot
 227                 *bnx_jalloc(struct bnx_softc *);
 228 static void     bnx_jfree(void *);
 229 static void     bnx_jref(void *);
 230 static int      bnx_newbuf_std(struct bnx_rx_ret_ring *, int, int);
 231 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
 232 static void     bnx_setup_rxdesc_std(struct bnx_rx_std_ring *, int);
 233 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
 234 static int      bnx_init_rx_ring_std(struct bnx_rx_std_ring *);
 235 static void     bnx_free_rx_ring_std(struct bnx_rx_std_ring *);
 236 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
 237 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
 238 static void     bnx_free_tx_ring(struct bnx_tx_ring *);
 239 static int      bnx_init_tx_ring(struct bnx_tx_ring *);
 240 static int      bnx_create_tx_ring(struct bnx_tx_ring *);
 241 static void     bnx_destroy_tx_ring(struct bnx_tx_ring *);
 242 static int      bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *);
 243 static void     bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *);
 244 static int      bnx_dma_alloc(device_t);
 245 static void     bnx_dma_free(struct bnx_softc *);
 246 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
 247                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
 248 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 249 static struct mbuf *
 250                 bnx_defrag_shortdma(struct mbuf *);
 251 static int      bnx_encap(struct bnx_tx_ring *, struct mbuf **,
 252                     uint32_t *, int *);
 253 static int      bnx_setup_tso(struct bnx_tx_ring *, struct mbuf **,
 254                     uint16_t *, uint16_t *);
 255 static void     bnx_setup_serialize(struct bnx_softc *);
 256 static void     bnx_set_tick_cpuid(struct bnx_softc *, boolean_t);
 257 static void     bnx_setup_ring_cnt(struct bnx_softc *);
 258
 259 static struct pktinfo *bnx_rss_info(struct pktinfo *,
 260                     const struct bge_rx_bd *);
 261 static void     bnx_init_rss(struct bnx_softc *);
 262 static void     bnx_reset(struct bnx_softc *);
 263 static int      bnx_chipinit(struct bnx_softc *);
 264 static int      bnx_blockinit(struct bnx_softc *);
 265 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
 266 static void     bnx_enable_msi(struct bnx_softc *, boolean_t);
 267 static void     bnx_setmulti(struct bnx_softc *);
 268 static void     bnx_setpromisc(struct bnx_softc *);
 269 static void     bnx_stats_update_regs(struct bnx_softc *);
 270 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
 271
 272 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
 273 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
 274 #ifdef notdef
 275 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
 276 #endif
 277 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
 278 static void     bnx_writembx(struct bnx_softc *, int, int);
 279 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
 280 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
 281 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
 282
 283 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
 284 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
 285 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
 286 static void     bnx_link_poll(struct bnx_softc *);
 287
 288 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
 289 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
 290 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
 291 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
 292
 293 static void     bnx_coal_change(struct bnx_softc *);
 294 static int      bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS);
 295 static int      bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS);
 296 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 297 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 298 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
 299 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
 300 static int      bnx_sysctl_tx_coal_bds_poll(SYSCTL_HANDLER_ARGS);
 301 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 302 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 303 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
 304                     int, int, uint32_t);
 305 #ifdef IFPOLL_ENABLE
 306 static int      bnx_sysctl_npoll_offset(SYSCTL_HANDLER_ARGS);
 307 static int      bnx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
 308 static int      bnx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
 309 #endif
 310 static int      bnx_sysctl_std_refill(SYSCTL_HANDLER_ARGS);
 311
 312 static int      bnx_msi_enable = 1;
 313 static int      bnx_msix_enable = 1;
 314
 315 static int      bnx_rx_rings = 0; /* auto */
 316 static int      bnx_tx_rings = 0; /* auto */
 317
 318 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
 319 TUNABLE_INT("hw.bnx.msix.enable", &bnx_msix_enable);
 320 TUNABLE_INT("hw.bnx.rx_rings", &bnx_rx_rings);
 321 TUNABLE_INT("hw.bnx.tx_rings", &bnx_tx_rings);
 322
 323 static device_method_t bnx_methods[] = {
 324         /* Device interface */
 325         DEVMETHOD(device_probe,         bnx_probe),
 326         DEVMETHOD(device_attach,        bnx_attach),
 327         DEVMETHOD(device_detach,        bnx_detach),
 328         DEVMETHOD(device_shutdown,      bnx_shutdown),
 329         DEVMETHOD(device_suspend,       bnx_suspend),
 330         DEVMETHOD(device_resume,        bnx_resume),
 331
 332         /* bus interface */
 333         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 334         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 335
 336         /* MII interface */
 337         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
 338         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
 339         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
 340
 341         DEVMETHOD_END
 342 };
 343
 344 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
 345 static devclass_t bnx_devclass;
 346
 347 DECLARE_DUMMY_MODULE(if_bnx);
 348 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
 349 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
 350
 351 static uint32_t
 352 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
 353 {
 354         device_t dev = sc->bnx_dev;
 355         uint32_t val;
 356
 357         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 358         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 359         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 360         return (val);
 361 }
 362
 363 static void
 364 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 365 {
 366         device_t dev = sc->bnx_dev;
 367
 368         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 369         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 370         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 371 }
 372
 373 static void
 374 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
 375 {
 376         CSR_WRITE_4(sc, off, val);
 377 }
 378
 379 static void
 380 bnx_writembx(struct bnx_softc *sc, int off, int val)
 381 {
 382         CSR_WRITE_4(sc, off, val);
 383 }
 384
 385 /*
 386  * Read a sequence of bytes from NVRAM.
 387  */
 388 static int
 389 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
 390 {
 391         return (1);
 392 }
 393
 394 /*
 395  * Read a byte of data stored in the EEPROM at address 'addr.' The
 396  * BCM570x supports both the traditional bitbang interface and an
 397  * auto access interface for reading the EEPROM. We use the auto
 398  * access method.
 399  */
 400 static uint8_t
 401 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
 402 {
 403         int i;
 404         uint32_t byte = 0;
 405
 406         /*
 407          * Enable use of auto EEPROM access so we can avoid
 408          * having to use the bitbang method.
 409          */
 410         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 411
 412         /* Reset the EEPROM, load the clock period. */
 413         CSR_WRITE_4(sc, BGE_EE_ADDR,
 414             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 415         DELAY(20);
 416
 417         /* Issue the read EEPROM command. */
 418         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 419
 420         /* Wait for completion */
 421         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
 422                 DELAY(10);
 423                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 424                         break;
 425         }
 426
 427         if (i == BNX_TIMEOUT) {
 428                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 429                 return(1);
 430         }
 431
 432         /* Get result. */
 433         byte = CSR_READ_4(sc, BGE_EE_DATA);
 434
 435         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 436
 437         return(0);
 438 }
 439
 440 /*
 441  * Read a sequence of bytes from the EEPROM.
 442  */
 443 static int
 444 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
 445 {
 446         size_t i;
 447         int err;
 448         uint8_t byte;
 449
 450         for (byte = 0, err = 0, i = 0; i < len; i++) {
 451                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
 452                 if (err)
 453                         break;
 454                 *(dest + i) = byte;
 455         }
 456
 457         return(err ? 1 : 0);
 458 }
 459
 460 static int
 461 bnx_miibus_readreg(device_t dev, int phy, int reg)
 462 {
 463         struct bnx_softc *sc = device_get_softc(dev);
 464         uint32_t val;
 465         int i;
 466
 467         KASSERT(phy == sc->bnx_phyno,
 468             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 469
 470         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 471         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 472                 CSR_WRITE_4(sc, BGE_MI_MODE,
 473                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 474                 DELAY(80);
 475         }
 476
 477         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 478             BGE_MIPHY(phy) | BGE_MIREG(reg));
 479
 480         /* Poll for the PHY register access to complete. */
 481         for (i = 0; i < BNX_TIMEOUT; i++) {
 482                 DELAY(10);
 483                 val = CSR_READ_4(sc, BGE_MI_COMM);
 484                 if ((val & BGE_MICOMM_BUSY) == 0) {
 485                         DELAY(5);
 486                         val = CSR_READ_4(sc, BGE_MI_COMM);
 487                         break;
 488                 }
 489         }
 490         if (i == BNX_TIMEOUT) {
 491                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 492                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 493                 val = 0;
 494         }
 495
 496         /* Restore the autopoll bit if necessary. */
 497         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 498                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 499                 DELAY(80);
 500         }
 501
 502         if (val & BGE_MICOMM_READFAIL)
 503                 return 0;
 504
 505         return (val & 0xFFFF);
 506 }
 507
 508 static int
 509 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
 510 {
 511         struct bnx_softc *sc = device_get_softc(dev);
 512         int i;
 513
 514         KASSERT(phy == sc->bnx_phyno,
 515             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 516
 517         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 518         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 519                 CSR_WRITE_4(sc, BGE_MI_MODE,
 520                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 521                 DELAY(80);
 522         }
 523
 524         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 525             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 526
 527         for (i = 0; i < BNX_TIMEOUT; i++) {
 528                 DELAY(10);
 529                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 530                         DELAY(5);
 531                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 532                         break;
 533                 }
 534         }
 535         if (i == BNX_TIMEOUT) {
 536                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 537                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 538         }
 539
 540         /* Restore the autopoll bit if necessary. */
 541         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 542                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 543                 DELAY(80);
 544         }
 545
 546         return 0;
 547 }
 548
 549 static void
 550 bnx_miibus_statchg(device_t dev)
 551 {
 552         struct bnx_softc *sc;
 553         struct mii_data *mii;
 554
 555         sc = device_get_softc(dev);
 556         mii = device_get_softc(sc->bnx_miibus);
 557
 558         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 559             (IFM_ACTIVE | IFM_AVALID)) {
 560                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 561                 case IFM_10_T:
 562                 case IFM_100_TX:
 563                         sc->bnx_link = 1;
 564                         break;
 565                 case IFM_1000_T:
 566                 case IFM_1000_SX:
 567                 case IFM_2500_SX:
 568                         sc->bnx_link = 1;
 569                         break;
 570                 default:
 571                         sc->bnx_link = 0;
 572                         break;
 573                 }
 574         } else {
 575                 sc->bnx_link = 0;
 576         }
 577         if (sc->bnx_link == 0)
 578                 return;
 579
 580         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 581         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 582             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 583                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 584         } else {
 585                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 586         }
 587
 588         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 589                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 590         } else {
 591                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 592         }
 593 }
 594
 595 /*
 596  * Memory management for jumbo frames.
 597  */
 598 static int
 599 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
 600 {
 601         struct ifnet *ifp = &sc->arpcom.ac_if;
 602         struct bnx_jslot *entry;
 603         uint8_t *ptr;
 604         bus_addr_t paddr;
 605         int i, error;
 606
 607         /*
 608          * Create tag for jumbo mbufs.
 609          * This is really a bit of a kludge. We allocate a special
 610          * jumbo buffer pool which (thanks to the way our DMA
 611          * memory allocation works) will consist of contiguous
 612          * pages. This means that even though a jumbo buffer might
 613          * be larger than a page size, we don't really need to
 614          * map it into more than one DMA segment. However, the
 615          * default mbuf tag will result in multi-segment mappings,
 616          * so we have to create a special jumbo mbuf tag that
 617          * lets us get away with mapping the jumbo buffers as
 618          * a single segment. I think eventually the driver should
 619          * be changed so that it uses ordinary mbufs and cluster
 620          * buffers, i.e. jumbo frames can span multiple DMA
 621          * descriptors. But that's a project for another day.
 622          */
 623
 624         /*
 625          * Create DMA stuffs for jumbo RX ring.
 626          */
 627         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 628                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 629                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 630                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
 631                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
 632         if (error) {
 633                 if_printf(ifp, "could not create jumbo RX ring\n");
 634                 return error;
 635         }
 636
 637         /*
 638          * Create DMA stuffs for jumbo buffer block.
 639          */
 640         error = bnx_dma_block_alloc(sc, BNX_JMEM,
 641                                     &sc->bnx_cdata.bnx_jumbo_tag,
 642                                     &sc->bnx_cdata.bnx_jumbo_map,
 643                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
 644                                     &paddr);
 645         if (error) {
 646                 if_printf(ifp, "could not create jumbo buffer\n");
 647                 return error;
 648         }
 649
 650         SLIST_INIT(&sc->bnx_jfree_listhead);
 651
 652         /*
 653          * Now divide it up into 9K pieces and save the addresses
 654          * in an array. Note that we play an evil trick here by using
 655          * the first few bytes in the buffer to hold the the address
 656          * of the softc structure for this interface. This is because
 657          * bnx_jfree() needs it, but it is called by the mbuf management
 658          * code which will not pass it to us explicitly.
 659          */
 660         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
 661                 entry = &sc->bnx_cdata.bnx_jslots[i];
 662                 entry->bnx_sc = sc;
 663                 entry->bnx_buf = ptr;
 664                 entry->bnx_paddr = paddr;
 665                 entry->bnx_inuse = 0;
 666                 entry->bnx_slot = i;
 667                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
 668
 669                 ptr += BNX_JLEN;
 670                 paddr += BNX_JLEN;
 671         }
 672         return 0;
 673 }
 674
 675 static void
 676 bnx_free_jumbo_mem(struct bnx_softc *sc)
 677 {
 678         /* Destroy jumbo RX ring. */
 679         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 680                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 681                            sc->bnx_ldata.bnx_rx_jumbo_ring);
 682
 683         /* Destroy jumbo buffer block. */
 684         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
 685                            sc->bnx_cdata.bnx_jumbo_map,
 686                            sc->bnx_ldata.bnx_jumbo_buf);
 687 }
 688
 689 /*
 690  * Allocate a jumbo buffer.
 691  */
 692 static struct bnx_jslot *
 693 bnx_jalloc(struct bnx_softc *sc)
 694 {
 695         struct bnx_jslot *entry;
 696
 697         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 698         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
 699         if (entry) {
 700                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
 701                 entry->bnx_inuse = 1;
 702         } else {
 703                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 704         }
 705         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 706         return(entry);
 707 }
 708
 709 /*
 710  * Adjust usage count on a jumbo buffer.
 711  */
 712 static void
 713 bnx_jref(void *arg)
 714 {
 715         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 716         struct bnx_softc *sc = entry->bnx_sc;
 717
 718         if (sc == NULL)
 719                 panic("bnx_jref: can't find softc pointer!");
 720
 721         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 722                 panic("bnx_jref: asked to reference buffer "
 723                     "that we don't manage!");
 724         } else if (entry->bnx_inuse == 0) {
 725                 panic("bnx_jref: buffer already free!");
 726         } else {
 727                 atomic_add_int(&entry->bnx_inuse, 1);
 728         }
 729 }
 730
 731 /*
 732  * Release a jumbo buffer.
 733  */
 734 static void
 735 bnx_jfree(void *arg)
 736 {
 737         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 738         struct bnx_softc *sc = entry->bnx_sc;
 739
 740         if (sc == NULL)
 741                 panic("bnx_jfree: can't find softc pointer!");
 742
 743         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 744                 panic("bnx_jfree: asked to free buffer that we don't manage!");
 745         } else if (entry->bnx_inuse == 0) {
 746                 panic("bnx_jfree: buffer already free!");
 747         } else {
 748                 /*
 749                  * Possible MP race to 0, use the serializer.  The atomic insn
 750                  * is still needed for races against bnx_jref().
 751                  */
 752                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 753                 atomic_subtract_int(&entry->bnx_inuse, 1);
 754                 if (entry->bnx_inuse == 0) {
 755                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead,
 756                                           entry, jslot_link);
 757                 }
 758                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 759         }
 760 }
 761
 762
 763 /*
 764  * Intialize a standard receive ring descriptor.
 765  */
 766 static int
 767 bnx_newbuf_std(struct bnx_rx_ret_ring *ret, int i, int init)
 768 {
 769         struct mbuf *m_new = NULL;
 770         bus_dma_segment_t seg;
 771         bus_dmamap_t map;
 772         int error, nsegs;
 773         struct bnx_rx_buf *rb;
 774
 775         rb = &ret->bnx_std->bnx_rx_std_buf[i];
 776         KASSERT(!rb->bnx_rx_refilled, ("RX buf %dth has been refilled", i));
 777
 778         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 779         if (m_new == NULL) {
 780                 error = ENOBUFS;
 781                 goto back;
 782         }
 783         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 784         m_adj(m_new, ETHER_ALIGN);
 785
 786         error = bus_dmamap_load_mbuf_segment(ret->bnx_rx_mtag,
 787             ret->bnx_rx_tmpmap, m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 788         if (error) {
 789                 m_freem(m_new);
 790                 goto back;
 791         }
 792
 793         if (!init) {
 794                 bus_dmamap_sync(ret->bnx_rx_mtag, rb->bnx_rx_dmamap,
 795                     BUS_DMASYNC_POSTREAD);
 796                 bus_dmamap_unload(ret->bnx_rx_mtag, rb->bnx_rx_dmamap);
 797         }
 798
 799         map = ret->bnx_rx_tmpmap;
 800         ret->bnx_rx_tmpmap = rb->bnx_rx_dmamap;
 801
 802         rb->bnx_rx_dmamap = map;
 803         rb->bnx_rx_mbuf = m_new;
 804         rb->bnx_rx_paddr = seg.ds_addr;
 805         rb->bnx_rx_len = m_new->m_len;
 806 back:
 807         cpu_sfence();
 808         rb->bnx_rx_refilled = 1;
 809         return error;
 810 }
 811
 812 static void
 813 bnx_setup_rxdesc_std(struct bnx_rx_std_ring *std, int i)
 814 {
 815         struct bnx_rx_buf *rb;
 816         struct bge_rx_bd *r;
 817         bus_addr_t paddr;
 818         int len;
 819
 820         rb = &std->bnx_rx_std_buf[i];
 821         KASSERT(rb->bnx_rx_refilled, ("RX buf %dth is not refilled", i));
 822
 823         paddr = rb->bnx_rx_paddr;
 824         len = rb->bnx_rx_len;
 825
 826         cpu_mfence();
 827
 828         rb->bnx_rx_refilled = 0;
 829
 830         r = &std->bnx_rx_std_ring[i];
 831         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
 832         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
 833         r->bge_len = len;
 834         r->bge_idx = i;
 835         r->bge_flags = BGE_RXBDFLAG_END;
 836 }
 837
 838 /*
 839  * Initialize a jumbo receive ring descriptor. This allocates
 840  * a jumbo buffer from the pool managed internally by the driver.
 841  */
 842 static int
 843 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
 844 {
 845         struct mbuf *m_new = NULL;
 846         struct bnx_jslot *buf;
 847         bus_addr_t paddr;
 848
 849         /* Allocate the mbuf. */
 850         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 851         if (m_new == NULL)
 852                 return ENOBUFS;
 853
 854         /* Allocate the jumbo buffer */
 855         buf = bnx_jalloc(sc);
 856         if (buf == NULL) {
 857                 m_freem(m_new);
 858                 return ENOBUFS;
 859         }
 860
 861         /* Attach the buffer to the mbuf. */
 862         m_new->m_ext.ext_arg = buf;
 863         m_new->m_ext.ext_buf = buf->bnx_buf;
 864         m_new->m_ext.ext_free = bnx_jfree;
 865         m_new->m_ext.ext_ref = bnx_jref;
 866         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
 867
 868         m_new->m_flags |= M_EXT;
 869
 870         m_new->m_data = m_new->m_ext.ext_buf;
 871         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 872
 873         paddr = buf->bnx_paddr;
 874         m_adj(m_new, ETHER_ALIGN);
 875         paddr += ETHER_ALIGN;
 876
 877         /* Save necessary information */
 878         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_mbuf = m_new;
 879         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_paddr = paddr;
 880
 881         /* Set up the descriptor. */
 882         bnx_setup_rxdesc_jumbo(sc, i);
 883         return 0;
 884 }
 885
 886 static void
 887 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
 888 {
 889         struct bge_rx_bd *r;
 890         struct bnx_rx_buf *rc;
 891
 892         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
 893         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 894
 895         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_rx_paddr);
 896         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_rx_paddr);
 897         r->bge_len = rc->bnx_rx_mbuf->m_len;
 898         r->bge_idx = i;
 899         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 900 }
 901
 902 static int
 903 bnx_init_rx_ring_std(struct bnx_rx_std_ring *std)
 904 {
 905         int i, error;
 906
 907         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 908                 /* Use the first RX return ring's tmp RX mbuf DMA map */
 909                 error = bnx_newbuf_std(&std->bnx_sc->bnx_rx_ret_ring[0], i, 1);
 910                 if (error)
 911                         return error;
 912                 bnx_setup_rxdesc_std(std, i);
 913         }
 914
 915         std->bnx_rx_std_used = 0;
 916         std->bnx_rx_std_refill = 0;
 917         std->bnx_rx_std_running = 0;
 918         cpu_sfence();
 919         lwkt_serialize_handler_enable(&std->bnx_rx_std_serialize);
 920
 921         std->bnx_rx_std = BGE_STD_RX_RING_CNT - 1;
 922         bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO, std->bnx_rx_std);
 923
 924         return(0);
 925 }
 926
 927 static void
 928 bnx_free_rx_ring_std(struct bnx_rx_std_ring *std)
 929 {
 930         int i;
 931
 932         lwkt_serialize_handler_disable(&std->bnx_rx_std_serialize);
 933
 934         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 935                 struct bnx_rx_buf *rb = &std->bnx_rx_std_buf[i];
 936
 937                 rb->bnx_rx_refilled = 0;
 938                 if (rb->bnx_rx_mbuf != NULL) {
 939                         bus_dmamap_unload(std->bnx_rx_mtag, rb->bnx_rx_dmamap);
 940                         m_freem(rb->bnx_rx_mbuf);
 941                         rb->bnx_rx_mbuf = NULL;
 942                 }
 943                 bzero(&std->bnx_rx_std_ring[i], sizeof(struct bge_rx_bd));
 944         }
 945 }
 946
 947 static int
 948 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
 949 {
 950         struct bge_rcb *rcb;
 951         int i, error;
 952
 953         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 954                 error = bnx_newbuf_jumbo(sc, i, 1);
 955                 if (error)
 956                         return error;
 957         }
 958
 959         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
 960
 961         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
 962         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 963         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 964
 965         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
 966
 967         return(0);
 968 }
 969
 970 static void
 971 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
 972 {
 973         int i;
 974
 975         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 976                 struct bnx_rx_buf *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 977
 978                 if (rc->bnx_rx_mbuf != NULL) {
 979                         m_freem(rc->bnx_rx_mbuf);
 980                         rc->bnx_rx_mbuf = NULL;
 981                 }
 982                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
 983                     sizeof(struct bge_rx_bd));
 984         }
 985 }
 986
 987 static void
 988 bnx_free_tx_ring(struct bnx_tx_ring *txr)
 989 {
 990         int i;
 991
 992         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 993                 struct bnx_tx_buf *buf = &txr->bnx_tx_buf[i];
 994
 995                 if (buf->bnx_tx_mbuf != NULL) {
 996                         bus_dmamap_unload(txr->bnx_tx_mtag,
 997                             buf->bnx_tx_dmamap);
 998                         m_freem(buf->bnx_tx_mbuf);
 999                         buf->bnx_tx_mbuf = NULL;
1000                 }
1001                 bzero(&txr->bnx_tx_ring[i], sizeof(struct bge_tx_bd));
1002         }
1003         txr->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
1004 }
1005
1006 static int
1007 bnx_init_tx_ring(struct bnx_tx_ring *txr)
1008 {
1009         txr->bnx_tx_cnt = 0;
1010         txr->bnx_tx_saved_considx = 0;
1011         txr->bnx_tx_prodidx = 0;
1012
1013         /* Initialize transmit producer index for host-memory send ring. */
1014         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, txr->bnx_tx_prodidx);
1015
1016         return(0);
1017 }
1018
1019 static void
1020 bnx_setmulti(struct bnx_softc *sc)
1021 {
1022         struct ifnet *ifp;
1023         struct ifmultiaddr *ifma;
1024         uint32_t hashes[4] = { 0, 0, 0, 0 };
1025         int h, i;
1026
1027         ifp = &sc->arpcom.ac_if;
1028
1029         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1030                 for (i = 0; i < 4; i++)
1031                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1032                 return;
1033         }
1034
1035         /* First, zot all the existing filters. */
1036         for (i = 0; i < 4; i++)
1037                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1038
1039         /* Now program new ones. */
1040         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1041                 if (ifma->ifma_addr->sa_family != AF_LINK)
1042                         continue;
1043                 h = ether_crc32_le(
1044                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1045                     ETHER_ADDR_LEN) & 0x7f;
1046                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1047         }
1048
1049         for (i = 0; i < 4; i++)
1050                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1051 }
1052
1053 /*
1054  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1055  * self-test results.
1056  */
1057 static int
1058 bnx_chipinit(struct bnx_softc *sc)
1059 {
1060         uint32_t dma_rw_ctl, mode_ctl;
1061         int i;
1062
1063         /* Set endian type before we access any non-PCI registers. */
1064         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
1065             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
1066
1067         /* Clear the MAC control register */
1068         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1069
1070         /*
1071          * Clear the MAC statistics block in the NIC's
1072          * internal memory.
1073          */
1074         for (i = BGE_STATS_BLOCK;
1075             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1076                 BNX_MEMWIN_WRITE(sc, i, 0);
1077
1078         for (i = BGE_STATUS_BLOCK;
1079             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1080                 BNX_MEMWIN_WRITE(sc, i, 0);
1081
1082         if (BNX_IS_57765_FAMILY(sc)) {
1083                 uint32_t val;
1084
1085                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
1086                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1087                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1088
1089                         /* Access the lower 1K of PL PCI-E block registers. */
1090                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1091                             val | BGE_MODECTL_PCIE_PL_SEL);
1092
1093                         val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
1094                         val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
1095                         CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
1096
1097                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1098                 }
1099                 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1100                         /* Fix transmit hangs */
1101                         val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
1102                         val |= BGE_CPMU_PADRNG_CTL_RDIV2;
1103                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val);
1104
1105                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1106                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1107
1108                         /* Access the lower 1K of DL PCI-E block registers. */
1109                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1110                             val | BGE_MODECTL_PCIE_DL_SEL);
1111
1112                         val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1113                         val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1114                         val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1115                         CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1116
1117                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1118                 }
1119
1120                 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1121                 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1122                 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1123                 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1124         }
1125
1126         /*
1127          * Set up the PCI DMA control register.
1128          */
1129         dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1130         /*
1131          * Disable 32bytes cache alignment for DMA write to host memory
1132          *
1133          * NOTE:
1134          * 64bytes cache alignment for DMA write to host memory is still
1135          * enabled.
1136          */
1137         dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1138         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1139                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1140         /*
1141          * Enable HW workaround for controllers that misinterpret
1142          * a status tag update and leave interrupts permanently
1143          * disabled.
1144          */
1145         if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1146             sc->bnx_asicrev != BGE_ASICREV_BCM5762 &&
1147             !BNX_IS_57765_FAMILY(sc))
1148                 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1149         if (bootverbose) {
1150                 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1151                     dma_rw_ctl);
1152         }
1153         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1154
1155         /*
1156          * Set up general mode register.
1157          */
1158         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1159             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1160         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1161
1162         /*
1163          * Disable memory write invalidate.  Apparently it is not supported
1164          * properly by these devices.  Also ensure that INTx isn't disabled,
1165          * as these chips need it even when using MSI.
1166          */
1167         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1168             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1169
1170         /* Set the timer prescaler (always 66Mhz) */
1171         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1172
1173         return(0);
1174 }
1175
1176 static int
1177 bnx_blockinit(struct bnx_softc *sc)
1178 {
1179         struct bnx_intr_data *intr;
1180         struct bge_rcb *rcb;
1181         bus_size_t vrcb;
1182         bge_hostaddr taddr;
1183         uint32_t val;
1184         int i, limit;
1185
1186         /*
1187          * Initialize the memory window pointer register so that
1188          * we can access the first 32K of internal NIC RAM. This will
1189          * allow us to set up the TX send ring RCBs and the RX return
1190          * ring RCBs, plus other things which live in NIC memory.
1191          */
1192         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1193
1194         /* Configure mbuf pool watermarks */
1195         if (BNX_IS_57765_PLUS(sc)) {
1196                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1197                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1198                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1199                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1200                 } else {
1201                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1202                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1203                 }
1204         } else {
1205                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1206                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1207                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1208         }
1209
1210         /* Configure DMA resource watermarks */
1211         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1212         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1213
1214         /* Enable buffer manager */
1215         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1216         /*
1217          * Change the arbitration algorithm of TXMBUF read request to
1218          * round-robin instead of priority based for BCM5719.  When
1219          * TXFIFO is almost empty, RDMA will hold its request until
1220          * TXFIFO is not almost empty.
1221          */
1222         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1223                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1224         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1225             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1226             sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1227                 val |= BGE_BMANMODE_LOMBUF_ATTN;
1228         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1229
1230         /* Poll for buffer manager start indication */
1231         for (i = 0; i < BNX_TIMEOUT; i++) {
1232                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1233                         break;
1234                 DELAY(10);
1235         }
1236
1237         if (i == BNX_TIMEOUT) {
1238                 if_printf(&sc->arpcom.ac_if,
1239                           "buffer manager failed to start\n");
1240                 return(ENXIO);
1241         }
1242
1243         /* Enable flow-through queues */
1244         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1245         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1246
1247         /* Wait until queue initialization is complete */
1248         for (i = 0; i < BNX_TIMEOUT; i++) {
1249                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1250                         break;
1251                 DELAY(10);
1252         }
1253
1254         if (i == BNX_TIMEOUT) {
1255                 if_printf(&sc->arpcom.ac_if,
1256                           "flow-through queue init failed\n");
1257                 return(ENXIO);
1258         }
1259
1260         /*
1261          * Summary of rings supported by the controller:
1262          *
1263          * Standard Receive Producer Ring
1264          * - This ring is used to feed receive buffers for "standard"
1265          *   sized frames (typically 1536 bytes) to the controller.
1266          *
1267          * Jumbo Receive Producer Ring
1268          * - This ring is used to feed receive buffers for jumbo sized
1269          *   frames (i.e. anything bigger than the "standard" frames)
1270          *   to the controller.
1271          *
1272          * Mini Receive Producer Ring
1273          * - This ring is used to feed receive buffers for "mini"
1274          *   sized frames to the controller.
1275          * - This feature required external memory for the controller
1276          *   but was never used in a production system.  Should always
1277          *   be disabled.
1278          *
1279          * Receive Return Ring
1280          * - After the controller has placed an incoming frame into a
1281          *   receive buffer that buffer is moved into a receive return
1282          *   ring.  The driver is then responsible to passing the
1283          *   buffer up to the stack.  BCM5718/BCM57785 families support
1284          *   multiple receive return rings.
1285          *
1286          * Send Ring
1287          * - This ring is used for outgoing frames.  BCM5719/BCM5720
1288          *   support multiple send rings.
1289          */
1290
1291         /* Initialize the standard receive producer ring control block. */
1292         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1293         rcb->bge_hostaddr.bge_addr_lo =
1294             BGE_ADDR_LO(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1295         rcb->bge_hostaddr.bge_addr_hi =
1296             BGE_ADDR_HI(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1297         if (BNX_IS_57765_PLUS(sc)) {
1298                 /*
1299                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1300                  * Bits 15-2 : Maximum RX frame size
1301                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1302                  * Bit 0     : Reserved
1303                  */
1304                 rcb->bge_maxlen_flags =
1305                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1306         } else {
1307                 /*
1308                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1309                  * Bits 15-2 : Reserved (should be 0)
1310                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1311                  * Bit 0     : Reserved
1312                  */
1313                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1314         }
1315         if (BNX_IS_5717_PLUS(sc))
1316                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1317         else
1318                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1319         /* Write the standard receive producer ring control block. */
1320         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1321         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1322         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1323         if (!BNX_IS_5717_PLUS(sc))
1324                 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1325         /* Reset the standard receive producer ring producer index. */
1326         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1327
1328         /*
1329          * Initialize the jumbo RX producer ring control
1330          * block.  We set the 'ring disabled' bit in the
1331          * flags field until we're actually ready to start
1332          * using this ring (i.e. once we set the MTU
1333          * high enough to require it).
1334          */
1335         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1336                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1337                 /* Get the jumbo receive producer ring RCB parameters. */
1338                 rcb->bge_hostaddr.bge_addr_lo =
1339                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1340                 rcb->bge_hostaddr.bge_addr_hi =
1341                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1342                 rcb->bge_maxlen_flags =
1343                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1344                     BGE_RCB_FLAG_RING_DISABLED);
1345                 if (BNX_IS_5717_PLUS(sc))
1346                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1347                 else
1348                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1349                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1350                     rcb->bge_hostaddr.bge_addr_hi);
1351                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1352                     rcb->bge_hostaddr.bge_addr_lo);
1353                 /* Program the jumbo receive producer ring RCB parameters. */
1354                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1355                     rcb->bge_maxlen_flags);
1356                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1357                 /* Reset the jumbo receive producer ring producer index. */
1358                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1359         }
1360
1361         /*
1362          * The BD ring replenish thresholds control how often the
1363          * hardware fetches new BD's from the producer rings in host
1364          * memory.  Setting the value too low on a busy system can
1365          * starve the hardware and recue the throughpout.
1366          *
1367          * Set the BD ring replentish thresholds. The recommended
1368          * values are 1/8th the number of descriptors allocated to
1369          * each ring.
1370          */
1371         val = 8;
1372         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1373         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1374                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1375                     BGE_JUMBO_RX_RING_CNT/8);
1376         }
1377         if (BNX_IS_57765_PLUS(sc)) {
1378                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1379                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1380         }
1381
1382         /*
1383          * Disable all send rings by setting the 'ring disabled' bit
1384          * in the flags field of all the TX send ring control blocks,
1385          * located in NIC memory.
1386          */
1387         if (BNX_IS_5717_PLUS(sc))
1388                 limit = 4;
1389         else if (BNX_IS_57765_FAMILY(sc) ||
1390             sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1391                 limit = 2;
1392         else
1393                 limit = 1;
1394         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1395         for (i = 0; i < limit; i++) {
1396                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1397                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1398                 vrcb += sizeof(struct bge_rcb);
1399         }
1400
1401         /*
1402          * Configure send ring RCBs
1403          */
1404         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1405         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
1406                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
1407
1408                 BGE_HOSTADDR(taddr, txr->bnx_tx_ring_paddr);
1409                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi,
1410                     taddr.bge_addr_hi);
1411                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo,
1412                     taddr.bge_addr_lo);
1413                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1414                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1415                 vrcb += sizeof(struct bge_rcb);
1416         }
1417
1418         /*
1419          * Disable all receive return rings by setting the
1420          * 'ring disabled' bit in the flags field of all the receive
1421          * return ring control blocks, located in NIC memory.
1422          */
1423         if (BNX_IS_5717_PLUS(sc)) {
1424                 /* Should be 17, use 16 until we get an SRAM map. */
1425                 limit = 16;
1426         } else if (BNX_IS_57765_FAMILY(sc) ||
1427             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1428                 limit = 4;
1429         } else {
1430                 limit = 1;
1431         }
1432         /* Disable all receive return rings. */
1433         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1434         for (i = 0; i < limit; i++) {
1435                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1436                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1437                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1438                     BGE_RCB_FLAG_RING_DISABLED);
1439                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1440                     (i * (sizeof(uint64_t))), 0);
1441                 vrcb += sizeof(struct bge_rcb);
1442         }
1443
1444         /*
1445          * Set up receive return rings.
1446          */
1447         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1448         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
1449                 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
1450
1451                 BGE_HOSTADDR(taddr, ret->bnx_rx_ret_ring_paddr);
1452                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi,
1453                     taddr.bge_addr_hi);
1454                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo,
1455                     taddr.bge_addr_lo);
1456                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1457                     BGE_RCB_MAXLEN_FLAGS(BNX_RETURN_RING_CNT, 0));
1458                 vrcb += sizeof(struct bge_rcb);
1459         }
1460
1461         /* Set random backoff seed for TX */
1462         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1463             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1464             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1465             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1466             BGE_TX_BACKOFF_SEED_MASK);
1467
1468         /* Set inter-packet gap */
1469         val = 0x2620;
1470         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1471             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1472                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1473                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1474         }
1475         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1476
1477         /*
1478          * Specify which ring to use for packets that don't match
1479          * any RX rules.
1480          */
1481         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1482
1483         /*
1484          * Configure number of RX lists. One interrupt distribution
1485          * list, sixteen active lists, one bad frames class.
1486          */
1487         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1488
1489         /* Inialize RX list placement stats mask. */
1490         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1491         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1492
1493         /* Disable host coalescing until we get it set up */
1494         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1495
1496         /* Poll to make sure it's shut down. */
1497         for (i = 0; i < BNX_TIMEOUT; i++) {
1498                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1499                         break;
1500                 DELAY(10);
1501         }
1502
1503         if (i == BNX_TIMEOUT) {
1504                 if_printf(&sc->arpcom.ac_if,
1505                           "host coalescing engine failed to idle\n");
1506                 return(ENXIO);
1507         }
1508
1509         /* Set up host coalescing defaults */
1510         sc->bnx_coal_chg = BNX_RX_COAL_TICKS_CHG |
1511             BNX_TX_COAL_TICKS_CHG |
1512             BNX_RX_COAL_BDS_CHG |
1513             BNX_TX_COAL_BDS_CHG |
1514             BNX_RX_COAL_BDS_INT_CHG |
1515             BNX_TX_COAL_BDS_INT_CHG;
1516         bnx_coal_change(sc);
1517
1518         /*
1519          * Set up addresses of status blocks
1520          */
1521         intr = &sc->bnx_intr_data[0];
1522         bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ);
1523         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1524             BGE_ADDR_HI(intr->bnx_status_block_paddr));
1525         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1526             BGE_ADDR_LO(intr->bnx_status_block_paddr));
1527         for (i = 1; i < sc->bnx_intr_cnt; ++i) {
1528                 intr = &sc->bnx_intr_data[i];
1529                 bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ);
1530                 CSR_WRITE_4(sc, BGE_VEC1_STATUSBLK_ADDR_HI + ((i - 1) * 8),
1531                     BGE_ADDR_HI(intr->bnx_status_block_paddr));
1532                 CSR_WRITE_4(sc, BGE_VEC1_STATUSBLK_ADDR_LO + ((i - 1) * 8),
1533                     BGE_ADDR_LO(intr->bnx_status_block_paddr));
1534         }
1535
1536         /* Set up status block partail update size. */
1537         val = BGE_STATBLKSZ_32BYTE;
1538 #if 0
1539         /*
1540          * Does not seem to have visible effect in both
1541          * bulk data (1472B UDP datagram) and tiny data
1542          * (18B UDP datagram) TX tests.
1543          */
1544         val |= BGE_HCCMODE_CLRTICK_TX;
1545 #endif
1546         /* Turn on host coalescing state machine */
1547         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1548
1549         /* Turn on RX BD completion state machine and enable attentions */
1550         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1551             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1552
1553         /* Turn on RX list placement state machine */
1554         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1555
1556         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1557             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1558             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1559             BGE_MACMODE_FRMHDR_DMA_ENB;
1560
1561         if (sc->bnx_flags & BNX_FLAG_TBI)
1562                 val |= BGE_PORTMODE_TBI;
1563         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1564                 val |= BGE_PORTMODE_GMII;
1565         else
1566                 val |= BGE_PORTMODE_MII;
1567
1568         /* Turn on DMA, clear stats */
1569         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1570
1571         /* Set misc. local control, enable interrupts on attentions */
1572         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1573
1574 #ifdef notdef
1575         /* Assert GPIO pins for PHY reset */
1576         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1577             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1578         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1579             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1580 #endif
1581
1582         if (sc->bnx_intr_type == PCI_INTR_TYPE_MSIX)
1583                 bnx_enable_msi(sc, TRUE);
1584
1585         /* Turn on write DMA state machine */
1586         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1587         /* Enable host coalescing bug fix. */
1588         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1589         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1590                 /* Request larger DMA burst size to get better performance. */
1591                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1592         }
1593         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1594         DELAY(40);
1595
1596         if (BNX_IS_57765_PLUS(sc)) {
1597                 uint32_t dmactl, dmactl_reg;
1598
1599                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1600                         dmactl_reg = BGE_RDMA_RSRVCTRL2;
1601                 else
1602                         dmactl_reg = BGE_RDMA_RSRVCTRL;
1603
1604                 dmactl = CSR_READ_4(sc, dmactl_reg);
1605                 /*
1606                  * Adjust tx margin to prevent TX data corruption and
1607                  * fix internal FIFO overflow.
1608                  */
1609                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1610                     sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1611                     sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1612                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1613                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1614                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1615                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1616                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1617                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1618                 }
1619                 /*
1620                  * Enable fix for read DMA FIFO overruns.
1621                  * The fix is to limit the number of RX BDs
1622                  * the hardware would fetch at a fime.
1623                  */
1624                 CSR_WRITE_4(sc, dmactl_reg,
1625                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1626         }
1627
1628         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1629                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1630                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1631                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1632                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1633         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1634             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1635                 uint32_t ctrl_reg;
1636
1637                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1638                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2;
1639                 else
1640                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL;
1641
1642                 /*
1643                  * Allow 4KB burst length reads for non-LSO frames.
1644                  * Enable 512B burst length reads for buffer descriptors.
1645                  */
1646                 CSR_WRITE_4(sc, ctrl_reg,
1647                     CSR_READ_4(sc, ctrl_reg) |
1648                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1649                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1650         }
1651
1652         /* Turn on read DMA state machine */
1653         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1654         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1655                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1656         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1657             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1658             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1659                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1660                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1661                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1662         }
1663         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1664             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1665                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1666                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1667                 /*
1668                  * Allow multiple outstanding read requests from
1669                  * non-LSO read DMA engine.
1670                  */
1671                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1672         }
1673         if (sc->bnx_asicrev == BGE_ASICREV_BCM57766)
1674                 val |= BGE_RDMAMODE_JMB_2K_MMRR;
1675         if (sc->bnx_flags & BNX_FLAG_TSO)
1676                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1677         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1678         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1679         DELAY(40);
1680
1681         /* Turn on RX data completion state machine */
1682         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1683
1684         /* Turn on RX BD initiator state machine */
1685         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1686
1687         /* Turn on RX data and RX BD initiator state machine */
1688         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1689
1690         /* Turn on send BD completion state machine */
1691         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1692
1693         /* Turn on send data completion state machine */
1694         val = BGE_SDCMODE_ENABLE;
1695         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1696                 val |= BGE_SDCMODE_CDELAY;
1697         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1698
1699         /* Turn on send data initiator state machine */
1700         if (sc->bnx_flags & BNX_FLAG_TSO) {
1701                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1702                     BGE_SDIMODE_HW_LSO_PRE_DMA);
1703         } else {
1704                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1705         }
1706
1707         /* Turn on send BD initiator state machine */
1708         val = BGE_SBDIMODE_ENABLE;
1709         if (sc->bnx_tx_ringcnt > 1)
1710                 val |= BGE_SBDIMODE_MULTI_TXR;
1711         CSR_WRITE_4(sc, BGE_SBDI_MODE, val);
1712
1713         /* Turn on send BD selector state machine */
1714         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1715
1716         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1717         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1718             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1719
1720         /* ack/clear link change events */
1721         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1722             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1723             BGE_MACSTAT_LINK_CHANGED);
1724         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1725
1726         /*
1727          * Enable attention when the link has changed state for
1728          * devices that use auto polling.
1729          */
1730         if (sc->bnx_flags & BNX_FLAG_TBI) {
1731                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1732         } else {
1733                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1734                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1735                         DELAY(80);
1736                 }
1737         }
1738
1739         /*
1740          * Clear any pending link state attention.
1741          * Otherwise some link state change events may be lost until attention
1742          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1743          * It's not necessary on newer BCM chips - perhaps enabling link
1744          * state change attentions implies clearing pending attention.
1745          */
1746         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1747             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1748             BGE_MACSTAT_LINK_CHANGED);
1749
1750         /* Enable link state change attentions. */
1751         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1752
1753         return(0);
1754 }
1755
1756 /*
1757  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1758  * against our list and return its name if we find a match. Note
1759  * that since the Broadcom controller contains VPD support, we
1760  * can get the device name string from the controller itself instead
1761  * of the compiled-in string. This is a little slow, but it guarantees
1762  * we'll always announce the right product name.
1763  */
1764 static int
1765 bnx_probe(device_t dev)
1766 {
1767         const struct bnx_type *t;
1768         uint16_t product, vendor;
1769
1770         if (!pci_is_pcie(dev))
1771                 return ENXIO;
1772
1773         product = pci_get_device(dev);
1774         vendor = pci_get_vendor(dev);
1775
1776         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1777                 if (vendor == t->bnx_vid && product == t->bnx_did)
1778                         break;
1779         }
1780         if (t->bnx_name == NULL)
1781                 return ENXIO;
1782
1783         device_set_desc(dev, t->bnx_name);
1784         return 0;
1785 }
1786
1787 static int
1788 bnx_attach(device_t dev)
1789 {
1790         struct ifnet *ifp;
1791         struct bnx_softc *sc;
1792         struct bnx_rx_std_ring *std;
1793         uint32_t hwcfg = 0;
1794         int error = 0, rid, capmask, i, std_cpuid, std_cpuid_def;
1795         uint8_t ether_addr[ETHER_ADDR_LEN];
1796         uint16_t product;
1797         uintptr_t mii_priv = 0;
1798 #if defined(BNX_TSO_DEBUG) || defined(BNX_RSS_DEBUG) || defined(BNX_TSS_DEBUG)
1799         char desc[32];
1800 #endif
1801 #ifdef IFPOLL_ENABLE
1802         int offset, offset_def;
1803 #endif
1804
1805         sc = device_get_softc(dev);
1806         sc->bnx_dev = dev;
1807         callout_init_mp(&sc->bnx_tick_timer);
1808         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1809         lwkt_serialize_init(&sc->bnx_main_serialize);
1810
1811         /* Always setup interrupt mailboxes */
1812         for (i = 0; i < BNX_INTR_MAX; ++i) {
1813                 callout_init_mp(&sc->bnx_intr_data[i].bnx_intr_timer);
1814                 sc->bnx_intr_data[i].bnx_sc = sc;
1815                 sc->bnx_intr_data[i].bnx_intr_mbx = BGE_MBX_IRQ0_LO + (i * 8);
1816                 sc->bnx_intr_data[i].bnx_intr_rid = -1;
1817                 sc->bnx_intr_data[i].bnx_intr_cpuid = -1;
1818         }
1819
1820         product = pci_get_device(dev);
1821
1822 #ifndef BURN_BRIDGES
1823         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1824                 uint32_t irq, mem;
1825
1826                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1827                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1828
1829                 device_printf(dev, "chip is in D%d power mode "
1830                     "-- setting to D0\n", pci_get_powerstate(dev));
1831
1832                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1833
1834                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1835                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1836         }
1837 #endif  /* !BURN_BRIDGE */
1838
1839         /*
1840          * Map control/status registers.
1841          */
1842         pci_enable_busmaster(dev);
1843
1844         rid = BGE_PCI_BAR0;
1845         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1846             RF_ACTIVE);
1847
1848         if (sc->bnx_res == NULL) {
1849                 device_printf(dev, "couldn't map memory\n");
1850                 return ENXIO;
1851         }
1852
1853         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1854         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1855
1856         /* Save various chip information */
1857         sc->bnx_chipid =
1858             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1859             BGE_PCIMISCCTL_ASICREV_SHIFT;
1860         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1861                 /* All chips having dedicated ASICREV register have CPMU */
1862                 sc->bnx_flags |= BNX_FLAG_CPMU;
1863
1864                 switch (product) {
1865                 case PCI_PRODUCT_BROADCOM_BCM5717:
1866                 case PCI_PRODUCT_BROADCOM_BCM5717C:
1867                 case PCI_PRODUCT_BROADCOM_BCM5718:
1868                 case PCI_PRODUCT_BROADCOM_BCM5719:
1869                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1870                 case PCI_PRODUCT_BROADCOM_BCM5725:
1871                 case PCI_PRODUCT_BROADCOM_BCM5727:
1872                 case PCI_PRODUCT_BROADCOM_BCM5762:
1873                         sc->bnx_chipid = pci_read_config(dev,
1874                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1875                         break;
1876
1877                 case PCI_PRODUCT_BROADCOM_BCM57761:
1878                 case PCI_PRODUCT_BROADCOM_BCM57762:
1879                 case PCI_PRODUCT_BROADCOM_BCM57765:
1880                 case PCI_PRODUCT_BROADCOM_BCM57766:
1881                 case PCI_PRODUCT_BROADCOM_BCM57781:
1882                 case PCI_PRODUCT_BROADCOM_BCM57782:
1883                 case PCI_PRODUCT_BROADCOM_BCM57785:
1884                 case PCI_PRODUCT_BROADCOM_BCM57786:
1885                 case PCI_PRODUCT_BROADCOM_BCM57791:
1886                 case PCI_PRODUCT_BROADCOM_BCM57795:
1887                         sc->bnx_chipid = pci_read_config(dev,
1888                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1889                         break;
1890
1891                 default:
1892                         sc->bnx_chipid = pci_read_config(dev,
1893                             BGE_PCI_PRODID_ASICREV, 4);
1894                         break;
1895                 }
1896         }
1897         if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0)
1898                 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0;
1899
1900         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1901         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1902
1903         switch (sc->bnx_asicrev) {
1904         case BGE_ASICREV_BCM5717:
1905         case BGE_ASICREV_BCM5719:
1906         case BGE_ASICREV_BCM5720:
1907                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1908                 break;
1909
1910         case BGE_ASICREV_BCM5762:
1911                 sc->bnx_flags |= BNX_FLAG_57765_PLUS;
1912                 break;
1913
1914         case BGE_ASICREV_BCM57765:
1915         case BGE_ASICREV_BCM57766:
1916                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1917                 break;
1918         }
1919
1920         sc->bnx_flags |= BNX_FLAG_TSO;
1921         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1922             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1923                 sc->bnx_flags &= ~BNX_FLAG_TSO;
1924
1925         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1926             BNX_IS_57765_FAMILY(sc)) {
1927                 /*
1928                  * All BCM57785 and BCM5718 families chips have a bug that
1929                  * under certain situation interrupt will not be enabled
1930                  * even if status tag is written to interrupt mailbox.
1931                  *
1932                  * While BCM5719 and BCM5720 have a hardware workaround
1933                  * which could fix the above bug.
1934                  * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1935                  * bnx_chipinit().
1936                  *
1937                  * For the rest of the chips in these two families, we will
1938                  * have to poll the status block at high rate (10ms currently)
1939                  * to check whether the interrupt is hosed or not.
1940                  * See bnx_check_intr_*() for details.
1941                  */
1942                 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1943         }
1944
1945         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1946         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1947             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1948                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1949         else
1950                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1951         device_printf(dev, "CHIP ID 0x%08x; "
1952                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1953                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1954
1955         /*
1956          * Set various PHY quirk flags.
1957          */
1958
1959         capmask = MII_CAPMASK_DEFAULT;
1960         if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1961             product == PCI_PRODUCT_BROADCOM_BCM57795) {
1962                 /* 10/100 only */
1963                 capmask &= ~BMSR_EXTSTAT;
1964         }
1965
1966         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1967         if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0)
1968                 mii_priv |= BRGPHY_FLAG_5762_A0;
1969
1970         /* Initialize if_name earlier, so if_printf could be used */
1971         ifp = &sc->arpcom.ac_if;
1972         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1973
1974         /* Try to reset the chip. */
1975         bnx_reset(sc);
1976
1977         if (bnx_chipinit(sc)) {
1978                 device_printf(dev, "chip initialization failed\n");
1979                 error = ENXIO;
1980                 goto fail;
1981         }
1982
1983         /*
1984          * Get station address
1985          */
1986         error = bnx_get_eaddr(sc, ether_addr);
1987         if (error) {
1988                 device_printf(dev, "failed to read station address\n");
1989                 goto fail;
1990         }
1991
1992         /* Setup RX/TX and interrupt count */
1993         bnx_setup_ring_cnt(sc);
1994
1995         if ((sc->bnx_rx_retcnt == 1 && sc->bnx_tx_ringcnt == 1) ||
1996             (sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt > 1)) {
1997                 /*
1998                  * The RX ring and the corresponding TX ring processing
1999                  * should be on the same CPU, since they share the same
2000                  * status block.
2001                  */
2002                 sc->bnx_flags |= BNX_FLAG_RXTX_BUNDLE;
2003                 if (bootverbose)
2004                         device_printf(dev, "RX/TX bundle\n");
2005                 if (sc->bnx_tx_ringcnt > 1) {
2006                         /*
2007                          * Multiple TX rings do not share status block
2008                          * with link status, so link status will have
2009                          * to save its own status_tag.
2010                          */
2011                         sc->bnx_flags |= BNX_FLAG_STATUS_HASTAG;
2012                         if (bootverbose)
2013                                 device_printf(dev, "status needs tag\n");
2014                 }
2015         } else {
2016                 KKASSERT(sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt == 1);
2017                 if (bootverbose)
2018                         device_printf(dev, "RX/TX not bundled\n");
2019         }
2020
2021         error = bnx_dma_alloc(dev);
2022         if (error)
2023                 goto fail;
2024
2025 #ifdef IFPOLL_ENABLE
2026         if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
2027                 /*
2028                  * NPOLLING RX/TX CPU offset
2029                  */
2030                 if (sc->bnx_rx_retcnt == ncpus2) {
2031                         offset = 0;
2032                 } else {
2033                         offset_def =
2034                         (sc->bnx_rx_retcnt * device_get_unit(dev)) % ncpus2;
2035                         offset = device_getenv_int(dev, "npoll.offset",
2036                             offset_def);
2037                         if (offset >= ncpus2 ||
2038                             offset % sc->bnx_rx_retcnt != 0) {
2039                                 device_printf(dev, "invalid npoll.offset %d, "
2040                                     "use %d\n", offset, offset_def);
2041                                 offset = offset_def;
2042                         }
2043                 }
2044                 sc->bnx_npoll_rxoff = offset;
2045                 sc->bnx_npoll_txoff = offset;
2046         } else {
2047                 /*
2048                  * NPOLLING RX CPU offset
2049                  */
2050                 if (sc->bnx_rx_retcnt == ncpus2) {
2051                         offset = 0;
2052                 } else {
2053                         offset_def =
2054                         (sc->bnx_rx_retcnt * device_get_unit(dev)) % ncpus2;
2055                         offset = device_getenv_int(dev, "npoll.rxoff",
2056                             offset_def);
2057                         if (offset >= ncpus2 ||
2058                             offset % sc->bnx_rx_retcnt != 0) {
2059                                 device_printf(dev, "invalid npoll.rxoff %d, "
2060                                     "use %d\n", offset, offset_def);
2061                                 offset = offset_def;
2062                         }
2063                 }
2064                 sc->bnx_npoll_rxoff = offset;
2065
2066                 /*
2067                  * NPOLLING TX CPU offset
2068                  */
2069                 offset_def = device_get_unit(dev) % ncpus2;
2070                 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
2071                 if (offset >= ncpus2) {
2072                         device_printf(dev, "invalid npoll.txoff %d, use %d\n",
2073                             offset, offset_def);
2074                         offset = offset_def;
2075                 }
2076                 sc->bnx_npoll_txoff = offset;
2077         }
2078 #endif  /* IFPOLL_ENABLE */
2079
2080         /*
2081          * Allocate interrupt
2082          */
2083         error = bnx_alloc_intr(sc);
2084         if (error)
2085                 goto fail;
2086
2087         /* Setup serializers */
2088         bnx_setup_serialize(sc);
2089
2090         /* Set default tuneable values. */
2091         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
2092         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
2093         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
2094         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
2095         sc->bnx_tx_coal_bds_poll = BNX_TX_COAL_BDS_POLL_DEF;
2096         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
2097         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
2098
2099         /* Set up ifnet structure */
2100         ifp->if_softc = sc;
2101         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2102         ifp->if_ioctl = bnx_ioctl;
2103         ifp->if_start = bnx_start;
2104 #ifdef IFPOLL_ENABLE
2105         ifp->if_npoll = bnx_npoll;
2106 #endif
2107         ifp->if_init = bnx_init;
2108         ifp->if_serialize = bnx_serialize;
2109         ifp->if_deserialize = bnx_deserialize;
2110         ifp->if_tryserialize = bnx_tryserialize;
2111 #ifdef INVARIANTS
2112         ifp->if_serialize_assert = bnx_serialize_assert;
2113 #endif
2114         ifp->if_mtu = ETHERMTU;
2115         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2116
2117         ifp->if_capabilities |= IFCAP_HWCSUM;
2118         ifp->if_hwassist = BNX_CSUM_FEATURES;
2119         if (sc->bnx_flags & BNX_FLAG_TSO) {
2120                 ifp->if_capabilities |= IFCAP_TSO;
2121                 ifp->if_hwassist |= CSUM_TSO;
2122         }
2123         if (BNX_RSS_ENABLED(sc))
2124                 ifp->if_capabilities |= IFCAP_RSS;
2125         ifp->if_capenable = ifp->if_capabilities;
2126
2127         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2128         ifq_set_ready(&ifp->if_snd);
2129         ifq_set_subq_cnt(&ifp->if_snd, sc->bnx_tx_ringcnt);
2130
2131         if (sc->bnx_tx_ringcnt > 1) {
2132                 ifp->if_mapsubq = ifq_mapsubq_mask;
2133                 ifq_set_subq_mask(&ifp->if_snd, sc->bnx_tx_ringcnt - 1);
2134         }
2135
2136         /*
2137          * Figure out what sort of media we have by checking the
2138          * hardware config word in the first 32k of NIC internal memory,
2139          * or fall back to examining the EEPROM if necessary.
2140          * Note: on some BCM5700 cards, this value appears to be unset.
2141          * If that's the case, we have to rely on identifying the NIC
2142          * by its PCI subsystem ID, as we do below for the SysKonnect
2143          * SK-9D41.
2144          */
2145         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2146                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2147         } else {
2148                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2149                                     sizeof(hwcfg))) {
2150                         device_printf(dev, "failed to read EEPROM\n");
2151                         error = ENXIO;
2152                         goto fail;
2153                 }
2154                 hwcfg = ntohl(hwcfg);
2155         }
2156
2157         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2158         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2159             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2160                 sc->bnx_flags |= BNX_FLAG_TBI;
2161
2162         /* Setup MI MODE */
2163         if (sc->bnx_flags & BNX_FLAG_CPMU)
2164                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
2165         else
2166                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
2167
2168         /* Setup link status update stuffs */
2169         if (sc->bnx_flags & BNX_FLAG_TBI) {
2170                 sc->bnx_link_upd = bnx_tbi_link_upd;
2171                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2172         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
2173                 sc->bnx_link_upd = bnx_autopoll_link_upd;
2174                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2175         } else {
2176                 sc->bnx_link_upd = bnx_copper_link_upd;
2177                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2178         }
2179
2180         /* Set default PHY address */
2181         sc->bnx_phyno = 1;
2182
2183         /*
2184          * PHY address mapping for various devices.
2185          *
2186          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2187          * ---------+-------+-------+-------+-------+
2188          * BCM57XX  |   1   |   X   |   X   |   X   |
2189          * BCM5704  |   1   |   X   |   1   |   X   |
2190          * BCM5717  |   1   |   8   |   2   |   9   |
2191          * BCM5719  |   1   |   8   |   2   |   9   |
2192          * BCM5720  |   1   |   8   |   2   |   9   |
2193          *
2194          * Other addresses may respond but they are not
2195          * IEEE compliant PHYs and should be ignored.
2196          */
2197         if (BNX_IS_5717_PLUS(sc)) {
2198                 int f;
2199
2200                 f = pci_get_function(dev);
2201                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
2202                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2203                             BGE_SGDIGSTS_IS_SERDES)
2204                                 sc->bnx_phyno = f + 8;
2205                         else
2206                                 sc->bnx_phyno = f + 1;
2207                 } else {
2208                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2209                             BGE_CPMU_PHY_STRAP_IS_SERDES)
2210                                 sc->bnx_phyno = f + 8;
2211                         else
2212                                 sc->bnx_phyno = f + 1;
2213                 }
2214         }
2215
2216         if (sc->bnx_flags & BNX_FLAG_TBI) {
2217                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
2218                     bnx_ifmedia_upd, bnx_ifmedia_sts);
2219                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2220                 ifmedia_add(&sc->bnx_ifmedia,
2221                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2222                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2223                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2224                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2225         } else {
2226                 struct mii_probe_args mii_args;
2227
2228                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2229                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2230                 mii_args.mii_capmask = capmask;
2231                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2232                 mii_args.mii_priv = mii_priv;
2233
2234                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2235                 if (error) {
2236                         device_printf(dev, "MII without any PHY!\n");
2237                         goto fail;
2238                 }
2239         }
2240
2241         /*
2242          * Create sysctl nodes.
2243          */
2244         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2245         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2246                                               SYSCTL_STATIC_CHILDREN(_hw),
2247                                               OID_AUTO,
2248                                               device_get_nameunit(dev),
2249                                               CTLFLAG_RD, 0, "");
2250         if (sc->bnx_sysctl_tree == NULL) {
2251                 device_printf(dev, "can't add sysctl node\n");
2252                 error = ENXIO;
2253                 goto fail;
2254         }
2255
2256         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2257             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2258             "rx_rings", CTLFLAG_RD, &sc->bnx_rx_retcnt, 0, "# of RX rings");
2259         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2260             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2261             "tx_rings", CTLFLAG_RD, &sc->bnx_tx_ringcnt, 0, "# of TX rings");
2262
2263         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2264                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2265                         OID_AUTO, "rx_coal_ticks",
2266                         CTLTYPE_INT | CTLFLAG_RW,
2267                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2268                         "Receive coalescing ticks (usec).");
2269         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2270                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2271                         OID_AUTO, "tx_coal_ticks",
2272                         CTLTYPE_INT | CTLFLAG_RW,
2273                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2274                         "Transmit coalescing ticks (usec).");
2275         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2276                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2277                         OID_AUTO, "rx_coal_bds",
2278                         CTLTYPE_INT | CTLFLAG_RW,
2279                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2280                         "Receive max coalesced BD count.");
2281         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2282                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2283                         OID_AUTO, "tx_coal_bds",
2284                         CTLTYPE_INT | CTLFLAG_RW,
2285                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2286                         "Transmit max coalesced BD count.");
2287         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2288                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2289                         OID_AUTO, "tx_coal_bds_poll",
2290                         CTLTYPE_INT | CTLFLAG_RW,
2291                         sc, 0, bnx_sysctl_tx_coal_bds_poll, "I",
2292                         "Transmit max coalesced BD count in polling.");
2293         /*
2294          * A common design characteristic for many Broadcom
2295          * client controllers is that they only support a
2296          * single outstanding DMA read operation on the PCIe
2297          * bus. This means that it will take twice as long to
2298          * fetch a TX frame that is split into header and
2299          * payload buffers as it does to fetch a single,
2300          * contiguous TX frame (2 reads vs. 1 read). For these
2301          * controllers, coalescing buffers to reduce the number
2302          * of memory reads is effective way to get maximum
2303          * performance(about 940Mbps).  Without collapsing TX
2304          * buffers the maximum TCP bulk transfer performance
2305          * is about 850Mbps. However forcing coalescing mbufs
2306          * consumes a lot of CPU cycles, so leave it off by
2307          * default.
2308          */
2309         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2310             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2311             "force_defrag", CTLTYPE_INT | CTLFLAG_RW,
2312             sc, 0, bnx_sysctl_force_defrag, "I",
2313             "Force defragment on TX path");
2314
2315         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2316             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2317             "tx_wreg", CTLTYPE_INT | CTLFLAG_RW,
2318             sc, 0, bnx_sysctl_tx_wreg, "I",
2319             "# of segments before writing to hardware register");
2320
2321         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2322             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2323             "std_refill", CTLTYPE_INT | CTLFLAG_RW,
2324             sc, 0, bnx_sysctl_std_refill, "I",
2325             "# of packets received before scheduling standard refilling");
2326
2327         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2328             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2329             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2330             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2331             "Receive max coalesced BD count during interrupt.");
2332         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2333             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2334             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2335             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2336             "Transmit max coalesced BD count during interrupt.");
2337
2338 #ifdef IFPOLL_ENABLE
2339         if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
2340                 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2341                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2342                     "npoll_offset", CTLTYPE_INT | CTLFLAG_RW,
2343                     sc, 0, bnx_sysctl_npoll_offset, "I",
2344                     "NPOLLING cpu offset");
2345         } else {
2346                 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2347                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2348                     "npoll_rxoff", CTLTYPE_INT | CTLFLAG_RW,
2349                     sc, 0, bnx_sysctl_npoll_rxoff, "I",
2350                     "NPOLLING RX cpu offset");
2351                 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2352                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2353                     "npoll_txoff", CTLTYPE_INT | CTLFLAG_RW,
2354                     sc, 0, bnx_sysctl_npoll_txoff, "I",
2355                     "NPOLLING TX cpu offset");
2356         }
2357 #endif
2358
2359 #ifdef BNX_RSS_DEBUG
2360         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2361             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2362             "std_refill_mask", CTLFLAG_RD,
2363             &sc->bnx_rx_std_ring.bnx_rx_std_refill, 0, "");
2364         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2365             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2366             "std_used", CTLFLAG_RD,
2367             &sc->bnx_rx_std_ring.bnx_rx_std_used, 0, "");
2368         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2369             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2370             "rss_debug", CTLFLAG_RW, &sc->bnx_rss_debug, 0, "");
2371         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
2372                 ksnprintf(desc, sizeof(desc), "rx_pkt%d", i);
2373                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2374                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2375                     desc, CTLFLAG_RW, &sc->bnx_rx_ret_ring[i].bnx_rx_pkt, "");
2376
2377                 ksnprintf(desc, sizeof(desc), "rx_force_sched%d", i);
2378                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2379                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2380                     desc, CTLFLAG_RW,
2381                     &sc->bnx_rx_ret_ring[i].bnx_rx_force_sched, "");
2382         }
2383 #endif
2384 #ifdef BNX_TSS_DEBUG
2385         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2386                 ksnprintf(desc, sizeof(desc), "tx_pkt%d", i);
2387                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2388                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2389                     desc, CTLFLAG_RW, &sc->bnx_tx_ring[i].bnx_tx_pkt, "");
2390         }
2391 #endif
2392
2393         SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2394             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2395             "norxbds", CTLFLAG_RW, &sc->bnx_norxbds, "");
2396
2397         SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2398             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2399             "errors", CTLFLAG_RW, &sc->bnx_errors, "");
2400
2401 #ifdef BNX_TSO_DEBUG
2402         for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2403                 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2404                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2405                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2406                     desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2407         }
2408 #endif
2409
2410         /*
2411          * Call MI attach routine.
2412          */
2413         ether_ifattach(ifp, ether_addr, NULL);
2414
2415         /* Setup TX rings and subqueues */
2416         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2417                 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
2418                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
2419
2420                 ifsq_set_cpuid(ifsq, txr->bnx_tx_cpuid);
2421                 ifsq_set_hw_serialize(ifsq, &txr->bnx_tx_serialize);
2422                 ifsq_set_priv(ifsq, txr);
2423                 txr->bnx_ifsq = ifsq;
2424
2425                 ifsq_watchdog_init(&txr->bnx_tx_watchdog, ifsq, bnx_watchdog);
2426
2427                 if (bootverbose) {
2428                         device_printf(dev, "txr %d -> cpu%d\n", i,
2429                             txr->bnx_tx_cpuid);
2430                 }
2431         }
2432
2433         error = bnx_setup_intr(sc);
2434         if (error) {
2435                 ether_ifdetach(ifp);
2436                 goto fail;
2437         }
2438         bnx_set_tick_cpuid(sc, FALSE);
2439
2440         /*
2441          * Create RX standard ring refilling thread
2442          */
2443         std_cpuid_def = device_get_unit(dev) % ncpus;
2444         std_cpuid = device_getenv_int(dev, "std.cpuid", std_cpuid_def);
2445         if (std_cpuid < 0 || std_cpuid >= ncpus) {
2446                 device_printf(dev, "invalid std.cpuid %d, use %d\n",
2447                     std_cpuid, std_cpuid_def);
2448                 std_cpuid = std_cpuid_def;
2449         }
2450
2451         std = &sc->bnx_rx_std_ring;
2452         lwkt_create(bnx_rx_std_refill_ithread, std, NULL,
2453             &std->bnx_rx_std_ithread, TDF_NOSTART | TDF_INTTHREAD, std_cpuid,
2454             "%s std", device_get_nameunit(dev));
2455         lwkt_setpri(&std->bnx_rx_std_ithread, TDPRI_INT_MED);
2456         std->bnx_rx_std_ithread.td_preemptable = lwkt_preempt;
2457         sc->bnx_flags |= BNX_FLAG_STD_THREAD;
2458
2459         return(0);
2460 fail:
2461         bnx_detach(dev);
2462         return(error);
2463 }
2464
2465 static int
2466 bnx_detach(device_t dev)
2467 {
2468         struct bnx_softc *sc = device_get_softc(dev);
2469
2470         if (device_is_attached(dev)) {
2471                 struct ifnet *ifp = &sc->arpcom.ac_if;
2472
2473                 ifnet_serialize_all(ifp);
2474                 bnx_stop(sc);
2475                 bnx_reset(sc);
2476                 bnx_teardown_intr(sc, sc->bnx_intr_cnt);
2477                 ifnet_deserialize_all(ifp);
2478
2479                 ether_ifdetach(ifp);
2480         }
2481
2482         if (sc->bnx_flags & BNX_FLAG_STD_THREAD) {
2483                 struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
2484
2485                 tsleep_interlock(std, 0);
2486
2487                 if (std->bnx_rx_std_ithread.td_gd == mycpu) {
2488                         bnx_rx_std_refill_stop(std);
2489                 } else {
2490                         lwkt_send_ipiq(std->bnx_rx_std_ithread.td_gd,
2491                             bnx_rx_std_refill_stop, std);
2492                 }
2493
2494                 tsleep(std, PINTERLOCKED, "bnx_detach", 0);
2495                 if (bootverbose)
2496                         device_printf(dev, "RX std ithread exited\n");
2497
2498                 lwkt_synchronize_ipiqs("bnx_detach_ipiq");
2499         }
2500
2501         if (sc->bnx_flags & BNX_FLAG_TBI)
2502                 ifmedia_removeall(&sc->bnx_ifmedia);
2503         if (sc->bnx_miibus)
2504                 device_delete_child(dev, sc->bnx_miibus);
2505         bus_generic_detach(dev);
2506
2507         bnx_free_intr(sc);
2508
2509         if (sc->bnx_msix_mem_res != NULL) {
2510                 bus_release_resource(dev, SYS_RES_MEMORY, sc->bnx_msix_mem_rid,
2511                     sc->bnx_msix_mem_res);
2512         }
2513         if (sc->bnx_res != NULL) {
2514                 bus_release_resource(dev, SYS_RES_MEMORY,
2515                     BGE_PCI_BAR0, sc->bnx_res);
2516         }
2517
2518         if (sc->bnx_sysctl_tree != NULL)
2519                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2520
2521         bnx_dma_free(sc);
2522
2523         if (sc->bnx_serialize != NULL)
2524                 kfree(sc->bnx_serialize, M_DEVBUF);
2525
2526         return 0;
2527 }
2528
2529 static void
2530 bnx_reset(struct bnx_softc *sc)
2531 {
2532         device_t dev;
2533         uint32_t cachesize, command, pcistate, reset;
2534         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2535         int i, val = 0;
2536         uint16_t devctl;
2537
2538         dev = sc->bnx_dev;
2539
2540         write_op = bnx_writemem_direct;
2541
2542         /* Save some important PCI state. */
2543         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2544         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2545         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2546
2547         pci_write_config(dev, BGE_PCI_MISC_CTL,
2548             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2549             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2550             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2551
2552         /* Disable fastboot on controllers that support it. */
2553         if (bootverbose)
2554                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2555         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2556
2557         /*
2558          * Write the magic number to SRAM at offset 0xB50.
2559          * When firmware finishes its initialization it will
2560          * write ~BGE_MAGIC_NUMBER to the same location.
2561          */
2562         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2563
2564         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2565
2566         /* XXX: Broadcom Linux driver. */
2567         /* Force PCI-E 1.0a mode */
2568         if (!BNX_IS_57765_PLUS(sc) &&
2569             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2570             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2571              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2572                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2573                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2574         }
2575         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2576                 /* Prevent PCIE link training during global reset */
2577                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2578                 reset |= (1<<29);
2579         }
2580
2581         /*
2582          * Set GPHY Power Down Override to leave GPHY
2583          * powered up in D0 uninitialized.
2584          */
2585         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2586                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2587
2588         /* Issue global reset */
2589         write_op(sc, BGE_MISC_CFG, reset);
2590
2591         DELAY(1000);
2592
2593         /* XXX: Broadcom Linux driver. */
2594         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2595                 uint32_t v;
2596
2597                 DELAY(500000); /* wait for link training to complete */
2598                 v = pci_read_config(dev, 0xc4, 4);
2599                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2600         }
2601
2602         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2603
2604         /* Disable no snoop and disable relaxed ordering. */
2605         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2606
2607         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2608         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2609                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2610                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2611         }
2612
2613         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2614             devctl, 2);
2615
2616         /* Clear error status. */
2617         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2618             PCIEM_DEVSTS_CORR_ERR |
2619             PCIEM_DEVSTS_NFATAL_ERR |
2620             PCIEM_DEVSTS_FATAL_ERR |
2621             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2622
2623         /* Reset some of the PCI state that got zapped by reset */
2624         pci_write_config(dev, BGE_PCI_MISC_CTL,
2625             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2626             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2627             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2628         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2629         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2630         write_op(sc, BGE_MISC_CFG, (65 << 1));
2631
2632         /* Enable memory arbiter */
2633         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2634
2635         /*
2636          * Poll until we see the 1's complement of the magic number.
2637          * This indicates that the firmware initialization is complete.
2638          */
2639         for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2640                 val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2641                 if (val == ~BGE_MAGIC_NUMBER)
2642                         break;
2643                 DELAY(10);
2644         }
2645         if (i == BNX_FIRMWARE_TIMEOUT) {
2646                 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2647                           "timed out, found 0x%08x\n", val);
2648         }
2649
2650         /* BCM57765 A0 needs additional time before accessing. */
2651         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2652                 DELAY(10 * 1000);
2653
2654         /*
2655          * XXX Wait for the value of the PCISTATE register to
2656          * return to its original pre-reset state. This is a
2657          * fairly good indicator of reset completion. If we don't
2658          * wait for the reset to fully complete, trying to read
2659          * from the device's non-PCI registers may yield garbage
2660          * results.
2661          */
2662         for (i = 0; i < BNX_TIMEOUT; i++) {
2663                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2664                         break;
2665                 DELAY(10);
2666         }
2667
2668         /* Fix up byte swapping */
2669         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2670
2671         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2672
2673         /*
2674          * The 5704 in TBI mode apparently needs some special
2675          * adjustment to insure the SERDES drive level is set
2676          * to 1.2V.
2677          */
2678         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2679             (sc->bnx_flags & BNX_FLAG_TBI)) {
2680                 uint32_t serdescfg;
2681
2682                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2683                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2684                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2685         }
2686
2687         CSR_WRITE_4(sc, BGE_MI_MODE,
2688             sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2689         DELAY(80);
2690
2691         /* XXX: Broadcom Linux driver. */
2692         if (!BNX_IS_57765_PLUS(sc)) {
2693                 uint32_t v;
2694
2695                 /* Enable Data FIFO protection. */
2696                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2697                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2698         }
2699
2700         DELAY(10000);
2701
2702         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2703                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2704                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2705         }
2706 }
2707
2708 /*
2709  * Frame reception handling. This is called if there's a frame
2710  * on the receive return list.
2711  *
2712  * Note: we have to be able to handle two possibilities here:
2713  * 1) the frame is from the jumbo recieve ring
2714  * 2) the frame is from the standard receive ring
2715  */
2716
2717 static void
2718 bnx_rxeof(struct bnx_rx_ret_ring *ret, uint16_t rx_prod, int count)
2719 {
2720         struct bnx_softc *sc = ret->bnx_sc;
2721         struct bnx_rx_std_ring *std = ret->bnx_std;
2722         struct ifnet *ifp = &sc->arpcom.ac_if;
2723         int std_used = 0;
2724
2725         while (ret->bnx_rx_saved_considx != rx_prod && count != 0) {
2726                 struct pktinfo pi0, *pi = NULL;
2727                 struct bge_rx_bd *cur_rx;
2728                 struct bnx_rx_buf *rb;
2729                 uint32_t rxidx;
2730                 struct mbuf *m = NULL;
2731                 uint16_t vlan_tag = 0;
2732                 int have_tag = 0;
2733
2734                 --count;
2735
2736                 cur_rx = &ret->bnx_rx_ret_ring[ret->bnx_rx_saved_considx];
2737
2738                 rxidx = cur_rx->bge_idx;
2739                 KKASSERT(rxidx < BGE_STD_RX_RING_CNT);
2740
2741                 BNX_INC(ret->bnx_rx_saved_considx, BNX_RETURN_RING_CNT);
2742 #ifdef BNX_RSS_DEBUG
2743                 ret->bnx_rx_pkt++;
2744 #endif
2745
2746                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2747                         have_tag = 1;
2748                         vlan_tag = cur_rx->bge_vlan_tag;
2749                 }
2750
2751                 if (ret->bnx_rx_cnt >= ret->bnx_rx_cntmax) {
2752                         atomic_add_int(&std->bnx_rx_std_used, std_used);
2753                         std_used = 0;
2754
2755                         bnx_rx_std_refill_sched(ret, std);
2756                 }
2757                 ret->bnx_rx_cnt++;
2758                 ++std_used;
2759
2760                 rb = &std->bnx_rx_std_buf[rxidx];
2761                 m = rb->bnx_rx_mbuf;
2762                 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2763                         IFNET_STAT_INC(ifp, ierrors, 1);
2764                         cpu_sfence();
2765                         rb->bnx_rx_refilled = 1;
2766                         continue;
2767                 }
2768                 if (bnx_newbuf_std(ret, rxidx, 0)) {
2769                         IFNET_STAT_INC(ifp, ierrors, 1);
2770                         continue;
2771                 }
2772
2773                 IFNET_STAT_INC(ifp, ipackets, 1);
2774                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2775                 m->m_pkthdr.rcvif = ifp;
2776
2777                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2778                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2779                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2780                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2781                                 if ((cur_rx->bge_error_flag &
2782                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2783                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2784                         }
2785                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2786                                 m->m_pkthdr.csum_data =
2787                                     cur_rx->bge_tcp_udp_csum;
2788                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2789                                     CSUM_PSEUDO_HDR;
2790                         }
2791                 }
2792                 if (ifp->if_capenable & IFCAP_RSS) {
2793                         pi = bnx_rss_info(&pi0, cur_rx);
2794                         if (pi != NULL &&
2795                             (cur_rx->bge_flags & BGE_RXBDFLAG_RSS_HASH)) {
2796                                 m->m_flags |= M_HASH;
2797                                 m->m_pkthdr.hash =
2798                                     toeplitz_hash(cur_rx->bge_hash);
2799                         }
2800                 }
2801
2802                 /*
2803                  * If we received a packet with a vlan tag, pass it
2804                  * to vlan_input() instead of ether_input().
2805                  */
2806                 if (have_tag) {
2807                         m->m_flags |= M_VLANTAG;
2808                         m->m_pkthdr.ether_vlantag = vlan_tag;
2809                 }
2810                 ether_input_pkt(ifp, m, pi);
2811         }
2812         bnx_writembx(sc, ret->bnx_rx_mbx, ret->bnx_rx_saved_considx);
2813
2814         if (std_used > 0) {
2815                 int cur_std_used;
2816
2817                 cur_std_used = atomic_fetchadd_int(&std->bnx_rx_std_used,
2818                     std_used);
2819                 if (cur_std_used + std_used >= (BGE_STD_RX_RING_CNT / 2)) {
2820 #ifdef BNX_RSS_DEBUG
2821                         ret->bnx_rx_force_sched++;
2822 #endif
2823                         bnx_rx_std_refill_sched(ret, std);
2824                 }
2825         }
2826 }
2827
2828 static void
2829 bnx_txeof(struct bnx_tx_ring *txr, uint16_t tx_cons)
2830 {
2831         struct ifnet *ifp = &txr->bnx_sc->arpcom.ac_if;
2832
2833         /*
2834          * Go through our tx ring and free mbufs for those
2835          * frames that have been sent.
2836          */
2837         while (txr->bnx_tx_saved_considx != tx_cons) {
2838                 struct bnx_tx_buf *buf;
2839                 uint32_t idx = 0;
2840
2841                 idx = txr->bnx_tx_saved_considx;
2842                 buf = &txr->bnx_tx_buf[idx];
2843                 if (buf->bnx_tx_mbuf != NULL) {
2844                         IFNET_STAT_INC(ifp, opackets, 1);
2845 #ifdef BNX_TSS_DEBUG
2846                         txr->bnx_tx_pkt++;
2847 #endif
2848                         bus_dmamap_unload(txr->bnx_tx_mtag,
2849                             buf->bnx_tx_dmamap);
2850                         m_freem(buf->bnx_tx_mbuf);
2851                         buf->bnx_tx_mbuf = NULL;
2852                 }
2853                 txr->bnx_tx_cnt--;
2854                 BNX_INC(txr->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2855         }
2856
2857         if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) >=
2858             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2859                 ifsq_clr_oactive(txr->bnx_ifsq);
2860
2861         if (txr->bnx_tx_cnt == 0)
2862                 txr->bnx_tx_watchdog.wd_timer = 0;
2863
2864         if (!ifsq_is_empty(txr->bnx_ifsq))
2865                 ifsq_devstart(txr->bnx_ifsq);
2866 }
2867
2868 static void
2869 bnx_handle_status(struct bnx_softc *sc)
2870 {
2871         uint32_t status;
2872
2873         status = *sc->bnx_hw_status;
2874
2875         if (status & BGE_STATFLAG_ERROR) {
2876                 uint32_t val;
2877                 int reset = 0;
2878
2879                 sc->bnx_errors++;
2880
2881                 val = CSR_READ_4(sc, BGE_FLOW_ATTN);
2882                 if (val & ~BGE_FLOWATTN_MB_LOWAT) {
2883                         if_printf(&sc->arpcom.ac_if,
2884                             "flow attn 0x%08x\n", val);
2885                         reset = 1;
2886                 }
2887
2888                 val = CSR_READ_4(sc, BGE_MSI_STATUS);
2889                 if (val & ~BGE_MSISTAT_MSI_PCI_REQ) {
2890                         if_printf(&sc->arpcom.ac_if,
2891                             "msi status 0x%08x\n", val);
2892                         reset = 1;
2893                 }
2894
2895                 val = CSR_READ_4(sc, BGE_RDMA_STATUS);
2896                 if (val) {
2897                         if_printf(&sc->arpcom.ac_if,
2898                             "rmda status 0x%08x\n", val);
2899                         reset = 1;
2900                 }
2901
2902                 val = CSR_READ_4(sc, BGE_WDMA_STATUS);
2903                 if (val) {
2904                         if_printf(&sc->arpcom.ac_if,
2905                             "wdma status 0x%08x\n", val);
2906                         reset = 1;
2907                 }
2908
2909                 if (reset) {
2910                         bnx_serialize_skipmain(sc);
2911                         bnx_init(sc);
2912                         bnx_deserialize_skipmain(sc);
2913                 }
2914         }
2915
2916         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2917                 bnx_link_poll(sc);
2918 }
2919
2920 #ifdef IFPOLL_ENABLE
2921
2922 static void
2923 bnx_npoll_rx(struct ifnet *ifp __unused, void *xret, int cycle)
2924 {
2925         struct bnx_rx_ret_ring *ret = xret;
2926         uint16_t rx_prod;
2927
2928         ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
2929
2930         ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
2931         cpu_lfence();
2932
2933         rx_prod = *ret->bnx_rx_considx;
2934         if (ret->bnx_rx_saved_considx != rx_prod)
2935                 bnx_rxeof(ret, rx_prod, cycle);
2936 }
2937
2938 static void
2939 bnx_npoll_tx_notag(struct ifnet *ifp __unused, void *xtxr, int cycle __unused)
2940 {
2941         struct bnx_tx_ring *txr = xtxr;
2942         uint16_t tx_cons;
2943
2944         ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
2945
2946         tx_cons = *txr->bnx_tx_considx;
2947         if (txr->bnx_tx_saved_considx != tx_cons)
2948                 bnx_txeof(txr, tx_cons);
2949 }
2950
2951 static void
2952 bnx_npoll_tx(struct ifnet *ifp, void *xtxr, int cycle)
2953 {
2954         struct bnx_tx_ring *txr = xtxr;
2955
2956         ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
2957
2958         txr->bnx_saved_status_tag = *txr->bnx_hw_status_tag;
2959         cpu_lfence();
2960         bnx_npoll_tx_notag(ifp, txr, cycle);
2961 }
2962
2963 static void
2964 bnx_npoll_status_notag(struct ifnet *ifp)
2965 {
2966         struct bnx_softc *sc = ifp->if_softc;
2967
2968         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
2969
2970         bnx_handle_status(sc);
2971 }
2972
2973 static void
2974 bnx_npoll_status(struct ifnet *ifp)
2975 {
2976         struct bnx_softc *sc = ifp->if_softc;
2977
2978         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
2979
2980         sc->bnx_saved_status_tag = *sc->bnx_hw_status_tag;
2981         cpu_lfence();
2982         bnx_npoll_status_notag(ifp);
2983 }
2984
2985 static void
2986 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2987 {
2988         struct bnx_softc *sc = ifp->if_softc;
2989         int i;
2990
2991         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2992
2993         if (info != NULL) {
2994                 if (sc->bnx_flags & BNX_FLAG_STATUS_HASTAG)
2995                         info->ifpi_status.status_func = bnx_npoll_status;
2996                 else
2997                         info->ifpi_status.status_func = bnx_npoll_status_notag;
2998                 info->ifpi_status.serializer = &sc->bnx_main_serialize;
2999
3000                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3001                         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3002                         int idx = i + sc->bnx_npoll_txoff;
3003
3004                         KKASSERT(idx < ncpus2);
3005                         if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
3006                                 info->ifpi_tx[idx].poll_func =
3007                                     bnx_npoll_tx_notag;
3008                         } else {
3009                                 info->ifpi_tx[idx].poll_func = bnx_npoll_tx;
3010                         }
3011                         info->ifpi_tx[idx].arg = txr;
3012                         info->ifpi_tx[idx].serializer = &txr->bnx_tx_serialize;
3013                         ifsq_set_cpuid(txr->bnx_ifsq, idx);
3014                 }
3015
3016                 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
3017                         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
3018                         int idx = i + sc->bnx_npoll_rxoff;
3019
3020                         KKASSERT(idx < ncpus2);
3021                         info->ifpi_rx[idx].poll_func = bnx_npoll_rx;
3022                         info->ifpi_rx[idx].arg = ret;
3023                         info->ifpi_rx[idx].serializer =
3024                             &ret->bnx_rx_ret_serialize;
3025                 }
3026
3027                 if (ifp->if_flags & IFF_RUNNING) {
3028                         bnx_disable_intr(sc);
3029                         bnx_set_tick_cpuid(sc, TRUE);
3030
3031                         sc->bnx_coal_chg = BNX_TX_COAL_BDS_CHG;
3032                         bnx_coal_change(sc);
3033                 }
3034         } else {
3035                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3036                         ifsq_set_cpuid(sc->bnx_tx_ring[i].bnx_ifsq,
3037                             sc->bnx_tx_ring[i].bnx_tx_cpuid);
3038                 }
3039                 if (ifp->if_flags & IFF_RUNNING) {
3040                         sc->bnx_coal_chg = BNX_TX_COAL_BDS_CHG;
3041                         bnx_coal_change(sc);
3042
3043                         bnx_enable_intr(sc);
3044                         bnx_set_tick_cpuid(sc, FALSE);
3045                 }
3046         }
3047 }
3048
3049 #endif  /* IFPOLL_ENABLE */
3050
3051 static void
3052 bnx_intr_legacy(void *xsc)
3053 {
3054         struct bnx_softc *sc = xsc;
3055         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
3056
3057         if (ret->bnx_saved_status_tag == *ret->bnx_hw_status_tag) {
3058                 uint32_t val;
3059
3060                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
3061                 if (val & BGE_PCISTAT_INTR_NOTACT)
3062                         return;
3063         }
3064
3065         /*
3066          * NOTE:
3067          * Interrupt will have to be disabled if tagged status
3068          * is used, else interrupt will always be asserted on
3069          * certain chips (at least on BCM5750 AX/BX).
3070          */
3071         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3072
3073         bnx_intr(sc);
3074 }
3075
3076 static void
3077 bnx_msi(void *xsc)
3078 {
3079         bnx_intr(xsc);
3080 }
3081
3082 static void
3083 bnx_intr(struct bnx_softc *sc)
3084 {
3085         struct ifnet *ifp = &sc->arpcom.ac_if;
3086         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
3087
3088         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
3089
3090         ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
3091         /*
3092          * Use a load fence to ensure that status_tag is saved
3093          * before rx_prod, tx_cons and status.
3094          */
3095         cpu_lfence();
3096
3097         bnx_handle_status(sc);
3098
3099         if (ifp->if_flags & IFF_RUNNING) {
3100                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
3101                 uint16_t rx_prod, tx_cons;
3102
3103                 lwkt_serialize_enter(&ret->bnx_rx_ret_serialize);
3104                 rx_prod = *ret->bnx_rx_considx;
3105                 if (ret->bnx_rx_saved_considx != rx_prod)
3106                         bnx_rxeof(ret, rx_prod, -1);
3107                 lwkt_serialize_exit(&ret->bnx_rx_ret_serialize);
3108
3109                 lwkt_serialize_enter(&txr->bnx_tx_serialize);
3110                 tx_cons = *txr->bnx_tx_considx;
3111                 if (txr->bnx_tx_saved_considx != tx_cons)
3112                         bnx_txeof(txr, tx_cons);
3113                 lwkt_serialize_exit(&txr->bnx_tx_serialize);
3114         }
3115
3116         bnx_writembx(sc, BGE_MBX_IRQ0_LO, ret->bnx_saved_status_tag << 24);
3117 }
3118
3119 static void
3120 bnx_msix_tx_status(void *xtxr)
3121 {
3122         struct bnx_tx_ring *txr = xtxr;
3123         struct bnx_softc *sc = txr->bnx_sc;
3124         struct ifnet *ifp = &sc->arpcom.ac_if;
3125
3126         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
3127
3128         txr->bnx_saved_status_tag = *txr->bnx_hw_status_tag;
3129         /*
3130          * Use a load fence to ensure that status_tag is saved
3131          * before tx_cons and status.
3132          */
3133         cpu_lfence();
3134
3135         bnx_handle_status(sc);
3136
3137         if (ifp->if_flags & IFF_RUNNING) {
3138                 uint16_t tx_cons;
3139
3140                 lwkt_serialize_enter(&txr->bnx_tx_serialize);
3141                 tx_cons = *txr->bnx_tx_considx;
3142                 if (txr->bnx_tx_saved_considx != tx_cons)
3143                         bnx_txeof(txr, tx_cons);
3144                 lwkt_serialize_exit(&txr->bnx_tx_serialize);
3145         }
3146
3147         bnx_writembx(sc, BGE_MBX_IRQ0_LO, txr->bnx_saved_status_tag << 24);
3148 }
3149
3150 static void
3151 bnx_msix_rx(void *xret)
3152 {
3153         struct bnx_rx_ret_ring *ret = xret;
3154         uint16_t rx_prod;
3155
3156         ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
3157
3158         ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
3159         /*
3160          * Use a load fence to ensure that status_tag is saved
3161          * before rx_prod.
3162          */
3163         cpu_lfence();
3164
3165         rx_prod = *ret->bnx_rx_considx;
3166         if (ret->bnx_rx_saved_considx != rx_prod)
3167                 bnx_rxeof(ret, rx_prod, -1);
3168
3169         bnx_writembx(ret->bnx_sc, ret->bnx_msix_mbx,
3170             ret->bnx_saved_status_tag << 24);
3171 }
3172
3173 static void
3174 bnx_msix_rxtx(void *xret)
3175 {
3176         struct bnx_rx_ret_ring *ret = xret;
3177         struct bnx_tx_ring *txr = ret->bnx_txr;
3178         uint16_t rx_prod, tx_cons;
3179
3180         ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
3181
3182         ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
3183         /*
3184          * Use a load fence to ensure that status_tag is saved
3185          * before rx_prod and tx_cons.
3186          */
3187         cpu_lfence();
3188
3189         rx_prod = *ret->bnx_rx_considx;
3190         if (ret->bnx_rx_saved_considx != rx_prod)
3191                 bnx_rxeof(ret, rx_prod, -1);
3192
3193         lwkt_serialize_enter(&txr->bnx_tx_serialize);
3194         tx_cons = *txr->bnx_tx_considx;
3195         if (txr->bnx_tx_saved_considx != tx_cons)
3196                 bnx_txeof(txr, tx_cons);
3197         lwkt_serialize_exit(&txr->bnx_tx_serialize);
3198
3199         bnx_writembx(ret->bnx_sc, ret->bnx_msix_mbx,
3200             ret->bnx_saved_status_tag << 24);
3201 }
3202
3203 static void
3204 bnx_msix_status(void *xsc)
3205 {
3206         struct bnx_softc *sc = xsc;
3207
3208         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
3209
3210         sc->bnx_saved_status_tag = *sc->bnx_hw_status_tag;
3211         /*
3212          * Use a load fence to ensure that status_tag is saved
3213          * before status.
3214          */
3215         cpu_lfence();
3216
3217         bnx_handle_status(sc);
3218
3219         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_saved_status_tag << 24);
3220 }
3221
3222 static void
3223 bnx_tick(void *xsc)
3224 {
3225         struct bnx_softc *sc = xsc;
3226
3227         lwkt_serialize_enter(&sc->bnx_main_serialize);
3228
3229         bnx_stats_update_regs(sc);
3230
3231         if (sc->bnx_flags & BNX_FLAG_TBI) {
3232                 /*
3233                  * Since in TBI mode auto-polling can't be used we should poll
3234                  * link status manually. Here we register pending link event
3235                  * and trigger interrupt.
3236                  */
3237                 sc->bnx_link_evt++;
3238                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3239         } else if (!sc->bnx_link) {
3240                 mii_tick(device_get_softc(sc->bnx_miibus));
3241         }
3242
3243         callout_reset_bycpu(&sc->bnx_tick_timer, hz, bnx_tick, sc,
3244             sc->bnx_tick_cpuid);
3245
3246         lwkt_serialize_exit(&sc->bnx_main_serialize);
3247 }
3248
3249 static void
3250 bnx_stats_update_regs(struct bnx_softc *sc)
3251 {
3252         struct ifnet *ifp = &sc->arpcom.ac_if;
3253         struct bge_mac_stats_regs stats;
3254         uint32_t *s, val;
3255         int i;
3256
3257         s = (uint32_t *)&stats;
3258         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3259                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3260                 s++;
3261         }
3262
3263         IFNET_STAT_SET(ifp, collisions,
3264            (stats.dot3StatsSingleCollisionFrames +
3265            stats.dot3StatsMultipleCollisionFrames +
3266            stats.dot3StatsExcessiveCollisions +
3267            stats.dot3StatsLateCollisions));
3268
3269         val = CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
3270         sc->bnx_norxbds += val;
3271 }
3272
3273 /*
3274  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3275  * pointers to descriptors.
3276  */
3277 static int
3278 bnx_encap(struct bnx_tx_ring *txr, struct mbuf **m_head0, uint32_t *txidx,
3279     int *segs_used)
3280 {
3281         struct bge_tx_bd *d = NULL;
3282         uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
3283         bus_dma_segment_t segs[BNX_NSEG_NEW];
3284         bus_dmamap_t map;
3285         int error, maxsegs, nsegs, idx, i;
3286         struct mbuf *m_head = *m_head0, *m_new;
3287
3288         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3289 #ifdef BNX_TSO_DEBUG
3290                 int tso_nsegs;
3291 #endif
3292
3293                 error = bnx_setup_tso(txr, m_head0, &mss, &csum_flags);
3294                 if (error)
3295                         return error;
3296                 m_head = *m_head0;
3297
3298 #ifdef BNX_TSO_DEBUG
3299                 tso_nsegs = (m_head->m_pkthdr.len /
3300                     m_head->m_pkthdr.tso_segsz) - 1;
3301                 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
3302                         tso_nsegs = BNX_TSO_NSTATS - 1;
3303                 else if (tso_nsegs < 0)
3304                         tso_nsegs = 0;
3305                 txr->bnx_sc->bnx_tsosegs[tso_nsegs]++;
3306 #endif
3307         } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
3308                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3309                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3310                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3311                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3312                 if (m_head->m_flags & M_LASTFRAG)
3313                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3314                 else if (m_head->m_flags & M_FRAG)
3315                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3316         }
3317         if (m_head->m_flags & M_VLANTAG) {
3318                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
3319                 vlan_tag = m_head->m_pkthdr.ether_vlantag;
3320         }
3321
3322         idx = *txidx;
3323         map = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
3324
3325         maxsegs = (BGE_TX_RING_CNT - txr->bnx_tx_cnt) - BNX_NSEG_RSVD;
3326         KASSERT(maxsegs >= BNX_NSEG_SPARE,
3327                 ("not enough segments %d", maxsegs));
3328
3329         if (maxsegs > BNX_NSEG_NEW)
3330                 maxsegs = BNX_NSEG_NEW;
3331
3332         /*
3333          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
3334          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
3335          * but when such padded frames employ the bge IP/TCP checksum
3336          * offload, the hardware checksum assist gives incorrect results
3337          * (possibly from incorporating its own padding into the UDP/TCP
3338          * checksum; who knows).  If we pad such runts with zeros, the
3339          * onboard checksum comes out correct.
3340          */
3341         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3342             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
3343                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
3344                 if (error)
3345                         goto back;
3346         }
3347
3348         if ((txr->bnx_tx_flags & BNX_TX_FLAG_SHORTDMA) &&
3349             m_head->m_next != NULL) {
3350                 m_new = bnx_defrag_shortdma(m_head);
3351                 if (m_new == NULL) {
3352                         error = ENOBUFS;
3353                         goto back;
3354                 }
3355                 *m_head0 = m_head = m_new;
3356         }
3357         if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3358             (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG) &&
3359             m_head->m_next != NULL) {
3360                 /*
3361                  * Forcefully defragment mbuf chain to overcome hardware
3362                  * limitation which only support a single outstanding
3363                  * DMA read operation.  If it fails, keep moving on using
3364                  * the original mbuf chain.
3365                  */
3366                 m_new = m_defrag(m_head, MB_DONTWAIT);
3367                 if (m_new != NULL)
3368                         *m_head0 = m_head = m_new;
3369         }
3370
3371         error = bus_dmamap_load_mbuf_defrag(txr->bnx_tx_mtag, map,
3372             m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3373         if (error)
3374                 goto back;
3375         *segs_used += nsegs;
3376
3377         m_head = *m_head0;
3378         bus_dmamap_sync(txr->bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3379
3380         for (i = 0; ; i++) {
3381                 d = &txr->bnx_tx_ring[idx];
3382
3383                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3384                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3385                 d->bge_len = segs[i].ds_len;
3386                 d->bge_flags = csum_flags;
3387                 d->bge_vlan_tag = vlan_tag;
3388                 d->bge_mss = mss;
3389
3390                 if (i == nsegs - 1)
3391                         break;
3392                 BNX_INC(idx, BGE_TX_RING_CNT);
3393         }
3394         /* Mark the last segment as end of packet... */
3395         d->bge_flags |= BGE_TXBDFLAG_END;
3396
3397         /*
3398          * Insure that the map for this transmission is placed at
3399          * the array index of the last descriptor in this chain.
3400          */
3401         txr->bnx_tx_buf[*txidx].bnx_tx_dmamap = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
3402         txr->bnx_tx_buf[idx].bnx_tx_dmamap = map;
3403         txr->bnx_tx_buf[idx].bnx_tx_mbuf = m_head;
3404         txr->bnx_tx_cnt += nsegs;
3405
3406         BNX_INC(idx, BGE_TX_RING_CNT);
3407         *txidx = idx;
3408 back:
3409         if (error) {
3410                 m_freem(*m_head0);
3411                 *m_head0 = NULL;
3412         }
3413         return error;
3414 }
3415
3416 /*
3417  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3418  * to the mbuf data regions directly in the transmit descriptors.
3419  */
3420 static void
3421 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3422 {
3423         struct bnx_tx_ring *txr = ifsq_get_priv(ifsq);
3424         struct mbuf *m_head = NULL;
3425         uint32_t prodidx;
3426         int nsegs = 0;
3427
3428         KKASSERT(txr->bnx_ifsq == ifsq);
3429         ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
3430
3431         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3432                 return;
3433
3434         prodidx = txr->bnx_tx_prodidx;
3435
3436         while (txr->bnx_tx_buf[prodidx].bnx_tx_mbuf == NULL) {
3437                 /*
3438                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3439                  * descriptors of the end of the ring.  Also make
3440                  * sure there are BGE_NSEG_SPARE descriptors for
3441                  * jumbo buffers' or TSO segments' defragmentation.
3442                  */
3443                 if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) <
3444                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
3445                         ifsq_set_oactive(ifsq);
3446                         break;
3447                 }
3448
3449                 m_head = ifsq_dequeue(ifsq, NULL);
3450                 if (m_head == NULL)
3451                         break;
3452
3453                 /*
3454                  * Pack the data into the transmit ring. If we
3455                  * don't have room, set the OACTIVE flag and wait
3456                  * for the NIC to drain the ring.
3457                  */
3458                 if (bnx_encap(txr, &m_head, &prodidx, &nsegs)) {
3459                         ifsq_set_oactive(ifsq);
3460                         IFNET_STAT_INC(ifp, oerrors, 1);
3461                         break;
3462                 }
3463
3464                 if (nsegs >= txr->bnx_tx_wreg) {
3465                         /* Transmit */
3466                         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
3467                         nsegs = 0;
3468                 }
3469
3470                 ETHER_BPF_MTAP(ifp, m_head);
3471
3472                 /*
3473                  * Set a timeout in case the chip goes out to lunch.
3474                  */
3475                 txr->bnx_tx_watchdog.wd_timer = 5;
3476         }
3477
3478         if (nsegs > 0) {
3479                 /* Transmit */
3480                 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
3481         }
3482         txr->bnx_tx_prodidx = prodidx;
3483 }
3484
3485 static void
3486 bnx_init(void *xsc)
3487 {
3488         struct bnx_softc *sc = xsc;
3489         struct ifnet *ifp = &sc->arpcom.ac_if;
3490         uint16_t *m;
3491         uint32_t mode;
3492         int i;
3493         boolean_t polling;
3494
3495         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3496
3497         /* Cancel pending I/O and flush buffers. */
3498         bnx_stop(sc);
3499         bnx_reset(sc);
3500         bnx_chipinit(sc);
3501
3502         /*
3503          * Init the various state machines, ring
3504          * control blocks and firmware.
3505          */
3506         if (bnx_blockinit(sc)) {
3507                 if_printf(ifp, "initialization failure\n");
3508                 bnx_stop(sc);
3509                 return;
3510         }
3511
3512         /* Specify MTU. */
3513         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3514             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3515
3516         /* Load our MAC address. */
3517         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3518         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3519         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3520
3521         /* Enable or disable promiscuous mode as needed. */
3522         bnx_setpromisc(sc);
3523
3524         /* Program multicast filter. */
3525         bnx_setmulti(sc);
3526
3527         /* Init RX ring. */
3528         if (bnx_init_rx_ring_std(&sc->bnx_rx_std_ring)) {
3529                 if_printf(ifp, "RX ring initialization failed\n");
3530                 bnx_stop(sc);
3531                 return;
3532         }
3533
3534         /* Init jumbo RX ring. */
3535         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3536                 if (bnx_init_rx_ring_jumbo(sc)) {
3537                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3538                         bnx_stop(sc);
3539                         return;
3540                 }
3541         }
3542
3543         /* Init our RX return ring index */
3544         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
3545                 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
3546
3547                 ret->bnx_rx_saved_considx = 0;
3548                 ret->bnx_rx_cnt = 0;
3549         }
3550
3551         /* Init TX ring. */
3552         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3553                 bnx_init_tx_ring(&sc->bnx_tx_ring[i]);
3554
3555         /* Enable TX MAC state machine lockup fix. */
3556         mode = CSR_READ_4(sc, BGE_TX_MODE);
3557         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3558         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
3559             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
3560                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3561                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3562                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3563         }
3564         /* Turn on transmitter */
3565         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3566
3567         /* Initialize RSS */
3568         mode = BGE_RXMODE_ENABLE;
3569         if (BNX_RSS_ENABLED(sc)) {
3570                 bnx_init_rss(sc);
3571                 mode |= BGE_RXMODE_RSS_ENABLE |
3572                     BGE_RXMODE_RSS_HASH_MASK_BITS |
3573                     BGE_RXMODE_RSS_IPV4_HASH |
3574                     BGE_RXMODE_RSS_TCP_IPV4_HASH;
3575         }
3576         /* Turn on receiver */
3577         BNX_SETBIT(sc, BGE_RX_MODE, mode);
3578
3579         /*
3580          * Set the number of good frames to receive after RX MBUF
3581          * Low Watermark has been reached.  After the RX MAC receives
3582          * this number of frames, it will drop subsequent incoming
3583          * frames until the MBUF High Watermark is reached.
3584          */
3585         if (BNX_IS_57765_FAMILY(sc))
3586                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3587         else
3588                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3589
3590         if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI ||
3591             sc->bnx_intr_type == PCI_INTR_TYPE_MSIX) {
3592                 if (bootverbose) {
3593                         if_printf(ifp, "MSI_MODE: %#x\n",
3594                             CSR_READ_4(sc, BGE_MSI_MODE));
3595                 }
3596         }
3597
3598         /* Tell firmware we're alive. */
3599         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3600
3601         /* Enable host interrupts if polling(4) is not enabled. */
3602         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3603
3604         polling = FALSE;
3605 #ifdef IFPOLL_ENABLE
3606         if (ifp->if_flags & IFF_NPOLLING)
3607                 polling = TRUE;
3608 #endif
3609         if (polling)
3610                 bnx_disable_intr(sc);
3611         else
3612                 bnx_enable_intr(sc);
3613         bnx_set_tick_cpuid(sc, polling);
3614
3615         bnx_ifmedia_upd(ifp);
3616
3617         ifp->if_flags |= IFF_RUNNING;
3618         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3619                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3620
3621                 ifsq_clr_oactive(txr->bnx_ifsq);
3622                 ifsq_watchdog_start(&txr->bnx_tx_watchdog);
3623         }
3624
3625         callout_reset_bycpu(&sc->bnx_tick_timer, hz, bnx_tick, sc,
3626             sc->bnx_tick_cpuid);
3627 }
3628
3629 /*
3630  * Set media options.
3631  */
3632 static int
3633 bnx_ifmedia_upd(struct ifnet *ifp)
3634 {
3635         struct bnx_softc *sc = ifp->if_softc;
3636
3637         /* If this is a 1000baseX NIC, enable the TBI port. */
3638         if (sc->bnx_flags & BNX_FLAG_TBI) {
3639                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3640
3641                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3642                         return(EINVAL);
3643
3644                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3645                 case IFM_AUTO:
3646                         break;
3647
3648                 case IFM_1000_SX:
3649                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3650                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3651                                     BGE_MACMODE_HALF_DUPLEX);
3652                         } else {
3653                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3654                                     BGE_MACMODE_HALF_DUPLEX);
3655                         }
3656                         break;
3657                 default:
3658                         return(EINVAL);
3659                 }
3660         } else {
3661                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3662
3663                 sc->bnx_link_evt++;
3664                 sc->bnx_link = 0;
3665                 if (mii->mii_instance) {
3666                         struct mii_softc *miisc;
3667
3668                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3669                                 mii_phy_reset(miisc);
3670                 }
3671                 mii_mediachg(mii);
3672
3673                 /*
3674                  * Force an interrupt so that we will call bnx_link_upd
3675                  * if needed and clear any pending link state attention.
3676                  * Without this we are not getting any further interrupts
3677                  * for link state changes and thus will not UP the link and
3678                  * not be able to send in bnx_start.  The only way to get
3679                  * things working was to receive a packet and get an RX
3680                  * intr.
3681                  *
3682                  * bnx_tick should help for fiber cards and we might not
3683                  * need to do this here if BNX_FLAG_TBI is set but as
3684                  * we poll for fiber anyway it should not harm.
3685                  */
3686                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3687         }
3688         return(0);
3689 }
3690
3691 /*
3692  * Report current media status.
3693  */
3694 static void
3695 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3696 {
3697         struct bnx_softc *sc = ifp->if_softc;
3698
3699         if (sc->bnx_flags & BNX_FLAG_TBI) {
3700                 ifmr->ifm_status = IFM_AVALID;
3701                 ifmr->ifm_active = IFM_ETHER;
3702                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3703                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3704                         ifmr->ifm_status |= IFM_ACTIVE;
3705                 } else {
3706                         ifmr->ifm_active |= IFM_NONE;
3707                         return;
3708                 }
3709
3710                 ifmr->ifm_active |= IFM_1000_SX;
3711                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3712                         ifmr->ifm_active |= IFM_HDX;
3713                 else
3714                         ifmr->ifm_active |= IFM_FDX;
3715         } else {
3716                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3717
3718                 mii_pollstat(mii);
3719                 ifmr->ifm_active = mii->mii_media_active;
3720                 ifmr->ifm_status = mii->mii_media_status;
3721         }
3722 }
3723
3724 static int
3725 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3726 {
3727         struct bnx_softc *sc = ifp->if_softc;
3728         struct ifreq *ifr = (struct ifreq *)data;
3729         int mask, error = 0;
3730
3731         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3732
3733         switch (command) {
3734         case SIOCSIFMTU:
3735                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3736                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3737                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3738                         error = EINVAL;
3739                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3740                         ifp->if_mtu = ifr->ifr_mtu;
3741                         if (ifp->if_flags & IFF_RUNNING)
3742                                 bnx_init(sc);
3743                 }
3744                 break;
3745         case SIOCSIFFLAGS:
3746                 if (ifp->if_flags & IFF_UP) {
3747                         if (ifp->if_flags & IFF_RUNNING) {
3748                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3749
3750                                 /*
3751                                  * If only the state of the PROMISC flag
3752                                  * changed, then just use the 'set promisc
3753                                  * mode' command instead of reinitializing
3754                                  * the entire NIC. Doing a full re-init
3755                                  * means reloading the firmware and waiting
3756                                  * for it to start up, which may take a
3757                                  * second or two.  Similarly for ALLMULTI.
3758                                  */
3759                                 if (mask & IFF_PROMISC)
3760                                         bnx_setpromisc(sc);
3761                                 if (mask & IFF_ALLMULTI)
3762                                         bnx_setmulti(sc);
3763                         } else {
3764                                 bnx_init(sc);
3765                         }
3766                 } else if (ifp->if_flags & IFF_RUNNING) {
3767                         bnx_stop(sc);
3768                 }
3769                 sc->bnx_if_flags = ifp->if_flags;
3770                 break;
3771         case SIOCADDMULTI:
3772         case SIOCDELMULTI:
3773                 if (ifp->if_flags & IFF_RUNNING)
3774                         bnx_setmulti(sc);
3775                 break;
3776         case SIOCSIFMEDIA:
3777         case SIOCGIFMEDIA:
3778                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3779                         error = ifmedia_ioctl(ifp, ifr,
3780                             &sc->bnx_ifmedia, command);
3781                 } else {
3782                         struct mii_data *mii;
3783
3784                         mii = device_get_softc(sc->bnx_miibus);
3785                         error = ifmedia_ioctl(ifp, ifr,
3786                                               &mii->mii_media, command);
3787                 }
3788                 break;
3789         case SIOCSIFCAP:
3790                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3791                 if (mask & IFCAP_HWCSUM) {
3792                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3793                         if (ifp->if_capenable & IFCAP_TXCSUM)
3794                                 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3795                         else
3796                                 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3797                 }
3798                 if (mask & IFCAP_TSO) {
3799                         ifp->if_capenable ^= (mask & IFCAP_TSO);
3800                         if (ifp->if_capenable & IFCAP_TSO)
3801                                 ifp->if_hwassist |= CSUM_TSO;
3802                         else
3803                                 ifp->if_hwassist &= ~CSUM_TSO;
3804                 }
3805                 if (mask & IFCAP_RSS)
3806                         ifp->if_capenable ^= IFCAP_RSS;
3807                 break;
3808         default:
3809                 error = ether_ioctl(ifp, command, data);
3810                 break;
3811         }
3812         return error;
3813 }
3814
3815 static void
3816 bnx_watchdog(struct ifaltq_subque *ifsq)
3817 {
3818         struct ifnet *ifp = ifsq_get_ifp(ifsq);
3819         struct bnx_softc *sc = ifp->if_softc;
3820         int i;
3821
3822         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3823
3824         if_printf(ifp, "watchdog timeout -- resetting\n");
3825
3826         bnx_init(sc);
3827
3828         IFNET_STAT_INC(ifp, oerrors, 1);
3829
3830         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3831                 ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq);
3832 }
3833
3834 /*
3835  * Stop the adapter and free any mbufs allocated to the
3836  * RX and TX lists.
3837  */
3838 static void
3839 bnx_stop(struct bnx_softc *sc)
3840 {
3841         struct ifnet *ifp = &sc->arpcom.ac_if;
3842         int i;
3843
3844         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3845
3846         callout_stop(&sc->bnx_tick_timer);
3847
3848         /*
3849          * Disable all of the receiver blocks
3850          */
3851         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3852         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3853         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3854         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3855         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3856         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3857
3858         /*
3859          * Disable all of the transmit blocks
3860          */
3861         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3862         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3863         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3864         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3865         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3866         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3867
3868         /*
3869          * Shut down all of the memory managers and related
3870          * state machines.
3871          */
3872         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3873         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3874         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3875         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3876
3877         /* Disable host interrupts. */
3878         bnx_disable_intr(sc);
3879
3880         /*
3881          * Tell firmware we're shutting down.
3882          */
3883         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3884
3885         /* Free the RX lists. */
3886         bnx_free_rx_ring_std(&sc->bnx_rx_std_ring);
3887
3888         /* Free jumbo RX list. */
3889         if (BNX_IS_JUMBO_CAPABLE(sc))
3890                 bnx_free_rx_ring_jumbo(sc);
3891
3892         /* Free TX buffers. */
3893         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3894                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3895
3896                 txr->bnx_saved_status_tag = 0;
3897                 bnx_free_tx_ring(txr);
3898         }
3899
3900         /* Clear saved status tag */
3901         for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3902                 sc->bnx_rx_ret_ring[i].bnx_saved_status_tag = 0;
3903
3904         sc->bnx_link = 0;
3905         sc->bnx_coal_chg = 0;
3906
3907         ifp->if_flags &= ~IFF_RUNNING;
3908         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3909                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3910
3911                 ifsq_clr_oactive(txr->bnx_ifsq);
3912                 ifsq_watchdog_stop(&txr->bnx_tx_watchdog);
3913         }
3914 }
3915
3916 /*
3917  * Stop all chip I/O so that the kernel's probe routines don't
3918  * get confused by errant DMAs when rebooting.
3919  */
3920 static void
3921 bnx_shutdown(device_t dev)
3922 {
3923         struct bnx_softc *sc = device_get_softc(dev);
3924         struct ifnet *ifp = &sc->arpcom.ac_if;
3925
3926         ifnet_serialize_all(ifp);
3927         bnx_stop(sc);
3928         bnx_reset(sc);
3929         ifnet_deserialize_all(ifp);
3930 }
3931
3932 static int
3933 bnx_suspend(device_t dev)
3934 {
3935         struct bnx_softc *sc = device_get_softc(dev);
3936         struct ifnet *ifp = &sc->arpcom.ac_if;
3937
3938         ifnet_serialize_all(ifp);
3939         bnx_stop(sc);
3940         ifnet_deserialize_all(ifp);
3941
3942         return 0;
3943 }
3944
3945 static int
3946 bnx_resume(device_t dev)
3947 {
3948         struct bnx_softc *sc = device_get_softc(dev);
3949         struct ifnet *ifp = &sc->arpcom.ac_if;
3950
3951         ifnet_serialize_all(ifp);
3952
3953         if (ifp->if_flags & IFF_UP) {
3954                 int i;
3955
3956                 bnx_init(sc);
3957                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3958                         ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq);
3959         }
3960
3961         ifnet_deserialize_all(ifp);
3962
3963         return 0;
3964 }
3965
3966 static void
3967 bnx_setpromisc(struct bnx_softc *sc)
3968 {
3969         struct ifnet *ifp = &sc->arpcom.ac_if;
3970
3971         if (ifp->if_flags & IFF_PROMISC)
3972                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3973         else
3974                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3975 }
3976
3977 static void
3978 bnx_dma_free(struct bnx_softc *sc)
3979 {
3980         struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
3981         int i;
3982
3983         /* Destroy RX return rings */
3984         if (sc->bnx_rx_ret_ring != NULL) {
3985                 for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3986                         bnx_destroy_rx_ret_ring(&sc->bnx_rx_ret_ring[i]);
3987                 kfree(sc->bnx_rx_ret_ring, M_DEVBUF);
3988         }
3989
3990         /* Destroy RX mbuf DMA stuffs. */
3991         if (std->bnx_rx_mtag != NULL) {
3992                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3993                         KKASSERT(std->bnx_rx_std_buf[i].bnx_rx_mbuf == NULL);
3994                         bus_dmamap_destroy(std->bnx_rx_mtag,
3995                             std->bnx_rx_std_buf[i].bnx_rx_dmamap);
3996                 }
3997                 bus_dma_tag_destroy(std->bnx_rx_mtag);
3998         }
3999
4000         /* Destroy standard RX ring */
4001         bnx_dma_block_free(std->bnx_rx_std_ring_tag,
4002             std->bnx_rx_std_ring_map, std->bnx_rx_std_ring);
4003
4004         /* Destroy TX rings */
4005         if (sc->bnx_tx_ring != NULL) {
4006                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
4007                         bnx_destroy_tx_ring(&sc->bnx_tx_ring[i]);
4008                 kfree(sc->bnx_tx_ring, M_DEVBUF);
4009         }
4010
4011         if (BNX_IS_JUMBO_CAPABLE(sc))
4012                 bnx_free_jumbo_mem(sc);
4013
4014         /* Destroy status blocks */
4015         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4016                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4017
4018                 bnx_dma_block_free(intr->bnx_status_tag,
4019                     intr->bnx_status_map, intr->bnx_status_block);
4020         }
4021
4022         /* Destroy the parent tag */
4023         if (sc->bnx_cdata.bnx_parent_tag != NULL)
4024                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
4025 }
4026
4027 static int
4028 bnx_dma_alloc(device_t dev)
4029 {
4030         struct bnx_softc *sc = device_get_softc(dev);
4031         struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
4032         int i, error, mbx;
4033
4034         /*
4035          * Allocate the parent bus DMA tag appropriate for PCI.
4036          *
4037          * All of the NetExtreme/NetLink controllers have 4GB boundary
4038          * DMA bug.
4039          * Whenever an address crosses a multiple of the 4GB boundary
4040          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
4041          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
4042          * state machine will lockup and cause the device to hang.
4043          */
4044         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
4045             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
4046             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
4047             0, &sc->bnx_cdata.bnx_parent_tag);
4048         if (error) {
4049                 device_printf(dev, "could not create parent DMA tag\n");
4050                 return error;
4051         }
4052
4053         /*
4054          * Create DMA stuffs for status blocks.
4055          */
4056         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4057                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4058
4059                 error = bnx_dma_block_alloc(sc,
4060                     __VM_CACHELINE_ALIGN(BGE_STATUS_BLK_SZ),
4061                     &intr->bnx_status_tag, &intr->bnx_status_map,
4062                     (void *)&intr->bnx_status_block,
4063                     &intr->bnx_status_block_paddr);
4064                 if (error) {
4065                         device_printf(dev,
4066                             "could not create %dth status block\n", i);
4067                         return error;
4068                 }
4069         }
4070         sc->bnx_hw_status = &sc->bnx_intr_data[0].bnx_status_block->bge_status;
4071         if (sc->bnx_flags & BNX_FLAG_STATUS_HASTAG) {
4072                 sc->bnx_hw_status_tag =
4073                     &sc->bnx_intr_data[0].bnx_status_block->bge_status_tag;
4074         }
4075
4076         /*
4077          * Create DMA tag and maps for RX mbufs.
4078          */
4079         std->bnx_sc = sc;
4080         lwkt_serialize_init(&std->bnx_rx_std_serialize);
4081         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
4082             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4083             NULL, NULL, MCLBYTES, 1, MCLBYTES,
4084             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, &std->bnx_rx_mtag);
4085         if (error) {
4086                 device_printf(dev, "could not create RX mbuf DMA tag\n");
4087                 return error;
4088         }
4089
4090         for (i = 0; i < BGE_STD_RX_RING_CNT; ++i) {
4091                 error = bus_dmamap_create(std->bnx_rx_mtag, BUS_DMA_WAITOK,
4092                     &std->bnx_rx_std_buf[i].bnx_rx_dmamap);
4093                 if (error) {
4094                         int j;
4095
4096                         for (j = 0; j < i; ++j) {
4097                                 bus_dmamap_destroy(std->bnx_rx_mtag,
4098                                     std->bnx_rx_std_buf[j].bnx_rx_dmamap);
4099                         }
4100                         bus_dma_tag_destroy(std->bnx_rx_mtag);
4101                         std->bnx_rx_mtag = NULL;
4102
4103                         device_printf(dev,
4104                             "could not create %dth RX mbuf DMA map\n", i);
4105                         return error;
4106                 }
4107         }
4108
4109         /*
4110          * Create DMA stuffs for standard RX ring.
4111          */
4112         error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
4113             &std->bnx_rx_std_ring_tag,
4114             &std->bnx_rx_std_ring_map,
4115             (void *)&std->bnx_rx_std_ring,
4116             &std->bnx_rx_std_ring_paddr);
4117         if (error) {
4118                 device_printf(dev, "could not create std RX ring\n");
4119                 return error;
4120         }
4121
4122         /*
4123          * Create RX return rings
4124          */
4125         mbx = BGE_MBX_RX_CONS0_LO;
4126         sc->bnx_rx_ret_ring = kmalloc_cachealign(
4127             sizeof(struct bnx_rx_ret_ring) * sc->bnx_rx_retcnt, M_DEVBUF,
4128             M_WAITOK | M_ZERO);
4129         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4130                 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
4131                 struct bnx_intr_data *intr;
4132
4133                 ret->bnx_sc = sc;
4134                 ret->bnx_std = std;
4135                 ret->bnx_rx_mbx = mbx;
4136                 ret->bnx_rx_cntmax = (BGE_STD_RX_RING_CNT / 4) /
4137                     sc->bnx_rx_retcnt;
4138                 ret->bnx_rx_mask = 1 << i;
4139
4140                 if (!BNX_RSS_ENABLED(sc)) {
4141                         intr = &sc->bnx_intr_data[0];
4142                 } else {
4143                         KKASSERT(i + 1 < sc->bnx_intr_cnt);
4144                         intr = &sc->bnx_intr_data[i + 1];
4145                 }
4146
4147                 if (i == 0) {
4148                         ret->bnx_rx_considx =
4149                             &intr->bnx_status_block->bge_idx[0].bge_rx_prod_idx;
4150                 } else if (i == 1) {
4151                         ret->bnx_rx_considx =
4152                             &intr->bnx_status_block->bge_rx_jumbo_cons_idx;
4153                 } else if (i == 2) {
4154                         ret->bnx_rx_considx =
4155                             &intr->bnx_status_block->bge_rsvd1;
4156                 } else if (i == 3) {
4157                         ret->bnx_rx_considx =
4158                             &intr->bnx_status_block->bge_rx_mini_cons_idx;
4159                 } else {
4160                         panic("unknown RX return ring %d\n", i);
4161                 }
4162                 ret->bnx_hw_status_tag =
4163                     &intr->bnx_status_block->bge_status_tag;
4164
4165                 error = bnx_create_rx_ret_ring(ret);
4166                 if (error) {
4167                         device_printf(dev,
4168                             "could not create %dth RX ret ring\n", i);
4169                         return error;
4170                 }
4171                 mbx += 8;
4172         }
4173
4174         /*
4175          * Create TX rings
4176          */
4177         sc->bnx_tx_ring = kmalloc_cachealign(
4178             sizeof(struct bnx_tx_ring) * sc->bnx_tx_ringcnt, M_DEVBUF,
4179             M_WAITOK | M_ZERO);
4180         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4181                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
4182                 struct bnx_intr_data *intr;
4183
4184                 txr->bnx_sc = sc;
4185                 txr->bnx_tx_mbx = bnx_tx_mailbox[i];
4186
4187                 if (sc->bnx_tx_ringcnt == 1) {
4188                         intr = &sc->bnx_intr_data[0];
4189                 } else {
4190                         KKASSERT(i + 1 < sc->bnx_intr_cnt);
4191                         intr = &sc->bnx_intr_data[i + 1];
4192                 }
4193
4194                 if ((sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) == 0) {
4195                         txr->bnx_hw_status_tag =
4196                             &intr->bnx_status_block->bge_status_tag;
4197                 }
4198                 txr->bnx_tx_considx =
4199                     &intr->bnx_status_block->bge_idx[0].bge_tx_cons_idx;
4200
4201                 error = bnx_create_tx_ring(txr);
4202                 if (error) {
4203                         device_printf(dev,
4204                             "could not create %dth TX ring\n", i);
4205                         return error;
4206                 }
4207         }
4208
4209         /*
4210          * Create jumbo buffer pool.
4211          */
4212         if (BNX_IS_JUMBO_CAPABLE(sc)) {
4213                 error = bnx_alloc_jumbo_mem(sc);
4214                 if (error) {
4215                         device_printf(dev,
4216                             "could not create jumbo buffer pool\n");
4217                         return error;
4218                 }
4219         }
4220
4221         return 0;
4222 }
4223
4224 static int
4225 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
4226                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
4227 {
4228         bus_dmamem_t dmem;
4229         int error;
4230
4231         error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
4232                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4233                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
4234         if (error)
4235                 return error;
4236
4237         *tag = dmem.dmem_tag;
4238         *map = dmem.dmem_map;
4239         *addr = dmem.dmem_addr;
4240         *paddr = dmem.dmem_busaddr;
4241
4242         return 0;
4243 }
4244
4245 static void
4246 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
4247 {
4248         if (tag != NULL) {
4249                 bus_dmamap_unload(tag, map);
4250                 bus_dmamem_free(tag, addr, map);
4251                 bus_dma_tag_destroy(tag);
4252         }
4253 }
4254
4255 static void
4256 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
4257 {
4258         struct ifnet *ifp = &sc->arpcom.ac_if;
4259
4260 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
4261
4262         /*
4263          * Sometimes PCS encoding errors are detected in
4264          * TBI mode (on fiber NICs), and for some reason
4265          * the chip will signal them as link changes.
4266          * If we get a link change event, but the 'PCS
4267          * encoding error' bit in the MAC status register
4268          * is set, don't bother doing a link check.
4269          * This avoids spurious "gigabit link up" messages
4270          * that sometimes appear on fiber NICs during
4271          * periods of heavy traffic.
4272          */
4273         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4274                 if (!sc->bnx_link) {
4275                         sc->bnx_link++;
4276                         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
4277                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
4278                                     BGE_MACMODE_TBI_SEND_CFGS);
4279                         }
4280                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4281
4282                         if (bootverbose)
4283                                 if_printf(ifp, "link UP\n");
4284
4285                         ifp->if_link_state = LINK_STATE_UP;
4286                         if_link_state_change(ifp);
4287                 }
4288         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
4289                 if (sc->bnx_link) {
4290                         sc->bnx_link = 0;
4291
4292                         if (bootverbose)
4293                                 if_printf(ifp, "link DOWN\n");
4294
4295                         ifp->if_link_state = LINK_STATE_DOWN;
4296                         if_link_state_change(ifp);
4297                 }
4298         }
4299
4300 #undef PCS_ENCODE_ERR
4301
4302         /* Clear the attention. */
4303         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4304             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4305             BGE_MACSTAT_LINK_CHANGED);
4306 }
4307
4308 static void
4309 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
4310 {
4311         struct ifnet *ifp = &sc->arpcom.ac_if;
4312         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
4313
4314         mii_pollstat(mii);
4315         bnx_miibus_statchg(sc->bnx_dev);
4316
4317         if (bootverbose) {
4318                 if (sc->bnx_link)
4319                         if_printf(ifp, "link UP\n");
4320                 else
4321                         if_printf(ifp, "link DOWN\n");
4322         }
4323
4324         /* Clear the attention. */
4325         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4326             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4327             BGE_MACSTAT_LINK_CHANGED);
4328 }
4329
4330 static void
4331 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
4332 {
4333         struct ifnet *ifp = &sc->arpcom.ac_if;
4334         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
4335
4336         mii_pollstat(mii);
4337
4338         if (!sc->bnx_link &&
4339             (mii->mii_media_status & IFM_ACTIVE) &&
4340             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4341                 sc->bnx_link++;
4342                 if (bootverbose)
4343                         if_printf(ifp, "link UP\n");
4344         } else if (sc->bnx_link &&
4345             (!(mii->mii_media_status & IFM_ACTIVE) ||
4346             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4347                 sc->bnx_link = 0;
4348                 if (bootverbose)
4349                         if_printf(ifp, "link DOWN\n");
4350         }
4351
4352         /* Clear the attention. */
4353         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4354             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4355             BGE_MACSTAT_LINK_CHANGED);
4356 }
4357
4358 static int
4359 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
4360 {
4361         struct bnx_softc *sc = arg1;
4362
4363         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4364             &sc->bnx_rx_coal_ticks,
4365             BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
4366             BNX_RX_COAL_TICKS_CHG);
4367 }
4368
4369 static int
4370 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
4371 {
4372         struct bnx_softc *sc = arg1;
4373
4374         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4375             &sc->bnx_tx_coal_ticks,
4376             BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
4377             BNX_TX_COAL_TICKS_CHG);
4378 }
4379
4380 static int
4381 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
4382 {
4383         struct bnx_softc *sc = arg1;
4384
4385         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4386             &sc->bnx_rx_coal_bds,
4387             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
4388             BNX_RX_COAL_BDS_CHG);
4389 }
4390
4391 static int
4392 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
4393 {
4394         struct bnx_softc *sc = arg1;
4395
4396         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4397             &sc->bnx_tx_coal_bds,
4398             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
4399             BNX_TX_COAL_BDS_CHG);
4400 }
4401
4402 static int
4403 bnx_sysctl_tx_coal_bds_poll(SYSCTL_HANDLER_ARGS)
4404 {
4405         struct bnx_softc *sc = arg1;
4406
4407         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4408             &sc->bnx_tx_coal_bds_poll,
4409             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
4410             BNX_TX_COAL_BDS_CHG);
4411 }
4412
4413 static int
4414 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4415 {
4416         struct bnx_softc *sc = arg1;
4417
4418         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4419             &sc->bnx_rx_coal_bds_int,
4420             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
4421             BNX_RX_COAL_BDS_INT_CHG);
4422 }
4423
4424 static int
4425 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4426 {
4427         struct bnx_softc *sc = arg1;
4428
4429         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4430             &sc->bnx_tx_coal_bds_int,
4431             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
4432             BNX_TX_COAL_BDS_INT_CHG);
4433 }
4434
4435 static int
4436 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
4437     int coal_min, int coal_max, uint32_t coal_chg_mask)
4438 {
4439         struct bnx_softc *sc = arg1;
4440         struct ifnet *ifp = &sc->arpcom.ac_if;
4441         int error = 0, v;
4442
4443         ifnet_serialize_all(ifp);
4444
4445         v = *coal;
4446         error = sysctl_handle_int(oidp, &v, 0, req);
4447         if (!error && req->newptr != NULL) {
4448                 if (v < coal_min || v > coal_max) {
4449                         error = EINVAL;
4450                 } else {
4451                         *coal = v;
4452                         sc->bnx_coal_chg |= coal_chg_mask;
4453
4454                         /* Commit changes */
4455                         bnx_coal_change(sc);
4456                 }
4457         }
4458
4459         ifnet_deserialize_all(ifp);
4460         return error;
4461 }
4462
4463 static void
4464 bnx_coal_change(struct bnx_softc *sc)
4465 {
4466         struct ifnet *ifp = &sc->arpcom.ac_if;
4467         int i;
4468
4469         ASSERT_IFNET_SERIALIZED_ALL(ifp);
4470
4471         if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
4472                 if (sc->bnx_rx_retcnt == 1) {
4473                         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
4474                             sc->bnx_rx_coal_ticks);
4475                         i = 0;
4476                 } else {
4477                         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, 0);
4478                         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4479                                 CSR_WRITE_4(sc, BGE_VEC1_RX_COAL_TICKS +
4480                                     (i * BGE_VEC_COALSET_SIZE),
4481                                     sc->bnx_rx_coal_ticks);
4482                         }
4483                 }
4484                 for (; i < BNX_INTR_MAX - 1; ++i) {
4485                         CSR_WRITE_4(sc, BGE_VEC1_RX_COAL_TICKS +
4486                             (i * BGE_VEC_COALSET_SIZE), 0);
4487                 }
4488                 if (bootverbose) {
4489                         if_printf(ifp, "rx_coal_ticks -> %u\n",
4490                             sc->bnx_rx_coal_ticks);
4491                 }
4492         }
4493
4494         if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
4495                 if (sc->bnx_tx_ringcnt == 1) {
4496                         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
4497                             sc->bnx_tx_coal_ticks);
4498                         i = 0;
4499                 } else {
4500                         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, 0);
4501                         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4502                                 CSR_WRITE_4(sc, BGE_VEC1_TX_COAL_TICKS +
4503                                     (i * BGE_VEC_COALSET_SIZE),
4504                                     sc->bnx_tx_coal_ticks);
4505                         }
4506                 }
4507                 for (; i < BNX_INTR_MAX - 1; ++i) {
4508                         CSR_WRITE_4(sc, BGE_VEC1_TX_COAL_TICKS +
4509                             (i * BGE_VEC_COALSET_SIZE), 0);
4510                 }
4511                 if (bootverbose) {
4512                         if_printf(ifp, "tx_coal_ticks -> %u\n",
4513                             sc->bnx_tx_coal_ticks);
4514                 }
4515         }
4516
4517         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
4518                 if (sc->bnx_rx_retcnt == 1) {
4519                         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4520                             sc->bnx_rx_coal_bds);
4521                         i = 0;
4522                 } else {
4523                         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, 0);
4524                         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4525                                 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS +
4526                                     (i * BGE_VEC_COALSET_SIZE),
4527                                     sc->bnx_rx_coal_bds);
4528                         }
4529                 }
4530                 for (; i < BNX_INTR_MAX - 1; ++i) {
4531                         CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS +
4532                             (i * BGE_VEC_COALSET_SIZE), 0);
4533                 }
4534                 if (bootverbose) {
4535                         if_printf(ifp, "rx_coal_bds -> %u\n",
4536                             sc->bnx_rx_coal_bds);
4537                 }
4538         }
4539
4540         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
4541                 uint32_t tx_coal_bds;
4542
4543                 if (ifp->if_flags & IFF_NPOLLING)
4544                         tx_coal_bds = sc->bnx_tx_coal_bds_poll;
4545                 else
4546                         tx_coal_bds = sc->bnx_tx_coal_bds;
4547
4548                 if (sc->bnx_tx_ringcnt == 1) {
4549                         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, tx_coal_bds);
4550                         i = 0;
4551                 } else {
4552                         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, 0);
4553                         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4554                                 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS +
4555                                     (i * BGE_VEC_COALSET_SIZE), tx_coal_bds);
4556                         }
4557                 }
4558                 for (; i < BNX_INTR_MAX - 1; ++i) {
4559                         CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS +
4560                             (i * BGE_VEC_COALSET_SIZE), 0);
4561                 }
4562                 if (bootverbose) {
4563                         if_printf(ifp, "%stx_coal_bds -> %u\n",
4564                             (ifp->if_flags & IFF_NPOLLING) ? "polling " : "",
4565                             tx_coal_bds);
4566                 }
4567         }
4568
4569         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
4570                 if (sc->bnx_rx_retcnt == 1) {
4571                         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
4572                             sc->bnx_rx_coal_bds_int);
4573                         i = 0;
4574                 } else {
4575                         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
4576                         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4577                                 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS_INT +
4578                                     (i * BGE_VEC_COALSET_SIZE),
4579                                     sc->bnx_rx_coal_bds_int);
4580                         }
4581                 }
4582                 for (; i < BNX_INTR_MAX - 1; ++i) {
4583                         CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS_INT +
4584                             (i * BGE_VEC_COALSET_SIZE), 0);
4585                 }
4586                 if (bootverbose) {
4587                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
4588                             sc->bnx_rx_coal_bds_int);
4589                 }
4590         }
4591
4592         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
4593                 if (sc->bnx_tx_ringcnt == 1) {
4594                         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
4595                             sc->bnx_tx_coal_bds_int);
4596                         i = 0;
4597                 } else {
4598                         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
4599                         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4600                                 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS_INT +
4601                                     (i * BGE_VEC_COALSET_SIZE),
4602                                     sc->bnx_tx_coal_bds_int);
4603                         }
4604                 }
4605                 for (; i < BNX_INTR_MAX - 1; ++i) {
4606                         CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS_INT +
4607                             (i * BGE_VEC_COALSET_SIZE), 0);
4608                 }
4609                 if (bootverbose) {
4610                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
4611                             sc->bnx_tx_coal_bds_int);
4612                 }
4613         }
4614
4615         sc->bnx_coal_chg = 0;
4616 }
4617
4618 static void
4619 bnx_check_intr_rxtx(void *xintr)
4620 {
4621         struct bnx_intr_data *intr = xintr;
4622         struct bnx_rx_ret_ring *ret;
4623         struct bnx_tx_ring *txr;
4624         struct ifnet *ifp;
4625
4626         lwkt_serialize_enter(intr->bnx_intr_serialize);
4627
4628         KKASSERT(mycpuid == intr->bnx_intr_cpuid);
4629
4630         ifp = &intr->bnx_sc->arpcom.ac_if;
4631         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4632                 lwkt_serialize_exit(intr->bnx_intr_serialize);
4633                 return;
4634         }
4635
4636         txr = intr->bnx_txr;
4637         ret = intr->bnx_ret;
4638
4639         if (*ret->bnx_rx_considx != ret->bnx_rx_saved_considx ||
4640             *txr->bnx_tx_considx != txr->bnx_tx_saved_considx) {
4641                 if (intr->bnx_rx_check_considx == ret->bnx_rx_saved_considx &&
4642                     intr->bnx_tx_check_considx == txr->bnx_tx_saved_considx) {
4643                         if (!intr->bnx_intr_maylose) {
4644                                 intr->bnx_intr_maylose = TRUE;
4645                                 goto done;
4646                         }
4647                         if (bootverbose)
4648                                 if_printf(ifp, "lost interrupt\n");
4649                         intr->bnx_intr_func(intr->bnx_intr_arg);
4650                 }
4651         }
4652         intr->bnx_intr_maylose = FALSE;
4653         intr->bnx_rx_check_considx = ret->bnx_rx_saved_considx;
4654         intr->bnx_tx_check_considx = txr->bnx_tx_saved_considx;
4655
4656 done:
4657         callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL,
4658             intr->bnx_intr_check, intr);
4659         lwkt_serialize_exit(intr->bnx_intr_serialize);
4660 }
4661
4662 static void
4663 bnx_check_intr_tx(void *xintr)
4664 {
4665         struct bnx_intr_data *intr = xintr;
4666         struct bnx_tx_ring *txr;
4667         struct ifnet *ifp;
4668
4669         lwkt_serialize_enter(intr->bnx_intr_serialize);
4670
4671         KKASSERT(mycpuid == intr->bnx_intr_cpuid);
4672
4673         ifp = &intr->bnx_sc->arpcom.ac_if;
4674         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4675                 lwkt_serialize_exit(intr->bnx_intr_serialize);
4676                 return;
4677         }
4678
4679         txr = intr->bnx_txr;
4680
4681         if (*txr->bnx_tx_considx != txr->bnx_tx_saved_considx) {
4682                 if (intr->bnx_tx_check_considx == txr->bnx_tx_saved_considx) {
4683                         if (!intr->bnx_intr_maylose) {
4684                                 intr->bnx_intr_maylose = TRUE;
4685                                 goto done;
4686                         }
4687                         if (bootverbose)
4688                                 if_printf(ifp, "lost interrupt\n");
4689                         intr->bnx_intr_func(intr->bnx_intr_arg);
4690                 }
4691         }
4692         intr->bnx_intr_maylose = FALSE;
4693         intr->bnx_tx_check_considx = txr->bnx_tx_saved_considx;
4694
4695 done:
4696         callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL,
4697             intr->bnx_intr_check, intr);
4698         lwkt_serialize_exit(intr->bnx_intr_serialize);
4699 }
4700
4701 static void
4702 bnx_check_intr_rx(void *xintr)
4703 {
4704         struct bnx_intr_data *intr = xintr;
4705         struct bnx_rx_ret_ring *ret;
4706         struct ifnet *ifp;
4707
4708         lwkt_serialize_enter(intr->bnx_intr_serialize);
4709
4710         KKASSERT(mycpuid == intr->bnx_intr_cpuid);
4711
4712         ifp = &intr->bnx_sc->arpcom.ac_if;
4713         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4714                 lwkt_serialize_exit(intr->bnx_intr_serialize);
4715                 return;
4716         }
4717
4718         ret = intr->bnx_ret;
4719
4720         if (*ret->bnx_rx_considx != ret->bnx_rx_saved_considx) {
4721                 if (intr->bnx_rx_check_considx == ret->bnx_rx_saved_considx) {
4722                         if (!intr->bnx_intr_maylose) {
4723                                 intr->bnx_intr_maylose = TRUE;
4724                                 goto done;
4725                         }
4726                         if (bootverbose)
4727                                 if_printf(ifp, "lost interrupt\n");
4728                         intr->bnx_intr_func(intr->bnx_intr_arg);
4729                 }
4730         }
4731         intr->bnx_intr_maylose = FALSE;
4732         intr->bnx_rx_check_considx = ret->bnx_rx_saved_considx;
4733
4734 done:
4735         callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL,
4736             intr->bnx_intr_check, intr);
4737         lwkt_serialize_exit(intr->bnx_intr_serialize);
4738 }
4739
4740 static void
4741 bnx_enable_intr(struct bnx_softc *sc)
4742 {
4743         struct ifnet *ifp = &sc->arpcom.ac_if;
4744         int i;
4745
4746         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4747                 lwkt_serialize_handler_enable(
4748                     sc->bnx_intr_data[i].bnx_intr_serialize);
4749         }
4750
4751         /*
4752          * Enable interrupt.
4753          */
4754         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4755                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4756
4757                 bnx_writembx(sc, intr->bnx_intr_mbx,
4758                     (*intr->bnx_saved_status_tag) << 24);
4759                 /* XXX Linux driver */
4760                 bnx_writembx(sc, intr->bnx_intr_mbx,
4761                     (*intr->bnx_saved_status_tag) << 24);
4762         }
4763
4764         /*
4765          * Unmask the interrupt when we stop polling.
4766          */
4767         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4768             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4769
4770         /*
4771          * Trigger another interrupt, since above writing
4772          * to interrupt mailbox0 may acknowledge pending
4773          * interrupt.
4774          */
4775         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4776
4777         if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) {
4778                 if (bootverbose)
4779                         if_printf(ifp, "status tag bug workaround\n");
4780
4781                 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4782                         struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4783
4784                         if (intr->bnx_intr_check == NULL)
4785                                 continue;
4786                         intr->bnx_intr_maylose = FALSE;
4787                         intr->bnx_rx_check_considx = 0;
4788                         intr->bnx_tx_check_considx = 0;
4789                         callout_reset_bycpu(&intr->bnx_intr_timer,
4790                             BNX_INTR_CKINTVL, intr->bnx_intr_check, intr,
4791                             intr->bnx_intr_cpuid);
4792                 }
4793         }
4794 }
4795
4796 static void
4797 bnx_disable_intr(struct bnx_softc *sc)
4798 {
4799         int i;
4800
4801         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4802                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4803
4804                 callout_stop(&intr->bnx_intr_timer);
4805                 intr->bnx_intr_maylose = FALSE;
4806                 intr->bnx_rx_check_considx = 0;
4807                 intr->bnx_tx_check_considx = 0;
4808         }
4809
4810         /*
4811          * Mask the interrupt when we start polling.
4812          */
4813         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4814             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4815
4816         /*
4817          * Acknowledge possible asserted interrupt.
4818          */
4819         for (i = 0; i < BNX_INTR_MAX; ++i)
4820                 bnx_writembx(sc, sc->bnx_intr_data[i].bnx_intr_mbx, 1);
4821
4822         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4823                 lwkt_serialize_handler_disable(
4824                     sc->bnx_intr_data[i].bnx_intr_serialize);
4825         }
4826 }
4827
4828 static int
4829 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
4830 {
4831         uint32_t mac_addr;
4832         int ret = 1;
4833
4834         mac_addr = bnx_readmem_ind(sc, 0x0c14);
4835         if ((mac_addr >> 16) == 0x484b) {
4836                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4837                 ether_addr[1] = (uint8_t)mac_addr;
4838                 mac_addr = bnx_readmem_ind(sc, 0x0c18);
4839                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4840                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4841                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4842                 ether_addr[5] = (uint8_t)mac_addr;
4843                 ret = 0;
4844         }
4845         return ret;
4846 }
4847
4848 static int
4849 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
4850 {
4851         int mac_offset = BGE_EE_MAC_OFFSET;
4852
4853         if (BNX_IS_5717_PLUS(sc)) {
4854                 int f;
4855
4856                 f = pci_get_function(sc->bnx_dev);
4857                 if (f & 1)
4858                         mac_offset = BGE_EE_MAC_OFFSET_5717;
4859                 if (f > 1)
4860                         mac_offset += BGE_EE_MAC_OFFSET_5717_OFF;
4861         }
4862
4863         return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4864 }
4865
4866 static int
4867 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[])
4868 {
4869         if (sc->bnx_flags & BNX_FLAG_NO_EEPROM)
4870                 return 1;
4871
4872         return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4873                                ETHER_ADDR_LEN);
4874 }
4875
4876 static int
4877 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[])
4878 {
4879         static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = {
4880                 /* NOTE: Order is critical */
4881                 bnx_get_eaddr_mem,
4882                 bnx_get_eaddr_nvram,
4883                 bnx_get_eaddr_eeprom,
4884                 NULL
4885         };
4886         const bnx_eaddr_fcn_t *func;
4887
4888         for (func = bnx_eaddr_funcs; *func != NULL; ++func) {
4889                 if ((*func)(sc, eaddr) == 0)
4890                         break;
4891         }
4892         return (*func == NULL ? ENXIO : 0);
4893 }
4894
4895 /*
4896  * NOTE: 'm' is not freed upon failure
4897  */
4898 struct mbuf *
4899 bnx_defrag_shortdma(struct mbuf *m)
4900 {
4901         struct mbuf *n;
4902         int found;
4903
4904         /*
4905          * If device receive two back-to-back send BDs with less than
4906          * or equal to 8 total bytes then the device may hang.  The two
4907          * back-to-back send BDs must in the same frame for this failure
4908          * to occur.  Scan mbuf chains and see whether two back-to-back
4909          * send BDs are there.  If this is the case, allocate new mbuf
4910          * and copy the frame to workaround the silicon bug.
4911          */
4912         for (n = m, found = 0; n != NULL; n = n->m_next) {
4913                 if (n->m_len < 8) {
4914                         found++;
4915                         if (found > 1)
4916                                 break;
4917                         continue;
4918                 }
4919                 found = 0;
4920         }
4921
4922         if (found > 1)
4923                 n = m_defrag(m, MB_DONTWAIT);
4924         else
4925                 n = m;
4926         return n;
4927 }
4928
4929 static void
4930 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)
4931 {
4932         int i;
4933
4934         BNX_CLRBIT(sc, reg, bit);
4935         for (i = 0; i < BNX_TIMEOUT; i++) {
4936                 if ((CSR_READ_4(sc, reg) & bit) == 0)
4937                         return;
4938                 DELAY(100);
4939         }
4940 }
4941
4942 static void
4943 bnx_link_poll(struct bnx_softc *sc)
4944 {
4945         uint32_t status;
4946
4947         status = CSR_READ_4(sc, BGE_MAC_STS);
4948         if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) {
4949                 sc->bnx_link_evt = 0;
4950                 sc->bnx_link_upd(sc, status);
4951         }
4952 }
4953
4954 static void
4955 bnx_enable_msi(struct bnx_softc *sc, boolean_t is_msix)
4956 {
4957         uint32_t msi_mode;
4958
4959         msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4960         msi_mode |= BGE_MSIMODE_ENABLE;
4961         /*
4962          * NOTE:
4963          * 5718-PG105-R says that "one shot" mode does not work
4964          * if MSI is used, however, it obviously works.
4965          */
4966         msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4967         if (is_msix)
4968                 msi_mode |= BGE_MSIMODE_MSIX_MULTIMODE;
4969         else
4970                 msi_mode &= ~BGE_MSIMODE_MSIX_MULTIMODE;
4971         CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4972 }
4973
4974 static uint32_t
4975 bnx_dma_swap_options(struct bnx_softc *sc)
4976 {
4977         uint32_t dma_options;
4978
4979         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
4980             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
4981 #if BYTE_ORDER == BIG_ENDIAN
4982         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
4983 #endif
4984         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
4985             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
4986                 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
4987                     BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
4988                     BGE_MODECTL_HTX2B_ENABLE;
4989         }
4990         return dma_options;
4991 }
4992
4993 static int
4994 bnx_setup_tso(struct bnx_tx_ring *txr, struct mbuf **mp,
4995     uint16_t *mss0, uint16_t *flags0)
4996 {
4997         struct mbuf *m;
4998         struct ip *ip;
4999         struct tcphdr *th;
5000         int thoff, iphlen, hoff, hlen;
5001         uint16_t flags, mss;
5002
5003         m = *mp;
5004         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
5005
5006         hoff = m->m_pkthdr.csum_lhlen;
5007         iphlen = m->m_pkthdr.csum_iphlen;
5008         thoff = m->m_pkthdr.csum_thlen;
5009
5010         KASSERT(hoff > 0, ("invalid ether header len"));
5011         KASSERT(iphlen > 0, ("invalid ip header len"));
5012         KASSERT(thoff > 0, ("invalid tcp header len"));
5013
5014         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
5015                 m = m_pullup(m, hoff + iphlen + thoff);
5016                 if (m == NULL) {
5017                         *mp = NULL;
5018                         return ENOBUFS;
5019                 }
5020                 *mp = m;
5021         }
5022         ip = mtodoff(m, struct ip *, hoff);
5023         th = mtodoff(m, struct tcphdr *, hoff + iphlen);
5024
5025         mss = m->m_pkthdr.tso_segsz;
5026         flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
5027
5028         ip->ip_len = htons(mss + iphlen + thoff);
5029         th->th_sum = 0;
5030
5031         hlen = (iphlen + thoff) >> 2;
5032         mss |= ((hlen & 0x3) << 14);
5033         flags |= ((hlen & 0xf8) << 7) | ((hlen & 0x4) << 2);
5034
5035         *mss0 = mss;
5036         *flags0 = flags;
5037
5038         return 0;
5039 }
5040
5041 static int
5042 bnx_create_tx_ring(struct bnx_tx_ring *txr)
5043 {
5044         bus_size_t txmaxsz, txmaxsegsz;
5045         int i, error;
5046
5047         lwkt_serialize_init(&txr->bnx_tx_serialize);
5048
5049         /*
5050          * Create DMA tag and maps for TX mbufs.
5051          */
5052         if (txr->bnx_sc->bnx_flags & BNX_FLAG_TSO)
5053                 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
5054         else
5055                 txmaxsz = BNX_JUMBO_FRAMELEN;
5056         if (txr->bnx_sc->bnx_asicrev == BGE_ASICREV_BCM57766)
5057                 txmaxsegsz = MCLBYTES;
5058         else
5059                 txmaxsegsz = PAGE_SIZE;
5060         error = bus_dma_tag_create(txr->bnx_sc->bnx_cdata.bnx_parent_tag,
5061             1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
5062             txmaxsz, BNX_NSEG_NEW, txmaxsegsz,
5063             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
5064             &txr->bnx_tx_mtag);
5065         if (error) {
5066                 device_printf(txr->bnx_sc->bnx_dev,
5067                     "could not create TX mbuf DMA tag\n");
5068                 return error;
5069         }
5070
5071         for (i = 0; i < BGE_TX_RING_CNT; i++) {
5072                 error = bus_dmamap_create(txr->bnx_tx_mtag,
5073                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
5074                     &txr->bnx_tx_buf[i].bnx_tx_dmamap);
5075                 if (error) {
5076                         int j;
5077
5078                         for (j = 0; j < i; ++j) {
5079                                 bus_dmamap_destroy(txr->bnx_tx_mtag,
5080                                     txr->bnx_tx_buf[j].bnx_tx_dmamap);
5081                         }
5082                         bus_dma_tag_destroy(txr->bnx_tx_mtag);
5083                         txr->bnx_tx_mtag = NULL;
5084
5085                         device_printf(txr->bnx_sc->bnx_dev,
5086                             "could not create TX mbuf DMA map\n");
5087                         return error;
5088                 }
5089         }
5090
5091         /*
5092          * Create DMA stuffs for TX ring.
5093          */
5094         error = bnx_dma_block_alloc(txr->bnx_sc, BGE_TX_RING_SZ,
5095             &txr->bnx_tx_ring_tag,
5096             &txr->bnx_tx_ring_map,
5097             (void *)&txr->bnx_tx_ring,
5098             &txr->bnx_tx_ring_paddr);
5099         if (error) {
5100                 device_printf(txr->bnx_sc->bnx_dev,
5101                     "could not create TX ring\n");
5102                 return error;
5103         }
5104
5105         txr->bnx_tx_flags |= BNX_TX_FLAG_SHORTDMA;
5106         txr->bnx_tx_wreg = BNX_TX_WREG_NSEGS;
5107
5108         return 0;
5109 }
5110
5111 static void
5112 bnx_destroy_tx_ring(struct bnx_tx_ring *txr)
5113 {
5114         /* Destroy TX mbuf DMA stuffs. */
5115         if (txr->bnx_tx_mtag != NULL) {
5116                 int i;
5117
5118                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
5119                         KKASSERT(txr->bnx_tx_buf[i].bnx_tx_mbuf == NULL);
5120                         bus_dmamap_destroy(txr->bnx_tx_mtag,
5121                             txr->bnx_tx_buf[i].bnx_tx_dmamap);
5122                 }
5123                 bus_dma_tag_destroy(txr->bnx_tx_mtag);
5124         }
5125
5126         /* Destroy TX ring */
5127         bnx_dma_block_free(txr->bnx_tx_ring_tag,
5128             txr->bnx_tx_ring_map, txr->bnx_tx_ring);
5129 }
5130
5131 static int
5132 bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS)
5133 {
5134         struct bnx_softc *sc = (void *)arg1;
5135         struct ifnet *ifp = &sc->arpcom.ac_if;
5136         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
5137         int error, defrag, i;
5138
5139         if (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG)
5140                 defrag = 1;
5141         else
5142                 defrag = 0;
5143
5144         error = sysctl_handle_int(oidp, &defrag, 0, req);
5145         if (error || req->newptr == NULL)
5146                 return error;
5147
5148         ifnet_serialize_all(ifp);
5149         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
5150                 txr = &sc->bnx_tx_ring[i];
5151                 if (defrag)
5152                         txr->bnx_tx_flags |= BNX_TX_FLAG_FORCE_DEFRAG;
5153                 else
5154                         txr->bnx_tx_flags &= ~BNX_TX_FLAG_FORCE_DEFRAG;
5155         }
5156         ifnet_deserialize_all(ifp);
5157
5158         return 0;
5159 }
5160
5161 static int
5162 bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS)
5163 {
5164         struct bnx_softc *sc = (void *)arg1;
5165         struct ifnet *ifp = &sc->arpcom.ac_if;
5166         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
5167         int error, tx_wreg, i;
5168
5169         tx_wreg = txr->bnx_tx_wreg;
5170         error = sysctl_handle_int(oidp, &tx_wreg, 0, req);
5171         if (error || req->newptr == NULL)
5172                 return error;
5173
5174         ifnet_serialize_all(ifp);
5175         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
5176                 sc->bnx_tx_ring[i].bnx_tx_wreg = tx_wreg;
5177         ifnet_deserialize_all(ifp);
5178
5179         return 0;
5180 }
5181
5182 static int
5183 bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *ret)
5184 {
5185         int error;
5186
5187         lwkt_serialize_init(&ret->bnx_rx_ret_serialize);
5188
5189         /*
5190          * Create DMA stuffs for RX return ring.
5191          */
5192         error = bnx_dma_block_alloc(ret->bnx_sc,
5193             BGE_RX_RTN_RING_SZ(BNX_RETURN_RING_CNT),
5194             &ret->bnx_rx_ret_ring_tag,
5195             &ret->bnx_rx_ret_ring_map,
5196             (void *)&ret->bnx_rx_ret_ring,
5197             &ret->bnx_rx_ret_ring_paddr);
5198         if (error) {
5199                 device_printf(ret->bnx_sc->bnx_dev,
5200                     "could not create RX ret ring\n");
5201                 return error;
5202         }
5203
5204         /* Shadow standard ring's RX mbuf DMA tag */
5205         ret->bnx_rx_mtag = ret->bnx_std->bnx_rx_mtag;
5206
5207         /*
5208          * Create tmp DMA map for RX mbufs.
5209          */
5210         error = bus_dmamap_create(ret->bnx_rx_mtag, BUS_DMA_WAITOK,
5211             &ret->bnx_rx_tmpmap);
5212         if (error) {
5213                 device_printf(ret->bnx_sc->bnx_dev,
5214                     "could not create tmp RX mbuf DMA map\n");
5215                 ret->bnx_rx_mtag = NULL;
5216                 return error;
5217         }
5218         return 0;
5219 }
5220
5221 static void
5222 bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *ret)
5223 {
5224         /* Destroy tmp RX mbuf DMA map */
5225         if (ret->bnx_rx_mtag != NULL)
5226                 bus_dmamap_destroy(ret->bnx_rx_mtag, ret->bnx_rx_tmpmap);
5227
5228         /* Destroy RX return ring */
5229         bnx_dma_block_free(ret->bnx_rx_ret_ring_tag,
5230             ret->bnx_rx_ret_ring_map, ret->bnx_rx_ret_ring);
5231 }
5232
5233 static int
5234 bnx_alloc_intr(struct bnx_softc *sc)
5235 {
5236         struct bnx_intr_data *intr;
5237         u_int intr_flags;
5238         int error;
5239
5240         if (sc->bnx_intr_cnt > 1) {
5241                 error = bnx_alloc_msix(sc);
5242                 if (error)
5243                         return error;
5244                 KKASSERT(sc->bnx_intr_type == PCI_INTR_TYPE_MSIX);
5245                 return 0;
5246         }
5247
5248         KKASSERT(sc->bnx_intr_cnt == 1);
5249
5250         intr = &sc->bnx_intr_data[0];
5251         intr->bnx_ret = &sc->bnx_rx_ret_ring[0];
5252         intr->bnx_txr = &sc->bnx_tx_ring[0];
5253         intr->bnx_intr_serialize = &sc->bnx_main_serialize;
5254         intr->bnx_intr_check = bnx_check_intr_rxtx;
5255         intr->bnx_saved_status_tag = &intr->bnx_ret->bnx_saved_status_tag;
5256
5257         sc->bnx_intr_type = pci_alloc_1intr(sc->bnx_dev, bnx_msi_enable,
5258             &intr->bnx_intr_rid, &intr_flags);
5259
5260         intr->bnx_intr_res = bus_alloc_resource_any(sc->bnx_dev, SYS_RES_IRQ,
5261             &intr->bnx_intr_rid, intr_flags);
5262         if (intr->bnx_intr_res == NULL) {
5263                 device_printf(sc->bnx_dev, "could not alloc interrupt\n");
5264                 return ENXIO;
5265         }
5266
5267         if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI) {
5268                 bnx_enable_msi(sc, FALSE);
5269                 intr->bnx_intr_func = bnx_msi;
5270                 if (bootverbose)
5271                         device_printf(sc->bnx_dev, "oneshot MSI\n");
5272         } else {
5273                 intr->bnx_intr_func = bnx_intr_legacy;
5274         }
5275         intr->bnx_intr_arg = sc;
5276         intr->bnx_intr_cpuid = rman_get_cpuid(intr->bnx_intr_res);
5277
5278         intr->bnx_txr->bnx_tx_cpuid = intr->bnx_intr_cpuid;
5279
5280         return 0;
5281 }
5282
5283 static int
5284 bnx_setup_intr(struct bnx_softc *sc)
5285 {
5286         int error, i;
5287
5288         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
5289                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
5290
5291                 error = bus_setup_intr_descr(sc->bnx_dev, intr->bnx_intr_res,
5292                     INTR_MPSAFE, intr->bnx_intr_func, intr->bnx_intr_arg,
5293                     &intr->bnx_intr_hand, intr->bnx_intr_serialize,
5294                     intr->bnx_intr_desc);
5295                 if (error) {
5296                         device_printf(sc->bnx_dev,
5297                             "could not set up %dth intr\n", i);
5298                         bnx_teardown_intr(sc, i);
5299                         return error;
5300                 }
5301         }
5302         return 0;
5303 }
5304
5305 static void
5306 bnx_teardown_intr(struct bnx_softc *sc, int cnt)
5307 {
5308         int i;
5309
5310         for (i = 0; i < cnt; ++i) {
5311                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
5312
5313                 bus_teardown_intr(sc->bnx_dev, intr->bnx_intr_res,
5314                     intr->bnx_intr_hand);
5315         }
5316 }
5317
5318 static void
5319 bnx_free_intr(struct bnx_softc *sc)
5320 {
5321         if (sc->bnx_intr_type != PCI_INTR_TYPE_MSIX) {
5322                 struct bnx_intr_data *intr;
5323
5324                 KKASSERT(sc->bnx_intr_cnt <= 1);
5325                 intr = &sc->bnx_intr_data[0];
5326
5327                 if (intr->bnx_intr_res != NULL) {
5328                         bus_release_resource(sc->bnx_dev, SYS_RES_IRQ,
5329                             intr->bnx_intr_rid, intr->bnx_intr_res);
5330                 }
5331                 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI)
5332                         pci_release_msi(sc->bnx_dev);
5333         } else {
5334                 bnx_free_msix(sc, TRUE);
5335         }
5336 }
5337
5338 static void
5339 bnx_setup_serialize(struct bnx_softc *sc)
5340 {
5341         int i, j;
5342
5343         /*
5344          * Allocate serializer array
5345          */
5346
5347         /* Main + RX STD + TX + RX RET */
5348         sc->bnx_serialize_cnt = 1 + 1 + sc->bnx_tx_ringcnt + sc->bnx_rx_retcnt;
5349
5350         sc->bnx_serialize =
5351             kmalloc(sc->bnx_serialize_cnt * sizeof(struct lwkt_serialize *),
5352                 M_DEVBUF, M_WAITOK | M_ZERO);
5353
5354         /*
5355          * Setup serializers
5356          *
5357          * NOTE: Order is critical
5358          */
5359
5360         i = 0;
5361
5362         KKASSERT(i < sc->bnx_serialize_cnt);
5363         sc->bnx_serialize[i++] = &sc->bnx_main_serialize;
5364
5365         KKASSERT(i < sc->bnx_serialize_cnt);
5366         sc->bnx_serialize[i++] = &sc->bnx_rx_std_ring.bnx_rx_std_serialize;
5367
5368         for (j = 0; j < sc->bnx_rx_retcnt; ++j) {
5369                 KKASSERT(i < sc->bnx_serialize_cnt);
5370                 sc->bnx_serialize[i++] =
5371                     &sc->bnx_rx_ret_ring[j].bnx_rx_ret_serialize;
5372         }
5373
5374         for (j = 0; j < sc->bnx_tx_ringcnt; ++j) {
5375                 KKASSERT(i < sc->bnx_serialize_cnt);
5376                 sc->bnx_serialize[i++] =
5377                     &sc->bnx_tx_ring[j].bnx_tx_serialize;
5378         }
5379
5380         KKASSERT(i == sc->bnx_serialize_cnt);
5381 }
5382
5383 static void
5384 bnx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
5385 {
5386         struct bnx_softc *sc = ifp->if_softc;
5387
5388         ifnet_serialize_array_enter(sc->bnx_serialize,
5389             sc->bnx_serialize_cnt, slz);
5390 }
5391
5392 static void
5393 bnx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
5394 {
5395         struct bnx_softc *sc = ifp->if_softc;
5396
5397         ifnet_serialize_array_exit(sc->bnx_serialize,
5398             sc->bnx_serialize_cnt, slz);
5399 }
5400
5401 static int
5402 bnx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
5403 {
5404         struct bnx_softc *sc = ifp->if_softc;
5405
5406         return ifnet_serialize_array_try(sc->bnx_serialize,
5407             sc->bnx_serialize_cnt, slz);
5408 }
5409
5410 #ifdef INVARIANTS
5411
5412 static void
5413 bnx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
5414     boolean_t serialized)
5415 {
5416         struct bnx_softc *sc = ifp->if_softc;
5417
5418         ifnet_serialize_array_assert(sc->bnx_serialize, sc->bnx_serialize_cnt,
5419             slz, serialized);
5420 }
5421
5422 #endif  /* INVARIANTS */
5423
5424 #ifdef IFPOLL_ENABLE
5425
5426 static int
5427 bnx_sysctl_npoll_offset(SYSCTL_HANDLER_ARGS)
5428 {
5429         struct bnx_softc *sc = (void *)arg1;
5430         struct ifnet *ifp = &sc->arpcom.ac_if;
5431         int error, off;
5432
5433         off = sc->bnx_npoll_rxoff;
5434         error = sysctl_handle_int(oidp, &off, 0, req);
5435         if (error || req->newptr == NULL)
5436                 return error;
5437         if (off < 0)
5438                 return EINVAL;
5439
5440         ifnet_serialize_all(ifp);
5441         if (off >= ncpus2 || off % sc->bnx_rx_retcnt != 0) {
5442                 error = EINVAL;
5443         } else {
5444                 error = 0;
5445                 sc->bnx_npoll_txoff = off;
5446                 sc->bnx_npoll_rxoff = off;
5447         }
5448         ifnet_deserialize_all(ifp);
5449
5450         return error;
5451 }
5452
5453 static int
5454 bnx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
5455 {
5456         struct bnx_softc *sc = (void *)arg1;
5457         struct ifnet *ifp = &sc->arpcom.ac_if;
5458         int error, off;
5459
5460         off = sc->bnx_npoll_rxoff;
5461         error = sysctl_handle_int(oidp, &off, 0, req);
5462         if (error || req->newptr == NULL)
5463                 return error;
5464         if (off < 0)
5465                 return EINVAL;
5466
5467         ifnet_serialize_all(ifp);
5468         if (off >= ncpus2 || off % sc->bnx_rx_retcnt != 0) {
5469                 error = EINVAL;
5470         } else {
5471                 error = 0;
5472                 sc->bnx_npoll_rxoff = off;
5473         }
5474         ifnet_deserialize_all(ifp);
5475
5476         return error;
5477 }
5478
5479 static int
5480 bnx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
5481 {
5482         struct bnx_softc *sc = (void *)arg1;
5483         struct ifnet *ifp = &sc->arpcom.ac_if;
5484         int error, off;
5485
5486         off = sc->bnx_npoll_txoff;
5487         error = sysctl_handle_int(oidp, &off, 0, req);
5488         if (error || req->newptr == NULL)
5489                 return error;
5490         if (off < 0)
5491                 return EINVAL;
5492
5493         ifnet_serialize_all(ifp);
5494         if (off >= ncpus2) {
5495                 error = EINVAL;
5496         } else {
5497                 error = 0;
5498                 sc->bnx_npoll_txoff = off;
5499         }
5500         ifnet_deserialize_all(ifp);
5501
5502         return error;
5503 }
5504
5505 #endif  /* IFPOLL_ENABLE */
5506
5507 static void
5508 bnx_set_tick_cpuid(struct bnx_softc *sc, boolean_t polling)
5509 {
5510         if (polling)
5511                 sc->bnx_tick_cpuid = 0; /* XXX */
5512         else
5513                 sc->bnx_tick_cpuid = sc->bnx_intr_data[0].bnx_intr_cpuid;
5514 }
5515
5516 static void
5517 bnx_rx_std_refill_ithread(void *xstd)
5518 {
5519         struct bnx_rx_std_ring *std = xstd;
5520         struct globaldata *gd = mycpu;
5521
5522         crit_enter_gd(gd);
5523
5524         while (!std->bnx_rx_std_stop) {
5525                 if (std->bnx_rx_std_refill) {
5526                         lwkt_serialize_handler_call(
5527                             &std->bnx_rx_std_serialize,
5528                             bnx_rx_std_refill, std, NULL);
5529                 }
5530
5531                 crit_exit_gd(gd);
5532                 crit_enter_gd(gd);
5533
5534                 atomic_poll_release_int(&std->bnx_rx_std_running);
5535                 cpu_mfence();
5536
5537                 if (!std->bnx_rx_std_refill && !std->bnx_rx_std_stop) {
5538                         lwkt_deschedule_self(gd->gd_curthread);
5539                         lwkt_switch();
5540                 }
5541         }
5542
5543         crit_exit_gd(gd);
5544
5545         wakeup(std);
5546
5547         lwkt_exit();
5548 }
5549
5550 static void
5551 bnx_rx_std_refill(void *xstd, void *frame __unused)
5552 {
5553         struct bnx_rx_std_ring *std = xstd;
5554         int cnt, refill_mask;
5555
5556 again:
5557         cnt = 0;
5558
5559         cpu_lfence();
5560         refill_mask = std->bnx_rx_std_refill;
5561         atomic_clear_int(&std->bnx_rx_std_refill, refill_mask);
5562
5563         while (refill_mask) {
5564                 uint16_t check_idx = std->bnx_rx_std;
5565                 int ret_idx;
5566
5567                 ret_idx = bsfl(refill_mask);
5568                 for (;;) {
5569                         struct bnx_rx_buf *rb;
5570                         int refilled;
5571
5572                         BNX_INC(check_idx, BGE_STD_RX_RING_CNT);
5573                         rb = &std->bnx_rx_std_buf[check_idx];
5574                         refilled = rb->bnx_rx_refilled;
5575                         cpu_lfence();
5576                         if (refilled) {
5577                                 bnx_setup_rxdesc_std(std, check_idx);
5578                                 std->bnx_rx_std = check_idx;
5579                                 ++cnt;
5580                                 if (cnt >= 8) {
5581                                         atomic_subtract_int(
5582                                             &std->bnx_rx_std_used, cnt);
5583                                         bnx_writembx(std->bnx_sc,
5584                                             BGE_MBX_RX_STD_PROD_LO,
5585                                             std->bnx_rx_std);
5586                                         cnt = 0;
5587                                 }
5588                         } else {
5589                                 break;
5590                         }
5591                 }
5592                 refill_mask &= ~(1 << ret_idx);
5593         }
5594
5595         if (cnt) {
5596                 atomic_subtract_int(&std->bnx_rx_std_used, cnt);
5597                 bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO,
5598                     std->bnx_rx_std);
5599         }
5600
5601         if (std->bnx_rx_std_refill)
5602                 goto again;
5603
5604         atomic_poll_release_int(&std->bnx_rx_std_running);
5605         cpu_mfence();
5606
5607         if (std->bnx_rx_std_refill)
5608                 goto again;
5609 }
5610
5611 static int
5612 bnx_sysctl_std_refill(SYSCTL_HANDLER_ARGS)
5613 {
5614         struct bnx_softc *sc = (void *)arg1;
5615         struct ifnet *ifp = &sc->arpcom.ac_if;
5616         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
5617         int error, cntmax, i;
5618
5619         cntmax = ret->bnx_rx_cntmax;
5620         error = sysctl_handle_int(oidp, &cntmax, 0, req);
5621         if (error || req->newptr == NULL)
5622                 return error;
5623
5624         ifnet_serialize_all(ifp);
5625
5626         if ((cntmax * sc->bnx_rx_retcnt) >= BGE_STD_RX_RING_CNT / 2) {
5627                 error = EINVAL;
5628                 goto back;
5629         }
5630
5631         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
5632                 sc->bnx_rx_ret_ring[i].bnx_rx_cntmax = cntmax;
5633         error = 0;
5634
5635 back:
5636         ifnet_deserialize_all(ifp);
5637
5638         return error;
5639 }
5640
5641 static void
5642 bnx_init_rss(struct bnx_softc *sc)
5643 {
5644         uint8_t key[BGE_RSS_KEYREG_CNT * BGE_RSS_KEYREG_SIZE];
5645         int i, j, r;
5646
5647         KKASSERT(BNX_RSS_ENABLED(sc));
5648
5649         r = 0;
5650         for (j = 0; j < BGE_RSS_INDIR_TBL_CNT; ++j) {
5651                 uint32_t tbl = 0;
5652
5653                 for (i = 0; i < BGE_RSS_INDIR_TBLENT_CNT; ++i) {
5654                         uint32_t q;
5655
5656                         q = r % sc->bnx_rx_retcnt;
5657                         tbl |= q << (BGE_RSS_INDIR_TBLENT_SHIFT *
5658                             (BGE_RSS_INDIR_TBLENT_CNT - i - 1));
5659                         ++r;
5660                 }
5661
5662                 BNX_RSS_DPRINTF(sc, 1, "tbl%d %08x\n", j, tbl);
5663                 CSR_WRITE_4(sc, BGE_RSS_INDIR_TBL(j), tbl);
5664         }
5665
5666         toeplitz_get_key(key, sizeof(key));
5667         for (i = 0; i < BGE_RSS_KEYREG_CNT; ++i) {
5668                 uint32_t keyreg;
5669
5670                 keyreg = BGE_RSS_KEYREG_VAL(key, i);
5671
5672                 BNX_RSS_DPRINTF(sc, 1, "key%d %08x\n", i, keyreg);
5673                 CSR_WRITE_4(sc, BGE_RSS_KEYREG(i), keyreg);
5674         }
5675 }
5676
5677 static void
5678 bnx_setup_ring_cnt(struct bnx_softc *sc)
5679 {
5680         int msix_enable, i, msix_cnt, msix_cnt2, ring_max;
5681
5682         sc->bnx_tx_ringcnt = 1;
5683         sc->bnx_rx_retcnt = 1;
5684         sc->bnx_intr_cnt = 1;
5685
5686         msix_enable = device_getenv_int(sc->bnx_dev, "msix.enable",
5687             bnx_msix_enable);
5688         if (!msix_enable)
5689                 return;
5690
5691         if (ncpus2 == 1)
5692                 return;
5693
5694         msix_cnt = pci_msix_count(sc->bnx_dev);
5695         if (msix_cnt <= 1)
5696                 return;
5697
5698         i = 0;
5699         while ((1 << (i + 1)) <= msix_cnt)
5700                 ++i;
5701         msix_cnt2 = 1 << i;
5702
5703         /*
5704          * One MSI-X vector is dedicated to status or single TX queue,
5705          * so make sure that there are enough MSI-X vectors.
5706          */
5707         if (msix_cnt == msix_cnt2) {
5708                 /*
5709                  * XXX
5710                  * This probably will not happen; 57785/5718 families
5711                  * come with at least 5 MSI-X vectors.
5712                  */
5713                 msix_cnt2 >>= 1;
5714                 if (msix_cnt2 <= 1) {
5715                         device_printf(sc->bnx_dev,
5716                             "MSI-X count %d could not be used\n", msix_cnt);
5717                         return;
5718                 }
5719                 device_printf(sc->bnx_dev, "MSI-X count %d is power of 2\n",
5720                     msix_cnt);
5721         }
5722
5723         /*
5724          * Setup RX ring count
5725          */
5726         ring_max = BNX_RX_RING_MAX;
5727         if (ring_max > msix_cnt2)
5728                 ring_max = msix_cnt2;
5729         sc->bnx_rx_retcnt = device_getenv_int(sc->bnx_dev, "rx_rings",
5730             bnx_rx_rings);
5731         sc->bnx_rx_retcnt = if_ring_count2(sc->bnx_rx_retcnt, ring_max);
5732
5733         if (sc->bnx_rx_retcnt == 1)
5734                 return;
5735
5736         /*
5737          * We need one extra MSI-X vector for link status or
5738          * TX ring (if only one TX ring is enabled).
5739          */
5740         sc->bnx_intr_cnt = sc->bnx_rx_retcnt + 1;
5741
5742         /*
5743          * Setup TX ring count
5744          *
5745          * Currently only BCM5719 and BCM5720 support multiple TX rings
5746          * and the TX ring count must be less than the RX ring count.
5747          */
5748         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
5749             sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
5750                 ring_max = BNX_TX_RING_MAX;
5751                 if (ring_max > msix_cnt2)
5752                         ring_max = msix_cnt2;
5753                 if (ring_max > sc->bnx_rx_retcnt)
5754                         ring_max = sc->bnx_rx_retcnt;
5755                 sc->bnx_tx_ringcnt = device_getenv_int(sc->bnx_dev, "tx_rings",
5756                     bnx_tx_rings);
5757                 sc->bnx_tx_ringcnt = if_ring_count2(sc->bnx_tx_ringcnt,
5758                     ring_max);
5759         }
5760 }
5761
5762 static int
5763 bnx_alloc_msix(struct bnx_softc *sc)
5764 {
5765         struct bnx_intr_data *intr;
5766         boolean_t setup = FALSE;
5767         int error, i, offset, offset_def;
5768
5769         KKASSERT(sc->bnx_intr_cnt > 1);
5770         KKASSERT(sc->bnx_intr_cnt == sc->bnx_rx_retcnt + 1);
5771
5772         if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
5773                 /*
5774                  * Link status
5775                  */
5776                 intr = &sc->bnx_intr_data[0];
5777
5778                 intr->bnx_intr_serialize = &sc->bnx_main_serialize;
5779                 intr->bnx_saved_status_tag = &sc->bnx_saved_status_tag;
5780
5781                 intr->bnx_intr_func = bnx_msix_status;
5782                 intr->bnx_intr_arg = sc;
5783                 intr->bnx_intr_cpuid = 0; /* XXX */
5784
5785                 ksnprintf(intr->bnx_intr_desc0, sizeof(intr->bnx_intr_desc0),
5786                     "%s sts", device_get_nameunit(sc->bnx_dev));
5787                 intr->bnx_intr_desc = intr->bnx_intr_desc0;
5788
5789                 /*
5790                  * RX/TX rings
5791                  */
5792                 if (sc->bnx_rx_retcnt == ncpus2) {
5793                         offset = 0;
5794                 } else {
5795                         offset_def = (sc->bnx_rx_retcnt *
5796                             device_get_unit(sc->bnx_dev)) % ncpus2;
5797
5798                         offset = device_getenv_int(sc->bnx_dev,
5799                             "msix.offset", offset_def);
5800                         if (offset >= ncpus2 ||
5801                             offset % sc->bnx_rx_retcnt != 0) {
5802                                 device_printf(sc->bnx_dev,
5803                                     "invalid msix.offset %d, use %d\n",
5804                                     offset, offset_def);
5805                                 offset = offset_def;
5806                         }
5807                 }
5808
5809                 for (i = 1; i < sc->bnx_intr_cnt; ++i) {
5810                         int idx = i - 1;
5811
5812                         intr = &sc->bnx_intr_data[i];
5813
5814                         KKASSERT(idx < sc->bnx_rx_retcnt);
5815                         intr->bnx_ret = &sc->bnx_rx_ret_ring[idx];
5816                         if (idx < sc->bnx_tx_ringcnt) {
5817                                 intr->bnx_txr = &sc->bnx_tx_ring[idx];
5818                                 intr->bnx_ret->bnx_txr = intr->bnx_txr;
5819                         }
5820
5821                         intr->bnx_intr_serialize =
5822                             &intr->bnx_ret->bnx_rx_ret_serialize;
5823                         intr->bnx_saved_status_tag =
5824                             &intr->bnx_ret->bnx_saved_status_tag;
5825
5826                         intr->bnx_intr_arg = intr->bnx_ret;
5827                         KKASSERT(idx + offset < ncpus2);
5828                         intr->bnx_intr_cpuid = idx + offset;
5829
5830                         if (intr->bnx_txr == NULL) {
5831                                 intr->bnx_intr_check = bnx_check_intr_rx;
5832                                 intr->bnx_intr_func = bnx_msix_rx;
5833                                 ksnprintf(intr->bnx_intr_desc0,
5834                                     sizeof(intr->bnx_intr_desc0), "%s rx%d",
5835                                     device_get_nameunit(sc->bnx_dev), idx);
5836                         } else {
5837                                 intr->bnx_intr_check = bnx_check_intr_rxtx;
5838                                 intr->bnx_intr_func = bnx_msix_rxtx;
5839                                 ksnprintf(intr->bnx_intr_desc0,
5840                                     sizeof(intr->bnx_intr_desc0), "%s rxtx%d",
5841                                     device_get_nameunit(sc->bnx_dev), idx);
5842
5843                                 intr->bnx_txr->bnx_tx_cpuid =
5844                                     intr->bnx_intr_cpuid;
5845                         }
5846                         intr->bnx_intr_desc = intr->bnx_intr_desc0;
5847
5848                         intr->bnx_ret->bnx_msix_mbx = intr->bnx_intr_mbx;
5849                 }
5850         } else {
5851                 /*
5852                  * TX ring and link status
5853                  */
5854                 offset_def = device_get_unit(sc->bnx_dev) % ncpus2;
5855                 offset = device_getenv_int(sc->bnx_dev, "msix.txoff",
5856                     offset_def);
5857                 if (offset >= ncpus2) {
5858                         device_printf(sc->bnx_dev,
5859                             "invalid msix.txoff %d, use %d\n",
5860                             offset, offset_def);
5861                         offset = offset_def;
5862                 }
5863
5864                 intr = &sc->bnx_intr_data[0];
5865
5866                 intr->bnx_txr = &sc->bnx_tx_ring[0];
5867                 intr->bnx_intr_serialize = &sc->bnx_main_serialize;
5868                 intr->bnx_intr_check = bnx_check_intr_tx;
5869                 intr->bnx_saved_status_tag =
5870                     &intr->bnx_txr->bnx_saved_status_tag;
5871
5872                 intr->bnx_intr_func = bnx_msix_tx_status;
5873                 intr->bnx_intr_arg = intr->bnx_txr;
5874                 intr->bnx_intr_cpuid = offset;
5875
5876                 ksnprintf(intr->bnx_intr_desc0, sizeof(intr->bnx_intr_desc0),
5877                     "%s ststx", device_get_nameunit(sc->bnx_dev));
5878                 intr->bnx_intr_desc = intr->bnx_intr_desc0;
5879
5880                 intr->bnx_txr->bnx_tx_cpuid = intr->bnx_intr_cpuid;
5881
5882                 /*
5883                  * RX rings
5884                  */
5885                 if (sc->bnx_rx_retcnt == ncpus2) {
5886                         offset = 0;
5887                 } else {
5888                         offset_def = (sc->bnx_rx_retcnt *
5889                             device_get_unit(sc->bnx_dev)) % ncpus2;
5890
5891                         offset = device_getenv_int(sc->bnx_dev,
5892                             "msix.rxoff", offset_def);
5893                         if (offset >= ncpus2 ||
5894                             offset % sc->bnx_rx_retcnt != 0) {
5895                                 device_printf(sc->bnx_dev,
5896                                     "invalid msix.rxoff %d, use %d\n",
5897                                     offset, offset_def);
5898                                 offset = offset_def;
5899                         }
5900                 }
5901
5902                 for (i = 1; i < sc->bnx_intr_cnt; ++i) {
5903                         int idx = i - 1;
5904
5905                         intr = &sc->bnx_intr_data[i];
5906
5907                         KKASSERT(idx < sc->bnx_rx_retcnt);
5908                         intr->bnx_ret = &sc->bnx_rx_ret_ring[idx];
5909                         intr->bnx_intr_serialize =
5910                             &intr->bnx_ret->bnx_rx_ret_serialize;
5911                         intr->bnx_intr_check = bnx_check_intr_rx;
5912                         intr->bnx_saved_status_tag =
5913                             &intr->bnx_ret->bnx_saved_status_tag;
5914
5915                         intr->bnx_intr_func = bnx_msix_rx;
5916                         intr->bnx_intr_arg = intr->bnx_ret;
5917                         KKASSERT(idx + offset < ncpus2);
5918                         intr->bnx_intr_cpuid = idx + offset;
5919
5920                         ksnprintf(intr->bnx_intr_desc0,
5921                             sizeof(intr->bnx_intr_desc0), "%s rx%d",
5922                             device_get_nameunit(sc->bnx_dev), idx);
5923                         intr->bnx_intr_desc = intr->bnx_intr_desc0;
5924
5925                         intr->bnx_ret->bnx_msix_mbx = intr->bnx_intr_mbx;
5926                 }
5927         }
5928
5929         sc->bnx_msix_mem_rid = PCIR_BAR(4);
5930         sc->bnx_msix_mem_res = bus_alloc_resource_any(sc->bnx_dev,
5931             SYS_RES_MEMORY, &sc->bnx_msix_mem_rid, RF_ACTIVE);
5932         if (sc->bnx_msix_mem_res == NULL) {
5933                 device_printf(sc->bnx_dev, "could not alloc MSI-X table\n");
5934                 return ENXIO;
5935         }
5936
5937         bnx_enable_msi(sc, TRUE);
5938
5939         error = pci_setup_msix(sc->bnx_dev);
5940         if (error) {
5941                 device_printf(sc->bnx_dev, "could not setup MSI-X\n");
5942                 goto back;
5943         }
5944         setup = TRUE;
5945
5946         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
5947                 intr = &sc->bnx_intr_data[i];
5948
5949                 error = pci_alloc_msix_vector(sc->bnx_dev, i,
5950                     &intr->bnx_intr_rid, intr->bnx_intr_cpuid);
5951                 if (error) {
5952                         device_printf(sc->bnx_dev,
5953                             "could not alloc MSI-X %d on cpu%d\n",
5954                             i, intr->bnx_intr_cpuid);
5955                         goto back;
5956                 }
5957
5958                 intr->bnx_intr_res = bus_alloc_resource_any(sc->bnx_dev,
5959                     SYS_RES_IRQ, &intr->bnx_intr_rid, RF_ACTIVE);
5960                 if (intr->bnx_intr_res == NULL) {
5961                         device_printf(sc->bnx_dev,
5962                             "could not alloc MSI-X %d resource\n", i);
5963                         error = ENXIO;
5964                         goto back;
5965                 }
5966         }
5967
5968         pci_enable_msix(sc->bnx_dev);
5969         sc->bnx_intr_type = PCI_INTR_TYPE_MSIX;
5970 back:
5971         if (error)
5972                 bnx_free_msix(sc, setup);
5973         return error;
5974 }
5975
5976 static void
5977 bnx_free_msix(struct bnx_softc *sc, boolean_t setup)
5978 {
5979         int i;
5980
5981         KKASSERT(sc->bnx_intr_cnt > 1);
5982
5983         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
5984                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
5985
5986                 if (intr->bnx_intr_res != NULL) {
5987                         bus_release_resource(sc->bnx_dev, SYS_RES_IRQ,
5988                             intr->bnx_intr_rid, intr->bnx_intr_res);
5989                 }
5990                 if (intr->bnx_intr_rid >= 0) {
5991                         pci_release_msix_vector(sc->bnx_dev,
5992                             intr->bnx_intr_rid);
5993                 }
5994         }
5995         if (setup)
5996                 pci_teardown_msix(sc->bnx_dev);
5997 }
5998
5999 static void
6000 bnx_rx_std_refill_sched_ipi(void *xret)
6001 {
6002         struct bnx_rx_ret_ring *ret = xret;
6003         struct bnx_rx_std_ring *std = ret->bnx_std;
6004         struct globaldata *gd = mycpu;
6005
6006         crit_enter_gd(gd);
6007
6008         atomic_set_int(&std->bnx_rx_std_refill, ret->bnx_rx_mask);
6009         cpu_sfence();
6010
6011         KKASSERT(std->bnx_rx_std_ithread.td_gd == gd);
6012         lwkt_schedule(&std->bnx_rx_std_ithread);
6013
6014         crit_exit_gd(gd);
6015 }
6016
6017 static void
6018 bnx_rx_std_refill_stop(void *xstd)
6019 {
6020         struct bnx_rx_std_ring *std = xstd;
6021         struct globaldata *gd = mycpu;
6022
6023         crit_enter_gd(gd);
6024
6025         std->bnx_rx_std_stop = 1;
6026         cpu_sfence();
6027
6028         KKASSERT(std->bnx_rx_std_ithread.td_gd == gd);
6029         lwkt_schedule(&std->bnx_rx_std_ithread);
6030
6031         crit_exit_gd(gd);
6032 }
6033
6034 static void
6035 bnx_serialize_skipmain(struct bnx_softc *sc)
6036 {
6037         lwkt_serialize_array_enter(sc->bnx_serialize,
6038             sc->bnx_serialize_cnt, 1);
6039 }
6040
6041 static void
6042 bnx_deserialize_skipmain(struct bnx_softc *sc)
6043 {
6044         lwkt_serialize_array_exit(sc->bnx_serialize,
6045             sc->bnx_serialize_cnt, 1);
6046 }
6047
6048 static void
6049 bnx_rx_std_refill_sched(struct bnx_rx_ret_ring *ret,
6050     struct bnx_rx_std_ring *std)
6051 {
6052         struct globaldata *gd = mycpu;
6053
6054         ret->bnx_rx_cnt = 0;
6055         cpu_sfence();
6056
6057         crit_enter_gd(gd);
6058
6059         atomic_set_int(&std->bnx_rx_std_refill, ret->bnx_rx_mask);
6060         cpu_sfence();
6061         if (atomic_poll_acquire_int(&std->bnx_rx_std_running)) {
6062                 if (std->bnx_rx_std_ithread.td_gd == gd) {
6063                         lwkt_schedule(&std->bnx_rx_std_ithread);
6064                 } else {
6065                         lwkt_send_ipiq(
6066                             std->bnx_rx_std_ithread.td_gd,
6067                             bnx_rx_std_refill_sched_ipi, ret);
6068                 }
6069         }
6070
6071         crit_exit_gd(gd);
6072 }
6073
6074 static struct pktinfo *
6075 bnx_rss_info(struct pktinfo *pi, const struct bge_rx_bd *cur_rx)
6076 {
6077         /* Don't pick up IPv6 packet */
6078         if (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6)
6079                 return NULL;
6080
6081         /* Don't pick up IP packet w/o IP checksum */
6082         if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) == 0 ||
6083             (cur_rx->bge_error_flag & BGE_RXERRFLAG_IP_CSUM_NOK))
6084                 return NULL;
6085
6086         /* Don't pick up IP packet w/o TCP/UDP checksum */
6087         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) == 0)
6088                 return NULL;
6089
6090         /* May be IP fragment */
6091         if (cur_rx->bge_tcp_udp_csum != 0xffff)
6092                 return NULL;
6093
6094         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_IS_TCP)
6095                 pi->pi_l3proto = IPPROTO_TCP;
6096         else
6097                 pi->pi_l3proto = IPPROTO_UDP;
6098         pi->pi_netisr = NETISR_IP;
6099         pi->pi_flags = 0;
6100
6101         return pi;
6102 }