sys/dev/drm/i915/i915_drv.c

   1 /* i915_drv.c -- Intel i915 driver -*- linux-c -*-
   2  * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
   3  */
   4 /*-
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25  * OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *
  30  * $FreeBSD: src/sys/dev/drm2/i915/i915_drv.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  31  */
  32
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36 #include <drm/drm_pciids.h>
  37 #include "intel_drv.h"
  38
  39 /*               "Specify LVDS channel mode "
  40                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)" */
  41 int i915_lvds_channel_mode __read_mostly = 0;
  42 TUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode);
  43
  44 #define INTEL_VGA_DEVICE(id, info_) {           \
  45         .device = id,                           \
  46         .info = info_,                          \
  47 }
  48
  49 static const struct intel_device_info intel_i830_info = {
  50         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
  51         .has_overlay = 1, .overlay_needs_physical = 1,
  52 };
  53
  54 static const struct intel_device_info intel_845g_info = {
  55         .gen = 2,
  56         .has_overlay = 1, .overlay_needs_physical = 1,
  57 };
  58
  59 static const struct intel_device_info intel_i85x_info = {
  60         .gen = 2, .is_i85x = 1, .is_mobile = 1,
  61         .cursor_needs_physical = 1,
  62         .has_overlay = 1, .overlay_needs_physical = 1,
  63 };
  64
  65 static const struct intel_device_info intel_i865g_info = {
  66         .gen = 2,
  67         .has_overlay = 1, .overlay_needs_physical = 1,
  68 };
  69
  70 static const struct intel_device_info intel_i915g_info = {
  71         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
  72         .has_overlay = 1, .overlay_needs_physical = 1,
  73 };
  74 static const struct intel_device_info intel_i915gm_info = {
  75         .gen = 3, .is_mobile = 1,
  76         .cursor_needs_physical = 1,
  77         .has_overlay = 1, .overlay_needs_physical = 1,
  78         .supports_tv = 1,
  79 };
  80 static const struct intel_device_info intel_i945g_info = {
  81         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
  82         .has_overlay = 1, .overlay_needs_physical = 1,
  83 };
  84 static const struct intel_device_info intel_i945gm_info = {
  85         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
  86         .has_hotplug = 1, .cursor_needs_physical = 1,
  87         .has_overlay = 1, .overlay_needs_physical = 1,
  88         .supports_tv = 1,
  89 };
  90
  91 static const struct intel_device_info intel_i965g_info = {
  92         .gen = 4, .is_broadwater = 1,
  93         .has_hotplug = 1,
  94         .has_overlay = 1,
  95 };
  96
  97 static const struct intel_device_info intel_i965gm_info = {
  98         .gen = 4, .is_crestline = 1,
  99         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 100         .has_overlay = 1,
 101         .supports_tv = 1,
 102 };
 103
 104 static const struct intel_device_info intel_g33_info = {
 105         .gen = 3, .is_g33 = 1,
 106         .need_gfx_hws = 1, .has_hotplug = 1,
 107         .has_overlay = 1,
 108 };
 109
 110 static const struct intel_device_info intel_g45_info = {
 111         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 112         .has_pipe_cxsr = 1, .has_hotplug = 1,
 113         .has_bsd_ring = 1,
 114 };
 115
 116 static const struct intel_device_info intel_gm45_info = {
 117         .gen = 4, .is_g4x = 1,
 118         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 119         .has_pipe_cxsr = 1, .has_hotplug = 1,
 120         .supports_tv = 1,
 121         .has_bsd_ring = 1,
 122 };
 123
 124 static const struct intel_device_info intel_pineview_info = {
 125         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 126         .need_gfx_hws = 1, .has_hotplug = 1,
 127         .has_overlay = 1,
 128 };
 129
 130 static const struct intel_device_info intel_ironlake_d_info = {
 131         .gen = 5,
 132         .need_gfx_hws = 1, .has_hotplug = 1,
 133         .has_bsd_ring = 1,
 134 };
 135
 136 static const struct intel_device_info intel_ironlake_m_info = {
 137         .gen = 5, .is_mobile = 1,
 138         .need_gfx_hws = 1, .has_hotplug = 1,
 139         .has_fbc = 0, /* disabled due to buggy hardware */
 140         .has_bsd_ring = 1,
 141 };
 142
 143 static const struct intel_device_info intel_sandybridge_d_info = {
 144         .gen = 6,
 145         .need_gfx_hws = 1, .has_hotplug = 1,
 146         .has_bsd_ring = 1,
 147         .has_blt_ring = 1,
 148         .has_llc = 1,
 149         .has_force_wake = 1,
 150 };
 151
 152 static const struct intel_device_info intel_sandybridge_m_info = {
 153         .gen = 6, .is_mobile = 1,
 154         .need_gfx_hws = 1, .has_hotplug = 1,
 155         .has_fbc = 1,
 156         .has_bsd_ring = 1,
 157         .has_blt_ring = 1,
 158         .has_llc = 1,
 159         .has_force_wake = 1,
 160 };
 161
 162 static const struct intel_device_info intel_ivybridge_d_info = {
 163         .is_ivybridge = 1, .gen = 7,
 164         .need_gfx_hws = 1, .has_hotplug = 1,
 165         .has_bsd_ring = 1,
 166         .has_blt_ring = 1,
 167         .has_llc = 1,
 168         .has_force_wake = 1,
 169 };
 170
 171 static const struct intel_device_info intel_ivybridge_m_info = {
 172         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 173         .need_gfx_hws = 1, .has_hotplug = 1,
 174         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 175         .has_bsd_ring = 1,
 176         .has_blt_ring = 1,
 177         .has_llc = 1,
 178         .has_force_wake = 1,
 179 };
 180
 181 static const struct intel_device_info intel_valleyview_m_info = {
 182         .gen = 7, .is_mobile = 1,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_fbc = 0,
 185         .has_bsd_ring = 1,
 186         .has_blt_ring = 1,
 187         .is_valleyview = 1,
 188 };
 189
 190 static const struct intel_device_info intel_valleyview_d_info = {
 191         .gen = 7,
 192         .need_gfx_hws = 1, .has_hotplug = 1,
 193         .has_fbc = 0,
 194         .has_bsd_ring = 1,
 195         .has_blt_ring = 1,
 196         .is_valleyview = 1,
 197 };
 198
 199 static const struct intel_device_info intel_haswell_d_info = {
 200         .is_haswell = 1, .gen = 7,
 201         .need_gfx_hws = 1, .has_hotplug = 1,
 202         .has_bsd_ring = 1,
 203         .has_blt_ring = 1,
 204         .has_llc = 1,
 205         .has_force_wake = 1,
 206 };
 207
 208 static const struct intel_device_info intel_haswell_m_info = {
 209         .is_haswell = 1, .gen = 7, .is_mobile = 1,
 210         .need_gfx_hws = 1, .has_hotplug = 1,
 211         .has_bsd_ring = 1,
 212         .has_blt_ring = 1,
 213         .has_llc = 1,
 214         .has_force_wake = 1,
 215 };
 216
 217 static const struct intel_gfx_device_id {
 218         int device;
 219         const struct intel_device_info *info;
 220 } pciidlist[] = {               /* aka */
 221         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 222         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 223         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 224         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 225         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 226         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 227         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 228         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 229         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 230         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 231         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 232         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 233         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 234         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 235         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 236         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 237         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 238         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 239         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 240         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 241         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 242         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 243         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 244         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 245         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 246         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 247         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 248         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 249         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 250         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 251         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 252         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 253         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 254         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 255         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 256         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 257         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 258         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 259         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 260         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 261         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 262         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 263         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 264         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 265         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 266         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 267         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
 268         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 269         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 270         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
 271         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 272         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 273         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
 274         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
 275         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
 276         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
 277         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
 278         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
 279         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
 280         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
 281         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
 282         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
 283         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
 284         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
 285         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
 286         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
 287         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
 288         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
 289         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
 290         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
 291         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
 292         INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
 293         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
 294         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
 295         INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
 296         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
 297         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
 298         INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
 299         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
 300         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
 301         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 302         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 303         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 304         {0, 0}
 305 };
 306
 307 #define PCI_VENDOR_INTEL        0x8086
 308
 309 void intel_detect_pch(struct drm_device *dev)
 310 {
 311         struct drm_i915_private *dev_priv = dev->dev_private;
 312         device_t pch;
 313
 314         /*
 315          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 316          * make graphics device passthrough work easy for VMM, that only
 317          * need to expose ISA bridge to let driver know the real hardware
 318          * underneath. This is a requirement from virtualization team.
 319          */
 320         pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
 321         if (pch) {
 322                 if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
 323                         unsigned short id;
 324                         id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
 325                         dev_priv->pch_id = id;
 326
 327                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 328                                 dev_priv->pch_type = PCH_IBX;
 329                                 dev_priv->num_pch_pll = 2;
 330                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 331                                 WARN_ON(!IS_GEN5(dev));
 332                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 333                                 dev_priv->pch_type = PCH_CPT;
 334                                 dev_priv->num_pch_pll = 2;
 335                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 336                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 337                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 338                                 /* PantherPoint is CPT compatible */
 339                                 dev_priv->pch_type = PCH_CPT;
 340                                 dev_priv->num_pch_pll = 2;
 341                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 342                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 343                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 344                                 dev_priv->pch_type = PCH_LPT;
 345                                 dev_priv->num_pch_pll = 0;
 346                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 347                                 WARN_ON(!IS_HASWELL(dev));
 348                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 349                                 dev_priv->pch_type = PCH_LPT;
 350                                 dev_priv->num_pch_pll = 0;
 351                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 352                                 WARN_ON(!IS_HASWELL(dev));
 353                         }
 354                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 355                 }
 356 #if 0
 357                 pci_dev_put(pch);
 358 #endif
 359         }
 360 }
 361
 362 bool i915_semaphore_is_enabled(struct drm_device *dev)
 363 {
 364         if (INTEL_INFO(dev)->gen < 6)
 365                 return 0;
 366
 367         if (i915_semaphores >= 0)
 368                 return i915_semaphores;
 369
 370 #ifdef CONFIG_INTEL_IOMMU
 371         /* Enable semaphores on SNB when IO remapping is off */
 372         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 373                 return false;
 374 #endif
 375
 376         return 1;
 377 }
 378
 379 static int i915_drm_freeze(struct drm_device *dev)
 380 {
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382
 383         drm_kms_helper_poll_disable(dev);
 384
 385 #if 0
 386         pci_save_state(dev->pdev);
 387 #endif
 388
 389         /* If KMS is active, we do the leavevt stuff here */
 390         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 391                 int error = i915_gem_idle(dev);
 392                 if (error) {
 393                         device_printf(dev->dev,
 394                                 "GEM idle failed, resume might fail");
 395                         return error;
 396                 }
 397                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 398
 399 #if 0
 400                 intel_modeset_disable(dev);
 401 #endif
 402
 403                 drm_irq_uninstall(dev);
 404         }
 405
 406         i915_save_state(dev);
 407
 408         intel_opregion_fini(dev);
 409
 410         /* Modeset on resume, not lid events */
 411         dev_priv->modeset_on_lid = 0;
 412
 413         return 0;
 414 }
 415
 416 static int
 417 i915_suspend(device_t kdev)
 418 {
 419         struct drm_device *dev;
 420         int error;
 421
 422         dev = device_get_softc(kdev);
 423         if (dev == NULL || dev->dev_private == NULL) {
 424                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 425                 return -ENODEV;
 426         }
 427
 428         DRM_DEBUG_KMS("starting suspend\n");
 429         error = i915_drm_freeze(dev);
 430         if (error)
 431                 return (error);
 432
 433         error = bus_generic_suspend(kdev);
 434         DRM_DEBUG_KMS("finished suspend %d\n", error);
 435         return (error);
 436 }
 437
 438 static int i915_drm_thaw(struct drm_device *dev)
 439 {
 440         struct drm_i915_private *dev_priv = dev->dev_private;
 441         int error = 0;
 442
 443         intel_gt_reset(dev);
 444
 445         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 446                 DRM_LOCK(dev);
 447                 i915_gem_restore_gtt_mappings(dev);
 448                 DRM_UNLOCK(dev);
 449         }
 450
 451         i915_restore_state(dev);
 452         intel_opregion_setup(dev);
 453
 454         /* KMS EnterVT equivalent */
 455         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 456                 intel_init_pch_refclk(dev);
 457
 458                 DRM_LOCK(dev);
 459                 dev_priv->mm.suspended = 0;
 460
 461                 error = i915_gem_init_hw(dev);
 462                 DRM_UNLOCK(dev);
 463
 464                 intel_modeset_init_hw(dev);
 465                 intel_modeset_setup_hw_state(dev, false);
 466                 drm_irq_install(dev);
 467         }
 468
 469         intel_opregion_init(dev);
 470
 471         dev_priv->modeset_on_lid = 0;
 472
 473 #if 0
 474         console_lock();
 475         intel_fbdev_set_suspend(dev, 0);
 476         console_unlock();
 477 #endif
 478         return error;
 479 }
 480
 481 static int
 482 i915_resume(device_t kdev)
 483 {
 484         struct drm_device *dev;
 485         int ret;
 486
 487         dev = device_get_softc(kdev);
 488         DRM_DEBUG_KMS("starting resume\n");
 489 #if 0
 490         if (pci_enable_device(dev->pdev))
 491                 return -EIO;
 492
 493         pci_set_master(dev->pdev);
 494 #endif
 495
 496         ret = -i915_drm_thaw(dev);
 497         if (ret != 0)
 498                 return (ret);
 499
 500         drm_kms_helper_poll_enable(dev);
 501         ret = bus_generic_resume(kdev);
 502         DRM_DEBUG_KMS("finished resume %d\n", ret);
 503         return (ret);
 504 }
 505
 506 /* XXX Hack for the old *BSD drm code base
 507  * The device id field is set at probe time */
 508 static drm_pci_id_list_t i915_attach_list[] = {
 509         {0x8086, 0, 0, "Intel i915 GPU"},
 510         {0, 0, 0, NULL}
 511 };
 512
 513 static int
 514 i915_probe(device_t kdev)
 515 {
 516         int device, i = 0;
 517
 518         if (pci_get_class(kdev) != PCIC_DISPLAY)
 519                 return ENXIO;
 520
 521         if (pci_get_vendor(kdev) != PCI_VENDOR_INTEL)
 522                 return ENXIO;
 523
 524         device = pci_get_device(kdev);
 525
 526         for (i = 0; pciidlist[i].device != 0; i++) {
 527                 if (pciidlist[i].device == device) {
 528                         i915_attach_list[0].device = device;
 529                         return 0;
 530                 }
 531         }
 532
 533         return ENXIO;
 534 }
 535
 536 int i915_modeset;
 537
 538 static int
 539 i915_attach(device_t kdev)
 540 {
 541         struct drm_device *dev;
 542
 543         dev = device_get_softc(kdev);
 544         if (i915_modeset == 1)
 545                 i915_driver_info.driver_features |= DRIVER_MODESET;
 546         dev->driver = &i915_driver_info;
 547         return (drm_attach(kdev, i915_attach_list));
 548 }
 549
 550 const struct intel_device_info *
 551 i915_get_device_id(int device)
 552 {
 553         const struct intel_gfx_device_id *did;
 554
 555         for (did = &pciidlist[0]; did->device != 0; did++) {
 556                 if (did->device != device)
 557                         continue;
 558                 return (did->info);
 559         }
 560         return (NULL);
 561 }
 562
 563 static device_method_t i915_methods[] = {
 564         /* Device interface */
 565         DEVMETHOD(device_probe,         i915_probe),
 566         DEVMETHOD(device_attach,        i915_attach),
 567         DEVMETHOD(device_suspend,       i915_suspend),
 568         DEVMETHOD(device_resume,        i915_resume),
 569         DEVMETHOD(device_detach,        drm_detach),
 570         DEVMETHOD_END
 571 };
 572
 573 static driver_t i915_driver = {
 574         "drm",
 575         i915_methods,
 576         sizeof(struct drm_device)
 577 };
 578
 579 extern devclass_t drm_devclass;
 580 DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
 581     SI_ORDER_ANY);
 582 MODULE_DEPEND(i915kms, drm, 1, 1, 1);
 583 MODULE_DEPEND(i915kms, agp, 1, 1, 1);
 584 MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
 585 MODULE_DEPEND(i915kms, iic, 1, 1, 1);
 586 MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
 587
 588 int intel_iommu_enabled = 0;
 589 TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
 590
 591 int i915_semaphores = -1;
 592 TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
 593 static int i915_try_reset = 1;
 594 TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
 595 unsigned int i915_lvds_downclock = 0;
 596 TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
 597 int i915_vbt_sdvo_panel_type = -1;
 598 TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
 599 unsigned int i915_powersave = 1;
 600 TUNABLE_INT("drm.i915.powersave", &i915_powersave);
 601 int i915_enable_fbc = 0;
 602 TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
 603 int i915_enable_rc6 = 0;
 604 TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
 605 int i915_panel_use_ssc = -1;
 606 TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
 607 int i915_panel_ignore_lid = 0;
 608 TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
 609 int i915_modeset = 1;
 610 TUNABLE_INT("drm.i915.modeset", &i915_modeset);
 611 int i915_enable_ppgtt = -1;
 612 TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
 613 int i915_enable_hangcheck = 1;
 614 TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
 615
 616 static int i8xx_do_reset(struct drm_device *dev)
 617 {
 618         struct drm_i915_private *dev_priv = dev->dev_private;
 619
 620         if (IS_I85X(dev))
 621                 return -ENODEV;
 622
 623         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 624         POSTING_READ(D_STATE);
 625
 626         if (IS_I830(dev) || IS_845G(dev)) {
 627                 I915_WRITE(DEBUG_RESET_I830,
 628                            DEBUG_RESET_DISPLAY |
 629                            DEBUG_RESET_RENDER |
 630                            DEBUG_RESET_FULL);
 631                 POSTING_READ(DEBUG_RESET_I830);
 632                 msleep(1);
 633
 634                 I915_WRITE(DEBUG_RESET_I830, 0);
 635                 POSTING_READ(DEBUG_RESET_I830);
 636         }
 637
 638         msleep(1);
 639
 640         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 641         POSTING_READ(D_STATE);
 642
 643         return 0;
 644 }
 645
 646 static int i965_reset_complete(struct drm_device *dev)
 647 {
 648         u8 gdrst;
 649         gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
 650         return (gdrst & 0x1);
 651 }
 652
 653 static int i965_do_reset(struct drm_device *dev)
 654 {
 655         int ret;
 656         u8 gdrst;
 657
 658         /*
 659          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 660          * well as the reset bit (GR/bit 0).  Setting the GR bit
 661          * triggers the reset; when done, the hardware will clear it.
 662          */
 663         gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
 664         pci_write_config(dev->dev, I965_GDRST,
 665                               gdrst | GRDOM_RENDER |
 666                               GRDOM_RESET_ENABLE, 1);
 667         ret =  wait_for(i965_reset_complete(dev), 500);
 668         if (ret)
 669                 return ret;
 670
 671         /* We can't reset render&media without also resetting display ... */
 672         gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
 673         pci_write_config(dev->dev, I965_GDRST,
 674                               gdrst | GRDOM_MEDIA |
 675                               GRDOM_RESET_ENABLE, 1);
 676
 677         return wait_for(i965_reset_complete(dev), 500);
 678 }
 679
 680 static int ironlake_do_reset(struct drm_device *dev)
 681 {
 682         struct drm_i915_private *dev_priv = dev->dev_private;
 683         u32 gdrst;
 684         int ret;
 685
 686         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 687         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 688                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 689         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 690         if (ret)
 691                 return ret;
 692
 693         /* We can't reset render&media without also resetting display ... */
 694         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 695         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 696                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 697         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 698 }
 699
 700 static int gen6_do_reset(struct drm_device *dev)
 701 {
 702         struct drm_i915_private *dev_priv = dev->dev_private;
 703         int ret;
 704
 705         dev_priv = dev->dev_private;
 706
 707         /* Hold gt_lock across reset to prevent any register access
 708          * with forcewake not set correctly
 709          */
 710         lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
 711
 712         /* Reset the chip */
 713
 714         /* GEN6_GDRST is not in the gt power well, no need to check
 715          * for fifo space for the write or forcewake the chip for
 716          * the read
 717          */
 718         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 719
 720         /* Spin waiting for the device to ack the reset request */
 721         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 722
 723         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 724         if (dev_priv->forcewake_count)
 725                 dev_priv->gt.force_wake_get(dev_priv);
 726         else
 727                 dev_priv->gt.force_wake_put(dev_priv);
 728
 729         /* Restore fifo count */
 730         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 731
 732         lockmgr(&dev_priv->gt_lock, LK_RELEASE);
 733         return ret;
 734 }
 735
 736 int intel_gpu_reset(struct drm_device *dev)
 737 {
 738         struct drm_i915_private *dev_priv = dev->dev_private;
 739         int ret = -ENODEV;
 740
 741         switch (INTEL_INFO(dev)->gen) {
 742         case 7:
 743         case 6:
 744                 ret = gen6_do_reset(dev);
 745                 break;
 746         case 5:
 747                 ret = ironlake_do_reset(dev);
 748                 break;
 749         case 4:
 750                 ret = i965_do_reset(dev);
 751                 break;
 752         case 2:
 753                 ret = i8xx_do_reset(dev);
 754                 break;
 755         }
 756
 757         /* Also reset the gpu hangman. */
 758         if (dev_priv->stop_rings) {
 759                 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
 760                 dev_priv->stop_rings = 0;
 761                 if (ret == -ENODEV) {
 762                         DRM_ERROR("Reset not implemented, but ignoring "
 763                                   "error for simulated gpu hangs\n");
 764                         ret = 0;
 765                 }
 766         }
 767
 768         return ret;
 769 }
 770
 771 /**
 772  * i915_reset - reset chip after a hang
 773  * @dev: drm device to reset
 774  *
 775  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 776  * reset or otherwise an error code.
 777  *
 778  * Procedure is fairly simple:
 779  *   - reset the chip using the reset reg
 780  *   - re-init context state
 781  *   - re-init hardware status page
 782  *   - re-init ring buffer
 783  *   - re-init interrupt state
 784  *   - re-init display
 785  */
 786 int i915_reset(struct drm_device *dev)
 787 {
 788         drm_i915_private_t *dev_priv = dev->dev_private;
 789         int ret;
 790
 791         if (!i915_try_reset)
 792                 return 0;
 793
 794         DRM_LOCK(dev);
 795
 796         i915_gem_reset(dev);
 797
 798         ret = -ENODEV;
 799         if (time_uptime - dev_priv->last_gpu_reset < 5)
 800                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 801         else
 802                 ret = intel_gpu_reset(dev);
 803
 804         dev_priv->last_gpu_reset = time_uptime;
 805         if (ret) {
 806                 DRM_ERROR("Failed to reset chip.\n");
 807                 DRM_UNLOCK(dev);
 808                 return ret;
 809         }
 810
 811         /* Ok, now get things going again... */
 812
 813         /*
 814          * Everything depends on having the GTT running, so we need to start
 815          * there.  Fortunately we don't need to do this unless we reset the
 816          * chip at a PCI level.
 817          *
 818          * Next we need to restore the context, but we don't use those
 819          * yet either...
 820          *
 821          * Ring buffer needs to be re-initialized in the KMS case, or if X
 822          * was running at the time of the reset (i.e. we weren't VT
 823          * switched away).
 824          */
 825         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 826                         !dev_priv->mm.suspended) {
 827                 struct intel_ring_buffer *ring;
 828                 int i;
 829
 830                 dev_priv->mm.suspended = 0;
 831
 832                 i915_gem_init_swizzling(dev);
 833
 834                 for_each_ring(ring, dev_priv, i)
 835                         ring->init(ring);
 836
 837 #if 0   /* XXX: HW context support */
 838                 i915_gem_context_init(dev);
 839 #endif
 840                 i915_gem_init_ppgtt(dev);
 841
 842                 /*
 843                  * It would make sense to re-init all the other hw state, at
 844                  * least the rps/rc6/emon init done within modeset_init_hw. For
 845                  * some unknown reason, this blows up my ilk, so don't.
 846                  */
 847
 848                 DRM_UNLOCK(dev);
 849
 850                 drm_irq_uninstall(dev);
 851                 drm_irq_install(dev);
 852         } else {
 853                 DRM_UNLOCK(dev);
 854         }
 855
 856         return 0;
 857 }
 858
 859 /* We give fast paths for the really cool registers */
 860 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 861         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
 862          ((reg) < 0x40000) &&            \
 863          ((reg) != FORCEWAKE))
 864
 865 static bool IS_DISPLAYREG(u32 reg)
 866 {
 867         /*
 868          * This should make it easier to transition modules over to the
 869          * new register block scheme, since we can do it incrementally.
 870          */
 871         if (reg >= VLV_DISPLAY_BASE)
 872                 return false;
 873
 874         if (reg >= RENDER_RING_BASE &&
 875             reg < RENDER_RING_BASE + 0xff)
 876                 return false;
 877         if (reg >= GEN6_BSD_RING_BASE &&
 878             reg < GEN6_BSD_RING_BASE + 0xff)
 879                 return false;
 880         if (reg >= BLT_RING_BASE &&
 881             reg < BLT_RING_BASE + 0xff)
 882                 return false;
 883
 884         if (reg == PGTBL_ER)
 885                 return false;
 886
 887         if (reg >= IPEIR_I965 &&
 888             reg < HWSTAM)
 889                 return false;
 890
 891         if (reg == MI_MODE)
 892                 return false;
 893
 894         if (reg == GFX_MODE_GEN7)
 895                 return false;
 896
 897         if (reg == RENDER_HWS_PGA_GEN7 ||
 898             reg == BSD_HWS_PGA_GEN7 ||
 899             reg == BLT_HWS_PGA_GEN7)
 900                 return false;
 901
 902         if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
 903             reg == GEN6_BSD_RNCID)
 904                 return false;
 905
 906         if (reg == GEN6_BLITTER_ECOSKPD)
 907                 return false;
 908
 909         if (reg >= 0x4000c &&
 910             reg <= 0x4002c)
 911                 return false;
 912
 913         if (reg >= 0x4f000 &&
 914             reg <= 0x4f08f)
 915                 return false;
 916
 917         if (reg >= 0x4f100 &&
 918             reg <= 0x4f11f)
 919                 return false;
 920
 921         if (reg >= VLV_MASTER_IER &&
 922             reg <= GEN6_PMIER)
 923                 return false;
 924
 925         if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
 926             reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
 927                 return false;
 928
 929         if (reg >= VLV_IIR_RW &&
 930             reg <= VLV_ISR)
 931                 return false;
 932
 933         if (reg == FORCEWAKE_VLV ||
 934             reg == FORCEWAKE_ACK_VLV)
 935                 return false;
 936
 937         if (reg == GEN6_GDRST)
 938                 return false;
 939
 940         switch (reg) {
 941         case _3D_CHICKEN3:
 942         case IVB_CHICKEN3:
 943         case GEN7_COMMON_SLICE_CHICKEN1:
 944         case GEN7_L3CNTLREG1:
 945         case GEN7_L3_CHICKEN_MODE_REGISTER:
 946         case GEN7_ROW_CHICKEN2:
 947         case GEN7_L3SQCREG4:
 948         case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
 949         case GEN7_HALF_SLICE_CHICKEN1:
 950         case GEN6_MBCTL:
 951         case GEN6_UCGCTL2:
 952                 return false;
 953         default:
 954                 break;
 955         }
 956
 957         return true;
 958 }
 959
 960 static void
 961 ilk_dummy_write(struct drm_i915_private *dev_priv)
 962 {
 963         /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
 964          * chip from rc6 before touching it for real. MI_MODE is masked, hence
 965          * harmless to write 0 into. */
 966         I915_WRITE_NOTRACE(MI_MODE, 0);
 967 }
 968
 969 #define __i915_read(x, y) \
 970 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 971         u##x val = 0; \
 972         if (IS_GEN5(dev_priv->dev)) \
 973                 ilk_dummy_write(dev_priv); \
 974         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 975                 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE); \
 976                 if (dev_priv->forcewake_count == 0) \
 977                         dev_priv->gt.force_wake_get(dev_priv); \
 978                 val = DRM_READ##y(dev_priv->mmio_map, reg);     \
 979                 if (dev_priv->forcewake_count == 0) \
 980                         dev_priv->gt.force_wake_put(dev_priv); \
 981                 lockmgr(&dev_priv->gt_lock, LK_RELEASE); \
 982         } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
 983                 val = DRM_READ##y(dev_priv->mmio_map, reg + 0x180000);  \
 984         } else { \
 985                 val = DRM_READ##y(dev_priv->mmio_map, reg);     \
 986         } \
 987         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
 988         return val; \
 989 }
 990
 991 __i915_read(8, 8)
 992 __i915_read(16, 16)
 993 __i915_read(32, 32)
 994 __i915_read(64, 64)
 995 #undef __i915_read
 996
 997 #define __i915_write(x, y) \
 998 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
 999         u32 __fifo_ret = 0; \
1000         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1001         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1002                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1003         } \
1004         if (IS_GEN5(dev_priv->dev)) \
1005                 ilk_dummy_write(dev_priv); \
1006         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1007                 DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
1008                 I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
1009         } \
1010         if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1011                 DRM_WRITE##y(dev_priv->mmio_map, reg + 0x180000, val);  \
1012         } else {                                                        \
1013                 DRM_WRITE##y(dev_priv->mmio_map, reg, val);             \
1014         }                                                               \
1015         if (unlikely(__fifo_ret)) { \
1016                 gen6_gt_check_fifodbg(dev_priv); \
1017         } \
1018         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1019                 DRM_ERROR("Unclaimed write to %x\n", reg); \
1020                 DRM_WRITE32(dev_priv->mmio_map, GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED);  \
1021         } \
1022 }
1023
1024 __i915_write(8, 8)
1025 __i915_write(16, 16)
1026 __i915_write(32, 32)
1027 __i915_write(64, 64)
1028 #undef __i915_write