sys/dev/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  * $FreeBSD: src/sys/dev/drm2/i915/i915_debug.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34 #include "intel_ringbuffer.h"
  35
  36 #include <sys/sysctl.h>
  37
  38 enum {
  39         ACTIVE_LIST,
  40         FLUSHING_LIST,
  41         INACTIVE_LIST,
  42         PINNED_LIST,
  43         DEFERRED_FREE_LIST,
  44 };
  45
  46 static const char *
  47 yesno(int v)
  48 {
  49         return (v ? "yes" : "no");
  50 }
  51
  52 static int
  53 i915_capabilities(struct drm_device *dev, struct sbuf *m, void *data)
  54 {
  55         const struct intel_device_info *info = INTEL_INFO(dev);
  56
  57         sbuf_printf(m, "gen: %d\n", info->gen);
  58         if (HAS_PCH_SPLIT(dev))
  59                 sbuf_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  60 #define B(x) sbuf_printf(m, #x ": %s\n", yesno(info->x))
  61         B(is_mobile);
  62         B(is_i85x);
  63         B(is_i915g);
  64         B(is_i945gm);
  65         B(is_g33);
  66         B(need_gfx_hws);
  67         B(is_g4x);
  68         B(is_pineview);
  69         B(has_fbc);
  70         B(has_pipe_cxsr);
  71         B(has_hotplug);
  72         B(cursor_needs_physical);
  73         B(has_overlay);
  74         B(overlay_needs_physical);
  75         B(supports_tv);
  76         B(has_bsd_ring);
  77         B(has_blt_ring);
  78         B(has_llc);
  79 #undef B
  80
  81         return (0);
  82 }
  83
  84 static const char *
  85 get_pin_flag(struct drm_i915_gem_object *obj)
  86 {
  87         if (obj->user_pin_count > 0)
  88                 return "P";
  89         else if (obj->pin_count > 0)
  90                 return "p";
  91         else
  92                 return " ";
  93 }
  94
  95 static const char *
  96 get_tiling_flag(struct drm_i915_gem_object *obj)
  97 {
  98         switch (obj->tiling_mode) {
  99         default:
 100         case I915_TILING_NONE: return (" ");
 101         case I915_TILING_X: return ("X");
 102         case I915_TILING_Y: return ("Y");
 103         }
 104 }
 105
 106 static const char *
 107 cache_level_str(int type)
 108 {
 109         switch (type) {
 110         case I915_CACHE_NONE: return " uncached";
 111         case I915_CACHE_LLC: return " snooped (LLC)";
 112         case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
 113         default: return ("");
 114         }
 115 }
 116
 117 static void
 118 describe_obj(struct sbuf *m, struct drm_i915_gem_object *obj)
 119 {
 120
 121         sbuf_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d %d%s%s%s",
 122                    &obj->base,
 123                    get_pin_flag(obj),
 124                    get_tiling_flag(obj),
 125                    obj->base.size / 1024,
 126                    obj->base.read_domains,
 127                    obj->base.write_domain,
 128                    obj->last_read_seqno,
 129                    obj->last_write_seqno,
 130                    obj->last_fenced_seqno,
 131                    cache_level_str(obj->cache_level),
 132                    obj->dirty ? " dirty" : "",
 133                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 134         if (obj->base.name)
 135                 sbuf_printf(m, " (name: %d)", obj->base.name);
 136         if (obj->fence_reg != I915_FENCE_REG_NONE)
 137                 sbuf_printf(m, " (fence: %d)", obj->fence_reg);
 138         if (obj->gtt_space != NULL)
 139                 sbuf_printf(m, " (gtt offset: %08x, size: %08x)",
 140                            obj->gtt_offset, (unsigned int)obj->gtt_space->size);
 141         if (obj->pin_mappable || obj->fault_mappable) {
 142                 char s[3], *t = s;
 143                 if (obj->pin_mappable)
 144                         *t++ = 'p';
 145                 if (obj->fault_mappable)
 146                         *t++ = 'f';
 147                 *t = '\0';
 148                 sbuf_printf(m, " (%s mappable)", s);
 149         }
 150         if (obj->ring != NULL)
 151                 sbuf_printf(m, " (%s)", obj->ring->name);
 152 }
 153
 154 static int
 155 i915_gem_object_list_info(struct drm_device *dev, struct sbuf *m, void *data)
 156 {
 157         uintptr_t list = (uintptr_t)data;
 158         struct list_head *head;
 159         drm_i915_private_t *dev_priv = dev->dev_private;
 160         struct drm_i915_gem_object *obj;
 161         size_t total_obj_size, total_gtt_size;
 162         int count;
 163
 164         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 165                 return (EINTR);
 166
 167         switch (list) {
 168         case ACTIVE_LIST:
 169                 sbuf_printf(m, "Active:\n");
 170                 head = &dev_priv->mm.active_list;
 171                 break;
 172         case INACTIVE_LIST:
 173                 sbuf_printf(m, "Inactive:\n");
 174                 head = &dev_priv->mm.inactive_list;
 175                 break;
 176         case PINNED_LIST:
 177                 sbuf_printf(m, "Pinned:\n");
 178                 head = &dev_priv->mm.pinned_list;
 179                 break;
 180         case FLUSHING_LIST:
 181                 sbuf_printf(m, "Flushing:\n");
 182                 head = &dev_priv->mm.flushing_list;
 183                 break;
 184         case DEFERRED_FREE_LIST:
 185                 sbuf_printf(m, "Deferred free:\n");
 186                 head = &dev_priv->mm.deferred_free_list;
 187                 break;
 188         default:
 189                 DRM_UNLOCK(dev);
 190                 return (EINVAL);
 191         }
 192
 193         total_obj_size = total_gtt_size = count = 0;
 194         list_for_each_entry(obj, head, mm_list) {
 195                 sbuf_printf(m, "   ");
 196                 describe_obj(m, obj);
 197                 sbuf_printf(m, "\n");
 198                 total_obj_size += obj->base.size;
 199                 total_gtt_size += obj->gtt_space->size;
 200                 count++;
 201         }
 202         DRM_UNLOCK(dev);
 203
 204         sbuf_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 205                    count, total_obj_size, total_gtt_size);
 206         return (0);
 207 }
 208
 209 #define count_objects(list, member) do { \
 210         list_for_each_entry(obj, list, member) { \
 211                 size += obj->gtt_space->size; \
 212                 ++count; \
 213                 if (obj->map_and_fenceable) { \
 214                         mappable_size += obj->gtt_space->size; \
 215                         ++mappable_count; \
 216                 } \
 217         } \
 218 } while (0)
 219
 220 static int
 221 i915_gem_object_info(struct drm_device *dev, struct sbuf *m, void *data)
 222 {
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         u32 count, mappable_count;
 225         size_t size, mappable_size;
 226         struct drm_i915_gem_object *obj;
 227
 228         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 229                 return (EINTR);
 230         sbuf_printf(m, "%u objects, %zu bytes\n",
 231                    dev_priv->mm.object_count,
 232                    dev_priv->mm.object_memory);
 233
 234         size = count = mappable_size = mappable_count = 0;
 235         count_objects(&dev_priv->mm.gtt_list, gtt_list);
 236         sbuf_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 237                    count, mappable_count, size, mappable_size);
 238
 239         size = count = mappable_size = mappable_count = 0;
 240         count_objects(&dev_priv->mm.active_list, mm_list);
 241         count_objects(&dev_priv->mm.flushing_list, mm_list);
 242         sbuf_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 243                    count, mappable_count, size, mappable_size);
 244
 245         size = count = mappable_size = mappable_count = 0;
 246         count_objects(&dev_priv->mm.pinned_list, mm_list);
 247         sbuf_printf(m, "  %u [%u] pinned objects, %zu [%zu] bytes\n",
 248                    count, mappable_count, size, mappable_size);
 249
 250         size = count = mappable_size = mappable_count = 0;
 251         count_objects(&dev_priv->mm.inactive_list, mm_list);
 252         sbuf_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 253                    count, mappable_count, size, mappable_size);
 254
 255         size = count = mappable_size = mappable_count = 0;
 256         count_objects(&dev_priv->mm.deferred_free_list, mm_list);
 257         sbuf_printf(m, "  %u [%u] freed objects, %zu [%zu] bytes\n",
 258                    count, mappable_count, size, mappable_size);
 259
 260         size = count = mappable_size = mappable_count = 0;
 261         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
 262                 if (obj->fault_mappable) {
 263                         size += obj->gtt_space->size;
 264                         ++count;
 265                 }
 266                 if (obj->pin_mappable) {
 267                         mappable_size += obj->gtt_space->size;
 268                         ++mappable_count;
 269                 }
 270         }
 271         sbuf_printf(m, "%u pinned mappable objects, %zu bytes\n",
 272                    mappable_count, mappable_size);
 273         sbuf_printf(m, "%u fault mappable objects, %zu bytes\n",
 274                    count, size);
 275
 276         sbuf_printf(m, "%zu [%zu] gtt total\n",
 277                    dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
 278         DRM_UNLOCK(dev);
 279
 280         return (0);
 281 }
 282
 283 static int
 284 i915_gem_gtt_info(struct drm_device *dev, struct sbuf *m, void* data)
 285 {
 286         struct drm_i915_private *dev_priv = dev->dev_private;
 287         struct drm_i915_gem_object *obj;
 288         size_t total_obj_size, total_gtt_size;
 289         int count;
 290
 291         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 292                 return (EINTR);
 293
 294         total_obj_size = total_gtt_size = count = 0;
 295         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
 296                 sbuf_printf(m, "   ");
 297                 describe_obj(m, obj);
 298                 sbuf_printf(m, "\n");
 299                 total_obj_size += obj->base.size;
 300                 total_gtt_size += obj->gtt_space->size;
 301                 count++;
 302         }
 303
 304         DRM_UNLOCK(dev);
 305
 306         sbuf_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 307                    count, total_obj_size, total_gtt_size);
 308
 309         return (0);
 310 }
 311
 312 static int
 313 i915_gem_pageflip_info(struct drm_device *dev, struct sbuf *m, void *data)
 314 {
 315         struct intel_crtc *crtc;
 316         struct drm_i915_gem_object *obj;
 317         struct intel_unpin_work *work;
 318         char pipe;
 319         char plane;
 320
 321         if ((dev->driver->driver_features & DRIVER_MODESET) == 0)
 322                 return (0);
 323         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
 324                 pipe = pipe_name(crtc->pipe);
 325                 plane = plane_name(crtc->plane);
 326
 327                 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
 328                 work = crtc->unpin_work;
 329                 if (work == NULL) {
 330                         sbuf_printf(m, "No flip due on pipe %c (plane %c)\n",
 331                                    pipe, plane);
 332                 } else {
 333                         if (!atomic_read(&work->pending)) {
 334                                 sbuf_printf(m, "Flip queued on pipe %c (plane %c)\n",
 335                                            pipe, plane);
 336                         } else {
 337                                 sbuf_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 338                                            pipe, plane);
 339                         }
 340                         if (work->enable_stall_check)
 341                                 sbuf_printf(m, "Stall check enabled, ");
 342                         else
 343                                 sbuf_printf(m, "Stall check waiting for page flip ioctl, ");
 344                         sbuf_printf(m, "%d prepares\n", atomic_read(&work->pending));
 345
 346                         if (work->old_fb_obj) {
 347                                 obj = work->old_fb_obj;
 348                                 if (obj)
 349                                         sbuf_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
 350                         }
 351                         if (work->pending_flip_obj) {
 352                                 obj = work->pending_flip_obj;
 353                                 if (obj)
 354                                         sbuf_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
 355                         }
 356                 }
 357                 lockmgr(&dev->event_lock, LK_RELEASE);
 358         }
 359
 360         return (0);
 361 }
 362
 363 static int
 364 i915_gem_request_info(struct drm_device *dev, struct sbuf *m, void *data)
 365 {
 366         drm_i915_private_t *dev_priv = dev->dev_private;
 367         struct drm_i915_gem_request *gem_request;
 368         int count;
 369
 370         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 371                 return (EINTR);
 372
 373         count = 0;
 374         if (!list_empty(&dev_priv->ring[RCS].request_list)) {
 375                 sbuf_printf(m, "Render requests:\n");
 376                 list_for_each_entry(gem_request,
 377                                     &dev_priv->ring[RCS].request_list,
 378                                     list) {
 379                         sbuf_printf(m, "    %d @ %d\n",
 380                                    gem_request->seqno,
 381                                    (int) (jiffies - gem_request->emitted_jiffies));
 382                 }
 383                 count++;
 384         }
 385         if (!list_empty(&dev_priv->ring[VCS].request_list)) {
 386                 sbuf_printf(m, "BSD requests:\n");
 387                 list_for_each_entry(gem_request,
 388                                     &dev_priv->ring[VCS].request_list,
 389                                     list) {
 390                         sbuf_printf(m, "    %d @ %d\n",
 391                                    gem_request->seqno,
 392                                    (int) (jiffies - gem_request->emitted_jiffies));
 393                 }
 394                 count++;
 395         }
 396         if (!list_empty(&dev_priv->ring[BCS].request_list)) {
 397                 sbuf_printf(m, "BLT requests:\n");
 398                 list_for_each_entry(gem_request,
 399                                     &dev_priv->ring[BCS].request_list,
 400                                     list) {
 401                         sbuf_printf(m, "    %d @ %d\n",
 402                                    gem_request->seqno,
 403                                    (int) (jiffies - gem_request->emitted_jiffies));
 404                 }
 405                 count++;
 406         }
 407         DRM_UNLOCK(dev);
 408
 409         if (count == 0)
 410                 sbuf_printf(m, "No requests\n");
 411
 412         return 0;
 413 }
 414
 415 static void
 416 i915_ring_seqno_info(struct sbuf *m, struct intel_ring_buffer *ring)
 417 {
 418         if (ring->get_seqno) {
 419                 sbuf_printf(m, "Current sequence (%s): %d\n",
 420                            ring->name, ring->get_seqno(ring, false));
 421         }
 422 }
 423
 424 static int
 425 i915_gem_seqno_info(struct drm_device *dev, struct sbuf *m, void *data)
 426 {
 427         drm_i915_private_t *dev_priv = dev->dev_private;
 428         int i;
 429
 430         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 431                 return (EINTR);
 432         for (i = 0; i < I915_NUM_RINGS; i++)
 433                 i915_ring_seqno_info(m, &dev_priv->ring[i]);
 434         DRM_UNLOCK(dev);
 435         return (0);
 436 }
 437
 438
 439 static int
 440 i915_interrupt_info(struct drm_device *dev, struct sbuf *m, void *data)
 441 {
 442         drm_i915_private_t *dev_priv = dev->dev_private;
 443         int i, pipe;
 444
 445         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 446                 return (EINTR);
 447
 448         if (!HAS_PCH_SPLIT(dev)) {
 449                 sbuf_printf(m, "Interrupt enable:    %08x\n",
 450                            I915_READ(IER));
 451                 sbuf_printf(m, "Interrupt identity:  %08x\n",
 452                            I915_READ(IIR));
 453                 sbuf_printf(m, "Interrupt mask:      %08x\n",
 454                            I915_READ(IMR));
 455                 for_each_pipe(pipe)
 456                         sbuf_printf(m, "Pipe %c stat:         %08x\n",
 457                                    pipe_name(pipe),
 458                                    I915_READ(PIPESTAT(pipe)));
 459         } else {
 460                 sbuf_printf(m, "North Display Interrupt enable:         %08x\n",
 461                            I915_READ(DEIER));
 462                 sbuf_printf(m, "North Display Interrupt identity:       %08x\n",
 463                            I915_READ(DEIIR));
 464                 sbuf_printf(m, "North Display Interrupt mask:           %08x\n",
 465                            I915_READ(DEIMR));
 466                 sbuf_printf(m, "South Display Interrupt enable:         %08x\n",
 467                            I915_READ(SDEIER));
 468                 sbuf_printf(m, "South Display Interrupt identity:       %08x\n",
 469                            I915_READ(SDEIIR));
 470                 sbuf_printf(m, "South Display Interrupt mask:           %08x\n",
 471                            I915_READ(SDEIMR));
 472                 sbuf_printf(m, "Graphics Interrupt enable:              %08x\n",
 473                            I915_READ(GTIER));
 474                 sbuf_printf(m, "Graphics Interrupt identity:            %08x\n",
 475                            I915_READ(GTIIR));
 476                 sbuf_printf(m, "Graphics Interrupt mask:                %08x\n",
 477                            I915_READ(GTIMR));
 478         }
 479         sbuf_printf(m, "Interrupts received: %d\n",
 480                    atomic_read(&dev_priv->irq_received));
 481         for (i = 0; i < I915_NUM_RINGS; i++) {
 482                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
 483                         sbuf_printf(m, "Graphics Interrupt mask (%s):   %08x\n",
 484                                    dev_priv->ring[i].name,
 485                                    I915_READ_IMR(&dev_priv->ring[i]));
 486                 }
 487                 i915_ring_seqno_info(m, &dev_priv->ring[i]);
 488         }
 489         DRM_UNLOCK(dev);
 490
 491         return (0);
 492 }
 493
 494 static int
 495 i915_gem_fence_regs_info(struct drm_device *dev, struct sbuf *m, void *data)
 496 {
 497         drm_i915_private_t *dev_priv = dev->dev_private;
 498         int i;
 499
 500         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 501                 return (EINTR);
 502
 503         sbuf_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 504         sbuf_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 505         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 506                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 507
 508                 sbuf_printf(m, "Fenced object[%2d] = ", i);
 509                 if (obj == NULL)
 510                         sbuf_printf(m, "unused");
 511                 else
 512                         describe_obj(m, obj);
 513                 sbuf_printf(m, "\n");
 514         }
 515
 516         DRM_UNLOCK(dev);
 517         return (0);
 518 }
 519
 520 static int
 521 i915_hws_info(struct drm_device *dev, struct sbuf *m, void *data)
 522 {
 523         drm_i915_private_t *dev_priv = dev->dev_private;
 524         struct intel_ring_buffer *ring;
 525         const volatile u32 *hws;
 526         int i;
 527
 528         ring = &dev_priv->ring[(uintptr_t)data];
 529         hws = (volatile u32 *)ring->status_page.page_addr;
 530         if (hws == NULL)
 531                 return (0);
 532
 533         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 534                 sbuf_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 535                            i * 4,
 536                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 537         }
 538         return (0);
 539 }
 540
 541 static int
 542 i915_ringbuffer_data(struct drm_device *dev, struct sbuf *m, void *data)
 543 {
 544         drm_i915_private_t *dev_priv = dev->dev_private;
 545         struct intel_ring_buffer *ring;
 546
 547         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 548                 return (EINTR);
 549         ring = &dev_priv->ring[(uintptr_t)data];
 550         if (!ring->obj) {
 551                 sbuf_printf(m, "No ringbuffer setup\n");
 552         } else {
 553                 u8 *virt = ring->virtual_start;
 554                 uint32_t off;
 555
 556                 for (off = 0; off < ring->size; off += 4) {
 557                         uint32_t *ptr = (uint32_t *)(virt + off);
 558                         sbuf_printf(m, "%08x :  %08x\n", off, *ptr);
 559                 }
 560         }
 561         DRM_UNLOCK(dev);
 562         return (0);
 563 }
 564
 565 static int
 566 i915_ringbuffer_info(struct drm_device *dev, struct sbuf *m, void *data)
 567 {
 568         drm_i915_private_t *dev_priv = dev->dev_private;
 569         struct intel_ring_buffer *ring;
 570
 571         ring = &dev_priv->ring[(uintptr_t)data];
 572         if (ring->size == 0)
 573                 return (0);
 574
 575         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 576                 return (EINTR);
 577
 578         sbuf_printf(m, "Ring %s:\n", ring->name);
 579         sbuf_printf(m, "  Head :    %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
 580         sbuf_printf(m, "  Tail :    %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
 581         sbuf_printf(m, "  Size :    %08x\n", ring->size);
 582         sbuf_printf(m, "  Active :  %08x\n", intel_ring_get_active_head(ring));
 583         sbuf_printf(m, "  NOPID :   %08x\n", I915_READ_NOPID(ring));
 584         if (IS_GEN6(dev) || IS_GEN7(dev)) {
 585                 sbuf_printf(m, "  Sync 0 :   %08x\n", I915_READ_SYNC_0(ring));
 586                 sbuf_printf(m, "  Sync 1 :   %08x\n", I915_READ_SYNC_1(ring));
 587         }
 588         sbuf_printf(m, "  Control : %08x\n", I915_READ_CTL(ring));
 589         sbuf_printf(m, "  Start :   %08x\n", I915_READ_START(ring));
 590
 591         DRM_UNLOCK(dev);
 592
 593         return (0);
 594 }
 595
 596 static const char *
 597 ring_str(int ring)
 598 {
 599         switch (ring) {
 600         case RCS: return (" render");
 601         case VCS: return (" bsd");
 602         case BCS: return (" blt");
 603         default: return ("");
 604         }
 605 }
 606
 607 static const char *
 608 pin_flag(int pinned)
 609 {
 610         if (pinned > 0)
 611                 return (" P");
 612         else if (pinned < 0)
 613                 return (" p");
 614         else
 615                 return ("");
 616 }
 617
 618 static const char *tiling_flag(int tiling)
 619 {
 620         switch (tiling) {
 621         default:
 622         case I915_TILING_NONE: return "";
 623         case I915_TILING_X: return " X";
 624         case I915_TILING_Y: return " Y";
 625         }
 626 }
 627
 628 static const char *dirty_flag(int dirty)
 629 {
 630         return dirty ? " dirty" : "";
 631 }
 632
 633 static const char *purgeable_flag(int purgeable)
 634 {
 635         return purgeable ? " purgeable" : "";
 636 }
 637
 638 static void print_error_buffers(struct sbuf *m, const char *name,
 639     struct drm_i915_error_buffer *err, int count)
 640 {
 641
 642         sbuf_printf(m, "%s [%d]:\n", name, count);
 643
 644         while (count--) {
 645                 sbuf_printf(m, "  %08x %8u %04x %04x %x %x%s%s%s%s%s%s%s",
 646                            err->gtt_offset,
 647                            err->size,
 648                            err->read_domains,
 649                            err->write_domain,
 650                            err->rseqno, err->wseqno,
 651                            pin_flag(err->pinned),
 652                            tiling_flag(err->tiling),
 653                            dirty_flag(err->dirty),
 654                            purgeable_flag(err->purgeable),
 655                            err->ring != -1 ? " " : "",
 656                            ring_str(err->ring),
 657                            cache_level_str(err->cache_level));
 658
 659                 if (err->name)
 660                         sbuf_printf(m, " (name: %d)", err->name);
 661                 if (err->fence_reg != I915_FENCE_REG_NONE)
 662                         sbuf_printf(m, " (fence: %d)", err->fence_reg);
 663
 664                 sbuf_printf(m, "\n");
 665                 err++;
 666         }
 667 }
 668
 669 static void
 670 i915_ring_error_state(struct sbuf *m, struct drm_device *dev,
 671     struct drm_i915_error_state *error, unsigned ring)
 672 {
 673
 674         sbuf_printf(m, "%s command stream:\n", ring_str(ring));
 675         sbuf_printf(m, "  HEAD: 0x%08x\n", error->head[ring]);
 676         sbuf_printf(m, "  TAIL: 0x%08x\n", error->tail[ring]);
 677         sbuf_printf(m, "  ACTHD: 0x%08x\n", error->acthd[ring]);
 678         sbuf_printf(m, "  IPEIR: 0x%08x\n", error->ipeir[ring]);
 679         sbuf_printf(m, "  IPEHR: 0x%08x\n", error->ipehr[ring]);
 680         sbuf_printf(m, "  INSTDONE: 0x%08x\n", error->instdone[ring]);
 681         if (ring == RCS && INTEL_INFO(dev)->gen >= 4) {
 682                 sbuf_printf(m, "  INSTDONE1: 0x%08x\n", error->instdone1);
 683                 sbuf_printf(m, "  BBADDR: 0x%08jx\n", (uintmax_t)error->bbaddr);
 684         }
 685         if (INTEL_INFO(dev)->gen >= 4)
 686                 sbuf_printf(m, "  INSTPS: 0x%08x\n", error->instps[ring]);
 687         sbuf_printf(m, "  INSTPM: 0x%08x\n", error->instpm[ring]);
 688         if (INTEL_INFO(dev)->gen >= 6) {
 689                 sbuf_printf(m, "  FADDR: 0x%08x\n", error->faddr[ring]);
 690                 sbuf_printf(m, "  FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
 691                 sbuf_printf(m, "  SYNC_0: 0x%08x\n",
 692                            error->semaphore_mboxes[ring][0]);
 693                 sbuf_printf(m, "  SYNC_1: 0x%08x\n",
 694                            error->semaphore_mboxes[ring][1]);
 695         }
 696         sbuf_printf(m, "  seqno: 0x%08x\n", error->seqno[ring]);
 697         sbuf_printf(m, "  waiting: %s\n", yesno(error->waiting[ring]));
 698         sbuf_printf(m, "  ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
 699         sbuf_printf(m, "  ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
 700 }
 701
 702 static int i915_error_state(struct drm_device *dev, struct sbuf *m,
 703     void *unused)
 704 {
 705         drm_i915_private_t *dev_priv = dev->dev_private;
 706         struct drm_i915_error_state *error;
 707         int i, j, page, offset, elt;
 708
 709         lockmgr(&dev_priv->error_lock, LK_EXCLUSIVE);
 710         if (!dev_priv->first_error) {
 711                 sbuf_printf(m, "no error state collected\n");
 712                 goto out;
 713         }
 714
 715         error = dev_priv->first_error;
 716
 717         sbuf_printf(m, "Time: %jd s %jd us\n", (intmax_t)error->time.tv_sec,
 718             (intmax_t)error->time.tv_usec);
 719         sbuf_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
 720         sbuf_printf(m, "EIR: 0x%08x\n", error->eir);
 721         sbuf_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 722
 723         for (i = 0; i < dev_priv->num_fence_regs; i++)
 724                 sbuf_printf(m, "  fence[%d] = %08jx\n", i,
 725                     (uintmax_t)error->fence[i]);
 726
 727         if (INTEL_INFO(dev)->gen >= 6) {
 728                 sbuf_printf(m, "ERROR: 0x%08x\n", error->error);
 729                 sbuf_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 730         }
 731
 732         i915_ring_error_state(m, dev, error, RCS);
 733         if (HAS_BLT(dev))
 734                 i915_ring_error_state(m, dev, error, BCS);
 735         if (HAS_BSD(dev))
 736                 i915_ring_error_state(m, dev, error, VCS);
 737
 738         if (error->active_bo)
 739                 print_error_buffers(m, "Active",
 740                                     error->active_bo,
 741                                     error->active_bo_count);
 742
 743         if (error->pinned_bo)
 744                 print_error_buffers(m, "Pinned",
 745                                     error->pinned_bo,
 746                                     error->pinned_bo_count);
 747
 748         for (i = 0; i < DRM_ARRAY_SIZE(error->ring); i++) {
 749                 struct drm_i915_error_object *obj;
 750
 751                 if ((obj = error->ring[i].batchbuffer)) {
 752                         sbuf_printf(m, "%s --- gtt_offset = 0x%08x\n",
 753                                    dev_priv->ring[i].name,
 754                                    obj->gtt_offset);
 755                         offset = 0;
 756                         for (page = 0; page < obj->page_count; page++) {
 757                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 758                                         sbuf_printf(m, "%08x :  %08x\n",
 759                                             offset, obj->pages[page][elt]);
 760                                         offset += 4;
 761                                 }
 762                         }
 763                 }
 764
 765                 if (error->ring[i].num_requests) {
 766                         sbuf_printf(m, "%s --- %d requests\n",
 767                                    dev_priv->ring[i].name,
 768                                    error->ring[i].num_requests);
 769                         for (j = 0; j < error->ring[i].num_requests; j++) {
 770                                 sbuf_printf(m, "  seqno 0x%08x, emitted %ld, tail 0x%08x\n",
 771                                            error->ring[i].requests[j].seqno,
 772                                            error->ring[i].requests[j].jiffies,
 773                                            error->ring[i].requests[j].tail);
 774                         }
 775                 }
 776
 777                 if ((obj = error->ring[i].ringbuffer)) {
 778                         sbuf_printf(m, "%s --- ringbuffer = 0x%08x\n",
 779                                    dev_priv->ring[i].name,
 780                                    obj->gtt_offset);
 781                         offset = 0;
 782                         for (page = 0; page < obj->page_count; page++) {
 783                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 784                                         sbuf_printf(m, "%08x :  %08x\n",
 785                                                    offset,
 786                                                    obj->pages[page][elt]);
 787                                         offset += 4;
 788                                 }
 789                         }
 790                 }
 791         }
 792
 793         if (error->overlay)
 794                 intel_overlay_print_error_state(m, error->overlay);
 795
 796         if (error->display)
 797                 intel_display_print_error_state(m, dev, error->display);
 798
 799 out:
 800         lockmgr(&dev_priv->error_lock, LK_RELEASE);
 801
 802         return (0);
 803 }
 804
 805 static int
 806 i915_rstdby_delays(struct drm_device *dev, struct sbuf *m, void *unused)
 807 {
 808         drm_i915_private_t *dev_priv = dev->dev_private;
 809         u16 crstanddelay;
 810
 811         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 812                 return (EINTR);
 813         crstanddelay = I915_READ16(CRSTANDVID);
 814         DRM_UNLOCK(dev);
 815
 816         sbuf_printf(m, "w/ctx: %d, w/o ctx: %d\n",
 817             (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
 818
 819         return 0;
 820 }
 821
 822 static int
 823 i915_cur_delayinfo(struct drm_device *dev, struct sbuf *m, void *unused)
 824 {
 825         drm_i915_private_t *dev_priv = dev->dev_private;
 826
 827         if (IS_GEN5(dev)) {
 828                 u16 rgvswctl = I915_READ16(MEMSWCTL);
 829                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
 830
 831                 sbuf_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
 832                 sbuf_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
 833                 sbuf_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
 834                            MEMSTAT_VID_SHIFT);
 835                 sbuf_printf(m, "Current P-state: %d\n",
 836                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 837         } else if (IS_GEN6(dev)) {
 838                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 839                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
 840                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 841                 u32 rpstat;
 842                 u32 rpupei, rpcurup, rpprevup;
 843                 u32 rpdownei, rpcurdown, rpprevdown;
 844                 int max_freq;
 845
 846                 /* RPSTAT1 is in the GT power well */
 847                 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 848                         return (EINTR);
 849                 gen6_gt_force_wake_get(dev_priv);
 850
 851                 rpstat = I915_READ(GEN6_RPSTAT1);
 852                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
 853                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
 854                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
 855                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
 856                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
 857                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
 858
 859                 gen6_gt_force_wake_put(dev_priv);
 860                 DRM_UNLOCK(dev);
 861
 862                 sbuf_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 863                 sbuf_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
 864                 sbuf_printf(m, "Render p-state ratio: %d\n",
 865                            (gt_perf_status & 0xff00) >> 8);
 866                 sbuf_printf(m, "Render p-state VID: %d\n",
 867                            gt_perf_status & 0xff);
 868                 sbuf_printf(m, "Render p-state limit: %d\n",
 869                            rp_state_limits & 0xff);
 870                 sbuf_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
 871                                                 GEN6_CAGF_SHIFT) * 50);
 872                 sbuf_printf(m, "RP CUR UP EI: %dus\n", rpupei &
 873                            GEN6_CURICONT_MASK);
 874                 sbuf_printf(m, "RP CUR UP: %dus\n", rpcurup &
 875                            GEN6_CURBSYTAVG_MASK);
 876                 sbuf_printf(m, "RP PREV UP: %dus\n", rpprevup &
 877                            GEN6_CURBSYTAVG_MASK);
 878                 sbuf_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
 879                            GEN6_CURIAVG_MASK);
 880                 sbuf_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
 881                            GEN6_CURBSYTAVG_MASK);
 882                 sbuf_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
 883                            GEN6_CURBSYTAVG_MASK);
 884
 885                 max_freq = (rp_state_cap & 0xff0000) >> 16;
 886                 sbuf_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 887                            max_freq * 50);
 888
 889                 max_freq = (rp_state_cap & 0xff00) >> 8;
 890                 sbuf_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 891                            max_freq * 50);
 892
 893                 max_freq = rp_state_cap & 0xff;
 894                 sbuf_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 895                            max_freq * 50);
 896         } else {
 897                 sbuf_printf(m, "no P-state info available\n");
 898         }
 899
 900         return 0;
 901 }
 902
 903 static int
 904 i915_delayfreq_table(struct drm_device *dev, struct sbuf *m, void *unused)
 905 {
 906         drm_i915_private_t *dev_priv = dev->dev_private;
 907         u32 delayfreq;
 908         int i;
 909
 910         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 911                 return (EINTR);
 912         for (i = 0; i < 16; i++) {
 913                 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
 914                 sbuf_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
 915                            (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
 916         }
 917         DRM_UNLOCK(dev);
 918         return (0);
 919 }
 920
 921 static inline int
 922 MAP_TO_MV(int map)
 923 {
 924         return 1250 - (map * 25);
 925 }
 926
 927 static int
 928 i915_inttoext_table(struct drm_device *dev, struct sbuf *m, void *unused)
 929 {
 930         drm_i915_private_t *dev_priv = dev->dev_private;
 931         u32 inttoext;
 932         int i;
 933
 934         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 935                 return (EINTR);
 936         for (i = 1; i <= 32; i++) {
 937                 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
 938                 sbuf_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
 939         }
 940         DRM_UNLOCK(dev);
 941
 942         return (0);
 943 }
 944
 945 static int
 946 ironlake_drpc_info(struct drm_device *dev, struct sbuf *m)
 947 {
 948         drm_i915_private_t *dev_priv = dev->dev_private;
 949         u32 rgvmodectl;
 950         u32 rstdbyctl;
 951         u16 crstandvid;
 952
 953         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 954                 return (EINTR);
 955         rgvmodectl = I915_READ(MEMMODECTL);
 956         rstdbyctl = I915_READ(RSTDBYCTL);
 957         crstandvid = I915_READ16(CRSTANDVID);
 958         DRM_UNLOCK(dev);
 959
 960         sbuf_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
 961                    "yes" : "no");
 962         sbuf_printf(m, "Boost freq: %d\n",
 963                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
 964                    MEMMODE_BOOST_FREQ_SHIFT);
 965         sbuf_printf(m, "HW control enabled: %s\n",
 966                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
 967         sbuf_printf(m, "SW control enabled: %s\n",
 968                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
 969         sbuf_printf(m, "Gated voltage change: %s\n",
 970                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
 971         sbuf_printf(m, "Starting frequency: P%d\n",
 972                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
 973         sbuf_printf(m, "Max P-state: P%d\n",
 974                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
 975         sbuf_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
 976         sbuf_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
 977         sbuf_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
 978         sbuf_printf(m, "Render standby enabled: %s\n",
 979                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
 980         sbuf_printf(m, "Current RS state: ");
 981         switch (rstdbyctl & RSX_STATUS_MASK) {
 982         case RSX_STATUS_ON:
 983                 sbuf_printf(m, "on\n");
 984                 break;
 985         case RSX_STATUS_RC1:
 986                 sbuf_printf(m, "RC1\n");
 987                 break;
 988         case RSX_STATUS_RC1E:
 989                 sbuf_printf(m, "RC1E\n");
 990                 break;
 991         case RSX_STATUS_RS1:
 992                 sbuf_printf(m, "RS1\n");
 993                 break;
 994         case RSX_STATUS_RS2:
 995                 sbuf_printf(m, "RS2 (RC6)\n");
 996                 break;
 997         case RSX_STATUS_RS3:
 998                 sbuf_printf(m, "RC3 (RC6+)\n");
 999                 break;
1000         default:
1001                 sbuf_printf(m, "unknown\n");
1002                 break;
1003         }
1004
1005         return 0;
1006 }
1007
1008 static int
1009 gen6_drpc_info(struct drm_device *dev, struct sbuf *m)
1010 {
1011         drm_i915_private_t *dev_priv = dev->dev_private;
1012         u32 rpmodectl1, gt_core_status, rcctl1;
1013         unsigned forcewake_count;
1014         int count=0;
1015
1016         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1017                 return (EINTR);
1018
1019         lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
1020         forcewake_count = dev_priv->forcewake_count;
1021         lockmgr(&dev_priv->gt_lock, LK_RELEASE);
1022
1023         if (forcewake_count) {
1024                 sbuf_printf(m, "RC information inaccurate because userspace "
1025                               "holds a reference \n");
1026         } else {
1027                 /* NB: we cannot use forcewake, else we read the wrong values */
1028                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1029                         DRM_UDELAY(10);
1030                 sbuf_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1031         }
1032
1033         gt_core_status = DRM_READ32(dev_priv->mmio_map, GEN6_GT_CORE_STATUS);
1034         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1035
1036         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1037         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1038         DRM_UNLOCK(dev);
1039
1040         sbuf_printf(m, "Video Turbo Mode: %s\n",
1041                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1042         sbuf_printf(m, "HW control enabled: %s\n",
1043                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1044         sbuf_printf(m, "SW control enabled: %s\n",
1045                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1046                           GEN6_RP_MEDIA_SW_MODE));
1047         sbuf_printf(m, "RC1e Enabled: %s\n",
1048                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1049         sbuf_printf(m, "RC6 Enabled: %s\n",
1050                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1051         sbuf_printf(m, "Deep RC6 Enabled: %s\n",
1052                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1053         sbuf_printf(m, "Deepest RC6 Enabled: %s\n",
1054                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1055         sbuf_printf(m, "Current RC state: ");
1056         switch (gt_core_status & GEN6_RCn_MASK) {
1057         case GEN6_RC0:
1058                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1059                         sbuf_printf(m, "Core Power Down\n");
1060                 else
1061                         sbuf_printf(m, "on\n");
1062                 break;
1063         case GEN6_RC3:
1064                 sbuf_printf(m, "RC3\n");
1065                 break;
1066         case GEN6_RC6:
1067                 sbuf_printf(m, "RC6\n");
1068                 break;
1069         case GEN6_RC7:
1070                 sbuf_printf(m, "RC7\n");
1071                 break;
1072         default:
1073                 sbuf_printf(m, "Unknown\n");
1074                 break;
1075         }
1076
1077         sbuf_printf(m, "Core Power Down: %s\n",
1078                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1079         return 0;
1080 }
1081
1082 static int i915_drpc_info(struct drm_device *dev, struct sbuf *m, void *unused)
1083 {
1084
1085         if (IS_GEN6(dev) || IS_GEN7(dev))
1086                 return (gen6_drpc_info(dev, m));
1087         else
1088                 return (ironlake_drpc_info(dev, m));
1089 }
1090 static int
1091 i915_fbc_status(struct drm_device *dev, struct sbuf *m, void *unused)
1092 {
1093         drm_i915_private_t *dev_priv = dev->dev_private;
1094
1095         if (!I915_HAS_FBC(dev)) {
1096                 sbuf_printf(m, "FBC unsupported on this chipset");
1097                 return 0;
1098         }
1099
1100         if (intel_fbc_enabled(dev)) {
1101                 sbuf_printf(m, "FBC enabled");
1102         } else {
1103                 sbuf_printf(m, "FBC disabled: ");
1104                 switch (dev_priv->no_fbc_reason) {
1105                 case FBC_NO_OUTPUT:
1106                         sbuf_printf(m, "no outputs");
1107                         break;
1108                 case FBC_STOLEN_TOO_SMALL:
1109                         sbuf_printf(m, "not enough stolen memory");
1110                         break;
1111                 case FBC_UNSUPPORTED_MODE:
1112                         sbuf_printf(m, "mode not supported");
1113                         break;
1114                 case FBC_MODE_TOO_LARGE:
1115                         sbuf_printf(m, "mode too large");
1116                         break;
1117                 case FBC_BAD_PLANE:
1118                         sbuf_printf(m, "FBC unsupported on plane");
1119                         break;
1120                 case FBC_NOT_TILED:
1121                         sbuf_printf(m, "scanout buffer not tiled");
1122                         break;
1123                 case FBC_MULTIPLE_PIPES:
1124                         sbuf_printf(m, "multiple pipes are enabled");
1125                         break;
1126                 default:
1127                         sbuf_printf(m, "unknown reason");
1128                 }
1129         }
1130         return 0;
1131 }
1132
1133 static int
1134 i915_sr_status(struct drm_device *dev, struct sbuf *m, void *unused)
1135 {
1136         drm_i915_private_t *dev_priv = dev->dev_private;
1137         bool sr_enabled = false;
1138
1139         if (HAS_PCH_SPLIT(dev))
1140                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1141         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1142                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1143         else if (IS_I915GM(dev))
1144                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1145         else if (IS_PINEVIEW(dev))
1146                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1147
1148         sbuf_printf(m, "self-refresh: %s",
1149                    sr_enabled ? "enabled" : "disabled");
1150
1151         return (0);
1152 }
1153
1154 static int i915_ring_freq_table(struct drm_device *dev, struct sbuf *m,
1155     void *unused)
1156 {
1157         drm_i915_private_t *dev_priv = dev->dev_private;
1158         int gpu_freq, ia_freq;
1159
1160         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1161                 sbuf_printf(m, "unsupported on this chipset");
1162                 return (0);
1163         }
1164
1165         if (lockmgr(&dev_priv->rps.hw_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1166                 return -EINTR;
1167
1168         sbuf_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
1169
1170         for (gpu_freq = dev_priv->rps.min_delay;
1171              gpu_freq <= dev_priv->rps.max_delay;
1172              gpu_freq++) {
1173                 I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
1174                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
1175                            GEN6_PCODE_READ_MIN_FREQ_TABLE);
1176                 if (_intel_wait_for(dev,
1177                     (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
1178                     10, 1, "915frq")) {
1179                         DRM_ERROR("pcode read of freq table timed out\n");
1180                         continue;
1181                 }
1182                 ia_freq = I915_READ(GEN6_PCODE_DATA);
1183                 sbuf_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
1184         }
1185
1186         lockmgr(&dev_priv->rps.hw_lock, LK_RELEASE);
1187
1188         return 0;
1189 }
1190
1191 static int
1192 i915_emon_status(struct drm_device *dev, struct sbuf *m, void *unused)
1193 {
1194         drm_i915_private_t *dev_priv = dev->dev_private;
1195         unsigned long temp, chipset, gfx;
1196
1197         if (!IS_GEN5(dev)) {
1198                 sbuf_printf(m, "Not supported\n");
1199                 return (0);
1200         }
1201
1202         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1203                 return (EINTR);
1204         temp = i915_mch_val(dev_priv);
1205         chipset = i915_chipset_val(dev_priv);
1206         gfx = i915_gfx_val(dev_priv);
1207         DRM_UNLOCK(dev);
1208
1209         sbuf_printf(m, "GMCH temp: %ld\n", temp);
1210         sbuf_printf(m, "Chipset power: %ld\n", chipset);
1211         sbuf_printf(m, "GFX power: %ld\n", gfx);
1212         sbuf_printf(m, "Total power: %ld\n", chipset + gfx);
1213
1214         return (0);
1215 }
1216
1217 static int
1218 i915_gfxec(struct drm_device *dev, struct sbuf *m, void *unused)
1219 {
1220         drm_i915_private_t *dev_priv = dev->dev_private;
1221
1222         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1223                 return (EINTR);
1224         sbuf_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1225         DRM_UNLOCK(dev);
1226
1227         return (0);
1228 }
1229
1230 #if 0
1231 static int
1232 i915_opregion(struct drm_device *dev, struct sbuf *m, void *unused)
1233 {
1234         drm_i915_private_t *dev_priv = dev->dev_private;
1235         struct intel_opregion *opregion = &dev_priv->opregion;
1236
1237         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1238                 return (EINTR);
1239         if (opregion->header)
1240                 seq_write(m, opregion->header, OPREGION_SIZE);
1241         DRM_UNLOCK(dev);
1242
1243         return 0;
1244 }
1245 #endif
1246
1247 static int
1248 i915_gem_framebuffer_info(struct drm_device *dev, struct sbuf *m, void *data)
1249 {
1250         drm_i915_private_t *dev_priv = dev->dev_private;
1251         struct intel_fbdev *ifbdev;
1252         struct intel_framebuffer *fb;
1253
1254         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1255                 return (EINTR);
1256
1257         ifbdev = dev_priv->fbdev;
1258         if (ifbdev == NULL) {
1259                 DRM_UNLOCK(dev);
1260                 return (0);
1261         }
1262         fb = to_intel_framebuffer(ifbdev->helper.fb);
1263
1264         sbuf_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1265                    fb->base.width,
1266                    fb->base.height,
1267                    fb->base.depth,
1268                    fb->base.bits_per_pixel);
1269         describe_obj(m, fb->obj);
1270         sbuf_printf(m, "\n");
1271
1272         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1273                 if (&fb->base == ifbdev->helper.fb)
1274                         continue;
1275
1276                 sbuf_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1277                            fb->base.width,
1278                            fb->base.height,
1279                            fb->base.depth,
1280                            fb->base.bits_per_pixel);
1281                 describe_obj(m, fb->obj);
1282                 sbuf_printf(m, "\n");
1283         }
1284
1285         DRM_UNLOCK(dev);
1286
1287         return (0);
1288 }
1289
1290 static int
1291 i915_context_status(struct drm_device *dev, struct sbuf *m, void *data)
1292 {
1293         drm_i915_private_t *dev_priv;
1294         int ret;
1295
1296         if ((dev->driver->driver_features & DRIVER_MODESET) == 0)
1297                 return (0);
1298
1299         dev_priv = dev->dev_private;
1300         ret = lockmgr(&dev->mode_config.mutex, LK_EXCLUSIVE|LK_SLEEPFAIL);
1301         if (ret != 0)
1302                 return (EINTR);
1303
1304         if (dev_priv->pwrctx != NULL) {
1305                 sbuf_printf(m, "power context ");
1306                 describe_obj(m, dev_priv->pwrctx);
1307                 sbuf_printf(m, "\n");
1308         }
1309
1310         if (dev_priv->renderctx != NULL) {
1311                 sbuf_printf(m, "render context ");
1312                 describe_obj(m, dev_priv->renderctx);
1313                 sbuf_printf(m, "\n");
1314         }
1315
1316         lockmgr(&dev->mode_config.mutex, LK_RELEASE);
1317
1318         return (0);
1319 }
1320
1321 static int
1322 i915_gen6_forcewake_count_info(struct drm_device *dev, struct sbuf *m,
1323     void *data)
1324 {
1325         struct drm_i915_private *dev_priv;
1326         unsigned forcewake_count;
1327
1328         dev_priv = dev->dev_private;
1329         lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
1330         forcewake_count = dev_priv->forcewake_count;
1331         lockmgr(&dev_priv->gt_lock, LK_RELEASE);
1332
1333         sbuf_printf(m, "forcewake count = %u\n", forcewake_count);
1334
1335         return (0);
1336 }
1337
1338 static const char *
1339 swizzle_string(unsigned swizzle)
1340 {
1341
1342         switch(swizzle) {
1343         case I915_BIT_6_SWIZZLE_NONE:
1344                 return "none";
1345         case I915_BIT_6_SWIZZLE_9:
1346                 return "bit9";
1347         case I915_BIT_6_SWIZZLE_9_10:
1348                 return "bit9/bit10";
1349         case I915_BIT_6_SWIZZLE_9_11:
1350                 return "bit9/bit11";
1351         case I915_BIT_6_SWIZZLE_9_10_11:
1352                 return "bit9/bit10/bit11";
1353         case I915_BIT_6_SWIZZLE_9_17:
1354                 return "bit9/bit17";
1355         case I915_BIT_6_SWIZZLE_9_10_17:
1356                 return "bit9/bit10/bit17";
1357         case I915_BIT_6_SWIZZLE_UNKNOWN:
1358                 return "unknown";
1359         }
1360
1361         return "bug";
1362 }
1363
1364 static int
1365 i915_swizzle_info(struct drm_device *dev, struct sbuf *m, void *data)
1366 {
1367         struct drm_i915_private *dev_priv;
1368         int ret;
1369
1370         dev_priv = dev->dev_private;
1371         ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
1372         if (ret != 0)
1373                 return (EINTR);
1374
1375         sbuf_printf(m, "bit6 swizzle for X-tiling = %s\n",
1376                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1377         sbuf_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1378                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1379
1380         if (IS_GEN3(dev) || IS_GEN4(dev)) {
1381                 sbuf_printf(m, "DDC = 0x%08x\n",
1382                            I915_READ(DCC));
1383                 sbuf_printf(m, "C0DRB3 = 0x%04x\n",
1384                            I915_READ16(C0DRB3));
1385                 sbuf_printf(m, "C1DRB3 = 0x%04x\n",
1386                            I915_READ16(C1DRB3));
1387         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1388                 sbuf_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1389                            I915_READ(MAD_DIMM_C0));
1390                 sbuf_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1391                            I915_READ(MAD_DIMM_C1));
1392                 sbuf_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1393                            I915_READ(MAD_DIMM_C2));
1394                 sbuf_printf(m, "TILECTL = 0x%08x\n",
1395                            I915_READ(TILECTL));
1396                 sbuf_printf(m, "ARB_MODE = 0x%08x\n",
1397                            I915_READ(ARB_MODE));
1398                 sbuf_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1399                            I915_READ(DISP_ARB_CTL));
1400         }
1401         DRM_UNLOCK(dev);
1402
1403         return (0);
1404 }
1405
1406 static int
1407 i915_ppgtt_info(struct drm_device *dev, struct sbuf *m, void *data)
1408 {
1409         struct drm_i915_private *dev_priv;
1410         struct intel_ring_buffer *ring;
1411         int i, ret;
1412
1413         dev_priv = dev->dev_private;
1414
1415         ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
1416         if (ret != 0)
1417                 return (EINTR);
1418         if (INTEL_INFO(dev)->gen == 6)
1419                 sbuf_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1420
1421         for (i = 0; i < I915_NUM_RINGS; i++) {
1422                 ring = &dev_priv->ring[i];
1423
1424                 sbuf_printf(m, "%s\n", ring->name);
1425                 if (INTEL_INFO(dev)->gen == 7)
1426                         sbuf_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1427                 sbuf_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1428                 sbuf_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1429                 sbuf_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1430         }
1431         if (dev_priv->mm.aliasing_ppgtt) {
1432                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1433
1434                 sbuf_printf(m, "aliasing PPGTT:\n");
1435                 sbuf_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1436         }
1437         sbuf_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1438         DRM_UNLOCK(dev);
1439
1440         return (0);
1441 }
1442
1443 static int
1444 i915_max_freq(SYSCTL_HANDLER_ARGS)
1445 {
1446         struct drm_device *dev;
1447         drm_i915_private_t *dev_priv;
1448         int error, max_freq;
1449
1450         dev = arg1;
1451         dev_priv = dev->dev_private;
1452         if (dev_priv == NULL)
1453                 return (EBUSY);
1454         max_freq = dev_priv->rps.max_delay * 50;
1455         error = sysctl_handle_int(oidp, &max_freq, 0, req);
1456         if (error || !req->newptr)
1457                 return (error);
1458         DRM_DEBUG("Manually setting max freq to %d\n", max_freq);
1459
1460         if (lockmgr(&dev_priv->rps.hw_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1461                 return -EINTR;
1462
1463         /*
1464          * Turbo will still be enabled, but won't go above the set value.
1465          */
1466         dev_priv->rps.max_delay = max_freq / 50;
1467
1468         gen6_set_rps(dev, max_freq / 50);
1469         lockmgr(&dev_priv->rps.hw_lock, LK_RELEASE);
1470
1471         return (error);
1472 }
1473
1474 static int
1475 i915_cache_sharing(SYSCTL_HANDLER_ARGS)
1476 {
1477         struct drm_device *dev;
1478         drm_i915_private_t *dev_priv;
1479         int error, snpcr, cache_sharing;
1480
1481         dev = arg1;
1482         dev_priv = dev->dev_private;
1483         if (dev_priv == NULL)
1484                 return (EBUSY);
1485         DRM_LOCK(dev);
1486         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1487         DRM_UNLOCK(dev);
1488         cache_sharing = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
1489         error = sysctl_handle_int(oidp, &cache_sharing, 0, req);
1490         if (error || !req->newptr)
1491                 return (error);
1492         if (cache_sharing < 0 || cache_sharing > 3)
1493                 return (EINVAL);
1494         DRM_DEBUG("Manually setting uncore sharing to %d\n", cache_sharing);
1495
1496         DRM_LOCK(dev);
1497         /* Update the cache sharing policy here as well */
1498         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1499         snpcr &= ~GEN6_MBC_SNPCR_MASK;
1500         snpcr |= (cache_sharing << GEN6_MBC_SNPCR_SHIFT);
1501         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1502         DRM_UNLOCK(dev);
1503         return (0);
1504 }
1505
1506 static struct i915_info_sysctl_list {
1507         const char *name;
1508         int (*ptr)(struct drm_device *dev, struct sbuf *m, void *data);
1509         int flags;
1510         void *data;
1511 } i915_info_sysctl_list[] = {
1512         {"i915_capabilities", i915_capabilities, 0},
1513         {"i915_gem_objects", i915_gem_object_info, 0},
1514         {"i915_gem_gtt", i915_gem_gtt_info, 0},
1515         {"i915_gem_active", i915_gem_object_list_info, 0, (void *)ACTIVE_LIST},
1516         {"i915_gem_flushing", i915_gem_object_list_info, 0,
1517             (void *)FLUSHING_LIST},
1518         {"i915_gem_inactive", i915_gem_object_list_info, 0,
1519             (void *)INACTIVE_LIST},
1520         {"i915_gem_pinned", i915_gem_object_list_info, 0,
1521             (void *)PINNED_LIST},
1522         {"i915_gem_deferred_free", i915_gem_object_list_info, 0,
1523             (void *)DEFERRED_FREE_LIST},
1524         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
1525         {"i915_gem_request", i915_gem_request_info, 0},
1526         {"i915_gem_seqno", i915_gem_seqno_info, 0},
1527         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
1528         {"i915_gem_interrupt", i915_interrupt_info, 0},
1529         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
1530         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
1531         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
1532         {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS},
1533         {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS},
1534         {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS},
1535         {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS},
1536         {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS},
1537         {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS},
1538         {"i915_error_state", i915_error_state, 0},
1539         {"i915_rstdby_delays", i915_rstdby_delays, 0},
1540         {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
1541         {"i915_delayfreq_table", i915_delayfreq_table, 0},
1542         {"i915_inttoext_table", i915_inttoext_table, 0},
1543         {"i915_drpc_info", i915_drpc_info, 0},
1544         {"i915_emon_status", i915_emon_status, 0},
1545         {"i915_ring_freq_table", i915_ring_freq_table, 0},
1546         {"i915_gfxec", i915_gfxec, 0},
1547         {"i915_fbc_status", i915_fbc_status, 0},
1548         {"i915_sr_status", i915_sr_status, 0},
1549 #if 0
1550         {"i915_opregion", i915_opregion, 0},
1551 #endif
1552         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
1553         {"i915_context_status", i915_context_status, 0},
1554         {"i915_gen6_forcewake_count_info", i915_gen6_forcewake_count_info, 0},
1555         {"i915_swizzle_info", i915_swizzle_info, 0},
1556         {"i915_ppgtt_info", i915_ppgtt_info, 0},
1557 };
1558
1559 struct i915_info_sysctl_thunk {
1560         struct drm_device *dev;
1561         int idx;
1562         void *arg;
1563 };
1564
1565 static int
1566 i915_info_sysctl_handler(SYSCTL_HANDLER_ARGS)
1567 {
1568 #if 0
1569         struct sbuf m;
1570 #endif
1571         struct i915_info_sysctl_thunk *thunk;
1572         struct drm_device *dev;
1573         drm_i915_private_t *dev_priv;
1574         int error;
1575
1576         thunk = arg1;
1577         dev = thunk->dev;
1578         dev_priv = dev->dev_private;
1579         if (dev_priv == NULL)
1580                 return (EBUSY);
1581 #if 0
1582         error = sysctl_wire_old_buffer(req, 0);
1583         if (error != 0)
1584                 return (error);
1585         sbuf_new_for_sysctl(&m, NULL, 128, req);
1586         error = i915_info_sysctl_list[thunk->idx].ptr(dev, &m,
1587             thunk->arg);
1588         if (error == 0)
1589                 error = sbuf_finish(&m);
1590         sbuf_delete(&m);
1591 #else
1592         error = 0;
1593 #endif
1594         return (error);
1595 }
1596
1597 extern int i915_gem_sync_exec_requests;
1598 extern int i915_fix_mi_batchbuffer_end;
1599 extern int i915_intr_pf;
1600 extern long i915_gem_wired_pages_cnt;
1601
1602 int
1603 i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx,
1604     struct sysctl_oid *top)
1605 {
1606         struct sysctl_oid *oid, *info;
1607         struct i915_info_sysctl_thunk *thunks;
1608         int i, error;
1609
1610         thunks = kmalloc(sizeof(*thunks) * DRM_ARRAY_SIZE(i915_info_sysctl_list),
1611             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
1612         for (i = 0; i < DRM_ARRAY_SIZE(i915_info_sysctl_list); i++) {
1613                 thunks[i].dev = dev;
1614                 thunks[i].idx = i;
1615                 thunks[i].arg = i915_info_sysctl_list[i].data;
1616         }
1617         dev->sysctl_private = thunks;
1618         info = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "info",
1619             CTLFLAG_RW, NULL, NULL);
1620         if (info == NULL)
1621                 return (ENOMEM);
1622         for (i = 0; i < DRM_ARRAY_SIZE(i915_info_sysctl_list); i++) {
1623                 oid = SYSCTL_ADD_OID(ctx, SYSCTL_CHILDREN(info), OID_AUTO,
1624                     i915_info_sysctl_list[i].name, CTLTYPE_STRING | CTLFLAG_RD,
1625                     &thunks[i], 0, i915_info_sysctl_handler, "A", NULL);
1626                 if (oid == NULL)
1627                         return (ENOMEM);
1628         }
1629         oid = SYSCTL_ADD_LONG(ctx, SYSCTL_CHILDREN(info), OID_AUTO,
1630             "i915_gem_wired_pages", CTLFLAG_RD, &i915_gem_wired_pages_cnt,
1631             NULL);
1632         if (oid == NULL)
1633                 return (ENOMEM);
1634         oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "max_freq",
1635             CTLTYPE_INT | CTLFLAG_RW, dev, 0, i915_max_freq,
1636             "I", NULL);
1637         if (oid == NULL)
1638                 return (ENOMEM);
1639         oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO,
1640             "cache_sharing", CTLTYPE_INT | CTLFLAG_RW, dev,
1641             0, i915_cache_sharing, "I", NULL);
1642         if (oid == NULL)
1643                 return (ENOMEM);
1644         oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "sync_exec",
1645             CTLFLAG_RW, &i915_gem_sync_exec_requests, 0, NULL);
1646         if (oid == NULL)
1647                 return (ENOMEM);
1648         oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "fix_mi",
1649             CTLFLAG_RW, &i915_fix_mi_batchbuffer_end, 0, NULL);
1650         if (oid == NULL)
1651                 return (ENOMEM);
1652         oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "intr_pf",
1653             CTLFLAG_RW, &i915_intr_pf, 0, NULL);
1654         if (oid == NULL)
1655                 return (ENOMEM);
1656
1657         error = drm_add_busid_modesetting(dev, ctx, top);
1658         if (error != 0)
1659                 return (error);
1660
1661         return (0);
1662 }
1663
1664 void
1665 i915_sysctl_cleanup(struct drm_device *dev)
1666 {
1667
1668         drm_free(dev->sysctl_private, DRM_MEM_DRIVER);
1669 }