2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
71 #include <sys/param.h>
73 #include <sys/endian.h>
74 #include <sys/interrupt.h>
75 #include <sys/kernel.h>
77 #include <sys/malloc.h>
81 #include <sys/serialize.h>
82 #include <sys/serialize2.h>
83 #include <sys/socket.h>
84 #include <sys/sockio.h>
85 #include <sys/sysctl.h>
86 #include <sys/systm.h>
89 #include <net/ethernet.h>
91 #include <net/if_arp.h>
92 #include <net/if_dl.h>
93 #include <net/if_media.h>
94 #include <net/ifq_var.h>
95 #include <net/toeplitz.h>
96 #include <net/toeplitz2.h>
97 #include <net/vlan/if_vlan_var.h>
98 #include <net/vlan/if_vlan_ether.h>
99 #include <net/if_poll.h>
101 #include <netinet/in_systm.h>
102 #include <netinet/in.h>
103 #include <netinet/ip.h>
104 #include <netinet/tcp.h>
105 #include <netinet/udp.h>
107 #include <bus/pci/pcivar.h>
108 #include <bus/pci/pcireg.h>
110 #include <dev/netif/ig_hal/e1000_api.h>
111 #include <dev/netif/ig_hal/e1000_82571.h>
112 #include <dev/netif/emx/if_emx.h>
115 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
117 if (sc->rss_debug >= lvl) \
118 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
120 #else /* !EMX_RSS_DEBUG */
121 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
122 #endif /* EMX_RSS_DEBUG */
124 #define EMX_NAME "Intel(R) PRO/1000 "
126 #define EMX_DEVICE(id) \
127 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
128 #define EMX_DEVICE_NULL { 0, 0, NULL }
130 static const struct emx_device {
135 EMX_DEVICE(82571EB_COPPER),
136 EMX_DEVICE(82571EB_FIBER),
137 EMX_DEVICE(82571EB_SERDES),
138 EMX_DEVICE(82571EB_SERDES_DUAL),
139 EMX_DEVICE(82571EB_SERDES_QUAD),
140 EMX_DEVICE(82571EB_QUAD_COPPER),
141 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
142 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
143 EMX_DEVICE(82571EB_QUAD_FIBER),
144 EMX_DEVICE(82571PT_QUAD_COPPER),
146 EMX_DEVICE(82572EI_COPPER),
147 EMX_DEVICE(82572EI_FIBER),
148 EMX_DEVICE(82572EI_SERDES),
152 EMX_DEVICE(82573E_IAMT),
155 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
156 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
157 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
163 /* required last entry */
167 static int emx_probe(device_t);
168 static int emx_attach(device_t);
169 static int emx_detach(device_t);
170 static int emx_shutdown(device_t);
171 static int emx_suspend(device_t);
172 static int emx_resume(device_t);
174 static void emx_init(void *);
175 static void emx_stop(struct emx_softc *);
176 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
177 static void emx_start(struct ifnet *);
179 static void emx_qpoll(struct ifnet *, struct ifpoll_info *);
181 static void emx_watchdog(struct ifnet *);
182 static void emx_media_status(struct ifnet *, struct ifmediareq *);
183 static int emx_media_change(struct ifnet *);
184 static void emx_timer(void *);
185 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
186 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
187 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
189 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
193 static void emx_intr(void *);
194 static void emx_rxeof(struct emx_softc *, int, int);
195 static void emx_txeof(struct emx_softc *);
196 static void emx_tx_collect(struct emx_softc *);
197 static void emx_tx_purge(struct emx_softc *);
198 static void emx_enable_intr(struct emx_softc *);
199 static void emx_disable_intr(struct emx_softc *);
201 static int emx_dma_alloc(struct emx_softc *);
202 static void emx_dma_free(struct emx_softc *);
203 static void emx_init_tx_ring(struct emx_softc *);
204 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
205 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
206 static int emx_create_tx_ring(struct emx_softc *);
207 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
208 static void emx_destroy_tx_ring(struct emx_softc *, int);
209 static void emx_destroy_rx_ring(struct emx_softc *,
210 struct emx_rxdata *, int);
211 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
212 static int emx_encap(struct emx_softc *, struct mbuf **);
213 static int emx_txcsum_pullup(struct emx_softc *, struct mbuf **);
214 static int emx_txcsum(struct emx_softc *, struct mbuf *,
215 uint32_t *, uint32_t *);
217 static int emx_is_valid_eaddr(const uint8_t *);
218 static int emx_reset(struct emx_softc *);
219 static void emx_setup_ifp(struct emx_softc *);
220 static void emx_init_tx_unit(struct emx_softc *);
221 static void emx_init_rx_unit(struct emx_softc *);
222 static void emx_update_stats(struct emx_softc *);
223 static void emx_set_promisc(struct emx_softc *);
224 static void emx_disable_promisc(struct emx_softc *);
225 static void emx_set_multi(struct emx_softc *);
226 static void emx_update_link_status(struct emx_softc *);
227 static void emx_smartspeed(struct emx_softc *);
228 static void emx_set_itr(struct emx_softc *, uint32_t);
229 static void emx_disable_aspm(struct emx_softc *);
231 static void emx_print_debug_info(struct emx_softc *);
232 static void emx_print_nvm_info(struct emx_softc *);
233 static void emx_print_hw_stats(struct emx_softc *);
235 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
236 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
237 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
238 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
239 static void emx_add_sysctl(struct emx_softc *);
241 static void emx_serialize_skipmain(struct emx_softc *);
242 static void emx_deserialize_skipmain(struct emx_softc *);
244 /* Management and WOL Support */
245 static void emx_get_mgmt(struct emx_softc *);
246 static void emx_rel_mgmt(struct emx_softc *);
247 static void emx_get_hw_control(struct emx_softc *);
248 static void emx_rel_hw_control(struct emx_softc *);
249 static void emx_enable_wol(device_t);
251 static device_method_t emx_methods[] = {
252 /* Device interface */
253 DEVMETHOD(device_probe, emx_probe),
254 DEVMETHOD(device_attach, emx_attach),
255 DEVMETHOD(device_detach, emx_detach),
256 DEVMETHOD(device_shutdown, emx_shutdown),
257 DEVMETHOD(device_suspend, emx_suspend),
258 DEVMETHOD(device_resume, emx_resume),
262 static driver_t emx_driver = {
265 sizeof(struct emx_softc),
268 static devclass_t emx_devclass;
270 DECLARE_DUMMY_MODULE(if_emx);
271 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
272 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
277 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
278 static int emx_rxd = EMX_DEFAULT_RXD;
279 static int emx_txd = EMX_DEFAULT_TXD;
280 static int emx_smart_pwr_down = 0;
282 /* Controls whether promiscuous also shows bad packets */
283 static int emx_debug_sbp = FALSE;
285 static int emx_82573_workaround = 1;
286 static int emx_msi_enable = 1;
288 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
289 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
290 TUNABLE_INT("hw.emx.txd", &emx_txd);
291 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
292 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
293 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
294 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
296 /* Global used in WOL setup with multiport cards */
297 static int emx_global_quad_port_a = 0;
299 /* Set this to one to display debug statistics */
300 static int emx_display_debug_stats = 0;
302 #if !defined(KTR_IF_EMX)
303 #define KTR_IF_EMX KTR_ALL
305 KTR_INFO_MASTER(if_emx);
306 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
307 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
308 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
309 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
310 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
311 #define logif(name) KTR_LOG(if_emx_ ## name)
314 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
316 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
317 /* DD bit must be cleared */
318 rxd->rxd_staterr = 0;
322 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
324 /* Ignore Checksum bit is set */
325 if (staterr & E1000_RXD_STAT_IXSM)
328 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
330 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
332 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
333 E1000_RXD_STAT_TCPCS) {
334 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
336 CSUM_FRAG_NOT_CHECKED;
337 mp->m_pkthdr.csum_data = htons(0xffff);
341 static __inline struct pktinfo *
342 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
343 uint32_t mrq, uint32_t hash, uint32_t staterr)
345 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
346 case EMX_RXDMRQ_IPV4_TCP:
347 pi->pi_netisr = NETISR_IP;
349 pi->pi_l3proto = IPPROTO_TCP;
352 case EMX_RXDMRQ_IPV6_TCP:
353 pi->pi_netisr = NETISR_IPV6;
355 pi->pi_l3proto = IPPROTO_TCP;
358 case EMX_RXDMRQ_IPV4:
359 if (staterr & E1000_RXD_STAT_IXSM)
363 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
364 E1000_RXD_STAT_TCPCS) {
365 pi->pi_netisr = NETISR_IP;
367 pi->pi_l3proto = IPPROTO_UDP;
375 m->m_flags |= M_HASH;
376 m->m_pkthdr.hash = toeplitz_hash(hash);
381 emx_probe(device_t dev)
383 const struct emx_device *d;
386 vid = pci_get_vendor(dev);
387 did = pci_get_device(dev);
389 for (d = emx_devices; d->desc != NULL; ++d) {
390 if (vid == d->vid && did == d->did) {
391 device_set_desc(dev, d->desc);
392 device_set_async_attach(dev, TRUE);
400 emx_attach(device_t dev)
402 struct emx_softc *sc = device_get_softc(dev);
403 struct ifnet *ifp = &sc->arpcom.ac_if;
406 uint16_t eeprom_data, device_id, apme_mask;
408 lwkt_serialize_init(&sc->main_serialize);
409 lwkt_serialize_init(&sc->tx_serialize);
410 for (i = 0; i < EMX_NRX_RING; ++i)
411 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
414 sc->serializes[i++] = &sc->main_serialize;
415 sc->serializes[i++] = &sc->tx_serialize;
416 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
417 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
418 KKASSERT(i == EMX_NSERIALIZE);
420 callout_init_mp(&sc->timer);
422 sc->dev = sc->osdep.dev = dev;
425 * Determine hardware and mac type
427 sc->hw.vendor_id = pci_get_vendor(dev);
428 sc->hw.device_id = pci_get_device(dev);
429 sc->hw.revision_id = pci_get_revid(dev);
430 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
431 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
433 if (e1000_set_mac_type(&sc->hw))
436 /* Enable bus mastering */
437 pci_enable_busmaster(dev);
442 sc->memory_rid = EMX_BAR_MEM;
443 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
444 &sc->memory_rid, RF_ACTIVE);
445 if (sc->memory == NULL) {
446 device_printf(dev, "Unable to allocate bus resource: memory\n");
450 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
451 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
453 /* XXX This is quite goofy, it is not actually used */
454 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
459 sc->intr_type = pci_alloc_1intr(dev, emx_msi_enable,
460 &sc->intr_rid, &intr_flags);
462 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
464 if (sc->intr_res == NULL) {
465 device_printf(dev, "Unable to allocate bus resource: "
471 /* Save PCI command register for Shared Code */
472 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
473 sc->hw.back = &sc->osdep;
475 /* Do Shared Code initialization */
476 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
477 device_printf(dev, "Setup of Shared code failed\n");
481 e1000_get_bus_info(&sc->hw);
483 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
484 sc->hw.phy.autoneg_wait_to_complete = FALSE;
485 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
488 * Interrupt throttle rate
490 if (emx_int_throttle_ceil == 0) {
491 sc->int_throttle_ceil = 0;
493 int throttle = emx_int_throttle_ceil;
496 throttle = EMX_DEFAULT_ITR;
498 /* Recalculate the tunable value to get the exact frequency. */
499 throttle = 1000000000 / 256 / throttle;
501 /* Upper 16bits of ITR is reserved and should be zero */
502 if (throttle & 0xffff0000)
503 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
505 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
508 e1000_init_script_state_82541(&sc->hw, TRUE);
509 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
512 if (sc->hw.phy.media_type == e1000_media_type_copper) {
513 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
514 sc->hw.phy.disable_polarity_correction = FALSE;
515 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
518 /* Set the frame limits assuming standard ethernet sized frames. */
519 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
520 sc->min_frame_size = ETHER_MIN_LEN;
522 /* This controls when hardware reports transmit completion status. */
523 sc->hw.mac.report_tx_early = 1;
525 /* Calculate # of RX rings */
527 sc->rx_ring_cnt = EMX_NRX_RING;
530 sc->rx_ring_inuse = sc->rx_ring_cnt;
532 /* Allocate RX/TX rings' busdma(9) stuffs */
533 error = emx_dma_alloc(sc);
537 /* Allocate multicast array memory. */
538 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
541 /* Indicate SOL/IDER usage */
542 if (e1000_check_reset_block(&sc->hw)) {
544 "PHY reset is blocked due to SOL/IDER session.\n");
548 * Start from a known state, this is important in reading the
549 * nvm and mac from that.
551 e1000_reset_hw(&sc->hw);
553 /* Make sure we have a good EEPROM before we read from it */
554 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
556 * Some PCI-E parts fail the first check due to
557 * the link being in sleep state, call it again,
558 * if it fails a second time its a real issue.
560 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
562 "The EEPROM Checksum Is Not Valid\n");
568 /* Copy the permanent MAC address out of the EEPROM */
569 if (e1000_read_mac_addr(&sc->hw) < 0) {
570 device_printf(dev, "EEPROM read error while reading MAC"
575 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
576 device_printf(dev, "Invalid MAC address\n");
581 /* Determine if we have to control management hardware */
582 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
587 apme_mask = EMX_EEPROM_APME;
589 switch (sc->hw.mac.type) {
596 case e1000_80003es2lan:
597 if (sc->hw.bus.func == 1) {
598 e1000_read_nvm(&sc->hw,
599 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
601 e1000_read_nvm(&sc->hw,
602 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
607 e1000_read_nvm(&sc->hw,
608 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
611 if (eeprom_data & apme_mask)
612 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
615 * We have the eeprom settings, now apply the special cases
616 * where the eeprom may be wrong or the board won't support
617 * wake on lan on a particular port
619 device_id = pci_get_device(dev);
621 case E1000_DEV_ID_82571EB_FIBER:
623 * Wake events only supported on port A for dual fiber
624 * regardless of eeprom setting
626 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
631 case E1000_DEV_ID_82571EB_QUAD_COPPER:
632 case E1000_DEV_ID_82571EB_QUAD_FIBER:
633 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
634 /* if quad port sc, disable WoL on all but port A */
635 if (emx_global_quad_port_a != 0)
637 /* Reset for multiple quad port adapters */
638 if (++emx_global_quad_port_a == 4)
639 emx_global_quad_port_a = 0;
643 /* XXX disable wol */
646 /* Setup OS specific network interface */
649 /* Add sysctl tree, must after em_setup_ifp() */
652 /* Reset the hardware */
653 error = emx_reset(sc);
655 device_printf(dev, "Unable to reset the hardware\n");
659 /* Initialize statistics */
660 emx_update_stats(sc);
662 sc->hw.mac.get_link_status = 1;
663 emx_update_link_status(sc);
665 sc->spare_tx_desc = EMX_TX_SPARE;
668 * Keep following relationship between spare_tx_desc, oact_tx_desc
670 * (spare_tx_desc + EMX_TX_RESERVED) <=
671 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
673 sc->oact_tx_desc = sc->num_tx_desc / 8;
674 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
675 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
676 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
677 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
679 sc->tx_int_nsegs = sc->num_tx_desc / 16;
680 if (sc->tx_int_nsegs < sc->oact_tx_desc)
681 sc->tx_int_nsegs = sc->oact_tx_desc;
683 /* Non-AMT based hardware can now take control from firmware */
684 if (sc->has_manage && !sc->has_amt)
685 emx_get_hw_control(sc);
687 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, emx_intr, sc,
688 &sc->intr_tag, &sc->main_serialize);
690 device_printf(dev, "Failed to register interrupt handler");
691 ether_ifdetach(&sc->arpcom.ac_if);
695 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
696 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
704 emx_detach(device_t dev)
706 struct emx_softc *sc = device_get_softc(dev);
708 if (device_is_attached(dev)) {
709 struct ifnet *ifp = &sc->arpcom.ac_if;
711 ifnet_serialize_all(ifp);
715 e1000_phy_hw_reset(&sc->hw);
718 emx_rel_hw_control(sc);
721 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
722 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
726 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
728 ifnet_deserialize_all(ifp);
732 emx_rel_hw_control(sc);
734 bus_generic_detach(dev);
736 if (sc->intr_res != NULL) {
737 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
741 if (sc->intr_type == PCI_INTR_TYPE_MSI)
742 pci_release_msi(dev);
744 if (sc->memory != NULL) {
745 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
751 /* Free sysctl tree */
752 if (sc->sysctl_tree != NULL)
753 sysctl_ctx_free(&sc->sysctl_ctx);
759 emx_shutdown(device_t dev)
761 return emx_suspend(dev);
765 emx_suspend(device_t dev)
767 struct emx_softc *sc = device_get_softc(dev);
768 struct ifnet *ifp = &sc->arpcom.ac_if;
770 ifnet_serialize_all(ifp);
775 emx_rel_hw_control(sc);
778 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
779 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
783 ifnet_deserialize_all(ifp);
785 return bus_generic_suspend(dev);
789 emx_resume(device_t dev)
791 struct emx_softc *sc = device_get_softc(dev);
792 struct ifnet *ifp = &sc->arpcom.ac_if;
794 ifnet_serialize_all(ifp);
800 ifnet_deserialize_all(ifp);
802 return bus_generic_resume(dev);
806 emx_start(struct ifnet *ifp)
808 struct emx_softc *sc = ifp->if_softc;
811 ASSERT_SERIALIZED(&sc->tx_serialize);
813 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
816 if (!sc->link_active) {
817 ifq_purge(&ifp->if_snd);
821 while (!ifq_is_empty(&ifp->if_snd)) {
822 /* Now do we at least have a minimal? */
823 if (EMX_IS_OACTIVE(sc)) {
825 if (EMX_IS_OACTIVE(sc)) {
826 ifp->if_flags |= IFF_OACTIVE;
827 sc->no_tx_desc_avail1++;
833 m_head = ifq_dequeue(&ifp->if_snd, NULL);
837 if (emx_encap(sc, &m_head)) {
843 /* Send a copy of the frame to the BPF listener */
844 ETHER_BPF_MTAP(ifp, m_head);
846 /* Set timeout in case hardware has problems transmitting. */
847 ifp->if_timer = EMX_TX_TIMEOUT;
852 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
854 struct emx_softc *sc = ifp->if_softc;
855 struct ifreq *ifr = (struct ifreq *)data;
856 uint16_t eeprom_data = 0;
857 int max_frame_size, mask, reinit;
860 ASSERT_IFNET_SERIALIZED_ALL(ifp);
864 switch (sc->hw.mac.type) {
867 * 82573 only supports jumbo frames
868 * if ASPM is disabled.
870 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
872 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
873 max_frame_size = ETHER_MAX_LEN;
878 /* Limit Jumbo Frame size */
882 case e1000_80003es2lan:
883 max_frame_size = 9234;
887 max_frame_size = MAX_JUMBO_FRAME_SIZE;
890 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
896 ifp->if_mtu = ifr->ifr_mtu;
897 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
900 if (ifp->if_flags & IFF_RUNNING)
905 if (ifp->if_flags & IFF_UP) {
906 if ((ifp->if_flags & IFF_RUNNING)) {
907 if ((ifp->if_flags ^ sc->if_flags) &
908 (IFF_PROMISC | IFF_ALLMULTI)) {
909 emx_disable_promisc(sc);
915 } else if (ifp->if_flags & IFF_RUNNING) {
918 sc->if_flags = ifp->if_flags;
923 if (ifp->if_flags & IFF_RUNNING) {
924 emx_disable_intr(sc);
927 if (!(ifp->if_flags & IFF_NPOLLING))
934 /* Check SOL/IDER usage */
935 if (e1000_check_reset_block(&sc->hw)) {
936 device_printf(sc->dev, "Media change is"
937 " blocked due to SOL/IDER session.\n");
943 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
948 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
949 if (mask & IFCAP_HWCSUM) {
950 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
953 if (mask & IFCAP_VLAN_HWTAGGING) {
954 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
957 if (mask & IFCAP_RSS) {
958 ifp->if_capenable ^= IFCAP_RSS;
961 if (reinit && (ifp->if_flags & IFF_RUNNING))
966 error = ether_ioctl(ifp, command, data);
973 emx_watchdog(struct ifnet *ifp)
975 struct emx_softc *sc = ifp->if_softc;
977 ASSERT_IFNET_SERIALIZED_ALL(ifp);
980 * The timer is set to 5 every time start queues a packet.
981 * Then txeof keeps resetting it as long as it cleans at
982 * least one descriptor.
983 * Finally, anytime all descriptors are clean the timer is
987 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
988 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
990 * If we reach here, all TX jobs are completed and
991 * the TX engine should have been idled for some time.
992 * We don't need to call if_devstart() here.
994 ifp->if_flags &= ~IFF_OACTIVE;
1000 * If we are in this routine because of pause frames, then
1001 * don't reset the hardware.
1003 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1004 ifp->if_timer = EMX_TX_TIMEOUT;
1008 if (e1000_check_for_link(&sc->hw) == 0)
1009 if_printf(ifp, "watchdog timeout -- resetting\n");
1012 sc->watchdog_events++;
1016 if (!ifq_is_empty(&ifp->if_snd))
1023 struct emx_softc *sc = xsc;
1024 struct ifnet *ifp = &sc->arpcom.ac_if;
1025 device_t dev = sc->dev;
1029 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1034 * Packet Buffer Allocation (PBA)
1035 * Writing PBA sets the receive portion of the buffer
1036 * the remainder is used for the transmit buffer.
1038 switch (sc->hw.mac.type) {
1039 /* Total Packet Buffer on these is 48K */
1042 case e1000_80003es2lan:
1043 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1046 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1047 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1051 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1055 /* Devices before 82547 had a Packet Buffer of 64K. */
1056 if (sc->max_frame_size > 8192)
1057 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1059 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1061 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1063 /* Get the latest mac address, User can use a LAA */
1064 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1066 /* Put the address into the Receive Address Array */
1067 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1070 * With the 82571 sc, RAR[0] may be overwritten
1071 * when the other port is reset, we make a duplicate
1072 * in RAR[14] for that eventuality, this assures
1073 * the interface continues to function.
1075 if (sc->hw.mac.type == e1000_82571) {
1076 e1000_set_laa_state_82571(&sc->hw, TRUE);
1077 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1078 E1000_RAR_ENTRIES - 1);
1081 /* Initialize the hardware */
1082 if (emx_reset(sc)) {
1083 device_printf(dev, "Unable to reset the hardware\n");
1084 /* XXX emx_stop()? */
1087 emx_update_link_status(sc);
1089 /* Setup VLAN support, basic and offload if available */
1090 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1092 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1095 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1096 ctrl |= E1000_CTRL_VME;
1097 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1100 /* Set hardware offload abilities */
1101 if (ifp->if_capenable & IFCAP_TXCSUM)
1102 ifp->if_hwassist = EMX_CSUM_FEATURES;
1104 ifp->if_hwassist = 0;
1106 /* Configure for OS presence */
1109 /* Prepare transmit descriptors and buffers */
1110 emx_init_tx_ring(sc);
1111 emx_init_tx_unit(sc);
1113 /* Setup Multicast table */
1117 * Adjust # of RX ring to be used based on IFCAP_RSS
1119 if (ifp->if_capenable & IFCAP_RSS)
1120 sc->rx_ring_inuse = sc->rx_ring_cnt;
1122 sc->rx_ring_inuse = 1;
1124 /* Prepare receive descriptors and buffers */
1125 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1126 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1128 "Could not setup receive structures\n");
1133 emx_init_rx_unit(sc);
1135 /* Don't lose promiscuous settings */
1136 emx_set_promisc(sc);
1138 ifp->if_flags |= IFF_RUNNING;
1139 ifp->if_flags &= ~IFF_OACTIVE;
1141 callout_reset(&sc->timer, hz, emx_timer, sc);
1142 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1144 /* MSI/X configuration for 82574 */
1145 if (sc->hw.mac.type == e1000_82574) {
1148 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1149 tmp |= E1000_CTRL_EXT_PBA_CLR;
1150 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1153 * Set the IVAR - interrupt vector routing.
1154 * Each nibble represents a vector, high bit
1155 * is enable, other 3 bits are the MSIX table
1156 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1157 * Link (other) to 2, hence the magic number.
1159 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1162 #ifdef IFPOLL_ENABLE
1164 * Only enable interrupts if we are not polling, make sure
1165 * they are off otherwise.
1167 if (ifp->if_flags & IFF_NPOLLING)
1168 emx_disable_intr(sc);
1170 #endif /* IFPOLL_ENABLE */
1171 emx_enable_intr(sc);
1173 /* AMT based hardware can now take control from firmware */
1174 if (sc->has_manage && sc->has_amt)
1175 emx_get_hw_control(sc);
1177 /* Don't reset the phy next time init gets called */
1178 sc->hw.phy.reset_disable = TRUE;
1184 struct emx_softc *sc = xsc;
1185 struct ifnet *ifp = &sc->arpcom.ac_if;
1189 ASSERT_SERIALIZED(&sc->main_serialize);
1191 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1193 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1199 * XXX: some laptops trigger several spurious interrupts
1200 * on emx(4) when in the resume cycle. The ICR register
1201 * reports all-ones value in this case. Processing such
1202 * interrupts would lead to a freeze. I don't know why.
1204 if (reg_icr == 0xffffffff) {
1209 if (ifp->if_flags & IFF_RUNNING) {
1211 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1214 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1215 lwkt_serialize_enter(
1216 &sc->rx_data[i].rx_serialize);
1217 emx_rxeof(sc, i, -1);
1218 lwkt_serialize_exit(
1219 &sc->rx_data[i].rx_serialize);
1222 if (reg_icr & E1000_ICR_TXDW) {
1223 lwkt_serialize_enter(&sc->tx_serialize);
1225 if (!ifq_is_empty(&ifp->if_snd))
1227 lwkt_serialize_exit(&sc->tx_serialize);
1231 /* Link status change */
1232 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1233 emx_serialize_skipmain(sc);
1235 callout_stop(&sc->timer);
1236 sc->hw.mac.get_link_status = 1;
1237 emx_update_link_status(sc);
1239 /* Deal with TX cruft when link lost */
1242 callout_reset(&sc->timer, hz, emx_timer, sc);
1244 emx_deserialize_skipmain(sc);
1247 if (reg_icr & E1000_ICR_RXO)
1254 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1256 struct emx_softc *sc = ifp->if_softc;
1258 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1260 emx_update_link_status(sc);
1262 ifmr->ifm_status = IFM_AVALID;
1263 ifmr->ifm_active = IFM_ETHER;
1265 if (!sc->link_active)
1268 ifmr->ifm_status |= IFM_ACTIVE;
1270 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1271 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1272 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1274 switch (sc->link_speed) {
1276 ifmr->ifm_active |= IFM_10_T;
1279 ifmr->ifm_active |= IFM_100_TX;
1283 ifmr->ifm_active |= IFM_1000_T;
1286 if (sc->link_duplex == FULL_DUPLEX)
1287 ifmr->ifm_active |= IFM_FDX;
1289 ifmr->ifm_active |= IFM_HDX;
1294 emx_media_change(struct ifnet *ifp)
1296 struct emx_softc *sc = ifp->if_softc;
1297 struct ifmedia *ifm = &sc->media;
1299 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1301 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1304 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1306 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1307 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1313 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1314 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1318 sc->hw.mac.autoneg = FALSE;
1319 sc->hw.phy.autoneg_advertised = 0;
1320 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1321 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1323 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1327 sc->hw.mac.autoneg = FALSE;
1328 sc->hw.phy.autoneg_advertised = 0;
1329 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1330 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1332 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1336 if_printf(ifp, "Unsupported media type\n");
1341 * As the speed/duplex settings my have changed we need to
1344 sc->hw.phy.reset_disable = FALSE;
1352 emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1354 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1356 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1357 struct e1000_tx_desc *ctxd = NULL;
1358 struct mbuf *m_head = *m_headp;
1359 uint32_t txd_upper, txd_lower, cmd = 0;
1360 int maxsegs, nsegs, i, j, first, last = 0, error;
1362 if (m_head->m_len < EMX_TXCSUM_MINHL &&
1363 (m_head->m_flags & EMX_CSUM_FEATURES)) {
1365 * Make sure that ethernet header and ip.ip_hl are in
1366 * contiguous memory, since if TXCSUM is enabled, later
1367 * TX context descriptor's setup need to access ip.ip_hl.
1369 error = emx_txcsum_pullup(sc, m_headp);
1371 KKASSERT(*m_headp == NULL);
1377 txd_upper = txd_lower = 0;
1380 * Capture the first descriptor index, this descriptor
1381 * will have the index of the EOP which is the only one
1382 * that now gets a DONE bit writeback.
1384 first = sc->next_avail_tx_desc;
1385 tx_buffer = &sc->tx_buf[first];
1386 tx_buffer_mapped = tx_buffer;
1387 map = tx_buffer->map;
1389 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
1390 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc\n"));
1391 if (maxsegs > EMX_MAX_SCATTER)
1392 maxsegs = EMX_MAX_SCATTER;
1394 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1395 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1397 if (error == ENOBUFS)
1398 sc->mbuf_alloc_failed++;
1400 sc->no_tx_dma_setup++;
1406 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1409 sc->tx_nsegs += nsegs;
1411 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1412 /* TX csum offloading will consume one TX desc */
1413 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1415 i = sc->next_avail_tx_desc;
1417 /* Set up our transmit descriptors */
1418 for (j = 0; j < nsegs; j++) {
1419 tx_buffer = &sc->tx_buf[i];
1420 ctxd = &sc->tx_desc_base[i];
1422 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1423 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1424 txd_lower | segs[j].ds_len);
1425 ctxd->upper.data = htole32(txd_upper);
1428 if (++i == sc->num_tx_desc)
1432 sc->next_avail_tx_desc = i;
1434 KKASSERT(sc->num_tx_desc_avail > nsegs);
1435 sc->num_tx_desc_avail -= nsegs;
1437 /* Handle VLAN tag */
1438 if (m_head->m_flags & M_VLANTAG) {
1439 /* Set the vlan id. */
1440 ctxd->upper.fields.special =
1441 htole16(m_head->m_pkthdr.ether_vlantag);
1443 /* Tell hardware to add tag */
1444 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1447 tx_buffer->m_head = m_head;
1448 tx_buffer_mapped->map = tx_buffer->map;
1449 tx_buffer->map = map;
1451 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1455 * Report Status (RS) is turned on
1456 * every tx_int_nsegs descriptors.
1458 cmd = E1000_TXD_CMD_RS;
1461 * Keep track of the descriptor, which will
1462 * be written back by hardware.
1464 sc->tx_dd[sc->tx_dd_tail] = last;
1465 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1466 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1470 * Last Descriptor of Packet needs End Of Packet (EOP)
1472 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1475 * Advance the Transmit Descriptor Tail (TDT), this tells
1476 * the E1000 that this frame is available to transmit.
1478 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1484 emx_set_promisc(struct emx_softc *sc)
1486 struct ifnet *ifp = &sc->arpcom.ac_if;
1489 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1491 if (ifp->if_flags & IFF_PROMISC) {
1492 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1493 /* Turn this on if you want to see bad packets */
1495 reg_rctl |= E1000_RCTL_SBP;
1496 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1497 } else if (ifp->if_flags & IFF_ALLMULTI) {
1498 reg_rctl |= E1000_RCTL_MPE;
1499 reg_rctl &= ~E1000_RCTL_UPE;
1500 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1505 emx_disable_promisc(struct emx_softc *sc)
1509 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1511 reg_rctl &= ~E1000_RCTL_UPE;
1512 reg_rctl &= ~E1000_RCTL_MPE;
1513 reg_rctl &= ~E1000_RCTL_SBP;
1514 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1518 emx_set_multi(struct emx_softc *sc)
1520 struct ifnet *ifp = &sc->arpcom.ac_if;
1521 struct ifmultiaddr *ifma;
1522 uint32_t reg_rctl = 0;
1527 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1529 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1530 if (ifma->ifma_addr->sa_family != AF_LINK)
1533 if (mcnt == EMX_MCAST_ADDR_MAX)
1536 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1537 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1541 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1542 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1543 reg_rctl |= E1000_RCTL_MPE;
1544 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1546 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1551 * This routine checks for link status and updates statistics.
1554 emx_timer(void *xsc)
1556 struct emx_softc *sc = xsc;
1557 struct ifnet *ifp = &sc->arpcom.ac_if;
1559 ifnet_serialize_all(ifp);
1561 emx_update_link_status(sc);
1562 emx_update_stats(sc);
1564 /* Reset LAA into RAR[0] on 82571 */
1565 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1566 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1568 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1569 emx_print_hw_stats(sc);
1573 callout_reset(&sc->timer, hz, emx_timer, sc);
1575 ifnet_deserialize_all(ifp);
1579 emx_update_link_status(struct emx_softc *sc)
1581 struct e1000_hw *hw = &sc->hw;
1582 struct ifnet *ifp = &sc->arpcom.ac_if;
1583 device_t dev = sc->dev;
1584 uint32_t link_check = 0;
1586 /* Get the cached link value or read phy for real */
1587 switch (hw->phy.media_type) {
1588 case e1000_media_type_copper:
1589 if (hw->mac.get_link_status) {
1590 /* Do the work to read phy */
1591 e1000_check_for_link(hw);
1592 link_check = !hw->mac.get_link_status;
1593 if (link_check) /* ESB2 fix */
1594 e1000_cfg_on_link_up(hw);
1600 case e1000_media_type_fiber:
1601 e1000_check_for_link(hw);
1602 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1605 case e1000_media_type_internal_serdes:
1606 e1000_check_for_link(hw);
1607 link_check = sc->hw.mac.serdes_has_link;
1610 case e1000_media_type_unknown:
1615 /* Now check for a transition */
1616 if (link_check && sc->link_active == 0) {
1617 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1621 * Check if we should enable/disable SPEED_MODE bit on
1624 if (sc->link_speed != SPEED_1000 &&
1625 (hw->mac.type == e1000_82571 ||
1626 hw->mac.type == e1000_82572)) {
1629 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1630 tarc0 &= ~EMX_TARC_SPEED_MODE;
1631 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1634 device_printf(dev, "Link is up %d Mbps %s\n",
1636 ((sc->link_duplex == FULL_DUPLEX) ?
1637 "Full Duplex" : "Half Duplex"));
1639 sc->link_active = 1;
1641 ifp->if_baudrate = sc->link_speed * 1000000;
1642 ifp->if_link_state = LINK_STATE_UP;
1643 if_link_state_change(ifp);
1644 } else if (!link_check && sc->link_active == 1) {
1645 ifp->if_baudrate = sc->link_speed = 0;
1646 sc->link_duplex = 0;
1648 device_printf(dev, "Link is Down\n");
1649 sc->link_active = 0;
1651 /* Link down, disable watchdog */
1654 ifp->if_link_state = LINK_STATE_DOWN;
1655 if_link_state_change(ifp);
1660 emx_stop(struct emx_softc *sc)
1662 struct ifnet *ifp = &sc->arpcom.ac_if;
1665 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1667 emx_disable_intr(sc);
1669 callout_stop(&sc->timer);
1671 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1675 * Disable multiple receive queues.
1678 * We should disable multiple receive queues before
1679 * resetting the hardware.
1681 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1683 e1000_reset_hw(&sc->hw);
1684 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1686 for (i = 0; i < sc->num_tx_desc; i++) {
1687 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
1689 if (tx_buffer->m_head != NULL) {
1690 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1691 m_freem(tx_buffer->m_head);
1692 tx_buffer->m_head = NULL;
1696 for (i = 0; i < sc->rx_ring_inuse; ++i)
1697 emx_free_rx_ring(sc, &sc->rx_data[i]);
1701 sc->csum_iphlen = 0;
1709 emx_reset(struct emx_softc *sc)
1711 device_t dev = sc->dev;
1712 uint16_t rx_buffer_size;
1714 /* Set up smart power down as default off on newer adapters. */
1715 if (!emx_smart_pwr_down &&
1716 (sc->hw.mac.type == e1000_82571 ||
1717 sc->hw.mac.type == e1000_82572)) {
1718 uint16_t phy_tmp = 0;
1720 /* Speed up time to link by disabling smart power down. */
1721 e1000_read_phy_reg(&sc->hw,
1722 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1723 phy_tmp &= ~IGP02E1000_PM_SPD;
1724 e1000_write_phy_reg(&sc->hw,
1725 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1729 * These parameters control the automatic generation (Tx) and
1730 * response (Rx) to Ethernet PAUSE frames.
1731 * - High water mark should allow for at least two frames to be
1732 * received after sending an XOFF.
1733 * - Low water mark works best when it is very near the high water mark.
1734 * This allows the receiver to restart by sending XON when it has
1735 * drained a bit. Here we use an arbitary value of 1500 which will
1736 * restart after one full frame is pulled from the buffer. There
1737 * could be several smaller frames in the buffer and if so they will
1738 * not trigger the XON until their total number reduces the buffer
1740 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1742 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1744 sc->hw.fc.high_water = rx_buffer_size -
1745 roundup2(sc->max_frame_size, 1024);
1746 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1748 if (sc->hw.mac.type == e1000_80003es2lan)
1749 sc->hw.fc.pause_time = 0xFFFF;
1751 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1752 sc->hw.fc.send_xon = TRUE;
1753 sc->hw.fc.requested_mode = e1000_fc_full;
1755 /* Issue a global reset */
1756 e1000_reset_hw(&sc->hw);
1757 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1758 emx_disable_aspm(sc);
1760 if (e1000_init_hw(&sc->hw) < 0) {
1761 device_printf(dev, "Hardware Initialization Failed\n");
1765 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1766 e1000_get_phy_info(&sc->hw);
1767 e1000_check_for_link(&sc->hw);
1773 emx_setup_ifp(struct emx_softc *sc)
1775 struct ifnet *ifp = &sc->arpcom.ac_if;
1777 if_initname(ifp, device_get_name(sc->dev),
1778 device_get_unit(sc->dev));
1780 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1781 ifp->if_init = emx_init;
1782 ifp->if_ioctl = emx_ioctl;
1783 ifp->if_start = emx_start;
1784 #ifdef IFPOLL_ENABLE
1785 ifp->if_qpoll = emx_qpoll;
1787 ifp->if_watchdog = emx_watchdog;
1788 ifp->if_serialize = emx_serialize;
1789 ifp->if_deserialize = emx_deserialize;
1790 ifp->if_tryserialize = emx_tryserialize;
1792 ifp->if_serialize_assert = emx_serialize_assert;
1794 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1795 ifq_set_ready(&ifp->if_snd);
1797 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1799 ifp->if_capabilities = IFCAP_HWCSUM |
1800 IFCAP_VLAN_HWTAGGING |
1802 if (sc->rx_ring_cnt > 1)
1803 ifp->if_capabilities |= IFCAP_RSS;
1804 ifp->if_capenable = ifp->if_capabilities;
1805 ifp->if_hwassist = EMX_CSUM_FEATURES;
1808 * Tell the upper layer(s) we support long frames.
1810 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1813 * Specify the media types supported by this sc and register
1814 * callbacks to update media and link information
1816 ifmedia_init(&sc->media, IFM_IMASK,
1817 emx_media_change, emx_media_status);
1818 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1819 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1820 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1822 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1824 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1825 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1827 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1828 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1830 if (sc->hw.phy.type != e1000_phy_ife) {
1831 ifmedia_add(&sc->media,
1832 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1833 ifmedia_add(&sc->media,
1834 IFM_ETHER | IFM_1000_T, 0, NULL);
1837 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1838 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1842 * Workaround for SmartSpeed on 82541 and 82547 controllers
1845 emx_smartspeed(struct emx_softc *sc)
1849 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1850 sc->hw.mac.autoneg == 0 ||
1851 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1854 if (sc->smartspeed == 0) {
1856 * If Master/Slave config fault is asserted twice,
1857 * we assume back-to-back
1859 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1860 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1862 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1863 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1864 e1000_read_phy_reg(&sc->hw,
1865 PHY_1000T_CTRL, &phy_tmp);
1866 if (phy_tmp & CR_1000T_MS_ENABLE) {
1867 phy_tmp &= ~CR_1000T_MS_ENABLE;
1868 e1000_write_phy_reg(&sc->hw,
1869 PHY_1000T_CTRL, phy_tmp);
1871 if (sc->hw.mac.autoneg &&
1872 !e1000_phy_setup_autoneg(&sc->hw) &&
1873 !e1000_read_phy_reg(&sc->hw,
1874 PHY_CONTROL, &phy_tmp)) {
1875 phy_tmp |= MII_CR_AUTO_NEG_EN |
1876 MII_CR_RESTART_AUTO_NEG;
1877 e1000_write_phy_reg(&sc->hw,
1878 PHY_CONTROL, phy_tmp);
1883 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
1884 /* If still no link, perhaps using 2/3 pair cable */
1885 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
1886 phy_tmp |= CR_1000T_MS_ENABLE;
1887 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
1888 if (sc->hw.mac.autoneg &&
1889 !e1000_phy_setup_autoneg(&sc->hw) &&
1890 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
1891 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1892 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
1896 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1897 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
1902 emx_create_tx_ring(struct emx_softc *sc)
1904 device_t dev = sc->dev;
1905 struct emx_txbuf *tx_buffer;
1906 int error, i, tsize;
1909 * Validate number of transmit descriptors. It must not exceed
1910 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1912 if ((emx_txd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
1913 emx_txd > EMX_MAX_TXD || emx_txd < EMX_MIN_TXD) {
1914 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
1915 EMX_DEFAULT_TXD, emx_txd);
1916 sc->num_tx_desc = EMX_DEFAULT_TXD;
1918 sc->num_tx_desc = emx_txd;
1922 * Allocate Transmit Descriptor ring
1924 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
1926 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
1927 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1928 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
1929 &sc->tx_desc_paddr);
1930 if (sc->tx_desc_base == NULL) {
1931 device_printf(dev, "Unable to allocate tx_desc memory\n");
1935 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
1936 M_DEVBUF, M_WAITOK | M_ZERO);
1939 * Create DMA tags for tx buffers
1941 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
1942 1, 0, /* alignment, bounds */
1943 BUS_SPACE_MAXADDR, /* lowaddr */
1944 BUS_SPACE_MAXADDR, /* highaddr */
1945 NULL, NULL, /* filter, filterarg */
1946 EMX_TSO_SIZE, /* maxsize */
1947 EMX_MAX_SCATTER, /* nsegments */
1948 EMX_MAX_SEGSIZE, /* maxsegsize */
1949 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1950 BUS_DMA_ONEBPAGE, /* flags */
1953 device_printf(dev, "Unable to allocate TX DMA tag\n");
1954 kfree(sc->tx_buf, M_DEVBUF);
1960 * Create DMA maps for tx buffers
1962 for (i = 0; i < sc->num_tx_desc; i++) {
1963 tx_buffer = &sc->tx_buf[i];
1965 error = bus_dmamap_create(sc->txtag,
1966 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1969 device_printf(dev, "Unable to create TX DMA map\n");
1970 emx_destroy_tx_ring(sc, i);
1978 emx_init_tx_ring(struct emx_softc *sc)
1980 /* Clear the old ring contents */
1981 bzero(sc->tx_desc_base,
1982 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
1985 sc->next_avail_tx_desc = 0;
1986 sc->next_tx_to_clean = 0;
1987 sc->num_tx_desc_avail = sc->num_tx_desc;
1991 emx_init_tx_unit(struct emx_softc *sc)
1993 uint32_t tctl, tarc, tipg = 0;
1996 /* Setup the Base and Length of the Tx Descriptor Ring */
1997 bus_addr = sc->tx_desc_paddr;
1998 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
1999 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2000 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2001 (uint32_t)(bus_addr >> 32));
2002 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2003 (uint32_t)bus_addr);
2004 /* Setup the HW Tx Head and Tail descriptor pointers */
2005 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2006 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2008 /* Set the default values for the Tx Inter Packet Gap timer */
2009 switch (sc->hw.mac.type) {
2010 case e1000_80003es2lan:
2011 tipg = DEFAULT_82543_TIPG_IPGR1;
2012 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2013 E1000_TIPG_IPGR2_SHIFT;
2017 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2018 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2019 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2021 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2022 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2023 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2027 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2029 /* NOTE: 0 is not allowed for TIDV */
2030 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2031 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2033 if (sc->hw.mac.type == e1000_82571 ||
2034 sc->hw.mac.type == e1000_82572) {
2035 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2036 tarc |= EMX_TARC_SPEED_MODE;
2037 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2038 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2039 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2041 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2042 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2044 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2047 /* Program the Transmit Control Register */
2048 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2049 tctl &= ~E1000_TCTL_CT;
2050 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2051 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2052 tctl |= E1000_TCTL_MULR;
2054 /* This write will effectively turn on the transmit unit. */
2055 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2059 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2061 struct emx_txbuf *tx_buffer;
2064 /* Free Transmit Descriptor ring */
2065 if (sc->tx_desc_base) {
2066 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2067 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2069 bus_dma_tag_destroy(sc->tx_desc_dtag);
2071 sc->tx_desc_base = NULL;
2074 if (sc->tx_buf == NULL)
2077 for (i = 0; i < ndesc; i++) {
2078 tx_buffer = &sc->tx_buf[i];
2080 KKASSERT(tx_buffer->m_head == NULL);
2081 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2083 bus_dma_tag_destroy(sc->txtag);
2085 kfree(sc->tx_buf, M_DEVBUF);
2090 * The offload context needs to be set when we transfer the first
2091 * packet of a particular protocol (TCP/UDP). This routine has been
2092 * enhanced to deal with inserted VLAN headers.
2094 * If the new packet's ether header length, ip header length and
2095 * csum offloading type are same as the previous packet, we should
2096 * avoid allocating a new csum context descriptor; mainly to take
2097 * advantage of the pipeline effect of the TX data read request.
2099 * This function returns number of TX descrptors allocated for
2103 emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2104 uint32_t *txd_upper, uint32_t *txd_lower)
2106 struct e1000_context_desc *TXD;
2107 struct emx_txbuf *tx_buffer;
2108 struct ether_vlan_header *eh;
2110 int curr_txd, ehdrlen, csum_flags;
2111 uint32_t cmd, hdr_len, ip_hlen;
2115 * Determine where frame payload starts.
2116 * Jump over vlan headers if already present,
2117 * helpful for QinQ too.
2119 KASSERT(mp->m_len >= ETHER_HDR_LEN,
2120 ("emx_txcsum_pullup is not called (eh)?\n"));
2121 eh = mtod(mp, struct ether_vlan_header *);
2122 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2123 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
2124 ("emx_txcsum_pullup is not called (evh)?\n"));
2125 etype = ntohs(eh->evl_proto);
2126 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
2128 etype = ntohs(eh->evl_encap_proto);
2129 ehdrlen = ETHER_HDR_LEN;
2133 * We only support TCP/UDP for IPv4 for the moment.
2134 * TODO: Support SCTP too when it hits the tree.
2136 if (etype != ETHERTYPE_IP)
2139 KASSERT(mp->m_len >= ehdrlen + EMX_IPVHL_SIZE,
2140 ("emx_txcsum_pullup is not called (eh+ip_vhl)?\n"));
2142 /* NOTE: We could only safely access ip.ip_vhl part */
2143 ip = (struct ip *)(mp->m_data + ehdrlen);
2144 ip_hlen = ip->ip_hl << 2;
2146 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2148 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2149 sc->csum_flags == csum_flags) {
2151 * Same csum offload context as the previous packets;
2154 *txd_upper = sc->csum_txd_upper;
2155 *txd_lower = sc->csum_txd_lower;
2160 * Setup a new csum offload context.
2163 curr_txd = sc->next_avail_tx_desc;
2164 tx_buffer = &sc->tx_buf[curr_txd];
2165 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2169 /* Setup of IP header checksum. */
2170 if (csum_flags & CSUM_IP) {
2172 * Start offset for header checksum calculation.
2173 * End offset for header checksum calculation.
2174 * Offset of place to put the checksum.
2176 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2177 TXD->lower_setup.ip_fields.ipcse =
2178 htole16(ehdrlen + ip_hlen - 1);
2179 TXD->lower_setup.ip_fields.ipcso =
2180 ehdrlen + offsetof(struct ip, ip_sum);
2181 cmd |= E1000_TXD_CMD_IP;
2182 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2184 hdr_len = ehdrlen + ip_hlen;
2186 if (csum_flags & CSUM_TCP) {
2188 * Start offset for payload checksum calculation.
2189 * End offset for payload checksum calculation.
2190 * Offset of place to put the checksum.
2192 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2193 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2194 TXD->upper_setup.tcp_fields.tucso =
2195 hdr_len + offsetof(struct tcphdr, th_sum);
2196 cmd |= E1000_TXD_CMD_TCP;
2197 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2198 } else if (csum_flags & CSUM_UDP) {
2200 * Start offset for header checksum calculation.
2201 * End offset for header checksum calculation.
2202 * Offset of place to put the checksum.
2204 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2205 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2206 TXD->upper_setup.tcp_fields.tucso =
2207 hdr_len + offsetof(struct udphdr, uh_sum);
2208 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2211 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2212 E1000_TXD_DTYP_D; /* Data descr */
2214 /* Save the information for this csum offloading context */
2215 sc->csum_ehlen = ehdrlen;
2216 sc->csum_iphlen = ip_hlen;
2217 sc->csum_flags = csum_flags;
2218 sc->csum_txd_upper = *txd_upper;
2219 sc->csum_txd_lower = *txd_lower;
2221 TXD->tcp_seg_setup.data = htole32(0);
2222 TXD->cmd_and_length =
2223 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2225 if (++curr_txd == sc->num_tx_desc)
2228 KKASSERT(sc->num_tx_desc_avail > 0);
2229 sc->num_tx_desc_avail--;
2231 sc->next_avail_tx_desc = curr_txd;
2236 emx_txcsum_pullup(struct emx_softc *sc, struct mbuf **m0)
2238 struct mbuf *m = *m0;
2239 struct ether_header *eh;
2242 sc->tx_csum_try_pullup++;
2244 len = ETHER_HDR_LEN + EMX_IPVHL_SIZE;
2246 if (__predict_false(!M_WRITABLE(m))) {
2247 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2248 sc->tx_csum_drop1++;
2253 eh = mtod(m, struct ether_header *);
2255 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2256 len += EVL_ENCAPLEN;
2258 if (m->m_len < len) {
2259 sc->tx_csum_drop2++;
2267 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2268 sc->tx_csum_pullup1++;
2269 m = m_pullup(m, ETHER_HDR_LEN);
2271 sc->tx_csum_pullup1_failed++;
2277 eh = mtod(m, struct ether_header *);
2279 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2280 len += EVL_ENCAPLEN;
2282 if (m->m_len < len) {
2283 sc->tx_csum_pullup2++;
2284 m = m_pullup(m, len);
2286 sc->tx_csum_pullup2_failed++;
2296 emx_txeof(struct emx_softc *sc)
2298 struct ifnet *ifp = &sc->arpcom.ac_if;
2299 struct emx_txbuf *tx_buffer;
2300 int first, num_avail;
2302 if (sc->tx_dd_head == sc->tx_dd_tail)
2305 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2308 num_avail = sc->num_tx_desc_avail;
2309 first = sc->next_tx_to_clean;
2311 while (sc->tx_dd_head != sc->tx_dd_tail) {
2312 int dd_idx = sc->tx_dd[sc->tx_dd_head];
2313 struct e1000_tx_desc *tx_desc;
2315 tx_desc = &sc->tx_desc_base[dd_idx];
2316 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2317 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2319 if (++dd_idx == sc->num_tx_desc)
2322 while (first != dd_idx) {
2327 tx_buffer = &sc->tx_buf[first];
2328 if (tx_buffer->m_head) {
2330 bus_dmamap_unload(sc->txtag,
2332 m_freem(tx_buffer->m_head);
2333 tx_buffer->m_head = NULL;
2336 if (++first == sc->num_tx_desc)
2343 sc->next_tx_to_clean = first;
2344 sc->num_tx_desc_avail = num_avail;
2346 if (sc->tx_dd_head == sc->tx_dd_tail) {
2351 if (!EMX_IS_OACTIVE(sc)) {
2352 ifp->if_flags &= ~IFF_OACTIVE;
2354 /* All clean, turn off the timer */
2355 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2361 emx_tx_collect(struct emx_softc *sc)
2363 struct ifnet *ifp = &sc->arpcom.ac_if;
2364 struct emx_txbuf *tx_buffer;
2365 int tdh, first, num_avail, dd_idx = -1;
2367 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2370 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2371 if (tdh == sc->next_tx_to_clean)
2374 if (sc->tx_dd_head != sc->tx_dd_tail)
2375 dd_idx = sc->tx_dd[sc->tx_dd_head];
2377 num_avail = sc->num_tx_desc_avail;
2378 first = sc->next_tx_to_clean;
2380 while (first != tdh) {
2385 tx_buffer = &sc->tx_buf[first];
2386 if (tx_buffer->m_head) {
2388 bus_dmamap_unload(sc->txtag,
2390 m_freem(tx_buffer->m_head);
2391 tx_buffer->m_head = NULL;
2394 if (first == dd_idx) {
2395 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2396 if (sc->tx_dd_head == sc->tx_dd_tail) {
2401 dd_idx = sc->tx_dd[sc->tx_dd_head];
2405 if (++first == sc->num_tx_desc)
2408 sc->next_tx_to_clean = first;
2409 sc->num_tx_desc_avail = num_avail;
2411 if (!EMX_IS_OACTIVE(sc)) {
2412 ifp->if_flags &= ~IFF_OACTIVE;
2414 /* All clean, turn off the timer */
2415 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2421 * When Link is lost sometimes there is work still in the TX ring
2422 * which will result in a watchdog, rather than allow that do an
2423 * attempted cleanup and then reinit here. Note that this has been
2424 * seens mostly with fiber adapters.
2427 emx_tx_purge(struct emx_softc *sc)
2429 struct ifnet *ifp = &sc->arpcom.ac_if;
2431 if (!sc->link_active && ifp->if_timer) {
2433 if (ifp->if_timer) {
2434 if_printf(ifp, "Link lost, TX pending, reinit\n");
2442 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
2445 bus_dma_segment_t seg;
2447 struct emx_rxbuf *rx_buffer;
2450 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2452 rdata->mbuf_cluster_failed++;
2454 if_printf(&sc->arpcom.ac_if,
2455 "Unable to allocate RX mbuf\n");
2459 m->m_len = m->m_pkthdr.len = MCLBYTES;
2461 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2462 m_adj(m, ETHER_ALIGN);
2464 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2465 rdata->rx_sparemap, m,
2466 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2470 if_printf(&sc->arpcom.ac_if,
2471 "Unable to load RX mbuf\n");
2476 rx_buffer = &rdata->rx_buf[i];
2477 if (rx_buffer->m_head != NULL)
2478 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2480 map = rx_buffer->map;
2481 rx_buffer->map = rdata->rx_sparemap;
2482 rdata->rx_sparemap = map;
2484 rx_buffer->m_head = m;
2485 rx_buffer->paddr = seg.ds_addr;
2487 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2492 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2494 device_t dev = sc->dev;
2495 struct emx_rxbuf *rx_buffer;
2496 int i, error, rsize;
2499 * Validate number of receive descriptors. It must not exceed
2500 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2502 if ((emx_rxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2503 emx_rxd > EMX_MAX_RXD || emx_rxd < EMX_MIN_RXD) {
2504 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2505 EMX_DEFAULT_RXD, emx_rxd);
2506 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2508 rdata->num_rx_desc = emx_rxd;
2512 * Allocate Receive Descriptor ring
2514 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2516 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
2517 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2518 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2519 &rdata->rx_desc_paddr);
2520 if (rdata->rx_desc == NULL) {
2521 device_printf(dev, "Unable to allocate rx_desc memory\n");
2525 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2526 M_DEVBUF, M_WAITOK | M_ZERO);
2529 * Create DMA tag for rx buffers
2531 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2532 1, 0, /* alignment, bounds */
2533 BUS_SPACE_MAXADDR, /* lowaddr */
2534 BUS_SPACE_MAXADDR, /* highaddr */
2535 NULL, NULL, /* filter, filterarg */
2536 MCLBYTES, /* maxsize */
2538 MCLBYTES, /* maxsegsize */
2539 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2542 device_printf(dev, "Unable to allocate RX DMA tag\n");
2543 kfree(rdata->rx_buf, M_DEVBUF);
2544 rdata->rx_buf = NULL;
2549 * Create spare DMA map for rx buffers
2551 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2552 &rdata->rx_sparemap);
2554 device_printf(dev, "Unable to create spare RX DMA map\n");
2555 bus_dma_tag_destroy(rdata->rxtag);
2556 kfree(rdata->rx_buf, M_DEVBUF);
2557 rdata->rx_buf = NULL;
2562 * Create DMA maps for rx buffers
2564 for (i = 0; i < rdata->num_rx_desc; i++) {
2565 rx_buffer = &rdata->rx_buf[i];
2567 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2570 device_printf(dev, "Unable to create RX DMA map\n");
2571 emx_destroy_rx_ring(sc, rdata, i);
2579 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2583 for (i = 0; i < rdata->num_rx_desc; i++) {
2584 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2586 if (rx_buffer->m_head != NULL) {
2587 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2588 m_freem(rx_buffer->m_head);
2589 rx_buffer->m_head = NULL;
2593 if (rdata->fmp != NULL)
2594 m_freem(rdata->fmp);
2600 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2604 /* Reset descriptor ring */
2605 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2607 /* Allocate new ones. */
2608 for (i = 0; i < rdata->num_rx_desc; i++) {
2609 error = emx_newbuf(sc, rdata, i, 1);
2614 /* Setup our descriptor pointers */
2615 rdata->next_rx_desc_to_check = 0;
2621 emx_init_rx_unit(struct emx_softc *sc)
2623 struct ifnet *ifp = &sc->arpcom.ac_if;
2625 uint32_t rctl, itr, rfctl;
2629 * Make sure receives are disabled while setting
2630 * up the descriptor ring
2632 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2633 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2636 * Set the interrupt throttling rate. Value is calculated
2637 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2639 if (sc->int_throttle_ceil)
2640 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2643 emx_set_itr(sc, itr);
2645 /* Use extended RX descriptor */
2646 rfctl = E1000_RFCTL_EXTEN;
2648 /* Disable accelerated ackknowledge */
2649 if (sc->hw.mac.type == e1000_82574)
2650 rfctl |= E1000_RFCTL_ACK_DIS;
2652 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2655 * Receive Checksum Offload for TCP and UDP
2657 * Checksum offloading is also enabled if multiple receive
2658 * queue is to be supported, since we need it to figure out
2661 if (ifp->if_capenable & (IFCAP_RSS | IFCAP_RXCSUM)) {
2664 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2668 * PCSD must be enabled to enable multiple
2671 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2673 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2677 * Configure multiple receive queue (RSS)
2679 if (ifp->if_capenable & IFCAP_RSS) {
2680 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2683 KASSERT(sc->rx_ring_inuse == EMX_NRX_RING,
2684 ("invalid number of RX ring (%d)",
2685 sc->rx_ring_inuse));
2689 * When we reach here, RSS has already been disabled
2690 * in emx_stop(), so we could safely configure RSS key
2691 * and redirect table.
2697 toeplitz_get_key(key, sizeof(key));
2698 for (i = 0; i < EMX_NRSSRK; ++i) {
2701 rssrk = EMX_RSSRK_VAL(key, i);
2702 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2704 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2708 * Configure RSS redirect table in following fashion:
2709 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2712 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2715 q = (i % sc->rx_ring_inuse) << EMX_RETA_RINGIDX_SHIFT;
2716 reta |= q << (8 * i);
2718 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2720 for (i = 0; i < EMX_NRETA; ++i)
2721 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2724 * Enable multiple receive queues.
2725 * Enable IPv4 RSS standard hash functions.
2726 * Disable RSS interrupt.
2728 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2729 E1000_MRQC_ENABLE_RSS_2Q |
2730 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2731 E1000_MRQC_RSS_FIELD_IPV4);
2735 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2736 * long latencies are observed, like Lenovo X60. This
2737 * change eliminates the problem, but since having positive
2738 * values in RDTR is a known source of problems on other
2739 * platforms another solution is being sought.
2741 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2742 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2743 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2746 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2747 struct emx_rxdata *rdata = &sc->rx_data[i];
2750 * Setup the Base and Length of the Rx Descriptor Ring
2752 bus_addr = rdata->rx_desc_paddr;
2753 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2754 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2755 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2756 (uint32_t)(bus_addr >> 32));
2757 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2758 (uint32_t)bus_addr);
2761 * Setup the HW Rx Head and Tail Descriptor Pointers
2763 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2764 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2765 sc->rx_data[i].num_rx_desc - 1);
2768 /* Setup the Receive Control Register */
2769 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2770 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2771 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2772 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2774 /* Make sure VLAN Filters are off */
2775 rctl &= ~E1000_RCTL_VFE;
2777 /* Don't store bad paket */
2778 rctl &= ~E1000_RCTL_SBP;
2781 rctl |= E1000_RCTL_SZ_2048;
2783 if (ifp->if_mtu > ETHERMTU)
2784 rctl |= E1000_RCTL_LPE;
2786 rctl &= ~E1000_RCTL_LPE;
2788 /* Enable Receives */
2789 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
2793 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
2795 struct emx_rxbuf *rx_buffer;
2798 /* Free Receive Descriptor ring */
2799 if (rdata->rx_desc) {
2800 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
2801 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
2802 rdata->rx_desc_dmap);
2803 bus_dma_tag_destroy(rdata->rx_desc_dtag);
2805 rdata->rx_desc = NULL;
2808 if (rdata->rx_buf == NULL)
2811 for (i = 0; i < ndesc; i++) {
2812 rx_buffer = &rdata->rx_buf[i];
2814 KKASSERT(rx_buffer->m_head == NULL);
2815 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
2817 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2818 bus_dma_tag_destroy(rdata->rxtag);
2820 kfree(rdata->rx_buf, M_DEVBUF);
2821 rdata->rx_buf = NULL;
2825 emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
2827 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
2828 struct ifnet *ifp = &sc->arpcom.ac_if;
2830 emx_rxdesc_t *current_desc;
2834 i = rdata->next_rx_desc_to_check;
2835 current_desc = &rdata->rx_desc[i];
2836 staterr = le32toh(current_desc->rxd_staterr);
2838 if (!(staterr & E1000_RXD_STAT_DD))
2841 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2842 struct pktinfo *pi = NULL, pi0;
2843 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
2844 struct mbuf *m = NULL;
2849 mp = rx_buf->m_head;
2852 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2853 * needs to access the last received byte in the mbuf.
2855 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
2856 BUS_DMASYNC_POSTREAD);
2858 len = le16toh(current_desc->rxd_length);
2859 if (staterr & E1000_RXD_STAT_EOP) {
2866 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2868 uint32_t mrq, rss_hash;
2871 * Save several necessary information,
2872 * before emx_newbuf() destroy it.
2874 if ((staterr & E1000_RXD_STAT_VP) && eop)
2875 vlan = le16toh(current_desc->rxd_vlan);
2877 mrq = le32toh(current_desc->rxd_mrq);
2878 rss_hash = le32toh(current_desc->rxd_rss);
2880 EMX_RSS_DPRINTF(sc, 10,
2881 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2882 ring_idx, mrq, rss_hash);
2884 if (emx_newbuf(sc, rdata, i, 0) != 0) {
2889 /* Assign correct length to the current fragment */
2892 if (rdata->fmp == NULL) {
2893 mp->m_pkthdr.len = len;
2894 rdata->fmp = mp; /* Store the first mbuf */
2898 * Chain mbuf's together
2900 rdata->lmp->m_next = mp;
2901 rdata->lmp = rdata->lmp->m_next;
2902 rdata->fmp->m_pkthdr.len += len;
2906 rdata->fmp->m_pkthdr.rcvif = ifp;
2909 if (ifp->if_capenable & IFCAP_RXCSUM)
2910 emx_rxcsum(staterr, rdata->fmp);
2912 if (staterr & E1000_RXD_STAT_VP) {
2913 rdata->fmp->m_pkthdr.ether_vlantag =
2915 rdata->fmp->m_flags |= M_VLANTAG;
2921 if (ifp->if_capenable & IFCAP_RSS) {
2922 pi = emx_rssinfo(m, &pi0, mrq,
2925 #ifdef EMX_RSS_DEBUG
2932 emx_setup_rxdesc(current_desc, rx_buf);
2933 if (rdata->fmp != NULL) {
2934 m_freem(rdata->fmp);
2942 ether_input_pkt(ifp, m, pi);
2944 /* Advance our pointers to the next descriptor. */
2945 if (++i == rdata->num_rx_desc)
2948 current_desc = &rdata->rx_desc[i];
2949 staterr = le32toh(current_desc->rxd_staterr);
2951 rdata->next_rx_desc_to_check = i;
2953 /* Advance the E1000's Receive Queue "Tail Pointer". */
2955 i = rdata->num_rx_desc - 1;
2956 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
2960 emx_enable_intr(struct emx_softc *sc)
2962 uint32_t ims_mask = IMS_ENABLE_MASK;
2964 lwkt_serialize_handler_enable(&sc->main_serialize);
2967 if (sc->hw.mac.type == e1000_82574) {
2968 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
2969 ims_mask |= EM_MSIX_MASK;
2972 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
2976 emx_disable_intr(struct emx_softc *sc)
2978 if (sc->hw.mac.type == e1000_82574)
2979 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
2980 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2982 lwkt_serialize_handler_disable(&sc->main_serialize);
2986 * Bit of a misnomer, what this really means is
2987 * to enable OS management of the system... aka
2988 * to disable special hardware management features
2991 emx_get_mgmt(struct emx_softc *sc)
2993 /* A shared code workaround */
2994 if (sc->has_manage) {
2995 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2996 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2998 /* disable hardware interception of ARP */
2999 manc &= ~(E1000_MANC_ARP_EN);
3001 /* enable receiving management packets to the host */
3002 manc |= E1000_MANC_EN_MNG2HOST;
3003 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3004 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3005 manc2h |= E1000_MNG2HOST_PORT_623;
3006 manc2h |= E1000_MNG2HOST_PORT_664;
3007 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3009 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3014 * Give control back to hardware management
3015 * controller if there is one.
3018 emx_rel_mgmt(struct emx_softc *sc)
3020 if (sc->has_manage) {
3021 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3023 /* re-enable hardware interception of ARP */
3024 manc |= E1000_MANC_ARP_EN;
3025 manc &= ~E1000_MANC_EN_MNG2HOST;
3027 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3032 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3033 * For ASF and Pass Through versions of f/w this means that
3034 * the driver is loaded. For AMT version (only with 82573)
3035 * of the f/w this means that the network i/f is open.
3038 emx_get_hw_control(struct emx_softc *sc)
3040 /* Let firmware know the driver has taken over */
3041 if (sc->hw.mac.type == e1000_82573) {
3044 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3045 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3046 swsm | E1000_SWSM_DRV_LOAD);
3050 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3051 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3052 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3058 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3059 * For ASF and Pass Through versions of f/w this means that the
3060 * driver is no longer loaded. For AMT version (only with 82573)
3061 * of the f/w this means that the network i/f is closed.
3064 emx_rel_hw_control(struct emx_softc *sc)
3066 if (!sc->control_hw)
3070 /* Let firmware taken over control of h/w */
3071 if (sc->hw.mac.type == e1000_82573) {
3074 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3075 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3076 swsm & ~E1000_SWSM_DRV_LOAD);
3080 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3081 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3082 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3087 emx_is_valid_eaddr(const uint8_t *addr)
3089 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3091 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3098 * Enable PCI Wake On Lan capability
3101 emx_enable_wol(device_t dev)
3103 uint16_t cap, status;
3106 /* First find the capabilities pointer*/
3107 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3109 /* Read the PM Capabilities */
3110 id = pci_read_config(dev, cap, 1);
3111 if (id != PCIY_PMG) /* Something wrong */
3115 * OK, we have the power capabilities,
3116 * so now get the status register
3118 cap += PCIR_POWER_STATUS;
3119 status = pci_read_config(dev, cap, 2);
3120 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3121 pci_write_config(dev, cap, status, 2);
3125 emx_update_stats(struct emx_softc *sc)
3127 struct ifnet *ifp = &sc->arpcom.ac_if;
3129 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3130 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3131 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3132 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3134 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3135 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3136 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3137 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3139 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3140 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3141 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3142 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3143 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3144 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3145 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3146 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3147 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3148 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3149 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3150 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3151 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3152 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3153 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3154 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3155 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3156 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3157 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3158 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3160 /* For the 64-bit byte counters the low dword must be read first. */
3161 /* Both registers clear on the read of the high dword */
3163 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3164 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3166 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3167 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3168 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3169 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3170 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3172 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3173 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3175 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3176 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3177 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3178 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3179 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3180 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3181 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3182 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3183 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3184 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3186 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3187 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3188 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3189 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3190 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3191 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3193 ifp->if_collisions = sc->stats.colc;
3196 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3197 sc->stats.crcerrs + sc->stats.algnerrc +
3198 sc->stats.ruc + sc->stats.roc +
3199 sc->stats.mpc + sc->stats.cexterr;
3202 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3203 sc->watchdog_events;
3207 emx_print_debug_info(struct emx_softc *sc)
3209 device_t dev = sc->dev;
3210 uint8_t *hw_addr = sc->hw.hw_addr;
3212 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3213 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3214 E1000_READ_REG(&sc->hw, E1000_CTRL),
3215 E1000_READ_REG(&sc->hw, E1000_RCTL));
3216 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3217 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3218 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3219 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3220 sc->hw.fc.high_water, sc->hw.fc.low_water);
3221 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3222 E1000_READ_REG(&sc->hw, E1000_TIDV),
3223 E1000_READ_REG(&sc->hw, E1000_TADV));
3224 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3225 E1000_READ_REG(&sc->hw, E1000_RDTR),
3226 E1000_READ_REG(&sc->hw, E1000_RADV));
3227 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3228 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3229 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3230 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3231 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3232 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3233 device_printf(dev, "Num Tx descriptors avail = %d\n",
3234 sc->num_tx_desc_avail);
3235 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3236 sc->no_tx_desc_avail1);
3237 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3238 sc->no_tx_desc_avail2);
3239 device_printf(dev, "Std mbuf failed = %ld\n",
3240 sc->mbuf_alloc_failed);
3241 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3242 sc->rx_data[0].mbuf_cluster_failed);
3243 device_printf(dev, "Driver dropped packets = %ld\n",
3245 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3246 sc->no_tx_dma_setup);
3248 device_printf(dev, "TXCSUM try pullup = %lu\n",
3249 sc->tx_csum_try_pullup);
3250 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n",
3251 sc->tx_csum_pullup1);
3252 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n",
3253 sc->tx_csum_pullup1_failed);
3254 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n",
3255 sc->tx_csum_pullup2);
3256 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n",
3257 sc->tx_csum_pullup2_failed);
3258 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n",
3260 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n",
3265 emx_print_hw_stats(struct emx_softc *sc)
3267 device_t dev = sc->dev;
3269 device_printf(dev, "Excessive collisions = %lld\n",
3270 (long long)sc->stats.ecol);
3271 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3272 device_printf(dev, "Symbol errors = %lld\n",
3273 (long long)sc->stats.symerrs);
3275 device_printf(dev, "Sequence errors = %lld\n",
3276 (long long)sc->stats.sec);
3277 device_printf(dev, "Defer count = %lld\n",
3278 (long long)sc->stats.dc);
3279 device_printf(dev, "Missed Packets = %lld\n",
3280 (long long)sc->stats.mpc);
3281 device_printf(dev, "Receive No Buffers = %lld\n",
3282 (long long)sc->stats.rnbc);
3283 /* RLEC is inaccurate on some hardware, calculate our own. */
3284 device_printf(dev, "Receive Length Errors = %lld\n",
3285 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3286 device_printf(dev, "Receive errors = %lld\n",
3287 (long long)sc->stats.rxerrc);
3288 device_printf(dev, "Crc errors = %lld\n",
3289 (long long)sc->stats.crcerrs);
3290 device_printf(dev, "Alignment errors = %lld\n",
3291 (long long)sc->stats.algnerrc);
3292 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3293 (long long)sc->stats.cexterr);
3294 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3295 device_printf(dev, "watchdog timeouts = %ld\n",
3296 sc->watchdog_events);
3297 device_printf(dev, "XON Rcvd = %lld\n",
3298 (long long)sc->stats.xonrxc);
3299 device_printf(dev, "XON Xmtd = %lld\n",
3300 (long long)sc->stats.xontxc);
3301 device_printf(dev, "XOFF Rcvd = %lld\n",
3302 (long long)sc->stats.xoffrxc);
3303 device_printf(dev, "XOFF Xmtd = %lld\n",
3304 (long long)sc->stats.xofftxc);
3305 device_printf(dev, "Good Packets Rcvd = %lld\n",
3306 (long long)sc->stats.gprc);
3307 device_printf(dev, "Good Packets Xmtd = %lld\n",
3308 (long long)sc->stats.gptc);
3312 emx_print_nvm_info(struct emx_softc *sc)
3314 uint16_t eeprom_data;
3317 /* Its a bit crude, but it gets the job done */
3318 kprintf("\nInterface EEPROM Dump:\n");
3319 kprintf("Offset\n0x0000 ");
3320 for (i = 0, j = 0; i < 32; i++, j++) {
3321 if (j == 8) { /* Make the offset block */
3323 kprintf("\n0x00%x0 ",row);
3325 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3326 kprintf("%04x ", eeprom_data);
3332 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3334 struct emx_softc *sc;
3339 error = sysctl_handle_int(oidp, &result, 0, req);
3340 if (error || !req->newptr)
3343 sc = (struct emx_softc *)arg1;
3344 ifp = &sc->arpcom.ac_if;
3346 ifnet_serialize_all(ifp);
3349 emx_print_debug_info(sc);
3352 * This value will cause a hex dump of the
3353 * first 32 16-bit words of the EEPROM to
3357 emx_print_nvm_info(sc);
3359 ifnet_deserialize_all(ifp);
3365 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3370 error = sysctl_handle_int(oidp, &result, 0, req);
3371 if (error || !req->newptr)
3375 struct emx_softc *sc = (struct emx_softc *)arg1;
3376 struct ifnet *ifp = &sc->arpcom.ac_if;
3378 ifnet_serialize_all(ifp);
3379 emx_print_hw_stats(sc);
3380 ifnet_deserialize_all(ifp);
3386 emx_add_sysctl(struct emx_softc *sc)
3388 #ifdef EMX_RSS_DEBUG
3393 sysctl_ctx_init(&sc->sysctl_ctx);
3394 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3395 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3396 device_get_nameunit(sc->dev),
3398 if (sc->sysctl_tree == NULL) {
3399 device_printf(sc->dev, "can't add sysctl node\n");
3403 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3404 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3405 emx_sysctl_debug_info, "I", "Debug Information");
3407 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3408 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3409 emx_sysctl_stats, "I", "Statistics");
3411 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3412 OID_AUTO, "rxd", CTLFLAG_RD,
3413 &sc->rx_data[0].num_rx_desc, 0, NULL);
3414 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3415 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
3417 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3418 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3419 sc, 0, emx_sysctl_int_throttle, "I",
3420 "interrupt throttling rate");
3421 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3422 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3423 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3424 "# segments per TX interrupt");
3426 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3427 OID_AUTO, "rx_ring_inuse", CTLFLAG_RD,
3428 &sc->rx_ring_inuse, 0, "RX ring in use");
3430 #ifdef EMX_RSS_DEBUG
3431 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3432 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3433 0, "RSS debug level");
3434 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3435 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3436 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3437 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3439 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3445 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3447 struct emx_softc *sc = (void *)arg1;
3448 struct ifnet *ifp = &sc->arpcom.ac_if;
3449 int error, throttle;
3451 throttle = sc->int_throttle_ceil;
3452 error = sysctl_handle_int(oidp, &throttle, 0, req);
3453 if (error || req->newptr == NULL)
3455 if (throttle < 0 || throttle > 1000000000 / 256)
3460 * Set the interrupt throttling rate in 256ns increments,
3461 * recalculate sysctl value assignment to get exact frequency.
3463 throttle = 1000000000 / 256 / throttle;
3465 /* Upper 16bits of ITR is reserved and should be zero */
3466 if (throttle & 0xffff0000)
3470 ifnet_serialize_all(ifp);
3473 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3475 sc->int_throttle_ceil = 0;
3477 if (ifp->if_flags & IFF_RUNNING)
3478 emx_set_itr(sc, throttle);
3480 ifnet_deserialize_all(ifp);
3483 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3484 sc->int_throttle_ceil);
3490 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3492 struct emx_softc *sc = (void *)arg1;
3493 struct ifnet *ifp = &sc->arpcom.ac_if;
3496 segs = sc->tx_int_nsegs;
3497 error = sysctl_handle_int(oidp, &segs, 0, req);
3498 if (error || req->newptr == NULL)
3503 ifnet_serialize_all(ifp);
3506 * Don't allow int_tx_nsegs to become:
3507 * o Less the oact_tx_desc
3508 * o Too large that no TX desc will cause TX interrupt to
3509 * be generated (OACTIVE will never recover)
3510 * o Too small that will cause tx_dd[] overflow
3512 if (segs < sc->oact_tx_desc ||
3513 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3514 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3518 sc->tx_int_nsegs = segs;
3521 ifnet_deserialize_all(ifp);
3527 emx_dma_alloc(struct emx_softc *sc)
3532 * Create top level busdma tag
3534 error = bus_dma_tag_create(NULL, 1, 0,
3535 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3537 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3538 0, &sc->parent_dtag);
3540 device_printf(sc->dev, "could not create top level DMA tag\n");
3545 * Allocate transmit descriptors ring and buffers
3547 error = emx_create_tx_ring(sc);
3549 device_printf(sc->dev, "Could not setup transmit structures\n");
3554 * Allocate receive descriptors ring and buffers
3556 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3557 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3559 device_printf(sc->dev,
3560 "Could not setup receive structures\n");
3568 emx_dma_free(struct emx_softc *sc)
3572 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3574 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3575 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3576 sc->rx_data[i].num_rx_desc);
3579 /* Free top level busdma tag */
3580 if (sc->parent_dtag != NULL)
3581 bus_dma_tag_destroy(sc->parent_dtag);
3585 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3587 struct emx_softc *sc = ifp->if_softc;
3590 case IFNET_SERIALIZE_ALL:
3591 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 0);
3594 case IFNET_SERIALIZE_MAIN:
3595 lwkt_serialize_enter(&sc->main_serialize);
3598 case IFNET_SERIALIZE_TX:
3599 lwkt_serialize_enter(&sc->tx_serialize);
3602 case IFNET_SERIALIZE_RX(0):
3603 lwkt_serialize_enter(&sc->rx_data[0].rx_serialize);
3606 case IFNET_SERIALIZE_RX(1):
3607 lwkt_serialize_enter(&sc->rx_data[1].rx_serialize);
3611 panic("%s unsupported serialize type\n", ifp->if_xname);
3616 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3618 struct emx_softc *sc = ifp->if_softc;
3621 case IFNET_SERIALIZE_ALL:
3622 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 0);
3625 case IFNET_SERIALIZE_MAIN:
3626 lwkt_serialize_exit(&sc->main_serialize);
3629 case IFNET_SERIALIZE_TX:
3630 lwkt_serialize_exit(&sc->tx_serialize);
3633 case IFNET_SERIALIZE_RX(0):
3634 lwkt_serialize_exit(&sc->rx_data[0].rx_serialize);
3637 case IFNET_SERIALIZE_RX(1):
3638 lwkt_serialize_exit(&sc->rx_data[1].rx_serialize);
3642 panic("%s unsupported serialize type\n", ifp->if_xname);
3647 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3649 struct emx_softc *sc = ifp->if_softc;
3652 case IFNET_SERIALIZE_ALL:
3653 return lwkt_serialize_array_try(sc->serializes,
3656 case IFNET_SERIALIZE_MAIN:
3657 return lwkt_serialize_try(&sc->main_serialize);
3659 case IFNET_SERIALIZE_TX:
3660 return lwkt_serialize_try(&sc->tx_serialize);
3662 case IFNET_SERIALIZE_RX(0):
3663 return lwkt_serialize_try(&sc->rx_data[0].rx_serialize);
3665 case IFNET_SERIALIZE_RX(1):
3666 return lwkt_serialize_try(&sc->rx_data[1].rx_serialize);
3669 panic("%s unsupported serialize type\n", ifp->if_xname);
3674 emx_serialize_skipmain(struct emx_softc *sc)
3676 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3680 emx_deserialize_skipmain(struct emx_softc *sc)
3682 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3688 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3689 boolean_t serialized)
3691 struct emx_softc *sc = ifp->if_softc;
3695 case IFNET_SERIALIZE_ALL:
3697 for (i = 0; i < EMX_NSERIALIZE; ++i)
3698 ASSERT_SERIALIZED(sc->serializes[i]);
3700 for (i = 0; i < EMX_NSERIALIZE; ++i)
3701 ASSERT_NOT_SERIALIZED(sc->serializes[i]);
3705 case IFNET_SERIALIZE_MAIN:
3707 ASSERT_SERIALIZED(&sc->main_serialize);
3709 ASSERT_NOT_SERIALIZED(&sc->main_serialize);
3712 case IFNET_SERIALIZE_TX:
3714 ASSERT_SERIALIZED(&sc->tx_serialize);
3716 ASSERT_NOT_SERIALIZED(&sc->tx_serialize);
3719 case IFNET_SERIALIZE_RX(0):
3721 ASSERT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3723 ASSERT_NOT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3726 case IFNET_SERIALIZE_RX(1):
3728 ASSERT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3730 ASSERT_NOT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3734 panic("%s unsupported serialize type\n", ifp->if_xname);
3738 #endif /* INVARIANTS */
3740 #ifdef IFPOLL_ENABLE
3743 emx_qpoll_status(struct ifnet *ifp, int pollhz __unused)
3745 struct emx_softc *sc = ifp->if_softc;
3748 ASSERT_SERIALIZED(&sc->main_serialize);
3750 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3751 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3752 emx_serialize_skipmain(sc);
3754 callout_stop(&sc->timer);
3755 sc->hw.mac.get_link_status = 1;
3756 emx_update_link_status(sc);
3757 callout_reset(&sc->timer, hz, emx_timer, sc);
3759 emx_deserialize_skipmain(sc);
3764 emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3766 struct emx_softc *sc = ifp->if_softc;
3768 ASSERT_SERIALIZED(&sc->tx_serialize);
3771 if (!ifq_is_empty(&ifp->if_snd))
3776 emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle)
3778 struct emx_softc *sc = ifp->if_softc;
3779 struct emx_rxdata *rdata = arg;
3781 ASSERT_SERIALIZED(&rdata->rx_serialize);
3783 emx_rxeof(sc, rdata - sc->rx_data, cycle);
3787 emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info)
3789 struct emx_softc *sc = ifp->if_softc;
3791 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3796 info->ifpi_status.status_func = emx_qpoll_status;
3797 info->ifpi_status.serializer = &sc->main_serialize;
3799 info->ifpi_tx[0].poll_func = emx_qpoll_tx;
3800 info->ifpi_tx[0].arg = NULL;
3801 info->ifpi_tx[0].serializer = &sc->tx_serialize;
3803 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3804 info->ifpi_rx[i].poll_func = emx_qpoll_rx;
3805 info->ifpi_rx[i].arg = &sc->rx_data[i];
3806 info->ifpi_rx[i].serializer =
3807 &sc->rx_data[i].rx_serialize;
3810 if (ifp->if_flags & IFF_RUNNING)
3811 emx_disable_intr(sc);
3812 } else if (ifp->if_flags & IFF_RUNNING) {
3813 emx_enable_intr(sc);
3817 #endif /* IFPOLL_ENABLE */
3820 emx_set_itr(struct emx_softc *sc, uint32_t itr)
3822 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
3823 if (sc->hw.mac.type == e1000_82574) {
3827 * When using MSIX interrupts we need to
3828 * throttle using the EITR register
3830 for (i = 0; i < 4; ++i)
3831 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
3836 * Disable the L0s, 82574L Errata #20
3839 emx_disable_aspm(struct emx_softc *sc)
3841 uint16_t link_cap, link_ctrl;
3842 uint8_t pcie_ptr, reg;
3843 device_t dev = sc->dev;
3845 switch (sc->hw.mac.type) {
3854 pcie_ptr = pci_get_pciecap_ptr(dev);
3858 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
3859 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
3863 if_printf(&sc->arpcom.ac_if, "disable L0s\n");
3865 reg = pcie_ptr + PCIER_LINKCTRL;
3866 link_ctrl = pci_read_config(dev, reg, 2);
3867 link_ctrl &= ~PCIEM_LNKCTL_ASPM_L0S;
3868 pci_write_config(dev, reg, link_ctrl, 2);