2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/dev/coretemp/coretemp.c,v 1.14 2011/05/05 19:15:15 delphij Exp $
30 * Device driver for Intel's On Die thermal sensor via MSR.
31 * First introduced in Intel's Core line of processors.
34 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/module.h>
39 #include <sys/cpu_topology.h>
40 #include <sys/kernel.h>
41 #include <sys/sensors.h>
42 #include <sys/proc.h> /* for curthread */
43 #include <sys/sched.h>
44 #include <sys/thread2.h>
45 #include <sys/bitops.h>
47 #include <machine/specialreg.h>
48 #include <machine/cpufunc.h>
49 #include <machine/cputypes.h>
50 #include <machine/md_var.h>
52 #define MSR_THERM_STATUS_TM_STATUS __BIT64(0)
53 #define MSR_THERM_STATUS_TM_STATUS_LOG __BIT64(1)
54 #define MSR_THERM_STATUS_PROCHOT __BIT64(2)
55 #define MSR_THERM_STATUS_PROCHOT_LOG __BIT64(3)
56 #define MSR_THERM_STATUS_CRIT __BIT64(4)
57 #define MSR_THERM_STATUS_CRIT_LOG __BIT64(5)
58 #define MSR_THERM_STATUS_THRESH1 __BIT64(6)
59 #define MSR_THERM_STATUS_THRESH1_LOG __BIT64(7)
60 #define MSR_THERM_STATUS_THRESH2 __BIT64(8)
61 #define MSR_THERM_STATUS_THRESH2_LOG __BIT64(9)
62 #define MSR_THERM_STATUS_PWRLIM __BIT64(10)
63 #define MSR_THERM_STATUS_PWRLIM_LOG __BIT64(11)
64 #define MSR_THERM_STATUS_READ __BITS64(16, 22)
65 #define MSR_THERM_STATUS_RES __BITS64(27, 30)
66 #define MSR_THERM_STATUS_READ_VALID __BIT64(31)
68 #define MSR_THERM_STATUS_HAS_STATUS(msr) \
69 (((msr) & (MSR_THERM_STATUS_TM_STATUS | MSR_THERM_STATUS_TM_STATUS_LOG)) ==\
70 (MSR_THERM_STATUS_TM_STATUS | MSR_THERM_STATUS_TM_STATUS_LOG))
72 #define MSR_THERM_STATUS_IS_CRITICAL(msr) \
73 (((msr) & (MSR_THERM_STATUS_CRIT | MSR_THERM_STATUS_CRIT_LOG)) == \
74 (MSR_THERM_STATUS_CRIT | MSR_THERM_STATUS_CRIT_LOG))
76 #define MSR_PKGTM_STATUS_TM_STATUS __BIT64(0)
77 #define MSR_PKGTM_STATUS_TM_STATUS_LOG __BIT64(1)
78 #define MSR_PKGTM_STATUS_PROCHOT __BIT64(2)
79 #define MSR_PKGTM_STATUS_PROCHOT_LOG __BIT64(3)
80 #define MSR_PKGTM_STATUS_CRIT __BIT64(4)
81 #define MSR_PKGTM_STATUS_CRIT_LOG __BIT64(5)
82 #define MSR_PKGTM_STATUS_THRESH1 __BIT64(6)
83 #define MSR_PKGTM_STATUS_THRESH1_LOG __BIT64(7)
84 #define MSR_PKGTM_STATUS_THRESH2 __BIT64(8)
85 #define MSR_PKGTM_STATUS_THRESH2_LOG __BIT64(9)
86 #define MSR_PKGTM_STATUS_PWRLIM __BIT64(10)
87 #define MSR_PKGTM_STATUS_PWRLIM_LOG __BIT64(11)
88 #define MSR_PKGTM_STATUS_READ __BITS64(16, 22)
90 #define MSR_PKGTM_STATUS_HAS_STATUS(msr) \
91 (((msr) & (MSR_PKGTM_STATUS_TM_STATUS | MSR_PKGTM_STATUS_TM_STATUS_LOG)) ==\
92 (MSR_PKGTM_STATUS_TM_STATUS | MSR_PKGTM_STATUS_TM_STATUS_LOG))
94 #define MSR_PKGTM_STATUS_IS_CRITICAL(msr) \
95 (((msr) & (MSR_PKGTM_STATUS_CRIT | MSR_PKGTM_STATUS_CRIT_LOG)) == \
96 (MSR_PKGTM_STATUS_CRIT | MSR_PKGTM_STATUS_CRIT_LOG))
98 #define CORETEMP_TEMP_INVALID -1
99 #define CORETEMP_TEMP_NOUPDATE -2
101 struct coretemp_sensor {
102 struct ksensordev c_sensdev;
103 struct ksensor c_sens;
106 struct coretemp_softc {
111 struct coretemp_sensor *sc_sens;
112 struct coretemp_sensor *sc_pkg_sens;
114 struct globaldata *sc_gd;
116 volatile uint32_t sc_flags; /* CORETEMP_FLAG_ */
117 volatile uint64_t sc_msr;
118 volatile uint64_t sc_pkg_msr;
121 #define CORETEMP_FLAG_INITED 0x1
122 #define CORETEMP_FLAG_PENDING 0x2
123 #define CORETEMP_FLAG_CRIT 0x4
124 #define CORETEMP_FLAG_PKGCRIT 0x8
126 #define CORETEMP_HAS_PKGSENSOR(sc) ((sc)->sc_pkg_sens != NULL)
131 static void coretemp_identify(driver_t *driver, device_t parent);
132 static int coretemp_probe(device_t dev);
133 static int coretemp_attach(device_t dev);
134 static int coretemp_detach(device_t dev);
136 static void coretemp_ipi_func(void *sc);
137 static void coretemp_ipi_send(struct coretemp_softc *sc, uint32_t flags);
138 static boolean_t coretemp_msr_fetch(struct coretemp_softc *sc, uint64_t *msr,
140 static int coretemp_msr_temp(struct coretemp_softc *sc, uint64_t msr);
141 static void coretemp_sensor_update(struct coretemp_softc *sc, int temp);
142 static void coretemp_sensor_task(void *arg);
144 static void coretemp_pkg_sensor_task(void *arg);
145 static void coretemp_pkg_sensor_update(struct coretemp_softc *sc, int temp);
146 static int coretemp_pkg_msr_temp(struct coretemp_softc *sc, uint64_t msr);
148 static device_method_t coretemp_methods[] = {
149 /* Device interface */
150 DEVMETHOD(device_identify, coretemp_identify),
151 DEVMETHOD(device_probe, coretemp_probe),
152 DEVMETHOD(device_attach, coretemp_attach),
153 DEVMETHOD(device_detach, coretemp_detach),
158 static driver_t coretemp_driver = {
161 sizeof(struct coretemp_softc),
164 static devclass_t coretemp_devclass;
165 DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, NULL);
166 MODULE_VERSION(coretemp, 1);
169 coretemp_sensor_set(struct ksensor *sens, const struct coretemp_softc *sc,
170 uint32_t crit_flag, int temp)
172 enum sensor_status status;
174 if (sc->sc_flags & crit_flag)
175 status = SENSOR_S_CRIT;
177 status = SENSOR_S_OK;
178 sensor_set_temp_degc(sens, temp, status);
182 coretemp_identify(driver_t *driver, device_t parent)
186 /* Make sure we're not being doubly invoked. */
187 if (device_find_child(parent, "coretemp", -1) != NULL)
190 /* Check that the vendor is Intel. */
191 if (cpu_vendor_id != CPU_VENDOR_INTEL)
195 * Some Intel CPUs, namely the PIII, don't have thermal sensors,
196 * but report them in cpu_thermal_feature. This leads to a later
197 * GPF when the sensor is queried via a MSR, so we stop here.
199 if (CPUID_TO_MODEL(cpu_id) < 0xe)
202 if ((cpu_thermal_feature & CPUID_THERMAL_SENSOR) == 0)
206 * We add a child for each CPU since settings must be performed
207 * on each CPU in the SMP case.
209 child = device_add_child(parent, "coretemp", -1);
211 device_printf(parent, "add coretemp child failed\n");
215 coretemp_probe(device_t dev)
217 if (resource_disabled("coretemp", 0))
220 device_set_desc(dev, "CPU On-Die Thermal Sensors");
222 return (BUS_PROBE_GENERIC);
226 coretemp_attach(device_t dev)
228 struct coretemp_softc *sc = device_get_softc(dev);
229 const struct cpu_node *node, *start_node;
233 int cpu_model, cpu_stepping;
234 int ret, tjtarget, cpu, sens_idx;
236 struct coretemp_sensor *csens;
239 pdev = device_get_parent(dev);
240 cpu_model = CPUID_TO_MODEL(cpu_id);
241 cpu_stepping = cpu_id & CPUID_STEPPING;
245 * XXXrpaulo: I have this CPU model and when it returns from C3
246 * coretemp continues to function properly.
250 * Check for errata AE18.
251 * "Processor Digital Thermal Sensor (DTS) Readout stops
252 * updating upon returning from C3/C4 state."
254 * Adapted from the Linux coretemp driver.
256 if (cpu_model == 0xe && cpu_stepping < 0xc) {
257 msr = rdmsr(MSR_BIOS_SIGN);
260 device_printf(dev, "not supported (Intel errata "
261 "AE18), try updating your BIOS\n");
268 * Use 100C as the initial value.
272 if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) {
274 * On some Core 2 CPUs, there's an undocumented MSR that
275 * can tell us if Tj(max) is 100 or 85.
277 * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG
278 * was adapted from the Linux coretemp driver.
280 msr = rdmsr(MSR_IA32_EXT_CONFIG);
283 } else if (cpu_model == 0x17) {
284 switch (cpu_stepping) {
285 case 0x6: /* Mobile Core 2 Duo */
288 default: /* Unknown stepping */
291 } else if (cpu_model == 0x1c) {
292 switch (cpu_stepping) {
293 case 0xa: /* 45nm Atom D400, N400 and D500 series */
302 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET.
304 * This method is described in Intel white paper "CPU
305 * Monitoring With DTS/PECI". (#322683)
307 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr);
309 tjtarget = (msr >> 16) & 0xff;
312 * On earlier generation of processors, the value
313 * obtained from IA32_TEMPERATURE_TARGET register is
314 * an offset that needs to be summed with a model
315 * specific base. It is however not clear what
316 * these numbers are, with the publicly available
317 * documents from Intel.
319 * For now, we consider [70, 110]C range, as
320 * described in #322683, as "reasonable" and accept
321 * these values whenever the MSR is available for
322 * read, regardless the CPU model.
324 if (tjtarget >= 70 && tjtarget <= 110)
325 sc->sc_tjmax = tjtarget;
327 device_printf(dev, "Tj(target) value %d "
328 "does not seem right.\n", tjtarget);
330 device_printf(dev, "Can not get Tj(target) "
331 "from your CPU, using 100C.\n");
335 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax);
337 sc->sc_cpu = device_get_unit(device_get_parent(dev));
338 sc->sc_gd = globaldata_find(sc->sc_cpu);
340 start_node = get_cpu_node_by_cpuid(sc->sc_cpu);
343 while (node != NULL) {
344 if (node->type == CORE_LEVEL) {
345 if (node->child_no == 0)
349 node = node->parent_node;
352 master_cpu = BSRCPUMASK(node->members);
354 device_printf(dev, "master cpu%d, count %u\n",
355 master_cpu, node->child_no);
357 if (sc->sc_cpu != master_cpu)
360 KKASSERT(node->child_no > 0);
361 sc->sc_nsens = node->child_no;
362 cpu_mask = node->members;
365 CPUMASK_ASSBIT(cpu_mask, sc->sc_cpu);
367 sc->sc_sens = kmalloc(sizeof(struct coretemp_sensor) * sc->sc_nsens,
368 M_DEVBUF, M_WAITOK | M_ZERO);
371 CPUSET_FOREACH(cpu, cpu_mask) {
372 KKASSERT(sens_idx < sc->sc_nsens);
373 csens = &sc->sc_sens[sens_idx];
376 * Add hw.sensors.cpuN.temp0 MIB.
378 ksnprintf(csens->c_sensdev.xname,
379 sizeof(csens->c_sensdev.xname), "cpu%d", cpu);
380 ksnprintf(csens->c_sens.desc, sizeof(csens->c_sens.desc),
381 "node%d core%d", get_chip_ID(cpu),
382 get_core_number_within_chip(cpu));
383 csens->c_sens.type = SENSOR_TEMP;
384 sensor_set_unknown(&csens->c_sens);
385 sensor_attach(&csens->c_sensdev, &csens->c_sens);
386 sensordev_install(&csens->c_sensdev);
391 if (cpu_thermal_feature & CPUID_THERMAL_PTM) {
392 boolean_t pkg_sens = TRUE;
395 * Package thermal sensor
399 while (node != NULL) {
400 if (node->type == CHIP_LEVEL) {
401 if (node->child_no == 0)
405 node = node->parent_node;
408 master_cpu = BSRCPUMASK(node->members);
410 device_printf(dev, "pkg master cpu%d\n",
413 if (sc->sc_cpu != master_cpu)
418 csens = sc->sc_pkg_sens =
419 kmalloc(sizeof(struct coretemp_sensor), M_DEVBUF,
423 * Add hw.sensors.cpu_nodeN.temp0 MIB.
425 ksnprintf(csens->c_sensdev.xname,
426 sizeof(csens->c_sensdev.xname), "cpu_node%d",
427 get_chip_ID(sc->sc_cpu));
428 ksnprintf(csens->c_sens.desc,
429 sizeof(csens->c_sens.desc), "node%d",
430 get_chip_ID(sc->sc_cpu));
431 csens->c_sens.type = SENSOR_TEMP;
432 sensor_set_unknown(&csens->c_sens);
433 sensor_attach(&csens->c_sensdev, &csens->c_sens);
434 sensordev_install(&csens->c_sensdev);
438 if (CORETEMP_HAS_PKGSENSOR(sc))
439 sensor_task_register(sc, coretemp_pkg_sensor_task, 2);
441 sensor_task_register(sc, coretemp_sensor_task, 2);
447 coretemp_detach(device_t dev)
449 struct coretemp_softc *sc = device_get_softc(dev);
451 if (sc->sc_nsens > 0) {
454 sensor_task_unregister(sc);
455 lwkt_synchronize_ipiqs("coretemp");
457 for (i = 0; i < sc->sc_nsens; ++i)
458 sensordev_deinstall(&sc->sc_sens[i].c_sensdev);
459 kfree(sc->sc_sens, M_DEVBUF);
461 if (sc->sc_pkg_sens != NULL) {
462 sensordev_deinstall(&sc->sc_pkg_sens->c_sensdev);
463 kfree(sc->sc_pkg_sens, M_DEVBUF);
470 coretemp_ipi_func(void *xsc)
472 struct coretemp_softc *sc = xsc;
474 sc->sc_msr = rdmsr(MSR_THERM_STATUS);
475 if (CORETEMP_HAS_PKGSENSOR(sc))
476 sc->sc_pkg_msr = rdmsr(MSR_PKG_THERM_STATUS);
478 atomic_clear_int(&sc->sc_flags, CORETEMP_FLAG_PENDING);
482 coretemp_ipi_send(struct coretemp_softc *sc, uint32_t flags)
484 KASSERT((sc->sc_flags & CORETEMP_FLAG_PENDING) == 0,
485 ("coretemp: cpu%d ipi is still pending", sc->sc_cpu));
486 atomic_set_int(&sc->sc_flags, flags | CORETEMP_FLAG_PENDING);
488 lwkt_send_ipiq_passive(sc->sc_gd, coretemp_ipi_func, sc);
492 coretemp_msr_temp(struct coretemp_softc *sc, uint64_t msr)
497 * Check for Thermal Status and Thermal Status Log.
499 if (MSR_THERM_STATUS_HAS_STATUS(msr))
500 device_printf(sc->sc_dev, "PROCHOT asserted\n");
502 if (msr & MSR_THERM_STATUS_READ_VALID)
503 temp = sc->sc_tjmax - __SHIFTOUT(msr, MSR_THERM_STATUS_READ);
505 temp = CORETEMP_TEMP_INVALID;
508 * Check for Critical Temperature Status and Critical
510 * It doesn't really matter if the current temperature is
511 * invalid because the "Critical Temperature Log" bit will
512 * tell us if the Critical Temperature has been reached in
513 * past. It's not directly related to the current temperature.
515 * If we reach a critical level, allow devctl(4) to catch this
516 * and shutdown the system.
518 if (MSR_THERM_STATUS_IS_CRITICAL(msr)) {
519 if ((sc->sc_flags & CORETEMP_FLAG_CRIT) == 0) {
520 char stemp[16], data[64];
522 device_printf(sc->sc_dev,
523 "critical temperature detected, "
524 "suggest system shutdown\n");
525 ksnprintf(stemp, sizeof(stemp), "%d", temp);
526 ksnprintf(data, sizeof(data),
527 "notify=0xcc node=%d core=%d",
528 get_chip_ID(sc->sc_cpu),
529 get_core_number_within_chip(sc->sc_cpu));
530 devctl_notify("coretemp", "Thermal", stemp, data);
531 atomic_set_int(&sc->sc_flags, CORETEMP_FLAG_CRIT);
533 } else if (sc->sc_flags & CORETEMP_FLAG_CRIT) {
534 atomic_clear_int(&sc->sc_flags, CORETEMP_FLAG_CRIT);
541 coretemp_pkg_msr_temp(struct coretemp_softc *sc, uint64_t msr)
546 * Check for Thermal Status and Thermal Status Log.
548 if (MSR_PKGTM_STATUS_HAS_STATUS(msr))
549 device_printf(sc->sc_dev, "package PROCHOT asserted\n");
551 temp = sc->sc_tjmax - __SHIFTOUT(msr, MSR_PKGTM_STATUS_READ);
554 * Check for Critical Temperature Status and Critical
556 * It doesn't really matter if the current temperature is
557 * invalid because the "Critical Temperature Log" bit will
558 * tell us if the Critical Temperature has been reached in
559 * past. It's not directly related to the current temperature.
561 * If we reach a critical level, allow devctl(4) to catch this
562 * and shutdown the system.
564 if (MSR_PKGTM_STATUS_IS_CRITICAL(msr)) {
565 if ((sc->sc_flags & CORETEMP_FLAG_PKGCRIT) == 0) {
566 char stemp[16], data[64];
568 device_printf(sc->sc_dev,
569 "critical temperature detected, "
570 "suggest system shutdown\n");
571 ksnprintf(stemp, sizeof(stemp), "%d", temp);
572 ksnprintf(data, sizeof(data), "notify=0xcc node=%d",
573 get_chip_ID(sc->sc_cpu));
574 devctl_notify("coretemp", "Thermal", stemp, data);
575 atomic_set_int(&sc->sc_flags, CORETEMP_FLAG_PKGCRIT);
577 } else if (sc->sc_flags & CORETEMP_FLAG_PKGCRIT) {
578 atomic_clear_int(&sc->sc_flags, CORETEMP_FLAG_PKGCRIT);
585 coretemp_msr_fetch(struct coretemp_softc *sc, uint64_t *msr, uint64_t *pkg_msr)
588 * Send IPI to the specific CPU to read the correct temperature.
589 * If the IPI does not complete yet, i.e. CORETEMP_FLAG_PENDING,
592 if (sc->sc_cpu != mycpuid) {
593 if ((sc->sc_flags & CORETEMP_FLAG_INITED) == 0) {
594 coretemp_ipi_send(sc, CORETEMP_FLAG_INITED);
597 if (sc->sc_flags & CORETEMP_FLAG_PENDING) {
598 /* IPI does not complete yet */
603 *pkg_msr = sc->sc_pkg_msr;
604 coretemp_ipi_send(sc, 0);
607 *msr = rdmsr(MSR_THERM_STATUS);
609 *pkg_msr = rdmsr(MSR_PKG_THERM_STATUS);
615 coretemp_sensor_update(struct coretemp_softc *sc, int temp)
619 if (temp == CORETEMP_TEMP_NOUPDATE) {
620 /* No updates; keep the previous value */
621 } else if (temp == CORETEMP_TEMP_INVALID) {
622 for (i = 0; i < sc->sc_nsens; ++i)
623 sensor_set_invalid(&sc->sc_sens[i].c_sens);
625 for (i = 0; i < sc->sc_nsens; ++i) {
626 coretemp_sensor_set(&sc->sc_sens[i].c_sens, sc,
627 CORETEMP_FLAG_CRIT, temp);
633 coretemp_pkg_sensor_update(struct coretemp_softc *sc, int temp)
635 KKASSERT(sc->sc_pkg_sens != NULL);
636 if (temp == CORETEMP_TEMP_NOUPDATE) {
637 /* No updates; keep the previous value */
638 } else if (temp == CORETEMP_TEMP_INVALID) {
639 sensor_set_invalid(&sc->sc_pkg_sens->c_sens);
641 coretemp_sensor_set(&sc->sc_pkg_sens->c_sens, sc,
642 CORETEMP_FLAG_PKGCRIT, temp);
647 coretemp_sensor_task(void *arg)
649 struct coretemp_softc *sc = arg;
653 if (!coretemp_msr_fetch(sc, &msr, NULL))
654 temp = CORETEMP_TEMP_NOUPDATE;
656 temp = coretemp_msr_temp(sc, msr);
658 coretemp_sensor_update(sc, temp);
662 coretemp_pkg_sensor_task(void *arg)
664 struct coretemp_softc *sc = arg;
665 uint64_t msr, pkg_msr;
668 if (!coretemp_msr_fetch(sc, &msr, &pkg_msr)) {
669 temp = CORETEMP_TEMP_NOUPDATE;
670 pkg_temp = CORETEMP_TEMP_NOUPDATE;
672 temp = coretemp_msr_temp(sc, msr);
673 pkg_temp = coretemp_pkg_msr_temp(sc, pkg_msr);
676 coretemp_sensor_update(sc, temp);
677 coretemp_pkg_sensor_update(sc, pkg_temp);