sys/dev/agp/agp_i810.c

   1 /*
   2  * Copyright (c) 2000 Doug Rabson
   3  * Copyright (c) 2000 Ruslan Ermilov
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  *      $FreeBSD: src/sys/dev/agp/agp_i810.c,v 1.43 2007/11/12 21:51:36 jhb Exp $
  28  *      $DragonFly: src/sys/dev/agp/agp_i810.c,v 1.19 2008/10/03 08:56:58 hasso Exp $
  29  */
  30
  31 /*
  32  * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
  33  * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
  34  */
  35
  36 #include "opt_bus.h"
  37
  38 #include <sys/param.h>
  39 #include <sys/systm.h>
  40 #include <sys/malloc.h>
  41 #include <sys/kernel.h>
  42 #include <sys/bus.h>
  43 #include <sys/lock.h>
  44 #include <sys/rman.h>
  45
  46 #include <bus/pci/pcivar.h>
  47 #include <bus/pci/pcireg.h>
  48 #include "agppriv.h"
  49 #include "agpreg.h"
  50
  51 #include <vm/vm.h>
  52 #include <vm/vm_object.h>
  53 #include <vm/vm_page.h>
  54 #include <vm/vm_pageout.h>
  55 #include <vm/pmap.h>
  56
  57 #include <machine/md_var.h>
  58
  59 #define bus_read_1(r, o) \
  60                    bus_space_read_1((r)->r_bustag, (r)->r_bushandle, (o))
  61 #define bus_read_4(r, o) \
  62                    bus_space_read_4((r)->r_bustag, (r)->r_bushandle, (o))
  63 #define bus_write_4(r, o, v) \
  64                     bus_space_write_4((r)->r_bustag, (r)->r_bushandle, (o), (v))
  65
  66 MALLOC_DECLARE(M_AGP);
  67
  68 enum {
  69         CHIP_I810,      /* i810/i815 */
  70         CHIP_I830,      /* 830M/845G */
  71         CHIP_I855,      /* 852GM/855GM/865G */
  72         CHIP_I915,      /* 915G/915GM */
  73         CHIP_I965,      /* G965 */
  74         CHIP_G33,       /* G33/Q33/Q35 */
  75         CHIP_IGD,       /* G33 like IGD */
  76         CHIP_G4X,       /* G45/Q45 */
  77 };
  78
  79 /* The i810 through i855 have the registers at BAR 1, and the GATT gets
  80  * allocated by us.  The i915 has registers in BAR 0 and the GATT is at the
  81  * start of the stolen memory, and should only be accessed by the OS through
  82  * BAR 3.  The G965 has registers and GATT in the same BAR (0) -- first 512KB
  83  * is registers, second 512KB is GATT.
  84  */
  85 static struct resource_spec agp_i810_res_spec[] = {
  86         { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
  87         { -1, 0 }
  88 };
  89
  90 static struct resource_spec agp_i915_res_spec[] = {
  91         { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
  92         { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
  93         { -1, 0 }
  94 };
  95
  96 static struct resource_spec agp_i965_res_spec[] = {
  97         { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
  98         { -1, 0 }
  99 };
 100
 101 struct agp_i810_softc {
 102         struct agp_softc agp;
 103         u_int32_t initial_aperture;     /* aperture size at startup */
 104         struct agp_gatt *gatt;
 105         int chiptype;                   /* i810-like or i830 */
 106         u_int32_t dcache_size;          /* i810 only */
 107         u_int32_t stolen;               /* number of i830/845 gtt entries for stolen memory */
 108         device_t bdev;                  /* bridge device */
 109
 110         void *argb_cursor;              /* contigmalloc area for ARGB cursor */
 111
 112         struct resource_spec * sc_res_spec;
 113         struct resource *sc_res[2];
 114 };
 115
 116 /* For adding new devices, devid is the id of the graphics controller
 117  * (pci:0:2:0, for example).  The placeholder (usually at pci:0:2:1) for the
 118  * second head should never be added.  The bridge_offset is the offset to
 119  * subtract from devid to get the id of the hostb that the device is on.
 120  */
 121 static const struct agp_i810_match {
 122         int devid;
 123         int chiptype;
 124         int bridge_offset;
 125         char *name;
 126 } agp_i810_matches[] = {
 127         {0x71218086, CHIP_I810, 0x00010000,
 128             "Intel 82810 (i810 GMCH) SVGA controller"},
 129         {0x71238086, CHIP_I810, 0x00010000,
 130             "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
 131         {0x71258086, CHIP_I810, 0x00010000,
 132             "Intel 82810E (i810E GMCH) SVGA controller"},
 133         {0x11328086, CHIP_I810, 0x00020000,
 134             "Intel 82815 (i815 GMCH) SVGA controller"},
 135         {0x35778086, CHIP_I830, 0x00020000,
 136             "Intel 82830M (830M GMCH) SVGA controller"},
 137         {0x25628086, CHIP_I830, 0x00020000,
 138             "Intel 82845M (845M GMCH) SVGA controller"},
 139         {0x35828086, CHIP_I855, 0x00020000,
 140             "Intel 82852/855GM SVGA controller"},
 141         {0x25728086, CHIP_I855, 0x00020000,
 142             "Intel 82865G (865G GMCH) SVGA controller"},
 143         {0x25828086, CHIP_I915, 0x00020000,
 144             "Intel 82915G (915G GMCH) SVGA controller"},
 145         {0x258A8086, CHIP_I915, 0x00020000,
 146             "Intel E7221 SVGA controller"},
 147         {0x25928086, CHIP_I915, 0x00020000,
 148             "Intel 82915GM (915GM GMCH) SVGA controller"},
 149         {0x27728086, CHIP_I915, 0x00020000,
 150             "Intel 82945G (945G GMCH) SVGA controller"},
 151         {0x27A28086, CHIP_I915, 0x00020000,
 152             "Intel 82945GM (945GM GMCH) SVGA controller"},
 153         {0x27AE8086, CHIP_I915, 0x00020000,
 154             "Intel 945GME SVGA controller"},
 155         {0x29728086, CHIP_I965, 0x00020000,
 156             "Intel 946GZ SVGA controller"},
 157         {0x29828086, CHIP_I965, 0x00020000,
 158             "Intel G965 SVGA controller"},
 159         {0x29928086, CHIP_I965, 0x00020000,
 160             "Intel Q965 SVGA controller"},
 161         {0x29A28086, CHIP_I965, 0x00020000,
 162             "Intel G965 SVGA controller"},
 163         {0x29B28086, CHIP_G33, 0x00020000,
 164             "Intel Q35 SVGA controller"},
 165         {0x29C28086, CHIP_G33, 0x00020000,
 166             "Intel G33 SVGA controller"},
 167         {0x29D28086, CHIP_G33, 0x00020000,
 168             "Intel Q33 SVGA controller"},
 169         {0x2A028086, CHIP_I965, 0x00020000,
 170             "Intel GM965 SVGA controller"},
 171         {0x2A128086, CHIP_I965, 0x00020000,
 172             "Intel GME965 SVGA controller"},
 173         {0x2A428086, CHIP_G4X, 0x00020000,
 174             "Intel GM45 SVGA controller"},
 175         {0x2E028086, CHIP_G4X, 0x00020000,
 176             "Intel 4 Series SVGA controller"},
 177         {0x2E128086, CHIP_G4X, 0x00020000,
 178             "Intel Q45 SVGA controller"},
 179         {0x2E228086, CHIP_G4X, 0x00020000,
 180             "Intel G45 SVGA controller"},
 181         {0x2E328086, CHIP_G4X, 0x00020000,
 182             "Intel G41 SVGA controller"},
 183         {0xA0018086, CHIP_IGD, 0x00010000,
 184             "Intel IGD SVGA controller"},
 185         {0xA0118086, CHIP_IGD, 0x00010000,
 186             "Intel IGD SVGA controller"},
 187         {0, 0, 0, NULL}
 188 };
 189
 190 static const struct agp_i810_match*
 191 agp_i810_match(device_t dev)
 192 {
 193         int i, devid;
 194
 195         if (pci_get_class(dev) != PCIC_DISPLAY
 196             || pci_get_subclass(dev) != PCIS_DISPLAY_VGA)
 197                 return NULL;
 198
 199         devid = pci_get_devid(dev);
 200         for (i = 0; agp_i810_matches[i].devid != 0; i++) {
 201                 if (agp_i810_matches[i].devid == devid)
 202                     break;
 203         }
 204         if (agp_i810_matches[i].devid == 0)
 205                 return NULL;
 206         else
 207                 return &agp_i810_matches[i];
 208 }
 209
 210 /*
 211  * Find bridge device.
 212  */
 213 static device_t
 214 agp_i810_find_bridge(device_t dev)
 215 {
 216         device_t *children, child;
 217         int nchildren, i;
 218         u_int32_t devid;
 219         const struct agp_i810_match *match;
 220
 221         match = agp_i810_match(dev);
 222         devid = match->devid - match->bridge_offset;
 223
 224         if (device_get_children(device_get_parent(device_get_parent(dev)),
 225                     &children, &nchildren))
 226                 return 0;
 227
 228         for (i = 0; i < nchildren; i++) {
 229                 child = children[i];
 230
 231                 if (pci_get_devid(child) == devid) {
 232                         kfree(children, M_TEMP);
 233                         return child;
 234                 }
 235         }
 236         kfree(children, M_TEMP);
 237         return 0;
 238 }
 239
 240 static void
 241 agp_i810_identify(driver_t *driver, device_t parent)
 242 {
 243
 244         if (device_find_child(parent, "agp", -1) == NULL &&
 245             agp_i810_match(parent))
 246                 device_add_child(parent, "agp", -1);
 247 }
 248
 249 static int
 250 agp_i810_probe(device_t dev)
 251 {
 252         device_t bdev;
 253         const struct agp_i810_match *match;
 254         u_int8_t smram;
 255         int gcc1, deven;
 256
 257         if (resource_disabled("agp", device_get_unit(dev)))
 258                 return (ENXIO);
 259         match = agp_i810_match(dev);
 260         if (match == NULL)
 261                 return ENXIO;
 262
 263         bdev = agp_i810_find_bridge(dev);
 264         if (!bdev) {
 265                 if (bootverbose)
 266                         kprintf("I810: can't find bridge device\n");
 267                 return ENXIO;
 268         }
 269
 270         /*
 271          * checking whether internal graphics device has been activated.
 272          */
 273         switch (match->chiptype) {
 274         case CHIP_I810:
 275                 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
 276                 if ((smram & AGP_I810_SMRAM_GMS) ==
 277                     AGP_I810_SMRAM_GMS_DISABLED) {
 278                         if (bootverbose)
 279                                 kprintf("I810: disabled, not probing\n");
 280                         return ENXIO;
 281                 }
 282                 break;
 283         case CHIP_I830:
 284         case CHIP_I855:
 285                 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
 286                 if ((gcc1 & AGP_I830_GCC1_DEV2) ==
 287                     AGP_I830_GCC1_DEV2_DISABLED) {
 288                         if (bootverbose)
 289                                 kprintf("I830: disabled, not probing\n");
 290                         return ENXIO;
 291                 }
 292                 break;
 293         case CHIP_I915:
 294         case CHIP_I965:
 295         case CHIP_G33:
 296         case CHIP_IGD:
 297         case CHIP_G4X:
 298                 deven = pci_read_config(bdev, AGP_I915_DEVEN, 4);
 299                 if ((deven & AGP_I915_DEVEN_D2F0) ==
 300                     AGP_I915_DEVEN_D2F0_DISABLED) {
 301                         if (bootverbose)
 302                                 kprintf("I915: disabled, not probing\n");
 303                         return ENXIO;
 304                 }
 305                 break;
 306         }
 307
 308         device_verbose(dev);
 309         if (match->devid == 0x35828086) {
 310                 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
 311                 case AGP_I855_GME:
 312                         device_set_desc(dev,
 313                             "Intel 82855GME (855GME GMCH) SVGA controller");
 314                         break;
 315                 case AGP_I855_GM:
 316                         device_set_desc(dev,
 317                             "Intel 82855GM (855GM GMCH) SVGA controller");
 318                         break;
 319                 case AGP_I852_GME:
 320                         device_set_desc(dev,
 321                             "Intel 82852GME (852GME GMCH) SVGA controller");
 322                         break;
 323                 case AGP_I852_GM:
 324                         device_set_desc(dev,
 325                             "Intel 82852GM (852GM GMCH) SVGA controller");
 326                         break;
 327                 default:
 328                         device_set_desc(dev,
 329                             "Intel 8285xM (85xGM GMCH) SVGA controller");
 330                         break;
 331                 }
 332         } else {
 333                 device_set_desc(dev, match->name);
 334         }
 335
 336         return BUS_PROBE_DEFAULT;
 337 }
 338
 339 static void
 340 agp_i810_dump_regs(device_t dev)
 341 {
 342         struct agp_i810_softc *sc = device_get_softc(dev);
 343
 344         device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
 345             bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
 346
 347         switch (sc->chiptype) {
 348         case CHIP_I810:
 349                 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
 350                     pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
 351                 break;
 352         case CHIP_I830:
 353                 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
 354                     pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
 355                 break;
 356         case CHIP_I855:
 357                 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
 358                     pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
 359                 break;
 360         case CHIP_I915:
 361         case CHIP_I965:
 362         case CHIP_G33:
 363         case CHIP_IGD:
 364         case CHIP_G4X:
 365                 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
 366                     pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
 367                 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
 368                     pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
 369                 break;
 370         }
 371         device_printf(dev, "Aperture resource size: %d bytes\n",
 372             AGP_GET_APERTURE(dev));
 373 }
 374
 375 static int
 376 agp_i810_attach(device_t dev)
 377 {
 378         struct agp_i810_softc *sc = device_get_softc(dev);
 379         struct agp_gatt *gatt;
 380         const struct agp_i810_match *match;
 381         int error;
 382
 383         sc->bdev = agp_i810_find_bridge(dev);
 384         if (!sc->bdev)
 385                 return ENOENT;
 386
 387         match = agp_i810_match(dev);
 388         sc->chiptype = match->chiptype;
 389
 390         switch (sc->chiptype) {
 391         case CHIP_I810:
 392         case CHIP_I830:
 393         case CHIP_I855:
 394                 sc->sc_res_spec = agp_i810_res_spec;
 395                 agp_set_aperture_resource(dev, AGP_APBASE);
 396                 break;
 397         case CHIP_I915:
 398         case CHIP_G33:
 399         case CHIP_IGD:
 400                 sc->sc_res_spec = agp_i915_res_spec;
 401                 agp_set_aperture_resource(dev, AGP_I915_GMADR);
 402                 break;
 403         case CHIP_I965:
 404         case CHIP_G4X:
 405                 sc->sc_res_spec = agp_i965_res_spec;
 406                 agp_set_aperture_resource(dev, AGP_I915_GMADR);
 407                 break;
 408         }
 409
 410         error = agp_generic_attach(dev);
 411         if (error)
 412                 return error;
 413
 414         if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 &&
 415             sc->chiptype != CHIP_IGD && sc->chiptype != CHIP_G4X &&
 416             ptoa((vm_paddr_t)Maxmem) > 0xfffffffful)
 417         {
 418                 device_printf(dev, "agp_i810.c does not support physical "
 419                     "memory above 4GB.\n");
 420                 return ENOENT;
 421         }
 422
 423         if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) {
 424                 agp_generic_detach(dev);
 425                 return ENODEV;
 426         }
 427
 428         sc->initial_aperture = AGP_GET_APERTURE(dev);
 429         if (sc->initial_aperture == 0) {
 430                 device_printf(dev, "bad initial aperture size, disabling\n");
 431                 return ENXIO;
 432         }
 433
 434         gatt = kmalloc( sizeof(struct agp_gatt), M_AGP, M_INTWAIT);
 435         sc->gatt = gatt;
 436
 437         gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
 438
 439         if ( sc->chiptype == CHIP_I810 ) {
 440                 /* Some i810s have on-chip memory called dcache */
 441                 if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) &
 442                     AGP_I810_DRT_POPULATED)
 443                         sc->dcache_size = 4 * 1024 * 1024;
 444                 else
 445                         sc->dcache_size = 0;
 446
 447                 /* According to the specs the gatt on the i810 must be 64k */
 448                 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0,
 449                                         0, ~0, PAGE_SIZE, 0);
 450                 if (!gatt->ag_virtual) {
 451                         if (bootverbose)
 452                                 device_printf(dev, "contiguous allocation failed\n");
 453                         bus_release_resources(dev, sc->sc_res_spec,
 454                             sc->sc_res);
 455                         kfree(gatt, M_AGP);
 456                         agp_generic_detach(dev);
 457                         return ENOMEM;
 458                 }
 459                 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t));
 460
 461                 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
 462                 agp_flush_cache();
 463                 /* Install the GATT. */
 464                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
 465                     gatt->ag_physical | 1);
 466         } else if ( sc->chiptype == CHIP_I830 ) {
 467                 /* The i830 automatically initializes the 128k gatt on boot. */
 468                 unsigned int gcc1, pgtblctl;
 469
 470                 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
 471                 switch (gcc1 & AGP_I830_GCC1_GMS) {
 472                         case AGP_I830_GCC1_GMS_STOLEN_512:
 473                                 sc->stolen = (512 - 132) * 1024 / 4096;
 474                                 break;
 475                         case AGP_I830_GCC1_GMS_STOLEN_1024:
 476                                 sc->stolen = (1024 - 132) * 1024 / 4096;
 477                                 break;
 478                         case AGP_I830_GCC1_GMS_STOLEN_8192:
 479                                 sc->stolen = (8192 - 132) * 1024 / 4096;
 480                                 break;
 481                         default:
 482                                 sc->stolen = 0;
 483                                 device_printf(dev, "unknown memory configuration, disabling\n");
 484                                 bus_release_resources(dev, sc->sc_res_spec,
 485                                     sc->sc_res);
 486                                 kfree(gatt, M_AGP);
 487                                 agp_generic_detach(dev);
 488                                 return EINVAL;
 489                 }
 490                 if (sc->stolen > 0) {
 491                         device_printf(dev, "detected %dk stolen memory\n",
 492                             sc->stolen * 4);
 493                 }
 494                 device_printf(dev, "aperture size is %dM\n",
 495                     sc->initial_aperture / 1024 / 1024);
 496
 497                 /* GATT address is already in there, make sure it's enabled */
 498                 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
 499                 pgtblctl |= 1;
 500                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
 501
 502                 gatt->ag_physical = pgtblctl & ~1;
 503         } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 ||
 504             sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
 505             sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
 506                 unsigned int gcc1, pgtblctl, stolen, gtt_size;
 507
 508                 /* Stolen memory is set up at the beginning of the aperture by
 509                  * the BIOS, consisting of the GATT followed by 4kb for the
 510                  * BIOS display.
 511                  */
 512                 switch (sc->chiptype) {
 513                 case CHIP_I855:
 514                         gtt_size = 128;
 515                         break;
 516                 case CHIP_I915:
 517                         gtt_size = 256;
 518                         break;
 519                 case CHIP_I965:
 520                         switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
 521                             AGP_I810_PGTBL_SIZE_MASK) {
 522                         case AGP_I810_PGTBL_SIZE_128KB:
 523                                 gtt_size = 128;
 524                                 break;
 525                         case AGP_I810_PGTBL_SIZE_256KB:
 526                                 gtt_size = 256;
 527                                 break;
 528                         case AGP_I810_PGTBL_SIZE_512KB:
 529                                 gtt_size = 512;
 530                                 break;
 531                         case AGP_I965_PGTBL_SIZE_1MB:
 532                                 gtt_size = 1024;
 533                                 break;
 534                         case AGP_I965_PGTBL_SIZE_2MB:
 535                                 gtt_size = 2048;
 536                                 break;
 537                         case AGP_I965_PGTBL_SIZE_1_5MB:
 538                                 gtt_size = 1024 + 512;
 539                                 break;
 540                         default:
 541                                 device_printf(dev, "Bad PGTBL size\n");
 542                                 bus_release_resources(dev, sc->sc_res_spec,
 543                                     sc->sc_res);
 544                                 kfree(gatt, M_AGP);
 545                                 agp_generic_detach(dev);
 546                                 return EINVAL;
 547                         }
 548                         break;
 549                 case CHIP_G33:
 550                         gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
 551                         switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
 552                         case AGP_G33_MGGC_GGMS_SIZE_1M:
 553                                 gtt_size = 1024;
 554                                 break;
 555                         case AGP_G33_MGGC_GGMS_SIZE_2M:
 556                                 gtt_size = 2048;
 557                                 break;
 558                         default:
 559                                 device_printf(dev, "Bad PGTBL size\n");
 560                                 bus_release_resources(dev, sc->sc_res_spec,
 561                                     sc->sc_res);
 562                                 kfree(gatt, M_AGP);
 563                                 agp_generic_detach(dev);
 564                                 return EINVAL;
 565                         }
 566                         break;
 567                 case CHIP_IGD:
 568                 case CHIP_G4X:
 569                         gtt_size = 0;
 570                         break;
 571                 default:
 572                         device_printf(dev, "Bad chiptype\n");
 573                         bus_release_resources(dev, sc->sc_res_spec,
 574                             sc->sc_res);
 575                         kfree(gatt, M_AGP);
 576                         agp_generic_detach(dev);
 577                         return EINVAL;
 578                 }
 579
 580                 /* GCC1 is called MGGC on i915+ */
 581                 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
 582                 switch (gcc1 & AGP_I855_GCC1_GMS) {
 583                 case AGP_I855_GCC1_GMS_STOLEN_1M:
 584                         stolen = 1024;
 585                         break;
 586                 case AGP_I855_GCC1_GMS_STOLEN_4M:
 587                         stolen = 4 * 1024;
 588                         break;
 589                 case AGP_I855_GCC1_GMS_STOLEN_8M:
 590                         stolen = 8 * 1024;
 591                         break;
 592                 case AGP_I855_GCC1_GMS_STOLEN_16M:
 593                         stolen = 16 * 1024;
 594                         break;
 595                 case AGP_I855_GCC1_GMS_STOLEN_32M:
 596                         stolen = 32 * 1024;
 597                         break;
 598                 case AGP_I915_GCC1_GMS_STOLEN_48M:
 599                         if (sc->chiptype == CHIP_I915 ||
 600                             sc->chiptype == CHIP_I965 ||
 601                             sc->chiptype == CHIP_G33 ||
 602                             sc->chiptype == CHIP_IGD ||
 603                             sc->chiptype == CHIP_G4X) {
 604                                 stolen = 48 * 1024;
 605                         } else {
 606                                 stolen = 0;
 607                         }
 608                         break;
 609                 case AGP_I915_GCC1_GMS_STOLEN_64M:
 610                         if (sc->chiptype == CHIP_I915 ||
 611                             sc->chiptype == CHIP_I965 ||
 612                             sc->chiptype == CHIP_G33 ||
 613                             sc->chiptype == CHIP_IGD ||
 614                             sc->chiptype == CHIP_G4X) {
 615                                 stolen = 64 * 1024;
 616                         } else {
 617                                 stolen = 0;
 618                         }
 619                         break;
 620                 case AGP_G33_GCC1_GMS_STOLEN_128M:
 621                         if (sc->chiptype == CHIP_I965 ||
 622                             sc->chiptype == CHIP_G33 ||
 623                             sc->chiptype == CHIP_IGD ||
 624                             sc->chiptype == CHIP_G4X) {
 625                                 stolen = 128 * 1024;
 626                         } else {
 627                                 stolen = 0;
 628                         }
 629                         break;
 630                 case AGP_G33_GCC1_GMS_STOLEN_256M:
 631                         if (sc->chiptype == CHIP_I965 ||
 632                             sc->chiptype == CHIP_G33 ||
 633                             sc->chiptype == CHIP_IGD ||
 634                             sc->chiptype == CHIP_G4X) {
 635                                 stolen = 256 * 1024;
 636                         } else {
 637                                 stolen = 0;
 638                         }
 639                         break;
 640                 case AGP_G4X_GCC1_GMS_STOLEN_96M:
 641                         if (sc->chiptype == CHIP_I965 ||
 642                             sc->chiptype == CHIP_G4X) {
 643                                 stolen = 96 * 1024;
 644                         } else {
 645                                 stolen = 0;
 646                         }
 647                         break;
 648                 case AGP_G4X_GCC1_GMS_STOLEN_160M:
 649                         if (sc->chiptype == CHIP_I965 ||
 650                             sc->chiptype == CHIP_G4X) {
 651                                 stolen = 160 * 1024;
 652                         } else {
 653                                 stolen = 0;
 654                         }
 655                         break;
 656                 case AGP_G4X_GCC1_GMS_STOLEN_224M:
 657                         if (sc->chiptype == CHIP_I965 ||
 658                             sc->chiptype == CHIP_G4X) {
 659                                 stolen = 224 * 1024;
 660                         } else {
 661                                 stolen = 0;
 662                         }
 663                         break;
 664                 case AGP_G4X_GCC1_GMS_STOLEN_352M:
 665                         if (sc->chiptype == CHIP_I965 ||
 666                             sc->chiptype == CHIP_G4X) {
 667                                 stolen = 352 * 1024;
 668                         } else {
 669                                 stolen = 0;
 670                         }
 671                         break;
 672                 default:
 673                         device_printf(dev, "unknown memory configuration, "
 674                             "disabling\n");
 675                         bus_release_resources(dev, sc->sc_res_spec,
 676                             sc->sc_res);
 677                         kfree(gatt, M_AGP);
 678                         agp_generic_detach(dev);
 679                         return EINVAL;
 680                 }
 681
 682                 gtt_size += 4;
 683
 684                 sc->stolen = (stolen - gtt_size) * 1024 / 4096;
 685                 if (sc->stolen > 0)
 686                         device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
 687                 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
 688
 689                 /* GATT address is already in there, make sure it's enabled */
 690                 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
 691                 pgtblctl |= 1;
 692                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
 693
 694                 gatt->ag_physical = pgtblctl & ~1;
 695         }
 696
 697         if (0)
 698                 agp_i810_dump_regs(dev);
 699
 700         return 0;
 701 }
 702
 703 static int
 704 agp_i810_detach(device_t dev)
 705 {
 706         struct agp_i810_softc *sc = device_get_softc(dev);
 707
 708         agp_free_cdev(dev);
 709
 710         /* Clear the GATT base. */
 711         if ( sc->chiptype == CHIP_I810 ) {
 712                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
 713         } else {
 714                 unsigned int pgtblctl;
 715                 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
 716                 pgtblctl &= ~1;
 717                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
 718         }
 719
 720         /* Put the aperture back the way it started. */
 721         AGP_SET_APERTURE(dev, sc->initial_aperture);
 722
 723         if ( sc->chiptype == CHIP_I810 ) {
 724                 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
 725         }
 726         kfree(sc->gatt, M_AGP);
 727
 728         bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
 729         agp_free_res(dev);
 730
 731         return 0;
 732 }
 733
 734 static int
 735 agp_i810_resume(device_t dev)
 736 {
 737         struct agp_i810_softc *sc;
 738         sc = device_get_softc(dev);
 739
 740         AGP_SET_APERTURE(dev, sc->initial_aperture);
 741
 742         /* Install the GATT. */
 743         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
 744         sc->gatt->ag_physical | 1);
 745
 746         return (bus_generic_resume(dev));
 747 }
 748
 749 /**
 750  * Sets the PCI resource size of the aperture on i830-class and below chipsets,
 751  * while returning failure on later chipsets when an actual change is
 752  * requested.
 753  *
 754  * This whole function is likely bogus, as the kernel would probably need to
 755  * reconfigure the placement of the AGP aperture if a larger size is requested,
 756  * which doesn't happen currently.
 757  */
 758 static int
 759 agp_i810_set_aperture(device_t dev, u_int32_t aperture)
 760 {
 761         struct agp_i810_softc *sc = device_get_softc(dev);
 762         u_int16_t miscc, gcc1;
 763
 764         switch (sc->chiptype) {
 765         case CHIP_I810:
 766                 /*
 767                  * Double check for sanity.
 768                  */
 769                 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
 770                         device_printf(dev, "bad aperture size %d\n", aperture);
 771                         return EINVAL;
 772                 }
 773
 774                 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
 775                 miscc &= ~AGP_I810_MISCC_WINSIZE;
 776                 if (aperture == 32 * 1024 * 1024)
 777                         miscc |= AGP_I810_MISCC_WINSIZE_32;
 778                 else
 779                         miscc |= AGP_I810_MISCC_WINSIZE_64;
 780
 781                 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
 782                 break;
 783         case CHIP_I830:
 784                 if (aperture != 64 * 1024 * 1024 &&
 785                     aperture != 128 * 1024 * 1024) {
 786                         device_printf(dev, "bad aperture size %d\n", aperture);
 787                         return EINVAL;
 788                 }
 789                 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
 790                 gcc1 &= ~AGP_I830_GCC1_GMASIZE;
 791                 if (aperture == 64 * 1024 * 1024)
 792                         gcc1 |= AGP_I830_GCC1_GMASIZE_64;
 793                 else
 794                         gcc1 |= AGP_I830_GCC1_GMASIZE_128;
 795
 796                 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
 797                 break;
 798         case CHIP_I855:
 799         case CHIP_I915:
 800         case CHIP_I965:
 801         case CHIP_G33:
 802         case CHIP_IGD:
 803         case CHIP_G4X:
 804                 return agp_generic_set_aperture(dev, aperture);
 805         }
 806
 807         return 0;
 808 }
 809
 810 /**
 811  * Writes a GTT entry mapping the page at the given offset from the beginning
 812  * of the aperture to the given physical address.
 813  */
 814 static void
 815 agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical,
 816     int enabled)
 817 {
 818         struct agp_i810_softc *sc = device_get_softc(dev);
 819         u_int32_t pte;
 820
 821         pte = (u_int32_t)physical | 1;
 822         if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
 823             sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
 824                 pte |= (physical & 0x0000000f00000000ull) >> 28;
 825         } else {
 826                 /* If we do actually have memory above 4GB on an older system,
 827                  * crash cleanly rather than scribble on system memory,
 828                  * so we know we need to fix it.
 829                  */
 830                 KASSERT((pte & 0x0000000f00000000ull) == 0,
 831                     (">4GB physical address in agp"));
 832         }
 833
 834         switch (sc->chiptype) {
 835         case CHIP_I810:
 836         case CHIP_I830:
 837         case CHIP_I855:
 838                 bus_write_4(sc->sc_res[0],
 839                     AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte);
 840                 break;
 841         case CHIP_I915:
 842         case CHIP_G33:
 843         case CHIP_IGD:
 844                 bus_write_4(sc->sc_res[1],
 845                     (offset >> AGP_PAGE_SHIFT) * 4, pte);
 846                 break;
 847         case CHIP_I965:
 848                 bus_write_4(sc->sc_res[0],
 849                     (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte);
 850                 break;
 851         case CHIP_G4X:
 852                 bus_write_4(sc->sc_res[0],
 853                     (offset >> AGP_PAGE_SHIFT) * 4 + (2 * 1024 * 1024), pte);
 854                 break;
 855         }
 856 }
 857
 858 static int
 859 agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical)
 860 {
 861         struct agp_i810_softc *sc = device_get_softc(dev);
 862
 863         if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
 864                 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries);
 865                 return EINVAL;
 866         }
 867
 868         if ( sc->chiptype != CHIP_I810 ) {
 869                 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
 870                         device_printf(dev, "trying to bind into stolen memory");
 871                         return EINVAL;
 872                 }
 873         }
 874
 875         agp_i810_write_gtt_entry(dev, offset, physical, 1);
 876
 877         return 0;
 878 }
 879
 880 static int
 881 agp_i810_unbind_page(device_t dev, int offset)
 882 {
 883         struct agp_i810_softc *sc = device_get_softc(dev);
 884
 885         if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
 886                 return EINVAL;
 887
 888         if ( sc->chiptype != CHIP_I810 ) {
 889                 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
 890                         device_printf(dev, "trying to unbind from stolen memory");
 891                         return EINVAL;
 892                 }
 893         }
 894
 895         agp_i810_write_gtt_entry(dev, offset, 0, 0);
 896
 897         return 0;
 898 }
 899
 900 /*
 901  * Writing via memory mapped registers already flushes all TLBs.
 902  */
 903 static void
 904 agp_i810_flush_tlb(device_t dev)
 905 {
 906 }
 907
 908 static int
 909 agp_i810_enable(device_t dev, u_int32_t mode)
 910 {
 911
 912         return 0;
 913 }
 914
 915 static struct agp_memory *
 916 agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
 917 {
 918         struct agp_i810_softc *sc = device_get_softc(dev);
 919         struct agp_memory *mem;
 920
 921         if ((size & (AGP_PAGE_SIZE - 1)) != 0)
 922                 return 0;
 923
 924         if (sc->agp.as_allocated + size > sc->agp.as_maxmem)
 925                 return 0;
 926
 927         if (type == 1) {
 928                 /*
 929                  * Mapping local DRAM into GATT.
 930                  */
 931                 if ( sc->chiptype != CHIP_I810 )
 932                         return 0;
 933                 if (size != sc->dcache_size)
 934                         return 0;
 935         } else if (type == 2) {
 936                 /*
 937                  * Type 2 is the contiguous physical memory type, that hands
 938                  * back a physical address.  This is used for cursors on i810.
 939                  * Hand back as many single pages with physical as the user
 940                  * wants, but only allow one larger allocation (ARGB cursor)
 941                  * for simplicity.
 942                  */
 943                 if (size != AGP_PAGE_SIZE) {
 944                         if (sc->argb_cursor != NULL)
 945                                 return 0;
 946
 947                         /* Allocate memory for ARGB cursor, if we can. */
 948                         sc->argb_cursor = contigmalloc(size, M_AGP,
 949                            0, 0, ~0, PAGE_SIZE, 0);
 950                         if (sc->argb_cursor == NULL)
 951                                 return 0;
 952                 }
 953         }
 954
 955         mem = kmalloc(sizeof *mem, M_AGP, M_INTWAIT);
 956         mem->am_id = sc->agp.as_nextid++;
 957         mem->am_size = size;
 958         mem->am_type = type;
 959         if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
 960                 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
 961                                                  atop(round_page(size)));
 962         else
 963                 mem->am_obj = 0;
 964
 965         if (type == 2) {
 966                 if (size == AGP_PAGE_SIZE) {
 967                         /*
 968                          * Allocate and wire down the page now so that we can
 969                          * get its physical address.
 970                          */
 971                         vm_page_t m;
 972
 973                         m = vm_page_grab(mem->am_obj, 0,
 974                                          VM_ALLOC_NORMAL|VM_ALLOC_ZERO|VM_ALLOC_RETRY);
 975                         if ((m->flags & PG_ZERO) == 0)
 976                                 vm_page_zero_fill(m);
 977                         vm_page_wire(m);
 978                         mem->am_physical = VM_PAGE_TO_PHYS(m);
 979                         vm_page_wakeup(m);
 980                 } else {
 981                         /* Our allocation is already nicely wired down for us.
 982                          * Just grab the physical address.
 983                          */
 984                         mem->am_physical = vtophys(sc->argb_cursor);
 985                 }
 986         } else {
 987                 mem->am_physical = 0;
 988         }
 989
 990         mem->am_offset = 0;
 991         mem->am_is_bound = 0;
 992         TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
 993         sc->agp.as_allocated += size;
 994
 995         return mem;
 996 }
 997
 998 static int
 999 agp_i810_free_memory(device_t dev, struct agp_memory *mem)
1000 {
1001         struct agp_i810_softc *sc = device_get_softc(dev);
1002
1003         if (mem->am_is_bound)
1004                 return EBUSY;
1005
1006         if (mem->am_type == 2) {
1007                 if (mem->am_size == AGP_PAGE_SIZE) {
1008                         /*
1009                          * Unwire the page which we wired in alloc_memory.
1010                          */
1011                         vm_page_t m;
1012                         lwkt_gettoken(&vm_token);
1013                         m = vm_page_lookup(mem->am_obj, 0);
1014                         vm_page_unwire(m, 0);
1015                         lwkt_reltoken(&vm_token);
1016                 } else {
1017                         contigfree(sc->argb_cursor, mem->am_size, M_AGP);
1018                         sc->argb_cursor = NULL;
1019                 }
1020         }
1021
1022         sc->agp.as_allocated -= mem->am_size;
1023         TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
1024         if (mem->am_obj)
1025                 vm_object_deallocate(mem->am_obj);
1026         kfree(mem, M_AGP);
1027         return 0;
1028 }
1029
1030 static int
1031 agp_i810_bind_memory(device_t dev, struct agp_memory *mem,
1032                      vm_offset_t offset)
1033 {
1034         struct agp_i810_softc *sc = device_get_softc(dev);
1035         vm_offset_t i;
1036
1037         /* Do some sanity checks first. */
1038         if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 ||
1039             offset + mem->am_size > AGP_GET_APERTURE(dev)) {
1040                 device_printf(dev, "binding memory at bad offset %#x\n",
1041                     (int)offset);
1042                 return EINVAL;
1043         }
1044
1045         if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1046                 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1047                 if (mem->am_is_bound) {
1048                         lockmgr(&sc->agp.as_lock, LK_RELEASE);
1049                         return EINVAL;
1050                 }
1051                 /* The memory's already wired down, just stick it in the GTT. */
1052                 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1053                         agp_i810_write_gtt_entry(dev, offset + i,
1054                             mem->am_physical + i, 1);
1055                 }
1056                 agp_flush_cache();
1057                 mem->am_offset = offset;
1058                 mem->am_is_bound = 1;
1059                 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1060                 return 0;
1061         }
1062
1063         if (mem->am_type != 1)
1064                 return agp_generic_bind_memory(dev, mem, offset);
1065
1066         if ( sc->chiptype != CHIP_I810 )
1067                 return EINVAL;
1068
1069         for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1070                 bus_write_4(sc->sc_res[0],
1071                     AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
1072         }
1073
1074         return 0;
1075 }
1076
1077 static int
1078 agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
1079 {
1080         struct agp_i810_softc *sc = device_get_softc(dev);
1081         vm_offset_t i;
1082
1083         if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1084                 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1085                 if (!mem->am_is_bound) {
1086                         lockmgr(&sc->agp.as_lock, LK_RELEASE);
1087                         return EINVAL;
1088                 }
1089
1090                 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1091                         agp_i810_write_gtt_entry(dev, mem->am_offset + i,
1092                             0, 0);
1093                 }
1094                 agp_flush_cache();
1095                 mem->am_is_bound = 0;
1096                 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1097                 return 0;
1098         }
1099
1100         if (mem->am_type != 1)
1101                 return agp_generic_unbind_memory(dev, mem);
1102
1103         if ( sc->chiptype != CHIP_I810 )
1104                 return EINVAL;
1105
1106         for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1107                 bus_write_4(sc->sc_res[0],
1108                     AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0);
1109         }
1110
1111         return 0;
1112 }
1113
1114 static device_method_t agp_i810_methods[] = {
1115         /* Device interface */
1116         DEVMETHOD(device_identify,      agp_i810_identify),
1117         DEVMETHOD(device_probe,         agp_i810_probe),
1118         DEVMETHOD(device_attach,        agp_i810_attach),
1119         DEVMETHOD(device_detach,        agp_i810_detach),
1120         DEVMETHOD(device_suspend,       bus_generic_suspend),
1121         DEVMETHOD(device_resume,        agp_i810_resume),
1122
1123         /* AGP interface */
1124         DEVMETHOD(agp_get_aperture,     agp_generic_get_aperture),
1125         DEVMETHOD(agp_set_aperture,     agp_i810_set_aperture),
1126         DEVMETHOD(agp_bind_page,        agp_i810_bind_page),
1127         DEVMETHOD(agp_unbind_page,      agp_i810_unbind_page),
1128         DEVMETHOD(agp_flush_tlb,        agp_i810_flush_tlb),
1129         DEVMETHOD(agp_enable,           agp_i810_enable),
1130         DEVMETHOD(agp_alloc_memory,     agp_i810_alloc_memory),
1131         DEVMETHOD(agp_free_memory,      agp_i810_free_memory),
1132         DEVMETHOD(agp_bind_memory,      agp_i810_bind_memory),
1133         DEVMETHOD(agp_unbind_memory,    agp_i810_unbind_memory),
1134
1135         { 0, 0 }
1136 };
1137
1138 static driver_t agp_i810_driver = {
1139         "agp",
1140         agp_i810_methods,
1141         sizeof(struct agp_i810_softc),
1142 };
1143
1144 static devclass_t agp_devclass;
1145
1146 DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, 0, 0);
1147 MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
1148 MODULE_DEPEND(agp_i810, pci, 1, 1, 1);