2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $
33 * $DragonFly: src/sys/dev/netif/sf/if_sf.c,v 1.25 2005/11/28 17:13:44 dillon Exp $
37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
38 * Programming manual is available from:
39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf.
41 * Written by Bill Paul <wpaul@ctr.columbia.edu>
42 * Department of Electical Engineering
43 * Columbia University, New York City
47 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
48 * controller designed with flexibility and reducing CPU load in mind.
49 * The Starfire offers high and low priority buffer queues, a
50 * producer/consumer index mechanism and several different buffer
51 * queue and completion queue descriptor types. Any one of a number
52 * of different driver designs can be used, depending on system and
53 * OS requirements. This driver makes use of type0 transmit frame
54 * descriptors (since BSD fragments packets across an mbuf chain)
55 * and two RX buffer queues prioritized on size (one queue for small
56 * frames that will fit into a single mbuf, another with full size
57 * mbuf clusters for everything else). The producer/consumer indexes
58 * and completion queues are also used.
60 * One downside to the Starfire has to do with alignment: buffer
61 * queues must be aligned on 256-byte boundaries, and receive buffers
62 * must be aligned on longword boundaries. The receive buffer alignment
63 * causes problems on the Alpha platform, where the packet payload
64 * should be longword aligned. There is no simple way around this.
66 * For receive filtering, the Starfire offers 16 perfect filter slots
67 * and a 512-bit hash table.
69 * The Starfire has no internal transceiver, relying instead on an
70 * external MII-based transceiver. Accessing registers on external
71 * PHYs is done through a special register map rather than with the
72 * usual bitbang MDIO method.
74 * Acesssing the registers on the Starfire is a little tricky. The
75 * Starfire has a 512K internal register space. When programmed for
76 * PCI memory mapped mode, the entire register space can be accessed
77 * directly. However in I/O space mode, only 256 bytes are directly
78 * mapped into PCI I/O space. The other registers can be accessed
79 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
80 * registers inside the 256-byte I/O window.
83 #include <sys/param.h>
84 #include <sys/systm.h>
85 #include <sys/sockio.h>
87 #include <sys/malloc.h>
88 #include <sys/kernel.h>
89 #include <sys/socket.h>
90 #include <sys/serialize.h>
92 #include <sys/thread2.h>
95 #include <net/ifq_var.h>
96 #include <net/if_arp.h>
97 #include <net/ethernet.h>
98 #include <net/if_dl.h>
99 #include <net/if_media.h>
103 #include <vm/vm.h> /* for vtophys */
104 #include <vm/pmap.h> /* for vtophys */
105 #include <machine/clock.h> /* for DELAY */
106 #include <machine/bus_pio.h>
107 #include <machine/bus_memio.h>
108 #include <machine/bus.h>
109 #include <machine/resource.h>
111 #include <sys/rman.h>
113 #include "../mii_layer/mii.h"
114 #include "../mii_layer/miivar.h"
116 /* "controller miibus0" required. See GENERIC if you get errors here. */
117 #include "miibus_if.h"
119 #include <bus/pci/pcireg.h>
120 #include <bus/pci/pcivar.h>
122 #define SF_USEIOSPACE
124 #include "if_sfreg.h"
126 static struct sf_type sf_devs[] = {
127 { AD_VENDORID, AD_DEVICEID_STARFIRE,
128 "Adaptec AIC-6915 10/100BaseTX" },
132 static int sf_probe (device_t);
133 static int sf_attach (device_t);
134 static int sf_detach (device_t);
135 static void sf_intr (void *);
136 static void sf_stats_update (void *);
137 static void sf_rxeof (struct sf_softc *);
138 static void sf_txeof (struct sf_softc *);
139 static int sf_encap (struct sf_softc *,
140 struct sf_tx_bufdesc_type0 *,
142 static void sf_start (struct ifnet *);
143 static int sf_ioctl (struct ifnet *, u_long, caddr_t,
145 static void sf_init (void *);
146 static void sf_stop (struct sf_softc *);
147 static void sf_watchdog (struct ifnet *);
148 static void sf_shutdown (device_t);
149 static int sf_ifmedia_upd (struct ifnet *);
150 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *);
151 static void sf_reset (struct sf_softc *);
152 static int sf_init_rx_ring (struct sf_softc *);
153 static void sf_init_tx_ring (struct sf_softc *);
154 static int sf_newbuf (struct sf_softc *,
155 struct sf_rx_bufdesc_type0 *,
157 static void sf_setmulti (struct sf_softc *);
158 static int sf_setperf (struct sf_softc *, int, caddr_t);
159 static int sf_sethash (struct sf_softc *, caddr_t, int);
161 static int sf_setvlan (struct sf_softc *, int, u_int32_t);
164 static u_int8_t sf_read_eeprom (struct sf_softc *, int);
165 static u_int32_t sf_calchash (caddr_t);
167 static int sf_miibus_readreg (device_t, int, int);
168 static int sf_miibus_writereg (device_t, int, int, int);
169 static void sf_miibus_statchg (device_t);
171 static u_int32_t csr_read_4 (struct sf_softc *, int);
172 static void csr_write_4 (struct sf_softc *, int, u_int32_t);
173 static void sf_txthresh_adjust (struct sf_softc *);
176 #define SF_RES SYS_RES_IOPORT
177 #define SF_RID SF_PCI_LOIO
179 #define SF_RES SYS_RES_MEMORY
180 #define SF_RID SF_PCI_LOMEM
183 static device_method_t sf_methods[] = {
184 /* Device interface */
185 DEVMETHOD(device_probe, sf_probe),
186 DEVMETHOD(device_attach, sf_attach),
187 DEVMETHOD(device_detach, sf_detach),
188 DEVMETHOD(device_shutdown, sf_shutdown),
191 DEVMETHOD(bus_print_child, bus_generic_print_child),
192 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
195 DEVMETHOD(miibus_readreg, sf_miibus_readreg),
196 DEVMETHOD(miibus_writereg, sf_miibus_writereg),
197 DEVMETHOD(miibus_statchg, sf_miibus_statchg),
202 static driver_t sf_driver = {
205 sizeof(struct sf_softc),
208 static devclass_t sf_devclass;
210 DECLARE_DUMMY_MODULE(if_sf);
211 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0);
212 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
214 #define SF_SETBIT(sc, reg, x) \
215 csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
217 #define SF_CLRBIT(sc, reg, x) \
218 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
220 static u_int32_t csr_read_4(sc, reg)
227 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
228 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
230 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
236 static u_int8_t sf_read_eeprom(sc, reg)
242 val = (csr_read_4(sc, SF_EEADDR_BASE +
243 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
248 static void csr_write_4(sc, reg, val)
254 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
255 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
257 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
262 static u_int32_t sf_calchash(addr)
265 u_int32_t crc, carry;
269 /* Compute CRC for the address value. */
270 crc = 0xFFFFFFFF; /* initial value */
272 for (i = 0; i < 6; i++) {
274 for (j = 0; j < 8; j++) {
275 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
279 crc = (crc ^ 0x04c11db6) | carry;
283 /* return the filter bit position */
284 return(crc >> 23 & 0x1FF);
288 * Copy the address 'mac' into the perfect RX filter entry at
289 * offset 'idx.' The perfect filter only has 16 entries so do
292 static int sf_setperf(sc, idx, mac)
299 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
305 p = (u_int16_t *)mac;
307 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
308 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
309 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
310 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
311 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
312 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
318 * Set the bit in the 512-bit hash table that corresponds to the
319 * specified mac address 'mac.' If 'prio' is nonzero, update the
320 * priority hash table instead of the filter hash table.
322 static int sf_sethash(sc, mac, prio)
332 h = sf_calchash(mac);
335 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
336 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
338 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
339 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
347 * Set a VLAN tag in the receive filter.
349 static int sf_setvlan(sc, idx, vlan)
354 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
357 csr_write_4(sc, SF_RXFILT_HASH_BASE +
358 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
364 static int sf_miibus_readreg(dev, phy, reg)
372 sc = device_get_softc(dev);
374 for (i = 0; i < SF_TIMEOUT; i++) {
375 val = csr_read_4(sc, SF_PHY_REG(phy, reg));
376 if (val & SF_MII_DATAVALID)
383 if ((val & 0x0000FFFF) == 0xFFFF)
386 return(val & 0x0000FFFF);
389 static int sf_miibus_writereg(dev, phy, reg, val)
397 sc = device_get_softc(dev);
399 csr_write_4(sc, SF_PHY_REG(phy, reg), val);
401 for (i = 0; i < SF_TIMEOUT; i++) {
402 busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
403 if (!(busy & SF_MII_BUSY))
410 static void sf_miibus_statchg(dev)
414 struct mii_data *mii;
416 sc = device_get_softc(dev);
417 mii = device_get_softc(sc->sf_miibus);
419 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
420 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
421 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
423 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
424 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
430 static void sf_setmulti(sc)
435 struct ifmultiaddr *ifma;
436 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
438 ifp = &sc->arpcom.ac_if;
440 /* First zot all the existing filters. */
441 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
442 sf_setperf(sc, i, (char *)&dummy);
443 for (i = SF_RXFILT_HASH_BASE;
444 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
445 csr_write_4(sc, i, 0);
446 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
448 /* Now program new ones. */
449 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
450 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
453 /* First find the tail of the list. */
454 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
455 ifma = ifma->ifma_link.le_next) {
456 if (ifma->ifma_link.le_next == NULL)
459 /* Now traverse the list backwards. */
460 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
461 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
462 if (ifma->ifma_addr->sa_family != AF_LINK)
465 * Program the first 15 multicast groups
466 * into the perfect filter. For all others,
467 * use the hash table.
469 if (i < SF_RXFILT_PERFECT_CNT) {
471 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
477 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
487 static int sf_ifmedia_upd(ifp)
491 struct mii_data *mii;
494 mii = device_get_softc(sc->sf_miibus);
496 if (mii->mii_instance) {
497 struct mii_softc *miisc;
498 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
499 miisc = LIST_NEXT(miisc, mii_list))
500 mii_phy_reset(miisc);
508 * Report current media status.
510 static void sf_ifmedia_sts(ifp, ifmr)
512 struct ifmediareq *ifmr;
515 struct mii_data *mii;
518 mii = device_get_softc(sc->sf_miibus);
521 ifmr->ifm_active = mii->mii_media_active;
522 ifmr->ifm_status = mii->mii_media_status;
527 static int sf_ioctl(ifp, command, data, cr)
533 struct sf_softc *sc = ifp->if_softc;
534 struct ifreq *ifr = (struct ifreq *) data;
535 struct mii_data *mii;
540 if (ifp->if_flags & IFF_UP) {
541 if (ifp->if_flags & IFF_RUNNING &&
542 ifp->if_flags & IFF_PROMISC &&
543 !(sc->sf_if_flags & IFF_PROMISC)) {
544 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
545 } else if (ifp->if_flags & IFF_RUNNING &&
546 !(ifp->if_flags & IFF_PROMISC) &&
547 sc->sf_if_flags & IFF_PROMISC) {
548 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
549 } else if (!(ifp->if_flags & IFF_RUNNING))
552 if (ifp->if_flags & IFF_RUNNING)
555 sc->sf_if_flags = ifp->if_flags;
565 mii = device_get_softc(sc->sf_miibus);
566 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
569 error = ether_ioctl(ifp, command, data);
576 static void sf_reset(sc)
581 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
582 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
584 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
586 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
588 for (i = 0; i < SF_TIMEOUT; i++) {
590 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
595 printf("sf%d: reset never completed!\n", sc->sf_unit);
597 /* Wait a little while for the chip to get its brains in order. */
603 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
604 * IDs against our list and return a device name if we find a match.
605 * We also check the subsystem ID so that we can identify exactly which
606 * NIC has been found, if possible.
608 static int sf_probe(dev)
615 while(t->sf_name != NULL) {
616 if ((pci_get_vendor(dev) == t->sf_vid) &&
617 (pci_get_device(dev) == t->sf_did)) {
618 switch((pci_read_config(dev,
619 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) {
620 case AD_SUBSYSID_62011_REV0:
621 case AD_SUBSYSID_62011_REV1:
623 "Adaptec ANA-62011 10/100BaseTX");
626 case AD_SUBSYSID_62022:
628 "Adaptec ANA-62022 10/100BaseTX");
631 case AD_SUBSYSID_62044_REV0:
632 case AD_SUBSYSID_62044_REV1:
634 "Adaptec ANA-62044 10/100BaseTX");
637 case AD_SUBSYSID_62020:
639 "Adaptec ANA-62020 10/100BaseFX");
642 case AD_SUBSYSID_69011:
644 "Adaptec ANA-69011 10/100BaseTX");
648 device_set_desc(dev, t->sf_name);
660 * Attach the interface. Allocate softc structures, do ifmedia
661 * setup and ethernet/BPF attach.
663 static int sf_attach(dev)
670 int unit, rid, error = 0;
672 sc = device_get_softc(dev);
673 unit = device_get_unit(dev);
676 * Handle power management nonsense.
678 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF;
679 if (command == 0x01) {
681 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4);
682 if (command & SF_PSTATE_MASK) {
683 u_int32_t iobase, membase, irq;
685 /* Save important PCI config data. */
686 iobase = pci_read_config(dev, SF_PCI_LOIO, 4);
687 membase = pci_read_config(dev, SF_PCI_LOMEM, 4);
688 irq = pci_read_config(dev, SF_PCI_INTLINE, 4);
690 /* Reset the power state. */
691 printf("sf%d: chip is in D%d power mode "
692 "-- setting to D0\n", unit, command & SF_PSTATE_MASK);
693 command &= 0xFFFFFFFC;
694 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4);
696 /* Restore PCI config data. */
697 pci_write_config(dev, SF_PCI_LOIO, iobase, 4);
698 pci_write_config(dev, SF_PCI_LOMEM, membase, 4);
699 pci_write_config(dev, SF_PCI_INTLINE, irq, 4);
704 * Map control/status registers.
706 command = pci_read_config(dev, PCIR_COMMAND, 4);
707 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
708 pci_write_config(dev, PCIR_COMMAND, command, 4);
709 command = pci_read_config(dev, PCIR_COMMAND, 4);
712 if (!(command & PCIM_CMD_PORTEN)) {
713 printf("sf%d: failed to enable I/O ports!\n", unit);
718 if (!(command & PCIM_CMD_MEMEN)) {
719 printf("sf%d: failed to enable memory mapping!\n", unit);
726 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE);
728 if (sc->sf_res == NULL) {
729 printf ("sf%d: couldn't map ports\n", unit);
734 sc->sf_btag = rman_get_bustag(sc->sf_res);
735 sc->sf_bhandle = rman_get_bushandle(sc->sf_res);
737 /* Allocate interrupt */
739 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
740 RF_SHAREABLE | RF_ACTIVE);
742 if (sc->sf_irq == NULL) {
743 printf("sf%d: couldn't map interrupt\n", unit);
748 callout_init(&sc->sf_stat_timer);
750 /* Reset the adapter. */
754 * Get station address from the EEPROM.
756 for (i = 0; i < ETHER_ADDR_LEN; i++)
757 sc->arpcom.ac_enaddr[i] =
758 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
762 /* Allocate the descriptor queues. */
763 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
764 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
766 if (sc->sf_ldata == NULL) {
767 printf("sf%d: no memory for list buffers!\n", unit);
772 bzero(sc->sf_ldata, sizeof(struct sf_list_data));
775 if (mii_phy_probe(dev, &sc->sf_miibus,
776 sf_ifmedia_upd, sf_ifmedia_sts)) {
777 printf("sf%d: MII without any phy!\n", sc->sf_unit);
782 ifp = &sc->arpcom.ac_if;
784 if_initname(ifp, "sf", unit);
785 ifp->if_mtu = ETHERMTU;
786 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
787 ifp->if_ioctl = sf_ioctl;
788 ifp->if_start = sf_start;
789 ifp->if_watchdog = sf_watchdog;
790 ifp->if_init = sf_init;
791 ifp->if_baudrate = 10000000;
792 ifq_set_maxlen(&ifp->if_snd, SF_TX_DLIST_CNT - 1);
793 ifq_set_ready(&ifp->if_snd);
796 * Call MI attach routine.
798 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
800 error = bus_setup_intr(dev, sc->sf_irq, INTR_NETSAFE,
801 sf_intr, sc, &sc->sf_intrhand,
806 device_printf(dev, "couldn't set up irq\n");
817 static int sf_detach(dev)
820 struct sf_softc *sc = device_get_softc(dev);
821 struct ifnet *ifp = &sc->arpcom.ac_if;
823 lwkt_serialize_enter(ifp->if_serializer);
825 if (device_is_attached(dev)) {
831 device_delete_child(dev, sc->sf_miibus);
832 bus_generic_detach(dev);
835 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
838 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
840 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
843 contigfree(sc->sf_ldata, sizeof(struct sf_list_data),
847 lwkt_serialize_exit(ifp->if_serializer);
851 static int sf_init_rx_ring(sc)
854 struct sf_list_data *ld;
859 bzero((char *)ld->sf_rx_dlist_big,
860 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
861 bzero((char *)ld->sf_rx_clist,
862 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
864 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
865 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
872 static void sf_init_tx_ring(sc)
875 struct sf_list_data *ld;
880 bzero((char *)ld->sf_tx_dlist,
881 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
882 bzero((char *)ld->sf_tx_clist,
883 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
885 for (i = 0; i < SF_TX_DLIST_CNT; i++)
886 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
887 for (i = 0; i < SF_TX_CLIST_CNT; i++)
888 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
890 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
896 static int sf_newbuf(sc, c, m)
898 struct sf_rx_bufdesc_type0 *c;
901 struct mbuf *m_new = NULL;
904 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
908 MCLGET(m_new, MB_DONTWAIT);
909 if (!(m_new->m_flags & M_EXT)) {
913 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
916 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
917 m_new->m_data = m_new->m_ext.ext_buf;
920 m_adj(m_new, sizeof(u_int64_t));
923 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
930 * The starfire is programmed to use 'normal' mode for packet reception,
931 * which means we use the consumer/producer model for both the buffer
932 * descriptor queue and the completion descriptor queue. The only problem
933 * with this is that it involves a lot of register accesses: we have to
934 * read the RX completion consumer and producer indexes and the RX buffer
935 * producer index, plus the RX completion consumer and RX buffer producer
936 * indexes have to be updated. It would have been easier if Adaptec had
937 * put each index in a separate register, especially given that the damn
938 * NIC has a 512K register space.
940 * In spite of all the lovely features that Adaptec crammed into the 6915,
941 * it is marred by one truly stupid design flaw, which is that receive
942 * buffer addresses must be aligned on a longword boundary. This forces
943 * the packet payload to be unaligned, which is suboptimal on the x86 and
944 * completely unuseable on the Alpha. Our only recourse is to copy received
945 * packets into properly aligned buffers before handing them off.
948 static void sf_rxeof(sc)
953 struct sf_rx_bufdesc_type0 *desc;
954 struct sf_rx_cmpdesc_type3 *cur_rx;
955 u_int32_t rxcons, rxprod;
956 int cmpprodidx, cmpconsidx, bufprodidx;
958 ifp = &sc->arpcom.ac_if;
960 rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
961 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
962 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
963 cmpconsidx = SF_IDX_LO(rxcons);
964 bufprodidx = SF_IDX_LO(rxprod);
966 while (cmpconsidx != cmpprodidx) {
969 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
970 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
972 SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
973 SF_INC(bufprodidx, SF_RX_DLIST_CNT);
975 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
977 sf_newbuf(sc, desc, m);
981 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
982 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL);
983 sf_newbuf(sc, desc, m);
988 m_adj(m0, ETHER_ALIGN);
993 ifp->if_input(ifp, m);
996 csr_write_4(sc, SF_CQ_CONSIDX,
997 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
998 csr_write_4(sc, SF_RXDQ_PTR_Q1,
999 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
1005 * Read the transmit status from the completion queue and release
1006 * mbufs. Note that the buffer descriptor index in the completion
1007 * descriptor is an offset from the start of the transmit buffer
1008 * descriptor list in bytes. This is important because the manual
1009 * gives the impression that it should match the producer/consumer
1010 * index, which is the offset in 8 byte blocks.
1012 static void sf_txeof(sc)
1013 struct sf_softc *sc;
1015 int txcons, cmpprodidx, cmpconsidx;
1016 struct sf_tx_cmpdesc_type1 *cur_cmp;
1017 struct sf_tx_bufdesc_type0 *cur_tx;
1020 ifp = &sc->arpcom.ac_if;
1022 txcons = csr_read_4(sc, SF_CQ_CONSIDX);
1023 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
1024 cmpconsidx = SF_IDX_HI(txcons);
1026 while (cmpconsidx != cmpprodidx) {
1027 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
1028 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
1030 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
1033 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN)
1034 sf_txthresh_adjust(sc);
1039 if (cur_tx->sf_mbuf != NULL) {
1040 m_freem(cur_tx->sf_mbuf);
1041 cur_tx->sf_mbuf = NULL;
1044 SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
1048 ifp->if_flags &= ~IFF_OACTIVE;
1050 csr_write_4(sc, SF_CQ_CONSIDX,
1051 (txcons & ~SF_CQ_CONSIDX_TXQ) |
1052 ((cmpconsidx << 16) & 0xFFFF0000));
1057 static void sf_txthresh_adjust(sc)
1058 struct sf_softc *sc;
1063 txfctl = csr_read_4(sc, SF_TX_FRAMCTL);
1064 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH;
1065 if (txthresh < 0xFF) {
1067 txfctl &= ~SF_TXFRMCTL_TXTHRESH;
1070 printf("sf%d: tx underrun, increasing "
1071 "tx threshold to %d bytes\n",
1072 sc->sf_unit, txthresh * 4);
1074 csr_write_4(sc, SF_TX_FRAMCTL, txfctl);
1080 static void sf_intr(arg)
1083 struct sf_softc *sc;
1088 ifp = &sc->arpcom.ac_if;
1090 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED))
1093 /* Disable interrupts. */
1094 csr_write_4(sc, SF_IMR, 0x00000000);
1097 status = csr_read_4(sc, SF_ISR);
1099 csr_write_4(sc, SF_ISR, status);
1101 if (!(status & SF_INTRS))
1104 if (status & SF_ISR_RXDQ1_DMADONE)
1107 if (status & SF_ISR_TX_TXDONE ||
1108 status & SF_ISR_TX_DMADONE ||
1109 status & SF_ISR_TX_QUEUEDONE)
1112 if (status & SF_ISR_TX_LOFIFO)
1113 sf_txthresh_adjust(sc);
1115 if (status & SF_ISR_ABNORMALINTR) {
1116 if (status & SF_ISR_STATSOFLOW) {
1117 callout_stop(&sc->sf_stat_timer);
1118 sf_stats_update(sc);
1124 /* Re-enable interrupts. */
1125 csr_write_4(sc, SF_IMR, SF_INTRS);
1127 if (!ifq_is_empty(&ifp->if_snd))
1133 static void sf_init(xsc)
1136 struct sf_softc *sc = xsc;
1137 struct ifnet *ifp = &sc->arpcom.ac_if;
1143 /* Init all the receive filter registers */
1144 for (i = SF_RXFILT_PERFECT_BASE;
1145 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
1146 csr_write_4(sc, i, 0);
1148 /* Empty stats counter registers. */
1149 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
1150 csr_write_4(sc, SF_STATS_BASE +
1151 (i + sizeof(u_int32_t)), 0);
1153 /* Init our MAC address */
1154 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1155 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1156 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
1158 if (sf_init_rx_ring(sc) == ENOBUFS) {
1159 printf("sf%d: initialization failed: no "
1160 "memory for rx buffers\n", sc->sf_unit);
1164 sf_init_tx_ring(sc);
1166 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
1168 /* If we want promiscuous mode, set the allframes bit. */
1169 if (ifp->if_flags & IFF_PROMISC) {
1170 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1172 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1175 if (ifp->if_flags & IFF_BROADCAST) {
1176 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1178 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1182 * Load the multicast filter.
1186 /* Init the completion queue indexes */
1187 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1188 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1190 /* Init the RX completion queue */
1191 csr_write_4(sc, SF_RXCQ_CTL_1,
1192 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
1193 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
1195 /* Init RX DMA control. */
1196 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
1198 /* Init the RX buffer descriptor queue. */
1199 csr_write_4(sc, SF_RXDQ_ADDR_Q1,
1200 vtophys(sc->sf_ldata->sf_rx_dlist_big));
1201 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
1202 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
1204 /* Init the TX completion queue */
1205 csr_write_4(sc, SF_TXCQ_CTL,
1206 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
1208 /* Init the TX buffer descriptor queue. */
1209 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
1210 vtophys(sc->sf_ldata->sf_tx_dlist));
1211 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
1212 csr_write_4(sc, SF_TXDQ_CTL,
1213 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
1214 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
1216 /* Enable autopadding of short TX frames. */
1217 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
1219 /* Enable interrupts. */
1220 csr_write_4(sc, SF_IMR, SF_INTRS);
1221 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
1223 /* Enable the RX and TX engines. */
1224 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
1225 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
1227 /*mii_mediachg(mii);*/
1228 sf_ifmedia_upd(ifp);
1230 ifp->if_flags |= IFF_RUNNING;
1231 ifp->if_flags &= ~IFF_OACTIVE;
1233 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc);
1236 static int sf_encap(sc, c, m_head)
1237 struct sf_softc *sc;
1238 struct sf_tx_bufdesc_type0 *c;
1239 struct mbuf *m_head;
1242 struct sf_frag *f = NULL;
1247 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1248 if (m->m_len != 0) {
1249 if (frag == SF_MAXFRAGS)
1251 f = &c->sf_frags[frag];
1253 f->sf_pktlen = m_head->m_pkthdr.len;
1254 f->sf_fraglen = m->m_len;
1255 f->sf_addr = vtophys(mtod(m, vm_offset_t));
1261 struct mbuf *m_new = NULL;
1263 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1264 if (m_new == NULL) {
1265 printf("sf%d: no memory for tx list", sc->sf_unit);
1269 if (m_head->m_pkthdr.len > MHLEN) {
1270 MCLGET(m_new, MB_DONTWAIT);
1271 if (!(m_new->m_flags & M_EXT)) {
1273 printf("sf%d: no memory for tx list",
1278 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1279 mtod(m_new, caddr_t));
1280 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1283 f = &c->sf_frags[0];
1284 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len;
1285 f->sf_addr = vtophys(mtod(m_head, caddr_t));
1289 c->sf_mbuf = m_head;
1290 c->sf_id = SF_TX_BUFDESC_ID;
1291 c->sf_fragcnt = frag;
1299 static void sf_start(ifp)
1302 struct sf_softc *sc;
1303 struct sf_tx_bufdesc_type0 *cur_tx = NULL;
1304 struct mbuf *m_head = NULL;
1312 if (ifp->if_flags & IFF_OACTIVE)
1315 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1316 i = SF_IDX_HI(txprod) >> 4;
1318 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1319 printf("sf%d: TX ring full, resetting\n", sc->sf_unit);
1321 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1322 i = SF_IDX_HI(txprod) >> 4;
1325 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
1326 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) {
1327 ifp->if_flags |= IFF_OACTIVE;
1331 m_head = ifq_poll(&ifp->if_snd);
1335 cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
1336 if (sf_encap(sc, cur_tx, m_head)) {
1337 ifp->if_flags |= IFF_OACTIVE;
1341 ifq_dequeue(&ifp->if_snd, m_head);
1342 BPF_MTAP(ifp, cur_tx->sf_mbuf);
1344 SF_INC(i, SF_TX_DLIST_CNT);
1347 * Don't get the TX DMA queue get too full.
1349 if (sc->sf_tx_cnt > 64)
1357 csr_write_4(sc, SF_TXDQ_PRODIDX,
1358 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
1359 ((i << 20) & 0xFFFF0000));
1366 static void sf_stop(sc)
1367 struct sf_softc *sc;
1372 ifp = &sc->arpcom.ac_if;
1374 callout_stop(&sc->sf_stat_timer);
1376 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
1377 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1378 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1379 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
1380 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
1381 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
1382 csr_write_4(sc, SF_TXCQ_CTL, 0);
1383 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
1384 csr_write_4(sc, SF_TXDQ_CTL, 0);
1389 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1390 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
1391 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
1392 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
1396 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1397 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1398 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
1399 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
1403 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1409 * Note: it is important that this function not be interrupted. We
1410 * use a two-stage register access scheme: if we are interrupted in
1411 * between setting the indirect address register and reading from the
1412 * indirect data register, the contents of the address register could
1413 * be changed out from under us.
1415 static void sf_stats_update(xsc)
1418 struct sf_softc *sc = xsc;
1419 struct ifnet *ifp = &sc->arpcom.ac_if;
1420 struct mii_data *mii = device_get_softc(sc->sf_miibus);
1421 struct sf_stats stats;
1425 lwkt_serialize_enter(ifp->if_serializer);
1427 ptr = (u_int32_t *)&stats;
1428 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1429 ptr[i] = csr_read_4(sc, SF_STATS_BASE +
1430 (i + sizeof(u_int32_t)));
1432 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1433 csr_write_4(sc, SF_STATS_BASE +
1434 (i + sizeof(u_int32_t)), 0);
1436 ifp->if_collisions += stats.sf_tx_single_colls +
1437 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
1442 if (mii->mii_media_status & IFM_ACTIVE &&
1443 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1445 if (!ifq_is_empty(&ifp->if_snd))
1449 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc);
1451 lwkt_serialize_exit(ifp->if_serializer);
1454 static void sf_watchdog(ifp)
1457 struct sf_softc *sc;
1462 printf("sf%d: watchdog timeout\n", sc->sf_unit);
1468 if (!ifq_is_empty(&ifp->if_snd))
1474 static void sf_shutdown(dev)
1477 struct sf_softc *sc;
1480 sc = device_get_softc(dev);
1481 ifp = &sc->arpcom.ac_if;
1482 lwkt_serialize_enter(ifp->if_serializer);
1484 lwkt_serialize_exit(ifp->if_serializer);