sys/dev/drm2/i915/i915_gem.c

   1 /*-
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  * Copyright (c) 2011 The FreeBSD Foundation
  27  * All rights reserved.
  28  *
  29  * This software was developed by Konstantin Belousov under sponsorship from
  30  * the FreeBSD Foundation.
  31  *
  32  * Redistribution and use in source and binary forms, with or without
  33  * modification, are permitted provided that the following conditions
  34  * are met:
  35  * 1. Redistributions of source code must retain the above copyright
  36  *    notice, this list of conditions and the following disclaimer.
  37  * 2. Redistributions in binary form must reproduce the above copyright
  38  *    notice, this list of conditions and the following disclaimer in the
  39  *    documentation and/or other materials provided with the distribution.
  40  *
  41  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  42  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  43  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  44  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  45  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  46  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  47  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  48  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  49  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  50  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  51  * SUCH DAMAGE.
  52  *
  53  * $FreeBSD: head/sys/dev/drm2/i915/i915_gem.c 253497 2013-07-20 13:52:40Z kib $
  54  */
  55
  56 #include <sys/resourcevar.h>
  57 #include <sys/sfbuf.h>
  58
  59 #include <dev/drm2/drmP.h>
  60 #include <dev/drm2/drm.h>
  61 #include <dev/drm2/i915/i915_drm.h>
  62 #include <dev/drm2/i915/i915_drv.h>
  63 #include <dev/drm2/i915/intel_drv.h>
  64 #include <dev/drm2/i915/intel_ringbuffer.h>
  65
  66 static void i915_gem_object_flush_cpu_write_domain(
  67     struct drm_i915_gem_object *obj);
  68 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
  69     int tiling_mode);
  70 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
  71     uint32_t size, int tiling_mode);
  72 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  73     unsigned alignment, bool map_and_fenceable);
  74 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
  75     int flags);
  76 static void i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj);
  77 static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  78     bool write);
  79 static void i915_gem_object_set_to_full_cpu_read_domain(
  80     struct drm_i915_gem_object *obj);
  81 static int i915_gem_object_set_cpu_read_domain_range(
  82     struct drm_i915_gem_object *obj, uint64_t offset, uint64_t size);
  83 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
  84 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  85 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
  86 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
  87 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
  88 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex);
  89 static void i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
  90     uint32_t flush_domains);
  91 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  92     struct drm_i915_fence_reg *reg);
  93 static void i915_gem_reset_fences(struct drm_device *dev);
  94 static void i915_gem_retire_task_handler(void *arg, int pending);
  95 static int i915_gem_phys_pwrite(struct drm_device *dev,
  96     struct drm_i915_gem_object *obj, uint64_t data_ptr, uint64_t offset,
  97     uint64_t size, struct drm_file *file_priv);
  98 static void i915_gem_lowmem(void *arg);
  99
 100 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
 101 long i915_gem_wired_pages_cnt;
 102
 103 static void
 104 i915_gem_info_add_obj(struct drm_i915_private *dev_priv, size_t size)
 105 {
 106
 107         dev_priv->mm.object_count++;
 108         dev_priv->mm.object_memory += size;
 109 }
 110
 111 static void
 112 i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, size_t size)
 113 {
 114
 115         dev_priv->mm.object_count--;
 116         dev_priv->mm.object_memory -= size;
 117 }
 118
 119 static int
 120 i915_gem_wait_for_error(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv;
 123         int ret;
 124
 125         dev_priv = dev->dev_private;
 126         if (!atomic_load_acq_int(&dev_priv->mm.wedged))
 127                 return (0);
 128
 129         lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
 130         while (dev_priv->error_completion == 0) {
 131                 ret = -lksleep(&dev_priv->error_completion,
 132                     &dev_priv->error_completion_lock, PCATCH, "915wco", 0);
 133                 if (ret != 0) {
 134                         lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 135                         return (ret);
 136                 }
 137         }
 138         lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 139
 140         if (atomic_read(&dev_priv->mm.wedged)) {
 141                 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
 142                 dev_priv->error_completion++;
 143                 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 144         }
 145         return (0);
 146 }
 147
 148 int
 149 i915_mutex_lock_interruptible(struct drm_device *dev)
 150 {
 151         struct drm_i915_private *dev_priv;
 152         int ret;
 153
 154         dev_priv = dev->dev_private;
 155         ret = i915_gem_wait_for_error(dev);
 156         if (ret != 0)
 157                 return (ret);
 158
 159         /*
 160          * interruptible shall it be. might indeed be if dev_lock is
 161          * changed to sx
 162          */
 163         ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
 164         if (ret != 0)
 165                 return (-ret);
 166
 167         return (0);
 168 }
 169
 170
 171 static void
 172 i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
 173 {
 174         struct drm_device *dev;
 175         drm_i915_private_t *dev_priv;
 176         int ret;
 177
 178         dev = obj->base.dev;
 179         dev_priv = dev->dev_private;
 180
 181         ret = i915_gem_object_unbind(obj);
 182         if (ret == -ERESTART) {
 183                 list_move(&obj->mm_list, &dev_priv->mm.deferred_free_list);
 184                 return;
 185         }
 186
 187         drm_gem_free_mmap_offset(&obj->base);
 188         drm_gem_object_release(&obj->base);
 189         i915_gem_info_remove_obj(dev_priv, obj->base.size);
 190
 191         drm_free(obj->page_cpu_valid, DRM_I915_GEM);
 192         drm_free(obj->bit_17, DRM_I915_GEM);
 193         drm_free(obj, DRM_I915_GEM);
 194 }
 195
 196 void
 197 i915_gem_free_object(struct drm_gem_object *gem_obj)
 198 {
 199         struct drm_i915_gem_object *obj;
 200         struct drm_device *dev;
 201
 202         obj = to_intel_bo(gem_obj);
 203         dev = obj->base.dev;
 204
 205         while (obj->pin_count > 0)
 206                 i915_gem_object_unpin(obj);
 207
 208         if (obj->phys_obj != NULL)
 209                 i915_gem_detach_phys_object(dev, obj);
 210
 211         i915_gem_free_object_tail(obj);
 212 }
 213
 214 static void
 215 init_ring_lists(struct intel_ring_buffer *ring)
 216 {
 217
 218         INIT_LIST_HEAD(&ring->active_list);
 219         INIT_LIST_HEAD(&ring->request_list);
 220         INIT_LIST_HEAD(&ring->gpu_write_list);
 221 }
 222
 223 void
 224 i915_gem_load(struct drm_device *dev)
 225 {
 226         drm_i915_private_t *dev_priv;
 227         int i;
 228
 229         dev_priv = dev->dev_private;
 230
 231         INIT_LIST_HEAD(&dev_priv->mm.active_list);
 232         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
 233         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
 234         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
 235         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
 236         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
 237         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
 238         for (i = 0; i < I915_NUM_RINGS; i++)
 239                 init_ring_lists(&dev_priv->rings[i]);
 240         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
 241                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
 242         TIMEOUT_TASK_INIT(dev_priv->tq, &dev_priv->mm.retire_task, 0,
 243             i915_gem_retire_task_handler, dev_priv);
 244         dev_priv->error_completion = 0;
 245
 246         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
 247         if (IS_GEN3(dev)) {
 248                 u32 tmp = I915_READ(MI_ARB_STATE);
 249                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
 250                         /*
 251                          * arb state is a masked write, so set bit +
 252                          * bit in mask.
 253                          */
 254                         tmp = MI_ARB_C3_LP_WRITE_ENABLE |
 255                             (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
 256                         I915_WRITE(MI_ARB_STATE, tmp);
 257                 }
 258         }
 259
 260         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
 261
 262         /* Old X drivers will take 0-2 for front, back, depth buffers */
 263         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 264                 dev_priv->fence_reg_start = 3;
 265
 266         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) ||
 267             IS_G33(dev))
 268                 dev_priv->num_fence_regs = 16;
 269         else
 270                 dev_priv->num_fence_regs = 8;
 271
 272         /* Initialize fence registers to zero */
 273         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 274                 i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
 275         }
 276         i915_gem_detect_bit_6_swizzle(dev);
 277         dev_priv->mm.interruptible = true;
 278
 279         dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
 280             i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
 281 }
 282
 283 int
 284 i915_gem_do_init(struct drm_device *dev, unsigned long start,
 285     unsigned long mappable_end, unsigned long end)
 286 {
 287         drm_i915_private_t *dev_priv;
 288         unsigned long mappable;
 289         int error;
 290
 291         dev_priv = dev->dev_private;
 292         mappable = min(end, mappable_end) - start;
 293
 294         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 295
 296         dev_priv->mm.gtt_start = start;
 297         dev_priv->mm.gtt_mappable_end = mappable_end;
 298         dev_priv->mm.gtt_end = end;
 299         dev_priv->mm.gtt_total = end - start;
 300         dev_priv->mm.mappable_gtt_total = mappable;
 301
 302         /* Take over this portion of the GTT */
 303         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 304         device_printf(dev->device,
 305             "taking over the fictitious range 0x%lx-0x%lx\n",
 306             dev->agp->base + start, dev->agp->base + start + mappable);
 307         error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
 308             dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
 309         return (error);
 310 }
 311
 312 int
 313 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 314     struct drm_file *file)
 315 {
 316         struct drm_i915_gem_init *args;
 317         drm_i915_private_t *dev_priv;
 318
 319         dev_priv = dev->dev_private;
 320         args = data;
 321
 322         if (args->gtt_start >= args->gtt_end ||
 323             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 324                 return (-EINVAL);
 325
 326         /*
 327          * XXXKIB. The second-time initialization should be guarded
 328          * against.
 329          */
 330         lockmgr(&dev->dev_lock, LK_EXCLUSIVE|LK_RETRY|LK_CANRECURSE);
 331         i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
 332         lockmgr(&dev->dev_lock, LK_RELEASE);
 333
 334         return 0;
 335 }
 336
 337 int
 338 i915_gem_idle(struct drm_device *dev)
 339 {
 340         drm_i915_private_t *dev_priv;
 341         int ret;
 342
 343         dev_priv = dev->dev_private;
 344         if (dev_priv->mm.suspended)
 345                 return (0);
 346
 347         ret = i915_gpu_idle(dev, true);
 348         if (ret != 0)
 349                 return (ret);
 350
 351         /* Under UMS, be paranoid and evict. */
 352         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 353                 ret = i915_gem_evict_inactive(dev, false);
 354                 if (ret != 0)
 355                         return ret;
 356         }
 357
 358         i915_gem_reset_fences(dev);
 359
 360         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
 361          * We need to replace this with a semaphore, or something.
 362          * And not confound mm.suspended!
 363          */
 364         dev_priv->mm.suspended = 1;
 365         callout_stop(&dev_priv->hangcheck_timer);
 366
 367         i915_kernel_lost_context(dev);
 368         i915_gem_cleanup_ringbuffer(dev);
 369
 370         /* Cancel the retire work handler, which should be idle now. */
 371         taskqueue_cancel_timeout(dev_priv->tq, &dev_priv->mm.retire_task, NULL);
 372         return (ret);
 373 }
 374
 375 void
 376 i915_gem_init_swizzling(struct drm_device *dev)
 377 {
 378         drm_i915_private_t *dev_priv;
 379
 380         dev_priv = dev->dev_private;
 381
 382         if (INTEL_INFO(dev)->gen < 5 ||
 383             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
 384                 return;
 385
 386         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
 387                                  DISP_TILE_SURFACE_SWIZZLING);
 388
 389         if (IS_GEN5(dev))
 390                 return;
 391
 392         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
 393         if (IS_GEN6(dev))
 394                 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB));
 395         else
 396                 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB));
 397 }
 398
 399 void
 400 i915_gem_init_ppgtt(struct drm_device *dev)
 401 {
 402         drm_i915_private_t *dev_priv;
 403         struct i915_hw_ppgtt *ppgtt;
 404         uint32_t pd_offset, pd_entry;
 405         vm_paddr_t pt_addr;
 406         struct intel_ring_buffer *ring;
 407         u_int first_pd_entry_in_global_pt, i;
 408
 409         dev_priv = dev->dev_private;
 410         ppgtt = dev_priv->mm.aliasing_ppgtt;
 411         if (ppgtt == NULL)
 412                 return;
 413
 414         first_pd_entry_in_global_pt = 512 * 1024 - I915_PPGTT_PD_ENTRIES;
 415         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 416                 pt_addr = VM_PAGE_TO_PHYS(ppgtt->pt_pages[i]);
 417                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 418                 pd_entry |= GEN6_PDE_VALID;
 419                 intel_gtt_write(first_pd_entry_in_global_pt + i, pd_entry);
 420         }
 421         intel_gtt_read_pte(first_pd_entry_in_global_pt);
 422
 423         pd_offset = ppgtt->pd_offset;
 424         pd_offset /= 64; /* in cachelines, */
 425         pd_offset <<= 16;
 426
 427         if (INTEL_INFO(dev)->gen == 6) {
 428                 uint32_t ecochk = I915_READ(GAM_ECOCHK);
 429                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 430                                        ECOCHK_PPGTT_CACHE64B);
 431                 I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
 432         } else if (INTEL_INFO(dev)->gen >= 7) {
 433                 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
 434                 /* GFX_MODE is per-ring on gen7+ */
 435         }
 436
 437         for (i = 0; i < I915_NUM_RINGS; i++) {
 438                 ring = &dev_priv->rings[i];
 439
 440                 if (INTEL_INFO(dev)->gen >= 7)
 441                         I915_WRITE(RING_MODE_GEN7(ring),
 442                                    GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
 443
 444                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 445                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 446         }
 447 }
 448
 449 int
 450 i915_gem_init_hw(struct drm_device *dev)
 451 {
 452         drm_i915_private_t *dev_priv;
 453         int ret;
 454
 455         dev_priv = dev->dev_private;
 456
 457         i915_gem_init_swizzling(dev);
 458
 459         ret = intel_init_render_ring_buffer(dev);
 460         if (ret != 0)
 461                 return (ret);
 462
 463         if (HAS_BSD(dev)) {
 464                 ret = intel_init_bsd_ring_buffer(dev);
 465                 if (ret != 0)
 466                         goto cleanup_render_ring;
 467         }
 468
 469         if (HAS_BLT(dev)) {
 470                 ret = intel_init_blt_ring_buffer(dev);
 471                 if (ret != 0)
 472                         goto cleanup_bsd_ring;
 473         }
 474
 475         dev_priv->next_seqno = 1;
 476         i915_gem_init_ppgtt(dev);
 477         return (0);
 478
 479 cleanup_bsd_ring:
 480         intel_cleanup_ring_buffer(&dev_priv->rings[VCS]);
 481 cleanup_render_ring:
 482         intel_cleanup_ring_buffer(&dev_priv->rings[RCS]);
 483         return (ret);
 484 }
 485
 486 int
 487 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 488     struct drm_file *file)
 489 {
 490         struct drm_i915_private *dev_priv;
 491         struct drm_i915_gem_get_aperture *args;
 492         struct drm_i915_gem_object *obj;
 493         size_t pinned;
 494
 495         dev_priv = dev->dev_private;
 496         args = data;
 497
 498         if (!(dev->driver->driver_features & DRIVER_GEM))
 499                 return (-ENODEV);
 500
 501         pinned = 0;
 502         DRM_LOCK(dev);
 503         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 504                 pinned += obj->gtt_space->size;
 505         DRM_UNLOCK(dev);
 506
 507         args->aper_size = dev_priv->mm.gtt_total;
 508         args->aper_available_size = args->aper_size - pinned;
 509
 510         return (0);
 511 }
 512
 513 int
 514 i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment,
 515      bool map_and_fenceable)
 516 {
 517         struct drm_device *dev;
 518         struct drm_i915_private *dev_priv;
 519         int ret;
 520
 521         dev = obj->base.dev;
 522         dev_priv = dev->dev_private;
 523
 524         KASSERT(obj->pin_count != DRM_I915_GEM_OBJECT_MAX_PIN_COUNT,
 525             ("Max pin count"));
 526
 527         if (obj->gtt_space != NULL) {
 528                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
 529                     (map_and_fenceable && !obj->map_and_fenceable)) {
 530                         DRM_DEBUG("bo is already pinned with incorrect alignment:"
 531                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
 532                              " obj->map_and_fenceable=%d\n",
 533                              obj->gtt_offset, alignment,
 534                              map_and_fenceable,
 535                              obj->map_and_fenceable);
 536                         ret = i915_gem_object_unbind(obj);
 537                         if (ret != 0)
 538                                 return (ret);
 539                 }
 540         }
 541
 542         if (obj->gtt_space == NULL) {
 543                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
 544                     map_and_fenceable);
 545                 if (ret)
 546                         return (ret);
 547         }
 548
 549         if (obj->pin_count++ == 0 && !obj->active)
 550                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
 551         obj->pin_mappable |= map_and_fenceable;
 552
 553 #if 1
 554         KIB_NOTYET();
 555 #else
 556         WARN_ON(i915_verify_lists(dev));
 557 #endif
 558         return (0);
 559 }
 560
 561 void
 562 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
 563 {
 564         struct drm_device *dev;
 565         drm_i915_private_t *dev_priv;
 566
 567         dev = obj->base.dev;
 568         dev_priv = dev->dev_private;
 569
 570 #if 1
 571         KIB_NOTYET();
 572 #else
 573         WARN_ON(i915_verify_lists(dev));
 574 #endif
 575
 576         KASSERT(obj->pin_count != 0, ("zero pin count"));
 577         KASSERT(obj->gtt_space != NULL, ("No gtt mapping"));
 578
 579         if (--obj->pin_count == 0) {
 580                 if (!obj->active)
 581                         list_move_tail(&obj->mm_list,
 582                             &dev_priv->mm.inactive_list);
 583                 obj->pin_mappable = false;
 584         }
 585 #if 1
 586         KIB_NOTYET();
 587 #else
 588         WARN_ON(i915_verify_lists(dev));
 589 #endif
 590 }
 591
 592 int
 593 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
 594     struct drm_file *file)
 595 {
 596         struct drm_i915_gem_pin *args;
 597         struct drm_i915_gem_object *obj;
 598         struct drm_gem_object *gobj;
 599         int ret;
 600
 601         args = data;
 602
 603         ret = i915_mutex_lock_interruptible(dev);
 604         if (ret != 0)
 605                 return ret;
 606
 607         gobj = drm_gem_object_lookup(dev, file, args->handle);
 608         if (gobj == NULL) {
 609                 ret = -ENOENT;
 610                 goto unlock;
 611         }
 612         obj = to_intel_bo(gobj);
 613
 614         if (obj->madv != I915_MADV_WILLNEED) {
 615                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
 616                 ret = -EINVAL;
 617                 goto out;
 618         }
 619
 620         if (obj->pin_filp != NULL && obj->pin_filp != file) {
 621                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
 622                     args->handle);
 623                 ret = -EINVAL;
 624                 goto out;
 625         }
 626
 627         obj->user_pin_count++;
 628         obj->pin_filp = file;
 629         if (obj->user_pin_count == 1) {
 630                 ret = i915_gem_object_pin(obj, args->alignment, true);
 631                 if (ret != 0)
 632                         goto out;
 633         }
 634
 635         /* XXX - flush the CPU caches for pinned objects
 636          * as the X server doesn't manage domains yet
 637          */
 638         i915_gem_object_flush_cpu_write_domain(obj);
 639         args->offset = obj->gtt_offset;
 640 out:
 641         drm_gem_object_unreference(&obj->base);
 642 unlock:
 643         DRM_UNLOCK(dev);
 644         return (ret);
 645 }
 646
 647 int
 648 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
 649     struct drm_file *file)
 650 {
 651         struct drm_i915_gem_pin *args;
 652         struct drm_i915_gem_object *obj;
 653         int ret;
 654
 655         args = data;
 656         ret = i915_mutex_lock_interruptible(dev);
 657         if (ret != 0)
 658                 return (ret);
 659
 660         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 661         if (&obj->base == NULL) {
 662                 ret = -ENOENT;
 663                 goto unlock;
 664         }
 665
 666         if (obj->pin_filp != file) {
 667                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
 668                     args->handle);
 669                 ret = -EINVAL;
 670                 goto out;
 671         }
 672         obj->user_pin_count--;
 673         if (obj->user_pin_count == 0) {
 674                 obj->pin_filp = NULL;
 675                 i915_gem_object_unpin(obj);
 676         }
 677
 678 out:
 679         drm_gem_object_unreference(&obj->base);
 680 unlock:
 681         DRM_UNLOCK(dev);
 682         return (ret);
 683 }
 684
 685 int
 686 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
 687     struct drm_file *file)
 688 {
 689         struct drm_i915_gem_busy *args;
 690         struct drm_i915_gem_object *obj;
 691         struct drm_i915_gem_request *request;
 692         int ret;
 693
 694         args = data;
 695
 696         ret = i915_mutex_lock_interruptible(dev);
 697         if (ret != 0)
 698                 return ret;
 699
 700         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 701         if (&obj->base == NULL) {
 702                 ret = -ENOENT;
 703                 goto unlock;
 704         }
 705
 706         args->busy = obj->active;
 707         if (args->busy) {
 708                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
 709                         ret = i915_gem_flush_ring(obj->ring,
 710                             0, obj->base.write_domain);
 711                 } else if (obj->ring->outstanding_lazy_request ==
 712                     obj->last_rendering_seqno) {
 713                         request = kmalloc(sizeof(*request), DRM_I915_GEM,
 714                             M_WAITOK | M_ZERO);
 715                         ret = i915_add_request(obj->ring, NULL, request);
 716                         if (ret != 0)
 717                                 drm_free(request, DRM_I915_GEM);
 718                 }
 719
 720                 i915_gem_retire_requests_ring(obj->ring);
 721                 args->busy = obj->active;
 722         }
 723
 724         drm_gem_object_unreference(&obj->base);
 725 unlock:
 726         DRM_UNLOCK(dev);
 727         return (ret);
 728 }
 729
 730 /* Throttle our rendering by waiting until the ring has completed our requests
 731  * emitted over 20 msec ago.
 732  *
 733  * Note that if we were to use the current jiffies each time around the loop,
 734  * we wouldn't escape the function with any frames outstanding if the time to
 735  * render a frame was over 20ms.
 736  *
 737  * This should get us reasonable parallelism between CPU and GPU but also
 738  * relatively low latency when blocking on a particular request to finish.
 739  */
 740 static int
 741 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
 742 {
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         struct drm_i915_file_private *file_priv = file->driver_priv;
 745         unsigned long recent_enough = ticks - (20 * hz / 1000);
 746         struct drm_i915_gem_request *request;
 747         struct intel_ring_buffer *ring = NULL;
 748         u32 seqno = 0;
 749         int ret;
 750
 751         if (atomic_read(&dev_priv->mm.wedged))
 752                 return -EIO;
 753
 754         spin_lock(&file_priv->mm.lock);
 755         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
 756                 if (time_after_eq(request->emitted_jiffies, recent_enough))
 757                         break;
 758
 759                 ring = request->ring;
 760                 seqno = request->seqno;
 761         }
 762         spin_unlock(&file_priv->mm.lock);
 763
 764         if (seqno == 0)
 765                 return 0;
 766
 767         ret = 0;
 768         lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
 769         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
 770                 if (ring->irq_get(ring)) {
 771                         while (ret == 0 &&
 772                             !(i915_seqno_passed(ring->get_seqno(ring), seqno) ||
 773                             atomic_read(&dev_priv->mm.wedged)))
 774                                 ret = -lksleep(ring, &ring->irq_lock, PCATCH,
 775                                     "915thr", 0);
 776                         ring->irq_put(ring);
 777                         if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
 778                                 ret = -EIO;
 779                 } else if (_intel_wait_for(dev,
 780                     i915_seqno_passed(ring->get_seqno(ring), seqno) ||
 781                     atomic_read(&dev_priv->mm.wedged), 3000, 0, "915rtr")) {
 782                         ret = -EBUSY;
 783                 }
 784         }
 785         lockmgr(&ring->irq_lock, LK_RELEASE);
 786
 787         if (ret == 0)
 788                 taskqueue_enqueue_timeout(dev_priv->tq,
 789                     &dev_priv->mm.retire_task, 0);
 790
 791         return ret;
 792 }
 793
 794 int
 795 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
 796     struct drm_file *file_priv)
 797 {
 798
 799         return (i915_gem_ring_throttle(dev, file_priv));
 800 }
 801
 802 int
 803 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
 804     struct drm_file *file_priv)
 805 {
 806         struct drm_i915_gem_madvise *args;
 807         struct drm_i915_gem_object *obj;
 808         int ret;
 809
 810         args = data;
 811         switch (args->madv) {
 812         case I915_MADV_DONTNEED:
 813         case I915_MADV_WILLNEED:
 814                 break;
 815         default:
 816                 return (-EINVAL);
 817         }
 818
 819         ret = i915_mutex_lock_interruptible(dev);
 820         if (ret != 0)
 821                 return (ret);
 822
 823         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
 824         if (&obj->base == NULL) {
 825                 ret = -ENOENT;
 826                 goto unlock;
 827         }
 828
 829         if (obj->pin_count != 0) {
 830                 ret = -EINVAL;
 831                 goto out;
 832         }
 833
 834         if (obj->madv != I915_MADV_PURGED_INTERNAL)
 835                 obj->madv = args->madv;
 836         if (i915_gem_object_is_purgeable(obj) && obj->gtt_space == NULL)
 837                 i915_gem_object_truncate(obj);
 838         args->retained = obj->madv != I915_MADV_PURGED_INTERNAL;
 839
 840 out:
 841         drm_gem_object_unreference(&obj->base);
 842 unlock:
 843         DRM_UNLOCK(dev);
 844         return (ret);
 845 }
 846
 847 void
 848 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
 849 {
 850         drm_i915_private_t *dev_priv;
 851         int i;
 852
 853         dev_priv = dev->dev_private;
 854         for (i = 0; i < I915_NUM_RINGS; i++)
 855                 intel_cleanup_ring_buffer(&dev_priv->rings[i]);
 856 }
 857
 858 int
 859 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 860     struct drm_file *file_priv)
 861 {
 862         drm_i915_private_t *dev_priv;
 863         int ret, i;
 864
 865         if (drm_core_check_feature(dev, DRIVER_MODESET))
 866                 return (0);
 867         dev_priv = dev->dev_private;
 868         if (atomic_load_acq_int(&dev_priv->mm.wedged) != 0) {
 869                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
 870                 atomic_store_rel_int(&dev_priv->mm.wedged, 0);
 871         }
 872
 873         dev_priv->mm.suspended = 0;
 874
 875         ret = i915_gem_init_hw(dev);
 876         if (ret != 0) {
 877                 return (ret);
 878         }
 879
 880         KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
 881         KASSERT(list_empty(&dev_priv->mm.flushing_list), ("flushing list"));
 882         KASSERT(list_empty(&dev_priv->mm.inactive_list), ("inactive list"));
 883         for (i = 0; i < I915_NUM_RINGS; i++) {
 884                 KASSERT(list_empty(&dev_priv->rings[i].active_list),
 885                     ("ring %d active list", i));
 886                 KASSERT(list_empty(&dev_priv->rings[i].request_list),
 887                     ("ring %d request list", i));
 888         }
 889
 890         DRM_UNLOCK(dev);
 891         ret = drm_irq_install(dev);
 892         DRM_LOCK(dev);
 893         if (ret)
 894                 goto cleanup_ringbuffer;
 895
 896         return (0);
 897
 898 cleanup_ringbuffer:
 899         i915_gem_cleanup_ringbuffer(dev);
 900         dev_priv->mm.suspended = 1;
 901
 902         return (ret);
 903 }
 904
 905 int
 906 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
 907     struct drm_file *file_priv)
 908 {
 909
 910         if (drm_core_check_feature(dev, DRIVER_MODESET))
 911                 return 0;
 912
 913         drm_irq_uninstall(dev);
 914         return (i915_gem_idle(dev));
 915 }
 916
 917 int
 918 i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size,
 919     uint32_t *handle_p)
 920 {
 921         struct drm_i915_gem_object *obj;
 922         uint32_t handle;
 923         int ret;
 924
 925         size = roundup(size, PAGE_SIZE);
 926         if (size == 0)
 927                 return (-EINVAL);
 928
 929         obj = i915_gem_alloc_object(dev, size);
 930         if (obj == NULL)
 931                 return (-ENOMEM);
 932
 933         handle = 0;
 934         ret = drm_gem_handle_create(file, &obj->base, &handle);
 935         if (ret != 0) {
 936                 drm_gem_object_release(&obj->base);
 937                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 938                 drm_free(obj, DRM_I915_GEM);
 939                 return (-ret);
 940         }
 941
 942         /* drop reference from allocate - handle holds it now */
 943         drm_gem_object_unreference(&obj->base);
 944         *handle_p = handle;
 945         return (0);
 946 }
 947
 948 int
 949 i915_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 950     struct drm_mode_create_dumb *args)
 951 {
 952
 953         /* have to work out size/pitch and return them */
 954         args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
 955         args->size = args->pitch * args->height;
 956         return (i915_gem_create(file, dev, args->size, &args->handle));
 957 }
 958
 959 int
 960 i915_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
 961     uint32_t handle)
 962 {
 963
 964         return (drm_gem_handle_delete(file, handle));
 965 }
 966
 967 int
 968 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 969     struct drm_file *file)
 970 {
 971         struct drm_i915_gem_create *args = data;
 972
 973         return (i915_gem_create(file, dev, args->size, &args->handle));
 974 }
 975
 976 static inline void vm_page_reference(vm_page_t m)
 977 {
 978         vm_page_flag_set(m, PG_REFERENCED);
 979 }
 980
 981 static int
 982 i915_gem_swap_io(struct drm_device *dev, struct drm_i915_gem_object *obj,
 983     uint64_t data_ptr, uint64_t size, uint64_t offset, enum uio_rw rw,
 984     struct drm_file *file)
 985 {
 986         vm_object_t vm_obj;
 987         vm_page_t m;
 988         struct sf_buf *sf;
 989         vm_offset_t mkva;
 990         vm_pindex_t obj_pi;
 991         int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
 992
 993         if (obj->gtt_offset != 0 && rw == UIO_READ)
 994                 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 995         else
 996                 do_bit17_swizzling = 0;
 997
 998         obj->dirty = 1;
 999         vm_obj = obj->base.vm_obj;
1000         ret = 0;
1001
1002         VM_OBJECT_LOCK(vm_obj);
1003         vm_object_pip_add(vm_obj, 1);
1004         while (size > 0) {
1005                 obj_pi = OFF_TO_IDX(offset);
1006                 obj_po = offset & PAGE_MASK;
1007
1008                 m = i915_gem_wire_page(vm_obj, obj_pi);
1009                 VM_OBJECT_UNLOCK(vm_obj);
1010
1011                 sf = sf_buf_alloc(m);
1012                 mkva = sf_buf_kva(sf);
1013                 length = min(size, PAGE_SIZE - obj_po);
1014                 while (length > 0) {
1015                         if (do_bit17_swizzling &&
1016                             (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
1017                                 cnt = roundup2(obj_po + 1, 64);
1018                                 cnt = min(cnt - obj_po, length);
1019                                 swizzled_po = obj_po ^ 64;
1020                         } else {
1021                                 cnt = length;
1022                                 swizzled_po = obj_po;
1023                         }
1024                         if (rw == UIO_READ)
1025                                 ret = -copyout_nofault(
1026                                     (char *)mkva + swizzled_po,
1027                                     (void *)(uintptr_t)data_ptr, cnt);
1028                         else
1029                                 ret = -copyin_nofault(
1030                                     (void *)(uintptr_t)data_ptr,
1031                                     (char *)mkva + swizzled_po, cnt);
1032                         if (ret != 0)
1033                                 break;
1034                         data_ptr += cnt;
1035                         size -= cnt;
1036                         length -= cnt;
1037                         offset += cnt;
1038                         obj_po += cnt;
1039                 }
1040                 sf_buf_free(sf);
1041                 VM_OBJECT_LOCK(vm_obj);
1042                 if (rw == UIO_WRITE)
1043                         vm_page_dirty(m);
1044                 vm_page_reference(m);
1045                 vm_page_busy_wait(m, FALSE, "i915gem");
1046                 vm_page_unwire(m, 1);
1047                 vm_page_wakeup(m);
1048                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
1049
1050                 if (ret != 0)
1051                         break;
1052         }
1053         vm_object_pip_wakeup(vm_obj);
1054         VM_OBJECT_UNLOCK(vm_obj);
1055
1056         return (ret);
1057 }
1058
1059 static int
1060 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
1061     uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
1062 {
1063         vm_offset_t mkva;
1064         int ret;
1065
1066         /*
1067          * Pass the unaligned physical address and size to pmap_mapdev_attr()
1068          * so it can properly calculate whether an extra page needs to be
1069          * mapped or not to cover the requested range.  The function will
1070          * add the page offset into the returned mkva for us.
1071          */
1072         mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
1073             offset, size, PAT_WRITE_COMBINING);
1074         ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
1075         pmap_unmapdev(mkva, size);
1076         return (ret);
1077 }
1078
1079 static int
1080 i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
1081     uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file)
1082 {
1083         struct drm_i915_gem_object *obj;
1084         vm_page_t *ma;
1085         vm_offset_t start, end;
1086         int npages, ret;
1087
1088         if (size == 0)
1089                 return (0);
1090         start = trunc_page(data_ptr);
1091         end = round_page(data_ptr + size);
1092         npages = howmany(end - start, PAGE_SIZE);
1093         ma = kmalloc(npages * sizeof(vm_page_t), DRM_I915_GEM, M_WAITOK |
1094             M_ZERO);
1095         npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
1096             (vm_offset_t)data_ptr, size,
1097             (rw == UIO_READ ? VM_PROT_WRITE : 0 ) | VM_PROT_READ, ma, npages);
1098         if (npages == -1) {
1099                 ret = -EFAULT;
1100                 goto free_ma;
1101         }
1102
1103         ret = i915_mutex_lock_interruptible(dev);
1104         if (ret != 0)
1105                 goto unlocked;
1106
1107         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1108         if (&obj->base == NULL) {
1109                 ret = -ENOENT;
1110                 goto unlock;
1111         }
1112         if (offset > obj->base.size || size > obj->base.size - offset) {
1113                 ret = -EINVAL;
1114                 goto out;
1115         }
1116
1117         if (rw == UIO_READ) {
1118                 ret = i915_gem_object_set_cpu_read_domain_range(obj,
1119                     offset, size);
1120                 if (ret != 0)
1121                         goto out;
1122                 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
1123                     UIO_READ, file);
1124         } else {
1125                 if (obj->phys_obj) {
1126                         ret = i915_gem_phys_pwrite(dev, obj, data_ptr, offset,
1127                             size, file);
1128                 } else if (obj->gtt_space &&
1129                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1130                         ret = i915_gem_object_pin(obj, 0, true);
1131                         if (ret != 0)
1132                                 goto out;
1133                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1134                         if (ret != 0)
1135                                 goto out_unpin;
1136                         ret = i915_gem_object_put_fence(obj);
1137                         if (ret != 0)
1138                                 goto out_unpin;
1139                         ret = i915_gem_gtt_write(dev, obj, data_ptr, size,
1140                             offset, file);
1141 out_unpin:
1142                         i915_gem_object_unpin(obj);
1143                 } else {
1144                         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1145                         if (ret != 0)
1146                                 goto out;
1147                         ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
1148                             UIO_WRITE, file);
1149                 }
1150         }
1151 out:
1152         drm_gem_object_unreference(&obj->base);
1153 unlock:
1154         DRM_UNLOCK(dev);
1155 unlocked:
1156         vm_page_unhold_pages(ma, npages);
1157 free_ma:
1158         drm_free(ma, DRM_I915_GEM);
1159         return (ret);
1160 }
1161
1162 int
1163 i915_gem_pread_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1164 {
1165         struct drm_i915_gem_pread *args;
1166
1167         args = data;
1168         return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
1169             args->offset, UIO_READ, file));
1170 }
1171
1172 int
1173 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1174 {
1175         struct drm_i915_gem_pwrite *args;
1176
1177         args = data;
1178         return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
1179             args->offset, UIO_WRITE, file));
1180 }
1181
1182 int
1183 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1184     struct drm_file *file)
1185 {
1186         struct drm_i915_gem_set_domain *args;
1187         struct drm_i915_gem_object *obj;
1188         uint32_t read_domains;
1189         uint32_t write_domain;
1190         int ret;
1191
1192         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1193                 return (-ENODEV);
1194
1195         args = data;
1196         read_domains = args->read_domains;
1197         write_domain = args->write_domain;
1198
1199         if ((write_domain & I915_GEM_GPU_DOMAINS) != 0 ||
1200             (read_domains & I915_GEM_GPU_DOMAINS) != 0 ||
1201             (write_domain != 0 && read_domains != write_domain))
1202                 return (-EINVAL);
1203
1204         ret = i915_mutex_lock_interruptible(dev);
1205         if (ret != 0)
1206                 return (ret);
1207
1208         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1209         if (&obj->base == NULL) {
1210                 ret = -ENOENT;
1211                 goto unlock;
1212         }
1213
1214         if ((read_domains & I915_GEM_DOMAIN_GTT) != 0) {
1215                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1216                 if (ret == -EINVAL)
1217                         ret = 0;
1218         } else
1219                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1220
1221         drm_gem_object_unreference(&obj->base);
1222 unlock:
1223         DRM_UNLOCK(dev);
1224         return (ret);
1225 }
1226
1227 int
1228 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1229     struct drm_file *file)
1230 {
1231         struct drm_i915_gem_sw_finish *args;
1232         struct drm_i915_gem_object *obj;
1233         int ret;
1234
1235         args = data;
1236         ret = 0;
1237         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1238                 return (ENODEV);
1239         ret = i915_mutex_lock_interruptible(dev);
1240         if (ret != 0)
1241                 return (ret);
1242         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1243         if (&obj->base == NULL) {
1244                 ret = -ENOENT;
1245                 goto unlock;
1246         }
1247         if (obj->pin_count != 0)
1248                 i915_gem_object_flush_cpu_write_domain(obj);
1249         drm_gem_object_unreference(&obj->base);
1250 unlock:
1251         DRM_UNLOCK(dev);
1252         return (ret);
1253 }
1254
1255 int
1256 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1257     struct drm_file *file)
1258 {
1259         struct drm_i915_gem_mmap *args;
1260         struct drm_gem_object *obj;
1261         struct proc *p;
1262         vm_map_t map;
1263         vm_offset_t addr;
1264         vm_size_t size;
1265         int error, rv;
1266
1267         args = data;
1268
1269         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1270                 return (-ENODEV);
1271
1272         obj = drm_gem_object_lookup(dev, file, args->handle);
1273         if (obj == NULL)
1274                 return (-ENOENT);
1275         error = 0;
1276         if (args->size == 0)
1277                 goto out;
1278         p = curproc;
1279         map = &p->p_vmspace->vm_map;
1280         size = round_page(args->size);
1281         PROC_LOCK(p);
1282         if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
1283                 PROC_UNLOCK(p);
1284                 error = ENOMEM;
1285                 goto out;
1286         }
1287         PROC_UNLOCK(p);
1288
1289         addr = 0;
1290         vm_object_hold(obj->vm_obj);
1291         vm_object_reference_locked(obj->vm_obj);
1292         vm_object_drop(obj->vm_obj);
1293         DRM_UNLOCK(dev);
1294         rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size,
1295             PAGE_SIZE, /* align */
1296             TRUE, /* fitit */
1297             VM_MAPTYPE_NORMAL, /* maptype */
1298             VM_PROT_READ | VM_PROT_WRITE, /* prot */
1299             VM_PROT_READ | VM_PROT_WRITE, /* max */
1300             MAP_SHARED /* cow */);
1301         if (rv != KERN_SUCCESS) {
1302                 vm_object_deallocate(obj->vm_obj);
1303                 error = -vm_mmap_to_errno(rv);
1304         } else {
1305                 args->addr_ptr = (uint64_t)addr;
1306         }
1307         DRM_LOCK(dev);
1308 out:
1309         drm_gem_object_unreference(obj);
1310         return (error);
1311 }
1312
1313 static int
1314 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
1315     vm_ooffset_t foff, struct ucred *cred, u_short *color)
1316 {
1317
1318         *color = 0; /* XXXKIB */
1319         return (0);
1320 }
1321
1322 int i915_intr_pf;
1323
1324 static int
1325 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
1326     vm_page_t *mres)
1327 {
1328         struct drm_gem_object *gem_obj;
1329         struct drm_i915_gem_object *obj;
1330         struct drm_device *dev;
1331         drm_i915_private_t *dev_priv;
1332         vm_page_t m, oldm;
1333         int cause, ret;
1334         bool write;
1335
1336         gem_obj = vm_obj->handle;
1337         obj = to_intel_bo(gem_obj);
1338         dev = obj->base.dev;
1339         dev_priv = dev->dev_private;
1340 #if 0
1341         write = (prot & VM_PROT_WRITE) != 0;
1342 #else
1343         write = true;
1344 #endif
1345         vm_object_pip_add(vm_obj, 1);
1346
1347         /*
1348          * Remove the placeholder page inserted by vm_fault() from the
1349          * object before dropping the object lock. If
1350          * i915_gem_release_mmap() is active in parallel on this gem
1351          * object, then it owns the drm device sx and might find the
1352          * placeholder already. Then, since the page is busy,
1353          * i915_gem_release_mmap() sleeps waiting for the busy state
1354          * of the page cleared. We will be not able to acquire drm
1355          * device lock until i915_gem_release_mmap() is able to make a
1356          * progress.
1357          */
1358         if (*mres != NULL) {
1359                 oldm = *mres;
1360                 vm_page_remove(oldm);
1361                 *mres = NULL;
1362         } else
1363                 oldm = NULL;
1364 retry:
1365         VM_OBJECT_UNLOCK(vm_obj);
1366 unlocked_vmobj:
1367         cause = ret = 0;
1368         m = NULL;
1369
1370         if (i915_intr_pf) {
1371                 ret = i915_mutex_lock_interruptible(dev);
1372                 if (ret != 0) {
1373                         cause = 10;
1374                         goto out;
1375                 }
1376         } else
1377                 DRM_LOCK(dev);
1378
1379         /*
1380          * Since the object lock was dropped, other thread might have
1381          * faulted on the same GTT address and instantiated the
1382          * mapping for the page.  Recheck.
1383          */
1384         VM_OBJECT_LOCK(vm_obj);
1385         m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1386         if (m != NULL) {
1387                 if ((m->flags & PG_BUSY) != 0) {
1388                         DRM_UNLOCK(dev);
1389 #if 0 /* XXX */
1390                         vm_page_sleep(m, "915pee");
1391 #endif
1392                         goto retry;
1393                 }
1394                 goto have_page;
1395         } else
1396                 VM_OBJECT_UNLOCK(vm_obj);
1397
1398         /* Now bind it into the GTT if needed */
1399         if (!obj->map_and_fenceable) {
1400                 ret = i915_gem_object_unbind(obj);
1401                 if (ret != 0) {
1402                         cause = 20;
1403                         goto unlock;
1404                 }
1405         }
1406         if (!obj->gtt_space) {
1407                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1408                 if (ret != 0) {
1409                         cause = 30;
1410                         goto unlock;
1411                 }
1412
1413                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1414                 if (ret != 0) {
1415                         cause = 40;
1416                         goto unlock;
1417                 }
1418         }
1419
1420         if (obj->tiling_mode == I915_TILING_NONE)
1421                 ret = i915_gem_object_put_fence(obj);
1422         else
1423                 ret = i915_gem_object_get_fence(obj, NULL);
1424         if (ret != 0) {
1425                 cause = 50;
1426                 goto unlock;
1427         }
1428
1429         if (i915_gem_object_is_inactive(obj))
1430                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1431
1432         obj->fault_mappable = true;
1433         VM_OBJECT_LOCK(vm_obj);
1434         m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
1435             offset);
1436         if (m == NULL) {
1437                 cause = 60;
1438                 ret = -EFAULT;
1439                 goto unlock;
1440         }
1441         KASSERT((m->flags & PG_FICTITIOUS) != 0,
1442             ("not fictitious %p", m));
1443         KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1444
1445         if ((m->flags & PG_BUSY) != 0) {
1446                 DRM_UNLOCK(dev);
1447 #if 0 /* XXX */
1448                 vm_page_sleep(m, "915pbs");
1449 #endif
1450                 goto retry;
1451         }
1452         m->valid = VM_PAGE_BITS_ALL;
1453         vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
1454 have_page:
1455         *mres = m;
1456         vm_page_busy_try(m, false);
1457
1458         DRM_UNLOCK(dev);
1459         if (oldm != NULL) {
1460                 vm_page_free(oldm);
1461         }
1462         vm_object_pip_wakeup(vm_obj);
1463         return (VM_PAGER_OK);
1464
1465 unlock:
1466         DRM_UNLOCK(dev);
1467 out:
1468         KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1469         if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
1470                 goto unlocked_vmobj;
1471         }
1472         VM_OBJECT_LOCK(vm_obj);
1473         vm_object_pip_wakeup(vm_obj);
1474         return (VM_PAGER_ERROR);
1475 }
1476
1477 static void
1478 i915_gem_pager_dtor(void *handle)
1479 {
1480         struct drm_gem_object *obj;
1481         struct drm_device *dev;
1482
1483         obj = handle;
1484         dev = obj->dev;
1485
1486         DRM_LOCK(dev);
1487         drm_gem_free_mmap_offset(obj);
1488         i915_gem_release_mmap(to_intel_bo(obj));
1489         drm_gem_object_unreference(obj);
1490         DRM_UNLOCK(dev);
1491 }
1492
1493 struct cdev_pager_ops i915_gem_pager_ops = {
1494         .cdev_pg_fault  = i915_gem_pager_fault,
1495         .cdev_pg_ctor   = i915_gem_pager_ctor,
1496         .cdev_pg_dtor   = i915_gem_pager_dtor
1497 };
1498
1499 int
1500 i915_gem_mmap_gtt(struct drm_file *file, struct drm_device *dev,
1501     uint32_t handle, uint64_t *offset)
1502 {
1503         struct drm_i915_private *dev_priv;
1504         struct drm_i915_gem_object *obj;
1505         int ret;
1506
1507         if (!(dev->driver->driver_features & DRIVER_GEM))
1508                 return (-ENODEV);
1509
1510         dev_priv = dev->dev_private;
1511
1512         ret = i915_mutex_lock_interruptible(dev);
1513         if (ret != 0)
1514                 return (ret);
1515
1516         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1517         if (&obj->base == NULL) {
1518                 ret = -ENOENT;
1519                 goto unlock;
1520         }
1521
1522         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1523                 ret = -E2BIG;
1524                 goto out;
1525         }
1526
1527         if (obj->madv != I915_MADV_WILLNEED) {
1528                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1529                 ret = -EINVAL;
1530                 goto out;
1531         }
1532
1533         ret = drm_gem_create_mmap_offset(&obj->base);
1534         if (ret != 0)
1535                 goto out;
1536
1537         *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1538             DRM_GEM_MAPPING_KEY;
1539 out:
1540         drm_gem_object_unreference(&obj->base);
1541 unlock:
1542         DRM_UNLOCK(dev);
1543         return (ret);
1544 }
1545
1546 int
1547 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1548     struct drm_file *file)
1549 {
1550         struct drm_i915_private *dev_priv;
1551         struct drm_i915_gem_mmap_gtt *args;
1552
1553         dev_priv = dev->dev_private;
1554         args = data;
1555
1556         return (i915_gem_mmap_gtt(file, dev, args->handle, &args->offset));
1557 }
1558
1559 struct drm_i915_gem_object *
1560 i915_gem_alloc_object(struct drm_device *dev, size_t size)
1561 {
1562         struct drm_i915_private *dev_priv;
1563         struct drm_i915_gem_object *obj;
1564
1565         dev_priv = dev->dev_private;
1566
1567         obj = kmalloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
1568
1569         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
1570                 drm_free(obj, DRM_I915_GEM);
1571                 return (NULL);
1572         }
1573
1574         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1575         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1576
1577         if (HAS_LLC(dev))
1578                 obj->cache_level = I915_CACHE_LLC;
1579         else
1580                 obj->cache_level = I915_CACHE_NONE;
1581         obj->base.driver_private = NULL;
1582         obj->fence_reg = I915_FENCE_REG_NONE;
1583         INIT_LIST_HEAD(&obj->mm_list);
1584         INIT_LIST_HEAD(&obj->gtt_list);
1585         INIT_LIST_HEAD(&obj->ring_list);
1586         INIT_LIST_HEAD(&obj->exec_list);
1587         INIT_LIST_HEAD(&obj->gpu_write_list);
1588         obj->madv = I915_MADV_WILLNEED;
1589         /* Avoid an unnecessary call to unbind on the first bind. */
1590         obj->map_and_fenceable = true;
1591
1592         i915_gem_info_add_obj(dev_priv, size);
1593
1594         return (obj);
1595 }
1596
1597 void
1598 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
1599 {
1600
1601         /* If we don't have a page list set up, then we're not pinned
1602          * to GPU, and we can ignore the cache flush because it'll happen
1603          * again at bind time.
1604          */
1605         if (obj->pages == NULL)
1606                 return;
1607
1608         /* If the GPU is snooping the contents of the CPU cache,
1609          * we do not need to manually clear the CPU cache lines.  However,
1610          * the caches are only snooped when the render cache is
1611          * flushed/invalidated.  As we always have to emit invalidations
1612          * and flushes when moving into and out of the RENDER domain, correct
1613          * snooping behaviour occurs naturally as the result of our domain
1614          * tracking.
1615          */
1616         if (obj->cache_level != I915_CACHE_NONE)
1617                 return;
1618
1619         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
1620 }
1621
1622 static void
1623 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
1624 {
1625         uint32_t old_write_domain;
1626
1627         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
1628                 return;
1629
1630         i915_gem_clflush_object(obj);
1631         intel_gtt_chipset_flush();
1632         old_write_domain = obj->base.write_domain;
1633         obj->base.write_domain = 0;
1634 }
1635
1636 static int
1637 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
1638 {
1639
1640         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
1641                 return (0);
1642         return (i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain));
1643 }
1644
1645 static void
1646 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
1647 {
1648         uint32_t old_write_domain;
1649
1650         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
1651                 return;
1652
1653         cpu_sfence();
1654
1655         old_write_domain = obj->base.write_domain;
1656         obj->base.write_domain = 0;
1657 }
1658
1659 int
1660 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
1661 {
1662         uint32_t old_write_domain, old_read_domains;
1663         int ret;
1664
1665         if (obj->gtt_space == NULL)
1666                 return (-EINVAL);
1667
1668         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
1669                 return 0;
1670
1671         ret = i915_gem_object_flush_gpu_write_domain(obj);
1672         if (ret != 0)
1673                 return (ret);
1674
1675         if (obj->pending_gpu_write || write) {
1676                 ret = i915_gem_object_wait_rendering(obj);
1677                 if (ret != 0)
1678                         return (ret);
1679         }
1680
1681         i915_gem_object_flush_cpu_write_domain(obj);
1682
1683         old_write_domain = obj->base.write_domain;
1684         old_read_domains = obj->base.read_domains;
1685
1686         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
1687             ("In GTT write domain"));
1688         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
1689         if (write) {
1690                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
1691                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
1692                 obj->dirty = 1;
1693         }
1694
1695         return (0);
1696 }
1697
1698 int
1699 i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1700     enum i915_cache_level cache_level)
1701 {
1702         struct drm_device *dev;
1703         drm_i915_private_t *dev_priv;
1704         int ret;
1705
1706         if (obj->cache_level == cache_level)
1707                 return 0;
1708
1709         if (obj->pin_count) {
1710                 DRM_DEBUG("can not change the cache level of pinned objects\n");
1711                 return (-EBUSY);
1712         }
1713
1714         dev = obj->base.dev;
1715         dev_priv = dev->dev_private;
1716         if (obj->gtt_space) {
1717                 ret = i915_gem_object_finish_gpu(obj);
1718                 if (ret != 0)
1719                         return (ret);
1720
1721                 i915_gem_object_finish_gtt(obj);
1722
1723                 /* Before SandyBridge, you could not use tiling or fence
1724                  * registers with snooped memory, so relinquish any fences
1725                  * currently pointing to our region in the aperture.
1726                  */
1727                 if (INTEL_INFO(obj->base.dev)->gen < 6) {
1728                         ret = i915_gem_object_put_fence(obj);
1729                         if (ret != 0)
1730                                 return (ret);
1731                 }
1732
1733                 i915_gem_gtt_rebind_object(obj, cache_level);
1734                 if (obj->has_aliasing_ppgtt_mapping)
1735                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
1736                             obj, cache_level);
1737         }
1738
1739         if (cache_level == I915_CACHE_NONE) {
1740                 u32 old_read_domains, old_write_domain;
1741
1742                 /* If we're coming from LLC cached, then we haven't
1743                  * actually been tracking whether the data is in the
1744                  * CPU cache or not, since we only allow one bit set
1745                  * in obj->write_domain and have been skipping the clflushes.
1746                  * Just set it to the CPU cache for now.
1747                  */
1748                 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1749                     ("obj %p in CPU write domain", obj));
1750                 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
1751                     ("obj %p in CPU read domain", obj));
1752
1753                 old_read_domains = obj->base.read_domains;
1754                 old_write_domain = obj->base.write_domain;
1755
1756                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1757                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1758
1759         }
1760
1761         obj->cache_level = cache_level;
1762         return (0);
1763 }
1764
1765 int
1766 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1767     u32 alignment, struct intel_ring_buffer *pipelined)
1768 {
1769         u32 old_read_domains, old_write_domain;
1770         int ret;
1771
1772         ret = i915_gem_object_flush_gpu_write_domain(obj);
1773         if (ret != 0)
1774                 return (ret);
1775
1776         if (pipelined != obj->ring) {
1777                 ret = i915_gem_object_wait_rendering(obj);
1778                 if (ret == -ERESTART || ret == -EINTR)
1779                         return (ret);
1780         }
1781
1782         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
1783         if (ret != 0)
1784                 return (ret);
1785
1786         ret = i915_gem_object_pin(obj, alignment, true);
1787         if (ret != 0)
1788                 return (ret);
1789
1790         i915_gem_object_flush_cpu_write_domain(obj);
1791
1792         old_write_domain = obj->base.write_domain;
1793         old_read_domains = obj->base.read_domains;
1794
1795         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
1796             ("obj %p in GTT write domain", obj));
1797         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
1798
1799         return (0);
1800 }
1801
1802 int
1803 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
1804 {
1805         int ret;
1806
1807         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
1808                 return (0);
1809
1810         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
1811                 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
1812                 if (ret != 0)
1813                         return (ret);
1814         }
1815
1816         ret = i915_gem_object_wait_rendering(obj);
1817         if (ret != 0)
1818                 return (ret);
1819
1820         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1821
1822         return (0);
1823 }
1824
1825 static int
1826 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
1827 {
1828         uint32_t old_write_domain, old_read_domains;
1829         int ret;
1830
1831         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
1832                 return 0;
1833
1834         ret = i915_gem_object_flush_gpu_write_domain(obj);
1835         if (ret != 0)
1836                 return (ret);
1837
1838         ret = i915_gem_object_wait_rendering(obj);
1839         if (ret != 0)
1840                 return (ret);
1841
1842         i915_gem_object_flush_gtt_write_domain(obj);
1843         i915_gem_object_set_to_full_cpu_read_domain(obj);
1844
1845         old_write_domain = obj->base.write_domain;
1846         old_read_domains = obj->base.read_domains;
1847
1848         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
1849                 i915_gem_clflush_object(obj);
1850                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
1851         }
1852
1853         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1854             ("In cpu write domain"));
1855
1856         if (write) {
1857                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1858                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1859         }
1860
1861         return (0);
1862 }
1863
1864 static void
1865 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
1866 {
1867         int i;
1868
1869         if (obj->page_cpu_valid == NULL)
1870                 return;
1871
1872         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) {
1873                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
1874                         if (obj->page_cpu_valid[i] != 0)
1875                                 continue;
1876                         drm_clflush_pages(obj->pages + i, 1);
1877                 }
1878         }
1879
1880         drm_free(obj->page_cpu_valid, DRM_I915_GEM);
1881         obj->page_cpu_valid = NULL;
1882 }
1883
1884 static int
1885 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
1886     uint64_t offset, uint64_t size)
1887 {
1888         uint32_t old_read_domains;
1889         int i, ret;
1890
1891         if (offset == 0 && size == obj->base.size)
1892                 return (i915_gem_object_set_to_cpu_domain(obj, 0));
1893
1894         ret = i915_gem_object_flush_gpu_write_domain(obj);
1895         if (ret != 0)
1896                 return (ret);
1897         ret = i915_gem_object_wait_rendering(obj);
1898         if (ret != 0)
1899                 return (ret);
1900
1901         i915_gem_object_flush_gtt_write_domain(obj);
1902
1903         if (obj->page_cpu_valid == NULL &&
1904             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
1905                 return (0);
1906
1907         if (obj->page_cpu_valid == NULL) {
1908                 obj->page_cpu_valid = kmalloc(obj->base.size / PAGE_SIZE,
1909                     DRM_I915_GEM, M_WAITOK | M_ZERO);
1910         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
1911                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
1912
1913         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
1914              i++) {
1915                 if (obj->page_cpu_valid[i])
1916                         continue;
1917                 drm_clflush_pages(obj->pages + i, 1);
1918                 obj->page_cpu_valid[i] = 1;
1919         }
1920
1921         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1922             ("In gpu write domain"));
1923
1924         old_read_domains = obj->base.read_domains;
1925         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
1926
1927         return (0);
1928 }
1929
1930 static uint32_t
1931 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1932 {
1933         uint32_t gtt_size;
1934
1935         if (INTEL_INFO(dev)->gen >= 4 ||
1936             tiling_mode == I915_TILING_NONE)
1937                 return (size);
1938
1939         /* Previous chips need a power-of-two fence region when tiling */
1940         if (INTEL_INFO(dev)->gen == 3)
1941                 gtt_size = 1024*1024;
1942         else
1943                 gtt_size = 512*1024;
1944
1945         while (gtt_size < size)
1946                 gtt_size <<= 1;
1947
1948         return (gtt_size);
1949 }
1950
1951 /**
1952  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1953  * @obj: object to check
1954  *
1955  * Return the required GTT alignment for an object, taking into account
1956  * potential fence register mapping.
1957  */
1958 static uint32_t
1959 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1960      int tiling_mode)
1961 {
1962
1963         /*
1964          * Minimum alignment is 4k (GTT page size), but might be greater
1965          * if a fence register is needed for the object.
1966          */
1967         if (INTEL_INFO(dev)->gen >= 4 ||
1968             tiling_mode == I915_TILING_NONE)
1969                 return (4096);
1970
1971         /*
1972          * Previous chips need to be aligned to the size of the smallest
1973          * fence register that can contain the object.
1974          */
1975         return (i915_gem_get_gtt_size(dev, size, tiling_mode));
1976 }
1977
1978 uint32_t
1979 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, uint32_t size,
1980     int tiling_mode)
1981 {
1982
1983         if (tiling_mode == I915_TILING_NONE)
1984                 return (4096);
1985
1986         /*
1987          * Minimum alignment is 4k (GTT page size) for sane hw.
1988          */
1989         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev))
1990                 return (4096);
1991
1992         /*
1993          * Previous hardware however needs to be aligned to a power-of-two
1994          * tile height. The simplest method for determining this is to reuse
1995          * the power-of-tile object size.
1996          */
1997         return (i915_gem_get_gtt_size(dev, size, tiling_mode));
1998 }
1999
2000 static int
2001 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2002     unsigned alignment, bool map_and_fenceable)
2003 {
2004         struct drm_device *dev;
2005         struct drm_i915_private *dev_priv;
2006         struct drm_mm_node *free_space;
2007         uint32_t size, fence_size, fence_alignment, unfenced_alignment;
2008         bool mappable, fenceable;
2009         int ret;
2010
2011         dev = obj->base.dev;
2012         dev_priv = dev->dev_private;
2013
2014         if (obj->madv != I915_MADV_WILLNEED) {
2015                 DRM_ERROR("Attempting to bind a purgeable object\n");
2016                 return (-EINVAL);
2017         }
2018
2019         fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
2020             obj->tiling_mode);
2021         fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
2022             obj->tiling_mode);
2023         unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
2024             obj->base.size, obj->tiling_mode);
2025         if (alignment == 0)
2026                 alignment = map_and_fenceable ? fence_alignment :
2027                     unfenced_alignment;
2028         if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
2029                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2030                 return (-EINVAL);
2031         }
2032
2033         size = map_and_fenceable ? fence_size : obj->base.size;
2034
2035         /* If the object is bigger than the entire aperture, reject it early
2036          * before evicting everything in a vain attempt to find space.
2037          */
2038         if (obj->base.size > (map_and_fenceable ?
2039             dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2040                 DRM_ERROR(
2041 "Attempting to bind an object larger than the aperture\n");
2042                 return (-E2BIG);
2043         }
2044
2045  search_free:
2046         if (map_and_fenceable)
2047                 free_space = drm_mm_search_free_in_range(
2048                     &dev_priv->mm.gtt_space, size, alignment, 0,
2049                     dev_priv->mm.gtt_mappable_end, 0);
2050         else
2051                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2052                     size, alignment, 0);
2053         if (free_space != NULL) {
2054                 if (map_and_fenceable)
2055                         obj->gtt_space = drm_mm_get_block_range_generic(
2056                             free_space, size, alignment, 0,
2057                             dev_priv->mm.gtt_mappable_end, 1);
2058                 else
2059                         obj->gtt_space = drm_mm_get_block_generic(free_space,
2060                             size, alignment, 1);
2061         }
2062         if (obj->gtt_space == NULL) {
2063                 ret = i915_gem_evict_something(dev, size, alignment,
2064                     map_and_fenceable);
2065                 if (ret != 0)
2066                         return (ret);
2067                 goto search_free;
2068         }
2069         ret = i915_gem_object_get_pages_gtt(obj, 0);
2070         if (ret != 0) {
2071                 drm_mm_put_block(obj->gtt_space);
2072                 obj->gtt_space = NULL;
2073                 /*
2074                  * i915_gem_object_get_pages_gtt() cannot return
2075                  * ENOMEM, since we use vm_page_grab(VM_ALLOC_RETRY)
2076                  * (which does not support operation without a flag
2077                  * anyway).
2078                  */
2079                 return (ret);
2080         }
2081
2082         ret = i915_gem_gtt_bind_object(obj);
2083         if (ret != 0) {
2084                 i915_gem_object_put_pages_gtt(obj);
2085                 drm_mm_put_block(obj->gtt_space);
2086                 obj->gtt_space = NULL;
2087                 if (i915_gem_evict_everything(dev, false))
2088                         return (ret);
2089                 goto search_free;
2090         }
2091
2092         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2093         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2094
2095         KASSERT((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0,
2096             ("Object in gpu read domain"));
2097         KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
2098             ("Object in gpu write domain"));
2099
2100         obj->gtt_offset = obj->gtt_space->start;
2101
2102         fenceable =
2103                 obj->gtt_space->size == fence_size &&
2104                 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2105
2106         mappable =
2107                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2108         obj->map_and_fenceable = mappable && fenceable;
2109
2110         return (0);
2111 }
2112
2113 static void
2114 i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2115 {
2116         u32 old_write_domain, old_read_domains;
2117
2118         /* Act a barrier for all accesses through the GTT */
2119         cpu_mfence();
2120
2121         /* Force a pagefault for domain tracking on next user access */
2122         i915_gem_release_mmap(obj);
2123
2124         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2125                 return;
2126
2127         old_read_domains = obj->base.read_domains;
2128         old_write_domain = obj->base.write_domain;
2129
2130         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2131         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2132
2133 }
2134
2135 int
2136 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2137 {
2138         drm_i915_private_t *dev_priv;
2139         int ret;
2140
2141         dev_priv = obj->base.dev->dev_private;
2142         ret = 0;
2143         if (obj->gtt_space == NULL)
2144                 return (0);
2145         if (obj->pin_count != 0) {
2146                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2147                 return (-EINVAL);
2148         }
2149
2150         ret = i915_gem_object_finish_gpu(obj);
2151         if (ret == -ERESTART || ret == -EINTR)
2152                 return (ret);
2153
2154         i915_gem_object_finish_gtt(obj);
2155
2156         if (ret == 0)
2157                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2158         if (ret == -ERESTART || ret == -EINTR)
2159                 return (ret);
2160         if (ret != 0) {
2161                 i915_gem_clflush_object(obj);
2162                 obj->base.read_domains = obj->base.write_domain =
2163                     I915_GEM_DOMAIN_CPU;
2164         }
2165
2166         ret = i915_gem_object_put_fence(obj);
2167         if (ret == -ERESTART)
2168                 return (ret);
2169
2170         i915_gem_gtt_unbind_object(obj);
2171         if (obj->has_aliasing_ppgtt_mapping) {
2172                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2173                 obj->has_aliasing_ppgtt_mapping = 0;
2174         }
2175         i915_gem_object_put_pages_gtt(obj);
2176
2177         list_del_init(&obj->gtt_list);
2178         list_del_init(&obj->mm_list);
2179         obj->map_and_fenceable = true;
2180
2181         drm_mm_put_block(obj->gtt_space);
2182         obj->gtt_space = NULL;
2183         obj->gtt_offset = 0;
2184
2185         if (i915_gem_object_is_purgeable(obj))
2186                 i915_gem_object_truncate(obj);
2187
2188         return (ret);
2189 }
2190
2191 static int
2192 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
2193     int flags)
2194 {
2195         struct drm_device *dev;
2196         vm_object_t vm_obj;
2197         vm_page_t m;
2198         int page_count, i, j;
2199
2200         dev = obj->base.dev;
2201         KASSERT(obj->pages == NULL, ("Obj already has pages"));
2202         page_count = obj->base.size / PAGE_SIZE;
2203         obj->pages = kmalloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
2204             M_WAITOK);
2205         vm_obj = obj->base.vm_obj;
2206         VM_OBJECT_LOCK(vm_obj);
2207         for (i = 0; i < page_count; i++) {
2208                 if ((obj->pages[i] = i915_gem_wire_page(vm_obj, i)) == NULL)
2209                         goto failed;
2210         }
2211         VM_OBJECT_UNLOCK(vm_obj);
2212         if (i915_gem_object_needs_bit17_swizzle(obj))
2213                 i915_gem_object_do_bit_17_swizzle(obj);
2214         return (0);
2215
2216 failed:
2217         for (j = 0; j < i; j++) {
2218                 m = obj->pages[j];
2219                 vm_page_busy_wait(m, FALSE, "i915gem");
2220                 vm_page_unwire(m, 0);
2221                 vm_page_wakeup(m);
2222                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2223         }
2224         VM_OBJECT_UNLOCK(vm_obj);
2225         drm_free(obj->pages, DRM_I915_GEM);
2226         obj->pages = NULL;
2227         return (-EIO);
2228 }
2229
2230 #define GEM_PARANOID_CHECK_GTT 0
2231 #if GEM_PARANOID_CHECK_GTT
2232 static void
2233 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
2234     int page_count)
2235 {
2236         struct drm_i915_private *dev_priv;
2237         vm_paddr_t pa;
2238         unsigned long start, end;
2239         u_int i;
2240         int j;
2241
2242         dev_priv = dev->dev_private;
2243         start = OFF_TO_IDX(dev_priv->mm.gtt_start);
2244         end = OFF_TO_IDX(dev_priv->mm.gtt_end);
2245         for (i = start; i < end; i++) {
2246                 pa = intel_gtt_read_pte_paddr(i);
2247                 for (j = 0; j < page_count; j++) {
2248                         if (pa == VM_PAGE_TO_PHYS(ma[j])) {
2249                                 panic("Page %p in GTT pte index %d pte %x",
2250                                     ma[i], i, intel_gtt_read_pte(i));
2251                         }
2252                 }
2253         }
2254 }
2255 #endif
2256
2257 static void
2258 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2259 {
2260         vm_page_t m;
2261         int page_count, i;
2262
2263         KASSERT(obj->madv != I915_MADV_PURGED_INTERNAL, ("Purged object"));
2264
2265         if (obj->tiling_mode != I915_TILING_NONE)
2266                 i915_gem_object_save_bit_17_swizzle(obj);
2267         if (obj->madv == I915_MADV_DONTNEED)
2268                 obj->dirty = 0;
2269         page_count = obj->base.size / PAGE_SIZE;
2270         VM_OBJECT_LOCK(obj->base.vm_obj);
2271 #if GEM_PARANOID_CHECK_GTT
2272         i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
2273 #endif
2274         for (i = 0; i < page_count; i++) {
2275                 m = obj->pages[i];
2276                 if (obj->dirty)
2277                         vm_page_dirty(m);
2278                 if (obj->madv == I915_MADV_WILLNEED)
2279                         vm_page_reference(m);
2280                 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
2281                 vm_page_unwire(obj->pages[i], 1);
2282                 vm_page_wakeup(obj->pages[i]);
2283                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2284         }
2285         VM_OBJECT_UNLOCK(obj->base.vm_obj);
2286         obj->dirty = 0;
2287         drm_free(obj->pages, DRM_I915_GEM);
2288         obj->pages = NULL;
2289 }
2290
2291 void
2292 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2293 {
2294         vm_object_t devobj;
2295         vm_page_t m;
2296         int i, page_count;
2297
2298         if (!obj->fault_mappable)
2299                 return;
2300
2301         devobj = cdev_pager_lookup(obj);
2302         if (devobj != NULL) {
2303                 page_count = OFF_TO_IDX(obj->base.size);
2304
2305                 VM_OBJECT_LOCK(devobj);
2306                 for (i = 0; i < page_count; i++) {
2307                         m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
2308                         if (m == NULL)
2309                                 continue;
2310                         cdev_pager_free_page(devobj, m);
2311                 }
2312                 VM_OBJECT_UNLOCK(devobj);
2313                 vm_object_deallocate(devobj);
2314         }
2315
2316         obj->fault_mappable = false;
2317 }
2318
2319 int
2320 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2321 {
2322         int ret;
2323
2324         KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
2325             ("In GPU write domain"));
2326
2327         if (obj->active) {
2328                 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno,
2329                     true);
2330                 if (ret != 0)
2331                         return (ret);
2332         }
2333         return (0);
2334 }
2335
2336 void
2337 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2338     struct intel_ring_buffer *ring, uint32_t seqno)
2339 {
2340         struct drm_device *dev = obj->base.dev;
2341         struct drm_i915_private *dev_priv = dev->dev_private;
2342         struct drm_i915_fence_reg *reg;
2343
2344         obj->ring = ring;
2345         KASSERT(ring != NULL, ("NULL ring"));
2346
2347         /* Add a reference if we're newly entering the active list. */
2348         if (!obj->active) {
2349                 drm_gem_object_reference(&obj->base);
2350                 obj->active = 1;
2351         }
2352
2353         /* Move from whatever list we were on to the tail of execution. */
2354         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
2355         list_move_tail(&obj->ring_list, &ring->active_list);
2356
2357         obj->last_rendering_seqno = seqno;
2358         if (obj->fenced_gpu_access) {
2359                 obj->last_fenced_seqno = seqno;
2360                 obj->last_fenced_ring = ring;
2361
2362                 /* Bump MRU to take account of the delayed flush */
2363                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2364                         reg = &dev_priv->fence_regs[obj->fence_reg];
2365                         list_move_tail(&reg->lru_list,
2366                                        &dev_priv->mm.fence_list);
2367                 }
2368         }
2369 }
2370
2371 static void
2372 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
2373 {
2374         list_del_init(&obj->ring_list);
2375         obj->last_rendering_seqno = 0;
2376         obj->last_fenced_seqno = 0;
2377 }
2378
2379 static void
2380 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
2381 {
2382         struct drm_device *dev = obj->base.dev;
2383         drm_i915_private_t *dev_priv = dev->dev_private;
2384
2385         KASSERT(obj->active, ("Object not active"));
2386         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
2387
2388         i915_gem_object_move_off_active(obj);
2389 }
2390
2391 static void
2392 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2393 {
2394         struct drm_device *dev = obj->base.dev;
2395         struct drm_i915_private *dev_priv = dev->dev_private;
2396
2397         if (obj->pin_count != 0)
2398                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
2399         else
2400                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2401
2402         KASSERT(list_empty(&obj->gpu_write_list), ("On gpu_write_list"));
2403         KASSERT(obj->active, ("Object not active"));
2404         obj->ring = NULL;
2405         obj->last_fenced_ring = NULL;
2406
2407         i915_gem_object_move_off_active(obj);
2408         obj->fenced_gpu_access = false;
2409
2410         obj->active = 0;
2411         obj->pending_gpu_write = false;
2412         drm_gem_object_unreference(&obj->base);
2413
2414 #if 1
2415         KIB_NOTYET();
2416 #else
2417         WARN_ON(i915_verify_lists(dev));
2418 #endif
2419 }
2420
2421 static void
2422 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2423 {
2424         vm_object_t vm_obj;
2425
2426         vm_obj = obj->base.vm_obj;
2427         VM_OBJECT_LOCK(vm_obj);
2428         vm_object_page_remove(vm_obj, 0, 0, false);
2429         VM_OBJECT_UNLOCK(vm_obj);
2430         obj->madv = I915_MADV_PURGED_INTERNAL;
2431 }
2432
2433 static inline int
2434 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
2435 {
2436
2437         return (obj->madv == I915_MADV_DONTNEED);
2438 }
2439
2440 static void
2441 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
2442     uint32_t flush_domains)
2443 {
2444         struct drm_i915_gem_object *obj, *next;
2445         uint32_t old_write_domain;
2446
2447         list_for_each_entry_safe(obj, next, &ring->gpu_write_list,
2448             gpu_write_list) {
2449                 if (obj->base.write_domain & flush_domains) {
2450                         old_write_domain = obj->base.write_domain;
2451                         obj->base.write_domain = 0;
2452                         list_del_init(&obj->gpu_write_list);
2453                         i915_gem_object_move_to_active(obj, ring,
2454                             i915_gem_next_request_seqno(ring));
2455                 }
2456         }
2457 }
2458
2459 static int
2460 i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2461 {
2462         drm_i915_private_t *dev_priv;
2463
2464         dev_priv = obj->base.dev->dev_private;
2465         return (dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2466             obj->tiling_mode != I915_TILING_NONE);
2467 }
2468
2469 #define VM_OBJECT_LOCK_ASSERT_OWNED(object)
2470
2471 static vm_page_t
2472 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex)
2473 {
2474         vm_page_t m;
2475         int rv;
2476
2477         VM_OBJECT_LOCK_ASSERT_OWNED(object);
2478         m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL | VM_ALLOC_RETRY);
2479         if (m->valid != VM_PAGE_BITS_ALL) {
2480                 if (vm_pager_has_page(object, pindex)) {
2481                         rv = vm_pager_get_page(object, &m, 1);
2482                         m = vm_page_lookup(object, pindex);
2483                         if (m == NULL)
2484                                 return (NULL);
2485                         if (rv != VM_PAGER_OK) {
2486                                 vm_page_free(m);
2487                                 return (NULL);
2488                         }
2489                 } else {
2490                         pmap_zero_page(VM_PAGE_TO_PHYS(m));
2491                         m->valid = VM_PAGE_BITS_ALL;
2492                         m->dirty = 0;
2493                 }
2494         }
2495         vm_page_wire(m);
2496         vm_page_wakeup(m);
2497         atomic_add_long(&i915_gem_wired_pages_cnt, 1);
2498         return (m);
2499 }
2500
2501 int
2502 i915_gem_flush_ring(struct intel_ring_buffer *ring, uint32_t invalidate_domains,
2503     uint32_t flush_domains)
2504 {
2505         int ret;
2506
2507         if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2508                 return 0;
2509
2510         ret = ring->flush(ring, invalidate_domains, flush_domains);
2511         if (ret)
2512                 return ret;
2513
2514         if (flush_domains & I915_GEM_GPU_DOMAINS)
2515                 i915_gem_process_flushing_list(ring, flush_domains);
2516         return 0;
2517 }
2518
2519 static int
2520 i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire)
2521 {
2522         int ret;
2523
2524         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2525                 return 0;
2526
2527         if (!list_empty(&ring->gpu_write_list)) {
2528                 ret = i915_gem_flush_ring(ring, I915_GEM_GPU_DOMAINS,
2529                     I915_GEM_GPU_DOMAINS);
2530                 if (ret != 0)
2531                         return ret;
2532         }
2533
2534         return (i915_wait_request(ring, i915_gem_next_request_seqno(ring),
2535             do_retire));
2536 }
2537
2538 int
2539 i915_gpu_idle(struct drm_device *dev, bool do_retire)
2540 {
2541         drm_i915_private_t *dev_priv = dev->dev_private;
2542         int ret, i;
2543
2544         /* Flush everything onto the inactive list. */
2545         for (i = 0; i < I915_NUM_RINGS; i++) {
2546                 ret = i915_ring_idle(&dev_priv->rings[i], do_retire);
2547                 if (ret)
2548                         return ret;
2549         }
2550
2551         return 0;
2552 }
2553
2554 int
2555 i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno, bool do_retire)
2556 {
2557         drm_i915_private_t *dev_priv;
2558         struct drm_i915_gem_request *request;
2559         uint32_t ier;
2560         int flags, ret;
2561         bool recovery_complete;
2562
2563         KASSERT(seqno != 0, ("Zero seqno"));
2564
2565         dev_priv = ring->dev->dev_private;
2566         ret = 0;
2567
2568         if (atomic_load_acq_int(&dev_priv->mm.wedged) != 0) {
2569                 /* Give the error handler a chance to run. */
2570                 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
2571                 recovery_complete = (&dev_priv->error_completion) > 0;
2572                 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
2573                 return (recovery_complete ? -EIO : -EAGAIN);
2574         }
2575
2576         if (seqno == ring->outstanding_lazy_request) {
2577                 request = kmalloc(sizeof(*request), DRM_I915_GEM,
2578                     M_WAITOK | M_ZERO);
2579                 if (request == NULL)
2580                         return (-ENOMEM);
2581
2582                 ret = i915_add_request(ring, NULL, request);
2583                 if (ret != 0) {
2584                         drm_free(request, DRM_I915_GEM);
2585                         return (ret);
2586                 }
2587
2588                 seqno = request->seqno;
2589         }
2590
2591         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2592                 if (HAS_PCH_SPLIT(ring->dev))
2593                         ier = I915_READ(DEIER) | I915_READ(GTIER);
2594                 else
2595                         ier = I915_READ(IER);
2596                 if (!ier) {
2597                         DRM_ERROR("something (likely vbetool) disabled "
2598                                   "interrupts, re-enabling\n");
2599                         ring->dev->driver->irq_preinstall(ring->dev);
2600                         ring->dev->driver->irq_postinstall(ring->dev);
2601                 }
2602
2603                 ring->waiting_seqno = seqno;
2604                 lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
2605                 if (ring->irq_get(ring)) {
2606                         flags = dev_priv->mm.interruptible ? PCATCH : 0;
2607                         while (!i915_seqno_passed(ring->get_seqno(ring), seqno)
2608                             && !atomic_load_acq_int(&dev_priv->mm.wedged) &&
2609                             ret == 0) {
2610                                 ret = -lksleep(ring, &ring->irq_lock, flags,
2611                                     "915gwr", 0);
2612                         }
2613                         ring->irq_put(ring);
2614                         lockmgr(&ring->irq_lock, LK_RELEASE);
2615                 } else {
2616                         lockmgr(&ring->irq_lock, LK_RELEASE);
2617                         if (_intel_wait_for(ring->dev,
2618                             i915_seqno_passed(ring->get_seqno(ring), seqno) ||
2619                             atomic_load_acq_int(&dev_priv->mm.wedged), 3000,
2620                             0, "i915wrq") != 0)
2621                                 ret = -EBUSY;
2622                 }
2623                 ring->waiting_seqno = 0;
2624
2625         }
2626         if (atomic_load_acq_int(&dev_priv->mm.wedged))
2627                 ret = -EAGAIN;
2628
2629         /* Directly dispatch request retiring.  While we have the work queue
2630          * to handle this, the waiter on a request often wants an associated
2631          * buffer to have made it to the inactive list, and we would need
2632          * a separate wait queue to handle that.
2633          */
2634         if (ret == 0 && do_retire)
2635                 i915_gem_retire_requests_ring(ring);
2636
2637         return (ret);
2638 }
2639
2640 static u32
2641 i915_gem_get_seqno(struct drm_device *dev)
2642 {
2643         drm_i915_private_t *dev_priv = dev->dev_private;
2644         u32 seqno = dev_priv->next_seqno;
2645
2646         /* reserve 0 for non-seqno */
2647         if (++dev_priv->next_seqno == 0)
2648                 dev_priv->next_seqno = 1;
2649
2650         return seqno;
2651 }
2652
2653 u32
2654 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
2655 {
2656         if (ring->outstanding_lazy_request == 0)
2657                 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
2658
2659         return ring->outstanding_lazy_request;
2660 }
2661
2662 int
2663 i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file,
2664      struct drm_i915_gem_request *request)
2665 {
2666         drm_i915_private_t *dev_priv;
2667         struct drm_i915_file_private *file_priv;
2668         uint32_t seqno;
2669         u32 request_ring_position;
2670         int was_empty;
2671         int ret;
2672
2673         KASSERT(request != NULL, ("NULL request in add"));
2674         DRM_LOCK_ASSERT(ring->dev);
2675         dev_priv = ring->dev->dev_private;
2676
2677         seqno = i915_gem_next_request_seqno(ring);
2678         request_ring_position = intel_ring_get_tail(ring);
2679
2680         ret = ring->add_request(ring, &seqno);
2681         if (ret != 0)
2682             return ret;
2683
2684         request->seqno = seqno;
2685         request->ring = ring;
2686         request->tail = request_ring_position;
2687         request->emitted_jiffies = ticks;
2688         was_empty = list_empty(&ring->request_list);
2689         list_add_tail(&request->list, &ring->request_list);
2690
2691         if (file != NULL) {
2692                 file_priv = file->driver_priv;
2693
2694                 spin_lock(&file_priv->mm.lock);
2695                 request->file_priv = file_priv;
2696                 list_add_tail(&request->client_list,
2697                     &file_priv->mm.request_list);
2698                 spin_unlock(&file_priv->mm.lock);
2699         }
2700
2701         ring->outstanding_lazy_request = 0;
2702
2703         if (!dev_priv->mm.suspended) {
2704                 if (i915_enable_hangcheck) {
2705                         callout_reset(&dev_priv->hangcheck_timer,
2706                             DRM_I915_HANGCHECK_PERIOD, i915_hangcheck_elapsed, ring->dev);
2707                 }
2708                 if (was_empty)
2709                         taskqueue_enqueue_timeout(dev_priv->tq,
2710                             &dev_priv->mm.retire_task, hz);
2711         }
2712         return (0);
2713 }
2714
2715 static inline void
2716 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2717 {
2718         struct drm_i915_file_private *file_priv = request->file_priv;
2719
2720         if (!file_priv)
2721                 return;
2722
2723         DRM_LOCK_ASSERT(request->ring->dev);
2724
2725         spin_lock(&file_priv->mm.lock);
2726         if (request->file_priv != NULL) {
2727                 list_del(&request->client_list);
2728                 request->file_priv = NULL;
2729         }
2730         spin_unlock(&file_priv->mm.lock);
2731 }
2732
2733 void
2734 i915_gem_release(struct drm_device *dev, struct drm_file *file)
2735 {
2736         struct drm_i915_file_private *file_priv;
2737         struct drm_i915_gem_request *request;
2738
2739         file_priv = file->driver_priv;
2740
2741         /* Clean up our request list when the client is going away, so that
2742          * later retire_requests won't dereference our soon-to-be-gone
2743          * file_priv.
2744          */
2745         spin_lock(&file_priv->mm.lock);
2746         while (!list_empty(&file_priv->mm.request_list)) {
2747                 request = list_first_entry(&file_priv->mm.request_list,
2748                                            struct drm_i915_gem_request,
2749                                            client_list);
2750                 list_del(&request->client_list);
2751                 request->file_priv = NULL;
2752         }
2753         spin_unlock(&file_priv->mm.lock);
2754 }
2755
2756 static void
2757 i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2758     struct intel_ring_buffer *ring)
2759 {
2760
2761         if (ring->dev != NULL)
2762                 DRM_LOCK_ASSERT(ring->dev);
2763
2764         while (!list_empty(&ring->request_list)) {
2765                 struct drm_i915_gem_request *request;
2766
2767                 request = list_first_entry(&ring->request_list,
2768                     struct drm_i915_gem_request, list);
2769
2770                 list_del(&request->list);
2771                 i915_gem_request_remove_from_client(request);
2772                 drm_free(request, DRM_I915_GEM);
2773         }
2774
2775         while (!list_empty(&ring->active_list)) {
2776                 struct drm_i915_gem_object *obj;
2777
2778                 obj = list_first_entry(&ring->active_list,
2779                     struct drm_i915_gem_object, ring_list);
2780
2781                 obj->base.write_domain = 0;
2782                 list_del_init(&obj->gpu_write_list);
2783                 i915_gem_object_move_to_inactive(obj);
2784         }
2785 }
2786
2787 static void
2788 i915_gem_reset_fences(struct drm_device *dev)
2789 {
2790         struct drm_i915_private *dev_priv = dev->dev_private;
2791         int i;
2792
2793         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2794                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2795                 struct drm_i915_gem_object *obj = reg->obj;
2796
2797                 if (!obj)
2798                         continue;
2799
2800                 if (obj->tiling_mode)
2801                         i915_gem_release_mmap(obj);
2802
2803                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
2804                 reg->obj->fenced_gpu_access = false;
2805                 reg->obj->last_fenced_seqno = 0;
2806                 reg->obj->last_fenced_ring = NULL;
2807                 i915_gem_clear_fence_reg(dev, reg);
2808         }
2809 }
2810
2811 void
2812 i915_gem_reset(struct drm_device *dev)
2813 {
2814         struct drm_i915_private *dev_priv = dev->dev_private;
2815         struct drm_i915_gem_object *obj;
2816         int i;
2817
2818         for (i = 0; i < I915_NUM_RINGS; i++)
2819                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->rings[i]);
2820
2821         /* Remove anything from the flushing lists. The GPU cache is likely
2822          * to be lost on reset along with the data, so simply move the
2823          * lost bo to the inactive list.
2824          */
2825         while (!list_empty(&dev_priv->mm.flushing_list)) {
2826                 obj = list_first_entry(&dev_priv->mm.flushing_list,
2827                                       struct drm_i915_gem_object,
2828                                       mm_list);
2829
2830                 obj->base.write_domain = 0;
2831                 list_del_init(&obj->gpu_write_list);
2832                 i915_gem_object_move_to_inactive(obj);
2833         }
2834
2835         /* Move everything out of the GPU domains to ensure we do any
2836          * necessary invalidation upon reuse.
2837          */
2838         list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
2839                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2840         }
2841
2842         /* The fence registers are invalidated so clear them out */
2843         i915_gem_reset_fences(dev);
2844 }
2845
2846 /**
2847  * This function clears the request list as sequence numbers are passed.
2848  */
2849 void
2850 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2851 {
2852         uint32_t seqno;
2853         int i;
2854
2855         if (list_empty(&ring->request_list))
2856                 return;
2857
2858         seqno = ring->get_seqno(ring);
2859         for (i = 0; i < DRM_ARRAY_SIZE(ring->sync_seqno); i++)
2860                 if (seqno >= ring->sync_seqno[i])
2861                         ring->sync_seqno[i] = 0;
2862
2863         while (!list_empty(&ring->request_list)) {
2864                 struct drm_i915_gem_request *request;
2865
2866                 request = list_first_entry(&ring->request_list,
2867                                            struct drm_i915_gem_request,
2868                                            list);
2869
2870                 if (!i915_seqno_passed(seqno, request->seqno))
2871                         break;
2872
2873                 ring->last_retired_head = request->tail;
2874
2875                 list_del(&request->list);
2876                 i915_gem_request_remove_from_client(request);
2877                 drm_free(request, DRM_I915_GEM);
2878         }
2879
2880         /* Move any buffers on the active list that are no longer referenced
2881          * by the ringbuffer to the flushing/inactive lists as appropriate.
2882          */
2883         while (!list_empty(&ring->active_list)) {
2884                 struct drm_i915_gem_object *obj;
2885
2886                 obj = list_first_entry(&ring->active_list,
2887                                       struct drm_i915_gem_object,
2888                                       ring_list);
2889
2890                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
2891                         break;
2892
2893                 if (obj->base.write_domain != 0)
2894                         i915_gem_object_move_to_flushing(obj);
2895                 else
2896                         i915_gem_object_move_to_inactive(obj);
2897         }
2898
2899         if (ring->trace_irq_seqno &&
2900             i915_seqno_passed(seqno, ring->trace_irq_seqno)) {
2901                 lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
2902                 ring->irq_put(ring);
2903                 lockmgr(&ring->irq_lock, LK_RELEASE);
2904                 ring->trace_irq_seqno = 0;
2905         }
2906 }
2907
2908 void
2909 i915_gem_retire_requests(struct drm_device *dev)
2910 {
2911         drm_i915_private_t *dev_priv = dev->dev_private;
2912         struct drm_i915_gem_object *obj, *next;
2913         int i;
2914
2915         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
2916                 list_for_each_entry_safe(obj, next,
2917                     &dev_priv->mm.deferred_free_list, mm_list)
2918                         i915_gem_free_object_tail(obj);
2919         }
2920
2921         for (i = 0; i < I915_NUM_RINGS; i++)
2922                 i915_gem_retire_requests_ring(&dev_priv->rings[i]);
2923 }
2924
2925 static int
2926 sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2927     struct intel_ring_buffer *pipelined)
2928 {
2929         struct drm_device *dev = obj->base.dev;
2930         drm_i915_private_t *dev_priv = dev->dev_private;
2931         u32 size = obj->gtt_space->size;
2932         int regnum = obj->fence_reg;
2933         uint64_t val;
2934
2935         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2936                          0xfffff000) << 32;
2937         val |= obj->gtt_offset & 0xfffff000;
2938         val |= (uint64_t)((obj->stride / 128) - 1) <<
2939                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2940
2941         if (obj->tiling_mode == I915_TILING_Y)
2942                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2943         val |= I965_FENCE_REG_VALID;
2944
2945         if (pipelined) {
2946                 int ret = intel_ring_begin(pipelined, 6);
2947                 if (ret)
2948                         return ret;
2949
2950                 intel_ring_emit(pipelined, MI_NOOP);
2951                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2952                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2953                 intel_ring_emit(pipelined, (u32)val);
2954                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2955                 intel_ring_emit(pipelined, (u32)(val >> 32));
2956                 intel_ring_advance(pipelined);
2957         } else
2958                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2959
2960         return 0;
2961 }
2962
2963 static int
2964 i965_write_fence_reg(struct drm_i915_gem_object *obj,
2965     struct intel_ring_buffer *pipelined)
2966 {
2967         struct drm_device *dev = obj->base.dev;
2968         drm_i915_private_t *dev_priv = dev->dev_private;
2969         u32 size = obj->gtt_space->size;
2970         int regnum = obj->fence_reg;
2971         uint64_t val;
2972
2973         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2974                     0xfffff000) << 32;
2975         val |= obj->gtt_offset & 0xfffff000;
2976         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2977         if (obj->tiling_mode == I915_TILING_Y)
2978                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2979         val |= I965_FENCE_REG_VALID;
2980
2981         if (pipelined) {
2982                 int ret = intel_ring_begin(pipelined, 6);
2983                 if (ret)
2984                         return ret;
2985
2986                 intel_ring_emit(pipelined, MI_NOOP);
2987                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2988                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2989                 intel_ring_emit(pipelined, (u32)val);
2990                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2991                 intel_ring_emit(pipelined, (u32)(val >> 32));
2992                 intel_ring_advance(pipelined);
2993         } else
2994                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2995
2996         return 0;
2997 }
2998
2999 static int
3000 i915_write_fence_reg(struct drm_i915_gem_object *obj,
3001     struct intel_ring_buffer *pipelined)
3002 {
3003         struct drm_device *dev = obj->base.dev;
3004         drm_i915_private_t *dev_priv = dev->dev_private;
3005         u32 size = obj->gtt_space->size;
3006         u32 fence_reg, val, pitch_val;
3007         int tile_width;
3008
3009         if ((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
3010             (size & -size) != size || (obj->gtt_offset & (size - 1))) {
3011                 kprintf(
3012 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3013                  obj->gtt_offset, obj->map_and_fenceable, size);
3014                 return -EINVAL;
3015         }
3016
3017         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3018                 tile_width = 128;
3019         else
3020                 tile_width = 512;
3021
3022         /* Note: pitch better be a power of two tile widths */
3023         pitch_val = obj->stride / tile_width;
3024         pitch_val = ffs(pitch_val) - 1;
3025
3026         val = obj->gtt_offset;
3027         if (obj->tiling_mode == I915_TILING_Y)
3028                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3029         val |= I915_FENCE_SIZE_BITS(size);
3030         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3031         val |= I830_FENCE_REG_VALID;
3032
3033         fence_reg = obj->fence_reg;
3034         if (fence_reg < 8)
3035                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
3036         else
3037                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
3038
3039         if (pipelined) {
3040                 int ret = intel_ring_begin(pipelined, 4);
3041                 if (ret)
3042                         return ret;
3043
3044                 intel_ring_emit(pipelined, MI_NOOP);
3045                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
3046                 intel_ring_emit(pipelined, fence_reg);
3047                 intel_ring_emit(pipelined, val);
3048                 intel_ring_advance(pipelined);
3049         } else
3050                 I915_WRITE(fence_reg, val);
3051
3052         return 0;
3053 }
3054
3055 static int
3056 i830_write_fence_reg(struct drm_i915_gem_object *obj,
3057     struct intel_ring_buffer *pipelined)
3058 {
3059         struct drm_device *dev = obj->base.dev;
3060         drm_i915_private_t *dev_priv = dev->dev_private;
3061         u32 size = obj->gtt_space->size;
3062         int regnum = obj->fence_reg;
3063         uint32_t val;
3064         uint32_t pitch_val;
3065
3066         if ((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
3067             (size & -size) != size || (obj->gtt_offset & (size - 1))) {
3068                 kprintf(
3069 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
3070                     obj->gtt_offset, size);
3071                 return -EINVAL;
3072         }
3073
3074         pitch_val = obj->stride / 128;
3075         pitch_val = ffs(pitch_val) - 1;
3076
3077         val = obj->gtt_offset;
3078         if (obj->tiling_mode == I915_TILING_Y)
3079                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3080         val |= I830_FENCE_SIZE_BITS(size);
3081         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3082         val |= I830_FENCE_REG_VALID;
3083
3084         if (pipelined) {
3085                 int ret = intel_ring_begin(pipelined, 4);
3086                 if (ret)
3087                         return ret;
3088
3089                 intel_ring_emit(pipelined, MI_NOOP);
3090                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
3091                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
3092                 intel_ring_emit(pipelined, val);
3093                 intel_ring_advance(pipelined);
3094         } else
3095                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
3096
3097         return 0;
3098 }
3099
3100 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
3101 {
3102         return i915_seqno_passed(ring->get_seqno(ring), seqno);
3103 }
3104
3105 static int
3106 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
3107     struct intel_ring_buffer *pipelined)
3108 {
3109         int ret;
3110
3111         if (obj->fenced_gpu_access) {
3112                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3113                         ret = i915_gem_flush_ring(obj->last_fenced_ring, 0,
3114                             obj->base.write_domain);
3115                         if (ret)
3116                                 return ret;
3117                 }
3118
3119                 obj->fenced_gpu_access = false;
3120         }
3121
3122         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
3123                 if (!ring_passed_seqno(obj->last_fenced_ring,
3124                                        obj->last_fenced_seqno)) {
3125                         ret = i915_wait_request(obj->last_fenced_ring,
3126                                                 obj->last_fenced_seqno,
3127                                                 true);
3128                         if (ret)
3129                                 return ret;
3130                 }
3131
3132                 obj->last_fenced_seqno = 0;
3133                 obj->last_fenced_ring = NULL;
3134         }
3135
3136         /* Ensure that all CPU reads are completed before installing a fence
3137          * and all writes before removing the fence.
3138          */
3139         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
3140                 cpu_mfence();
3141
3142         return 0;
3143 }
3144
3145 int
3146 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3147 {
3148         int ret;
3149
3150         if (obj->tiling_mode)
3151                 i915_gem_release_mmap(obj);
3152
3153         ret = i915_gem_object_flush_fence(obj, NULL);
3154         if (ret)
3155                 return ret;
3156
3157         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3158                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3159
3160                 if (dev_priv->fence_regs[obj->fence_reg].pin_count != 0)
3161                         kprintf("%s: pin_count %d\n", __func__,
3162                             dev_priv->fence_regs[obj->fence_reg].pin_count);
3163                 i915_gem_clear_fence_reg(obj->base.dev,
3164                                          &dev_priv->fence_regs[obj->fence_reg]);
3165
3166                 obj->fence_reg = I915_FENCE_REG_NONE;
3167         }
3168
3169         return 0;
3170 }
3171
3172 static struct drm_i915_fence_reg *
3173 i915_find_fence_reg(struct drm_device *dev, struct intel_ring_buffer *pipelined)
3174 {
3175         struct drm_i915_private *dev_priv = dev->dev_private;
3176         struct drm_i915_fence_reg *reg, *first, *avail;
3177         int i;
3178
3179         /* First try to find a free reg */
3180         avail = NULL;
3181         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3182                 reg = &dev_priv->fence_regs[i];
3183                 if (!reg->obj)
3184                         return reg;
3185
3186                 if (!reg->pin_count)
3187                         avail = reg;
3188         }
3189
3190         if (avail == NULL)
3191                 return NULL;
3192
3193         /* None available, try to steal one or wait for a user to finish */
3194         avail = first = NULL;
3195         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3196                 if (reg->pin_count)
3197                         continue;
3198
3199                 if (first == NULL)
3200                         first = reg;
3201
3202                 if (!pipelined ||
3203                     !reg->obj->last_fenced_ring ||
3204                     reg->obj->last_fenced_ring == pipelined) {
3205                         avail = reg;
3206                         break;
3207                 }
3208         }
3209
3210         if (avail == NULL)
3211                 avail = first;
3212
3213         return avail;
3214 }
3215
3216 int
3217 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
3218     struct intel_ring_buffer *pipelined)
3219 {
3220         struct drm_device *dev = obj->base.dev;
3221         struct drm_i915_private *dev_priv = dev->dev_private;
3222         struct drm_i915_fence_reg *reg;
3223         int ret;
3224
3225         pipelined = NULL;
3226         ret = 0;
3227
3228         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3229                 reg = &dev_priv->fence_regs[obj->fence_reg];
3230                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
3231
3232                 if (obj->tiling_changed) {
3233                         ret = i915_gem_object_flush_fence(obj, pipelined);
3234                         if (ret)
3235                                 return ret;
3236
3237                         if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
3238                                 pipelined = NULL;
3239
3240                         if (pipelined) {
3241                                 reg->setup_seqno =
3242                                         i915_gem_next_request_seqno(pipelined);
3243                                 obj->last_fenced_seqno = reg->setup_seqno;
3244                                 obj->last_fenced_ring = pipelined;
3245                         }
3246
3247                         goto update;
3248                 }
3249
3250                 if (!pipelined) {
3251                         if (reg->setup_seqno) {
3252                                 if (!ring_passed_seqno(obj->last_fenced_ring,
3253                                     reg->setup_seqno)) {
3254                                         ret = i915_wait_request(
3255                                             obj->last_fenced_ring,
3256                                             reg->setup_seqno,
3257                                             true);
3258                                         if (ret)
3259                                                 return ret;
3260                                 }
3261
3262                                 reg->setup_seqno = 0;
3263                         }
3264                 } else if (obj->last_fenced_ring &&
3265                            obj->last_fenced_ring != pipelined) {
3266                         ret = i915_gem_object_flush_fence(obj, pipelined);
3267                         if (ret)
3268                                 return ret;
3269                 }
3270
3271                 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
3272                         pipelined = NULL;
3273                 KASSERT(pipelined || reg->setup_seqno == 0, ("!pipelined"));
3274
3275                 if (obj->tiling_changed) {
3276                         if (pipelined) {
3277                                 reg->setup_seqno =
3278                                         i915_gem_next_request_seqno(pipelined);
3279                                 obj->last_fenced_seqno = reg->setup_seqno;
3280                                 obj->last_fenced_ring = pipelined;
3281                         }
3282                         goto update;
3283                 }
3284
3285                 return 0;
3286         }
3287
3288         reg = i915_find_fence_reg(dev, pipelined);
3289         if (reg == NULL)
3290                 return -EDEADLK;
3291
3292         ret = i915_gem_object_flush_fence(obj, pipelined);
3293         if (ret)
3294                 return ret;
3295
3296         if (reg->obj) {
3297                 struct drm_i915_gem_object *old = reg->obj;
3298
3299                 drm_gem_object_reference(&old->base);
3300
3301                 if (old->tiling_mode)
3302                         i915_gem_release_mmap(old);
3303
3304                 ret = i915_gem_object_flush_fence(old, pipelined);
3305                 if (ret) {
3306                         drm_gem_object_unreference(&old->base);
3307                         return ret;
3308                 }
3309
3310                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
3311                         pipelined = NULL;
3312
3313                 old->fence_reg = I915_FENCE_REG_NONE;
3314                 old->last_fenced_ring = pipelined;
3315                 old->last_fenced_seqno =
3316                         pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
3317
3318                 drm_gem_object_unreference(&old->base);
3319         } else if (obj->last_fenced_seqno == 0)
3320                 pipelined = NULL;
3321
3322         reg->obj = obj;
3323         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
3324         obj->fence_reg = reg - dev_priv->fence_regs;
3325         obj->last_fenced_ring = pipelined;
3326
3327         reg->setup_seqno =
3328                 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
3329         obj->last_fenced_seqno = reg->setup_seqno;
3330
3331 update:
3332         obj->tiling_changed = false;
3333         switch (INTEL_INFO(dev)->gen) {
3334         case 7:
3335         case 6:
3336                 ret = sandybridge_write_fence_reg(obj, pipelined);
3337                 break;
3338         case 5:
3339         case 4:
3340                 ret = i965_write_fence_reg(obj, pipelined);
3341                 break;
3342         case 3:
3343                 ret = i915_write_fence_reg(obj, pipelined);
3344                 break;
3345         case 2:
3346                 ret = i830_write_fence_reg(obj, pipelined);
3347                 break;
3348         }
3349
3350         return ret;
3351 }
3352
3353 static void
3354 i915_gem_clear_fence_reg(struct drm_device *dev, struct drm_i915_fence_reg *reg)
3355 {
3356         drm_i915_private_t *dev_priv = dev->dev_private;
3357         uint32_t fence_reg = reg - dev_priv->fence_regs;
3358
3359         switch (INTEL_INFO(dev)->gen) {
3360         case 7:
3361         case 6:
3362                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
3363                 break;
3364         case 5:
3365         case 4:
3366                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
3367                 break;
3368         case 3:
3369                 if (fence_reg >= 8)
3370                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
3371                 else
3372         case 2:
3373                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
3374
3375                 I915_WRITE(fence_reg, 0);
3376                 break;
3377         }
3378
3379         list_del_init(&reg->lru_list);
3380         reg->obj = NULL;
3381         reg->setup_seqno = 0;
3382         reg->pin_count = 0;
3383 }
3384
3385 int
3386 i915_gem_init_object(struct drm_gem_object *obj)
3387 {
3388
3389         kprintf("i915_gem_init_object called\n");
3390         return (0);
3391 }
3392
3393 static bool
3394 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
3395 {
3396
3397         return (obj->gtt_space && !obj->active && obj->pin_count == 0);
3398 }
3399
3400 static void
3401 i915_gem_retire_task_handler(void *arg, int pending)
3402 {
3403         drm_i915_private_t *dev_priv;
3404         struct drm_device *dev;
3405         bool idle;
3406         int i;
3407
3408         dev_priv = arg;
3409         dev = dev_priv->dev;
3410
3411         /* Come back later if the device is busy... */
3412         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT)) {
3413                 taskqueue_enqueue_timeout(dev_priv->tq,
3414                     &dev_priv->mm.retire_task, hz);
3415                 return;
3416         }
3417
3418         i915_gem_retire_requests(dev);
3419
3420         /* Send a periodic flush down the ring so we don't hold onto GEM
3421          * objects indefinitely.
3422          */
3423         idle = true;
3424         for (i = 0; i < I915_NUM_RINGS; i++) {
3425                 struct intel_ring_buffer *ring = &dev_priv->rings[i];
3426
3427                 if (!list_empty(&ring->gpu_write_list)) {
3428                         struct drm_i915_gem_request *request;
3429                         int ret;
3430
3431                         ret = i915_gem_flush_ring(ring,
3432                                                   0, I915_GEM_GPU_DOMAINS);
3433                         request = kmalloc(sizeof(*request), DRM_I915_GEM,
3434                             M_WAITOK | M_ZERO);
3435                         if (ret || request == NULL ||
3436                             i915_add_request(ring, NULL, request))
3437                                 drm_free(request, DRM_I915_GEM);
3438                 }
3439
3440                 idle &= list_empty(&ring->request_list);
3441         }
3442
3443         if (!dev_priv->mm.suspended && !idle)
3444                 taskqueue_enqueue_timeout(dev_priv->tq,
3445                     &dev_priv->mm.retire_task, hz);
3446
3447         DRM_UNLOCK(dev);
3448 }
3449
3450 void
3451 i915_gem_lastclose(struct drm_device *dev)
3452 {
3453         int ret;
3454
3455         if (drm_core_check_feature(dev, DRIVER_MODESET))
3456                 return;
3457
3458         ret = i915_gem_idle(dev);
3459         if (ret != 0)
3460                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3461 }
3462
3463 static int
3464 i915_gem_init_phys_object(struct drm_device *dev, int id, int size, int align)
3465 {
3466         drm_i915_private_t *dev_priv;
3467         struct drm_i915_gem_phys_object *phys_obj;
3468         int ret;
3469
3470         dev_priv = dev->dev_private;
3471         if (dev_priv->mm.phys_objs[id - 1] != NULL || size == 0)
3472                 return (0);
3473
3474         phys_obj = kmalloc(sizeof(struct drm_i915_gem_phys_object), DRM_I915_GEM,
3475             M_WAITOK | M_ZERO);
3476
3477         phys_obj->id = id;
3478
3479         phys_obj->handle = drm_pci_alloc(dev, size, align, ~0);
3480         if (phys_obj->handle == NULL) {
3481                 ret = -ENOMEM;
3482                 goto free_obj;
3483         }
3484         pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
3485             size / PAGE_SIZE, PAT_WRITE_COMBINING);
3486
3487         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3488
3489         return (0);
3490
3491 free_obj:
3492         drm_free(phys_obj, DRM_I915_GEM);
3493         return (ret);
3494 }
3495
3496 static void
3497 i915_gem_free_phys_object(struct drm_device *dev, int id)
3498 {
3499         drm_i915_private_t *dev_priv;
3500         struct drm_i915_gem_phys_object *phys_obj;
3501
3502         dev_priv = dev->dev_private;
3503         if (dev_priv->mm.phys_objs[id - 1] == NULL)
3504                 return;
3505
3506         phys_obj = dev_priv->mm.phys_objs[id - 1];
3507         if (phys_obj->cur_obj != NULL)
3508                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3509
3510         drm_pci_free(dev, phys_obj->handle);
3511         drm_free(phys_obj, DRM_I915_GEM);
3512         dev_priv->mm.phys_objs[id - 1] = NULL;
3513 }
3514
3515 void
3516 i915_gem_free_all_phys_object(struct drm_device *dev)
3517 {
3518         int i;
3519
3520         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3521                 i915_gem_free_phys_object(dev, i);
3522 }
3523
3524 void
3525 i915_gem_detach_phys_object(struct drm_device *dev,
3526     struct drm_i915_gem_object *obj)
3527 {
3528         vm_page_t m;
3529         struct sf_buf *sf;
3530         char *vaddr, *dst;
3531         int i, page_count;
3532
3533         if (obj->phys_obj == NULL)
3534                 return;
3535         vaddr = obj->phys_obj->handle->vaddr;
3536
3537         page_count = obj->base.size / PAGE_SIZE;
3538         VM_OBJECT_LOCK(obj->base.vm_obj);
3539         for (i = 0; i < page_count; i++) {
3540                 m = i915_gem_wire_page(obj->base.vm_obj, i);
3541                 if (m == NULL)
3542                         continue; /* XXX */
3543
3544                 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3545                 sf = sf_buf_alloc(m);
3546                 if (sf != NULL) {
3547                         dst = (char *)sf_buf_kva(sf);
3548                         memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
3549                         sf_buf_free(sf);
3550                 }
3551                 drm_clflush_pages(&m, 1);
3552
3553                 VM_OBJECT_LOCK(obj->base.vm_obj);
3554                 vm_page_reference(m);
3555                 vm_page_dirty(m);
3556                 vm_page_busy_wait(m, FALSE, "i915gem");
3557                 vm_page_unwire(m, 0);
3558                 vm_page_wakeup(m);
3559                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3560         }
3561         VM_OBJECT_UNLOCK(obj->base.vm_obj);
3562         intel_gtt_chipset_flush();
3563
3564         obj->phys_obj->cur_obj = NULL;
3565         obj->phys_obj = NULL;
3566 }
3567
3568 int
3569 i915_gem_attach_phys_object(struct drm_device *dev,
3570     struct drm_i915_gem_object *obj, int id, int align)
3571 {
3572         drm_i915_private_t *dev_priv;
3573         vm_page_t m;
3574         struct sf_buf *sf;
3575         char *dst, *src;
3576         int i, page_count, ret;
3577
3578         if (id > I915_MAX_PHYS_OBJECT)
3579                 return (-EINVAL);
3580
3581         if (obj->phys_obj != NULL) {
3582                 if (obj->phys_obj->id == id)
3583                         return (0);
3584                 i915_gem_detach_phys_object(dev, obj);
3585         }
3586
3587         dev_priv = dev->dev_private;
3588         if (dev_priv->mm.phys_objs[id - 1] == NULL) {
3589                 ret = i915_gem_init_phys_object(dev, id, obj->base.size, align);
3590                 if (ret != 0) {
3591                         DRM_ERROR("failed to init phys object %d size: %zu\n",
3592                                   id, obj->base.size);
3593                         return (ret);
3594                 }
3595         }
3596
3597         /* bind to the object */
3598         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3599         obj->phys_obj->cur_obj = obj;
3600
3601         page_count = obj->base.size / PAGE_SIZE;
3602
3603         VM_OBJECT_LOCK(obj->base.vm_obj);
3604         ret = 0;
3605         for (i = 0; i < page_count; i++) {
3606                 m = i915_gem_wire_page(obj->base.vm_obj, i);
3607                 if (m == NULL) {
3608                         ret = -EIO;
3609                         break;
3610                 }
3611                 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3612                 sf = sf_buf_alloc(m);
3613                 src = (char *)sf_buf_kva(sf);
3614                 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
3615                 memcpy(dst, src, PAGE_SIZE);
3616                 sf_buf_free(sf);
3617
3618                 VM_OBJECT_LOCK(obj->base.vm_obj);
3619
3620                 vm_page_reference(m);
3621                 vm_page_busy_wait(m, FALSE, "i915gem");
3622                 vm_page_unwire(m, 0);
3623                 vm_page_wakeup(m);
3624                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3625         }
3626         VM_OBJECT_UNLOCK(obj->base.vm_obj);
3627
3628         return (0);
3629 }
3630
3631 static int
3632 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_i915_gem_object *obj,
3633     uint64_t data_ptr, uint64_t offset, uint64_t size,
3634     struct drm_file *file_priv)
3635 {
3636         char *user_data, *vaddr;
3637         int ret;
3638
3639         vaddr = (char *)obj->phys_obj->handle->vaddr + offset;
3640         user_data = (char *)(uintptr_t)data_ptr;
3641
3642         if (copyin_nofault(user_data, vaddr, size) != 0) {
3643                 /* The physical object once assigned is fixed for the lifetime
3644                  * of the obj, so we can safely drop the lock and continue
3645                  * to access vaddr.
3646                  */
3647                 DRM_UNLOCK(dev);
3648                 ret = -copyin(user_data, vaddr, size);
3649                 DRM_LOCK(dev);
3650                 if (ret != 0)
3651                         return (ret);
3652         }
3653
3654         intel_gtt_chipset_flush();
3655         return (0);
3656 }
3657
3658 static int
3659 i915_gpu_is_active(struct drm_device *dev)
3660 {
3661         drm_i915_private_t *dev_priv;
3662
3663         dev_priv = dev->dev_private;
3664         return (!list_empty(&dev_priv->mm.flushing_list) ||
3665             !list_empty(&dev_priv->mm.active_list));
3666 }
3667
3668 static void
3669 i915_gem_lowmem(void *arg)
3670 {
3671         struct drm_device *dev;
3672         struct drm_i915_private *dev_priv;
3673         struct drm_i915_gem_object *obj, *next;
3674         int cnt, cnt_fail, cnt_total;
3675
3676         dev = arg;
3677         dev_priv = dev->dev_private;
3678
3679         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT))
3680                 return;
3681
3682 rescan:
3683         /* first scan for clean buffers */
3684         i915_gem_retire_requests(dev);
3685
3686         cnt_total = cnt_fail = cnt = 0;
3687
3688         list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3689             mm_list) {
3690                 if (i915_gem_object_is_purgeable(obj)) {
3691                         if (i915_gem_object_unbind(obj) != 0)
3692                                 cnt_total++;
3693                 } else
3694                         cnt_total++;
3695         }
3696
3697         /* second pass, evict/count anything still on the inactive list */
3698         list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3699             mm_list) {
3700                 if (i915_gem_object_unbind(obj) == 0)
3701                         cnt++;
3702                 else
3703                         cnt_fail++;
3704         }
3705
3706         if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
3707                 /*
3708                  * We are desperate for pages, so as a last resort, wait
3709                  * for the GPU to finish and discard whatever we can.
3710                  * This has a dramatic impact to reduce the number of
3711                  * OOM-killer events whilst running the GPU aggressively.
3712                  */
3713                 if (i915_gpu_idle(dev, true) == 0)
3714                         goto rescan;
3715         }
3716         DRM_UNLOCK(dev);
3717 }
3718
3719 void
3720 i915_gem_unload(struct drm_device *dev)
3721 {
3722         struct drm_i915_private *dev_priv;
3723
3724         dev_priv = dev->dev_private;
3725         EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);
3726 }